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Merge pull request #13083 from jeromecoutant/PR_H7_CUBE170 

STM32H7 update drivers version to CUBE V1.7.0
pull/12899/head
Martin Kojtal 2020-06-16 13:45:42 +02:00 committed by GitHub
parent 0b0ab6bf87 048f454a5a
commit 0614e92c5b
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
311 changed files with 316173 additions and 16392 deletions
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3
features/netsocket/emac-drivers/TARGET_STM/mbed_lib.json
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@ -49,6 +49,9 @@
"eth-rxbufnb": 2,
"eth-txbufnb": 4
},
"STM32H7": {
"eth-txbufnb": 10
},
"ARCH_MAX": {
"eth-phy-address": 1
}

2
targets/TARGET_STM/README.md
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@ -68,7 +68,7 @@ This table summarizes the STM32Cube versions currently used in Mbed OS master br
| F4 | 1.19.0 | https://github.com/STMicroelectronics/STM32CubeF4 |
| F7 | 1.16.0 | https://github.com/STMicroelectronics/STM32CubeF7 |
| G0 | 1.3.0 | https://github.com/STMicroelectronics/STM32CubeG0 |
| H7 | 1.4.0 | https://github.com/STMicroelectronics/STM32CubeH7 |
| H7 | 1.7.0 | https://github.com/STMicroelectronics/STM32CubeH7 |
| L0 | 1.10.0 | https://github.com/STMicroelectronics/STM32CubeL0 |
| L1 | 1.8.1 | https://github.com/STMicroelectronics/STM32CubeL1 |
| L4 | 1.11.0 | https://github.com/STMicroelectronics/STM32CubeL4 |

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targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h742xx.h Normal file
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targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/stm32h743xx.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h743xx.h
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0
targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/device/stm32h745xx.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h745xx.h
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targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/device/stm32h747xx.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h747xx.h
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targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7a3xx.h Normal file
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targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7a3xxq.h Normal file
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28
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7xx.h
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@ -59,7 +59,8 @@
*/
#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \
!defined (STM32H745xx) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H757xx)
!defined (STM32H745xx) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H757xx) && \
!defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx) && !defined (STM32H7B0xxQ)
/* #define STM32H742xx */ /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
/* #define STM32H743xx */ /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
/* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
@ -68,6 +69,11 @@
/* #define STM32H757xx */ /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
/* #define STM32H745xx */ /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices */
/* #define STM32H755xx */ /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices */
/* #define STM32H7B0xx */ /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */
/* #define STM32H7A3xx */ /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */
/* #define STM32H7A3xxQ */ /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */
/* #define STM32H7B3xx */ /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */
/* #define STM32H7B3xxQ */ /*!< STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@ -88,10 +94,10 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.6.0
* @brief CMSIS Device version number V1.8.0
*/
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x06) /*!< [23:16] sub1 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
@ -123,6 +129,18 @@
#include "stm32h747xx.h"
#elif defined(STM32H757xx)
#include "stm32h757xx.h"
#elif defined(STM32H7B0xx)
#include "stm32h7b0xx.h"
#elif defined(STM32H7B0xxQ)
#include "stm32h7b0xxq.h"
#elif defined(STM32H7A3xx)
#include "stm32h7a3xx.h"
#elif defined(STM32H7B3xx)
#include "stm32h7b3xx.h"
#elif defined(STM32H7A3xxQ)
#include "stm32h7a3xxq.h"
#elif defined(STM32H7B3xxQ)
#include "stm32h7b3xxq.h"
#else
#error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
#endif
@ -149,8 +167,8 @@ typedef enum
typedef enum
{
ERROR = 0,
SUCCESS = !ERROR
SUCCESS = 0,
ERROR = !SUCCESS
} ErrorStatus;
/**

7
targets/TARGET_STM/TARGET_STM32H7/device/system_stm32h7xx.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/system_stm32h7xx.h
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@ -55,12 +55,7 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
#if defined(DUAL_CORE) && defined(CORE_CM4)
#define SystemCoreClock SystemD2Clock /*!< System Domain1 Clock Frequency */
#else
#define SystemCoreClock SystemD1Clock
#endif
extern uint32_t SystemD1Clock; /*!< System Domain1 Clock Frequency */
extern uint32_t SystemCoreClock; /*!< System Domain1 Clock Frequency */
extern uint32_t SystemD2Clock; /*!< System Domain2 Clock Frequency */
extern const uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers table values */

184
targets/TARGET_STM/TARGET_STM32H7/device/stm32_hal_legacy.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32_hal_legacy.h
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@ -236,12 +236,12 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
#if defined(STM32G4)
#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH)
#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH)
#if defined(STM32G4) || defined(STM32H7)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0)
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
@ -306,8 +306,17 @@
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
#endif
#endif /* STM32L4 */
#if defined(STM32G0)
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
#endif
#if defined(STM32H7)
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
@ -365,6 +374,9 @@
#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
#endif /* STM32H7 */
/**
@ -460,7 +472,9 @@
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
#endif
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
#endif /* STM32H7 */
/**
* @}
@ -564,7 +578,14 @@
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
#endif
#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
@ -735,6 +756,66 @@
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
#endif /* STM32H7 */
#if defined(STM32F3)
/** @brief Constants defining available sources associated to external events.
*/
#define HRTIM_EVENTSRC_1 (0x00000000U)
#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
/** @brief Constants defining the events that can be selected to configure the
* set/reset crossbar of a timer output
*/
#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
/** @brief Constants defining the event filtering applied to external events
* by a timer
*/
#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
/** @brief Constants defining the DLL calibration periods (in micro seconds)
*/
#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
#endif /* STM32F3 */
/**
* @}
*/
@ -874,7 +955,7 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
#if defined(STM32L1) || defined(STM32L4)
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
@ -933,7 +1014,7 @@
/**
* @}
*/
/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
* @{
*/
@ -965,6 +1046,16 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
#if defined(STM32H7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
#endif /* STM32H7 */
/**
* @}
*/
@ -1358,6 +1449,30 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
@ -1380,6 +1495,13 @@
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
/**
* @}
*/
@ -1409,16 +1531,18 @@
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
#if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
@ -1437,6 +1561,13 @@
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
* @{
*/
#if defined(STM32G0)
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
#endif
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
@ -1509,14 +1640,14 @@
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4)
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */
#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
/**
* @}
*/
@ -3112,9 +3243,8 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
#if defined(STM32L4)
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
@ -3242,7 +3372,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4)
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@ -3350,9 +3480,9 @@
#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
/* alias CMSIS for compatibilities */
#define SDIO_IRQn SDMMC1_IRQn
#define SDIO_IRQHandler SDMMC1_IRQHandler
@ -3365,7 +3495,7 @@
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
#endif
#if defined(STM32H7)
#if defined(STM32H7) || defined(STM32L5)
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
@ -3606,12 +3736,12 @@
* @{
*/
#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
#endif
/**
* @}
@ -3620,9 +3750,9 @@
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32L4)
#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
#endif
#endif /* STM32L4 || STM32F4 || STM32F7 */
/**
* @}
*/

101
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal.c
View File

@ -47,10 +47,10 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
* @brief STM32H7xx HAL Driver version number V1.6.0
* @brief STM32H7xx HAL Driver version number V1.8.0
*/
#define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */
#define __STM32H7xx_HAL_VERSION_SUB1 (0x06UL) /*!< [23:16] sub1 version */
#define __STM32H7xx_HAL_VERSION_SUB1 (0x08UL) /*!< [23:16] sub1 version */
#define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */
#define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */
#define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
@ -134,6 +134,8 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
HAL_StatusTypeDef HAL_Init(void)
{
uint32_t common_system_clock;
#if defined(DUAL_CORE) && defined(CORE_CM4)
/* Configure Cortex-M4 Instruction cache through ART accelerator */
__HAL_RCC_ART_CLK_ENABLE(); /* Enable the Cortex-M4 ART Clock */
@ -145,10 +147,24 @@ HAL_StatusTypeDef HAL_Init(void)
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
/* Update the SystemCoreClock global variable */
SystemD1Clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
#if defined(RCC_D1CFGR_D1CPRE)
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
#else
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
#endif
/* Update the SystemD2Clock global variable */
SystemD2Clock = (SystemD1Clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#if defined(RCC_D1CFGR_HPRE)
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
#if defined(DUAL_CORE) && defined(CORE_CM4)
SystemCoreClock = SystemD2Clock;
#else
SystemCoreClock = common_system_clock;
#endif /* DUAL_CORE && CORE_CM4 */
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
@ -340,14 +356,26 @@ uint32_t HAL_GetTickPrio(void)
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_TickFreqTypeDef prevTickFreq;
assert_param(IS_TICKFREQ(Freq));
if (uwTickFreq != Freq)
{
/* Back up uwTickFreq frequency */
prevTickFreq = uwTickFreq;
/* Update uwTickFreq global variable used by HAL_InitTick() */
uwTickFreq = Freq;
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
if (status != HAL_OK)
{
/* Restore previous tick frequency */
uwTickFreq = prevTickFreq;
}
}
return status;
@ -560,6 +588,7 @@ void HAL_SYSCFG_DisableVREFBUF(void)
CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
}
#if defined(SYSCFG_PMCR_EPIS_SEL)
/**
* @brief Ethernet PHY Interface Selection either MII or RMII
* @param SYSCFG_ETHInterface: Selects the Ethernet PHY interface
@ -575,7 +604,7 @@ void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface)
MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface));
}
#endif /* SYSCFG_PMCR_EPIS_SEL */
/**
* @brief Analog Switch control for dual analog pads.
@ -607,7 +636,7 @@ void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCF
MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState));
}
#if defined(SYSCFG_PMCR_BOOSTEN)
/**
* @brief Enables the booster to reduce the total harmonic distortion of the analog
* switch when the supply voltage is lower than 2.7 V.
@ -632,8 +661,9 @@ void HAL_SYSCFG_DisableBOOST(void)
{
CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
}
#endif /* SYSCFG_PMCR_BOOSTEN */
#if defined (SYSCFG_UR2_BOOT_ADD0) || defined (SYSCFG_UR2_BCM7_ADD0)
/**
* @brief BootCM7 address 0 configuration
* @param BootRegister :Specifies the Boot Address register (Address0 or Address1)
@ -666,8 +696,8 @@ void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, (BootAddress >> 16));
#endif /*DUAL_CORE*/
}
}
#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0 */
#if defined(DUAL_CORE)
/**
@ -736,7 +766,6 @@ void HAL_SYSCFG_DisableCM4BOOT(void)
CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);
}
#endif /*DUAL_CORE*/
/**
* @brief Enables the I/O Compensation Cell.
* @note The I/O compensation cell can be used only when the device supply
@ -769,7 +798,11 @@ void HAL_DisableCompensationCell(void)
*/
void HAL_SYSCFG_EnableIOSpeedOptimize(void)
{
#if defined(SYSCFG_CCCSR_HSLV)
SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
#else
SET_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2 | SYSCFG_CCCSR_HSLV3));
#endif /* SYSCFG_CCCSR_HSLV */
}
/**
@ -781,7 +814,11 @@ void HAL_SYSCFG_EnableIOSpeedOptimize(void)
*/
void HAL_SYSCFG_DisableIOSpeedOptimize(void)
{
#if defined(SYSCFG_CCCSR_HSLV)
CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
#else
CLEAR_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2 | SYSCFG_CCCSR_HSLV3));
#endif /* SYSCFG_CCCSR_HSLV */
}
/**
@ -817,9 +854,28 @@ void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG
MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC|SYSCFG_CCCR_PCC, (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
}
#if defined(SYSCFG_CCCR_NCC_MMC)
/**
* @brief Code selection for the I/O Compensation cell
* @param SYSCFG_PMOSCode: VDDMMC PMOS compensation code
* This code is applied to the I/O compensation cell when the CS bit of the
* SYSCFG_CMPCR is set
* @param SYSCFG_NMOSCode: VDDMMC NMOS compensation code
* This code is applied to the I/O compensation cell when the CS bit of the
* SYSCFG_CMPCR is set
* @retval None
*/
void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
{
/* Check the parameter */
assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
MODIFY_REG(SYSCFG->CCCR, (SYSCFG_CCCR_NCC_MMC | SYSCFG_CCCR_PCC_MMC), (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
}
#endif /* SYSCFG_CCCR_NCC_MMC */
/**
* @brief Enable the Debug Module during Domain1 SLEEP mode
* @brief Enable the Debug Module during Domain1/CDomain SLEEP mode
* @retval None
*/
void HAL_EnableDBGSleepMode(void)
@ -828,7 +884,7 @@ void HAL_EnableDBGSleepMode(void)
}
/**
* @brief Disable the Debug Module during Domain1 SLEEP mode
* @brief Disable the Debug Module during Domain1/CDomain SLEEP mode
* @retval None
*/
void HAL_DisableDBGSleepMode(void)
@ -836,8 +892,9 @@ void HAL_DisableDBGSleepMode(void)
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
}
/**
* @brief Enable the Debug Module during Domain1 STOP mode
* @brief Enable the Debug Module during Domain1/CDomain STOP mode
* @retval None
*/
void HAL_EnableDBGStopMode(void)
@ -846,7 +903,7 @@ void HAL_EnableDBGStopMode(void)
}
/**
* @brief Disable the Debug Module during Domain1 STOP mode
* @brief Disable the Debug Module during Domain1/CDomain STOP mode
* @retval None
*/
void HAL_DisableDBGStopMode(void)
@ -855,7 +912,7 @@ void HAL_DisableDBGStopMode(void)
}
/**
* @brief Enable the Debug Module during Domain1 STANDBY mode
* @brief Enable the Debug Module during Domain1/CDomain STANDBY mode
* @retval None
*/
void HAL_EnableDBGStandbyMode(void)
@ -864,7 +921,7 @@ void HAL_EnableDBGStandbyMode(void)
}
/**
* @brief Disable the Debug Module during Domain1 STANDBY mode
* @brief Disable the Debug Module during Domain1/CDomain STANDBY mode
* @retval None
*/
void HAL_DisableDBGStandbyMode(void)
@ -928,18 +985,16 @@ void HAL_DisableDomain2DBGStandbyMode(void)
}
#endif /*DUAL_CORE*/
/**
* @brief Enable the Debug Module during Domain3 STOP mode
* @brief Enable the Debug Module during Domain3/SRDomain STOP mode
* @retval None
*/
void HAL_EnableDomain3DBGStopMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
}
/**
* @brief Disable the Debug Module during Domain3 STOP mode
* @brief Disable the Debug Module during Domain3/SRDomain STOP mode
* @retval None
*/
void HAL_DisableDomain3DBGStopMode(void)
@ -948,7 +1003,7 @@ void HAL_DisableDomain3DBGStopMode(void)
}
/**
* @brief Enable the Debug Module during Domain3 STANDBY mode
* @brief Enable the Debug Module during Domain3/SRDomain STANDBY mode
* @retval None
*/
void HAL_EnableDomain3DBGStandbyMode(void)
@ -957,7 +1012,7 @@ void HAL_EnableDomain3DBGStandbyMode(void)
}
/**
* @brief Disable the Debug Module during Domain3 STANDBY mode
* @brief Disable the Debug Module during Domain3/SRDomain STANDBY mode
* @retval None
*/
void HAL_DisableDomain3DBGStandbyMode(void)
@ -1045,7 +1100,7 @@ void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_D1_LINE(EXTI_Line));
SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
}
@ -1060,7 +1115,7 @@ void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_D2_LINE(EXTI_Line));
SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
}
#endif /*DUAL_CORE*/

141
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal.h
View File

@ -96,6 +96,28 @@ typedef enum
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0UL) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
/**
* @}
*/
#if !defined(SYSCFG_PMCR_BOOSTEN)
/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
* @{
*/
/** @brief Fast-mode Plus driving capability on a specific GPIO
*/
#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */
#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
#endif /* ! SYSCFG_PMCR_BOOSTEN */
/**
* @}
*/
@ -241,17 +263,16 @@ typedef enum
#define EXTI_LINE41 ((uint32_t)0x29)
#define EXTI_LINE42 ((uint32_t)0x2A)
#define EXTI_LINE43 ((uint32_t)0x2B)
#define EXTI_LINE44 ((uint32_t)0x2C)
#define EXTI_LINE44 ((uint32_t)0x2C) /* Not available in all family lines */
/* EXTI_LINE45 Reserved */
#if defined(DUAL_CORE)
#define EXTI_LINE46 ((uint32_t)0x2E)
#else
/* EXTI_LINE46 Reserved */
#endif
#endif /* DUAL_CORE */
#define EXTI_LINE47 ((uint32_t)0x2F)
#define EXTI_LINE48 ((uint32_t)0x30)
#define EXTI_LINE49 ((uint32_t)0x31)
#define EXTI_LINE50 ((uint32_t)0x32)
#define EXTI_LINE51 ((uint32_t)0x33)
#define EXTI_LINE52 ((uint32_t)0x34)
@ -262,7 +283,6 @@ typedef enum
#define EXTI_LINE57 ((uint32_t)0x39)
#define EXTI_LINE58 ((uint32_t)0x3A)
#define EXTI_LINE59 ((uint32_t)0x3B)
#define EXTI_LINE60 ((uint32_t)0x3C)
#define EXTI_LINE61 ((uint32_t)0x3D)
#define EXTI_LINE62 ((uint32_t)0x3E)
@ -273,45 +293,40 @@ typedef enum
#define EXTI_LINE67 ((uint32_t)0x43)
#define EXTI_LINE68 ((uint32_t)0x44)
#define EXTI_LINE69 ((uint32_t)0x45)
#define EXTI_LINE70 ((uint32_t)0x46)
#define EXTI_LINE71 ((uint32_t)0x47)
#define EXTI_LINE72 ((uint32_t)0x48)
#define EXTI_LINE73 ((uint32_t)0x49)
#define EXTI_LINE74 ((uint32_t)0x4A)
#define EXTI_LINE75 ((uint32_t)0x4B)
#define EXTI_LINE76 ((uint32_t)0x4C)
#define EXTI_LINE75 ((uint32_t)0x4B) /* Not available in all family lines */
#define EXTI_LINE76 ((uint32_t)0x4C) /* Not available in all family lines */
#if defined(DUAL_CORE)
#define EXTI_LINE77 ((uint32_t)0x4D)
#define EXTI_LINE78 ((uint32_t)0x4E)
#define EXTI_LINE79 ((uint32_t)0x4F)
#define EXTI_LINE80 ((uint32_t)0x50)
/* EXTI_LINE81 Reserved */
#define EXTI_LINE82 ((uint32_t)0x52)
/* EXTI_LINE83 Reserved */
#define EXTI_LINE84 ((uint32_t)0x54)
#define EXTI_LINE85 ((uint32_t)0x55)
#define EXTI_LINE86 ((uint32_t)0x56)
#define EXTI_LINE87 ((uint32_t)0x57)
/* EXTI_LINE88 Reserved */
#else
/* EXTI_LINE77 Reserved */
/* EXTI_LINE78 Reserved */
/* EXTI_LINE79 Reserved */
/* EXTI_LINE80 Reserved */
/* EXTI_LINE77 Reserved */
/* EXTI_LINE78 Reserved */
/* EXTI_LINE79 Reserved */
/* EXTI_LINE80 Reserved */
#endif /* DUAL_CORE */
/* EXTI_LINE81 Reserved */
/* EXTI_LINE82 Reserved */
#if defined(DUAL_CORE)
#define EXTI_LINE82 ((uint32_t)0x52)
#else
/* EXTI_LINE82 Reserved */
#endif /* DUAL_CORE */
/* EXTI_LINE83 Reserved */
/* EXTI_LINE84 Reserved */
#if defined(DUAL_CORE)
#define EXTI_LINE84 ((uint32_t)0x54)
#else
/* EXTI_LINE84 Reserved */
#endif /* DUAL_CORE */
#define EXTI_LINE85 ((uint32_t)0x55)
#define EXTI_LINE86 ((uint32_t)0x56)
#define EXTI_LINE86 ((uint32_t)0x56) /* Not available in all family lines */
#define EXTI_LINE87 ((uint32_t)0x57)
/* EXTI_LINE88 Reserved */
#endif
#define EXTI_LINE88 ((uint32_t)0x58) /* Not available in all family lines */
#if defined(DUAL_CORE)
#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
@ -342,7 +357,7 @@ typedef enum
((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \
((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
#endif
#endif /* DUAL_CORE */
#if defined(DUAL_CORE)
#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
@ -428,7 +443,8 @@ typedef enum
((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
((LINE) == EXTI_LINE85) || \
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
((LINE) == EXTI_LINE88))
#endif /*DUAL_CORE*/
#if defined(DUAL_CORE)
@ -513,7 +529,8 @@ typedef enum
((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
((LINE) == EXTI_LINE85) || \
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
((LINE) == EXTI_LINE88))
#endif /*DUAL_CORE*/
#if defined(DUAL_CORE)
@ -576,7 +593,7 @@ typedef enum
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
((LINE) == EXTI_LINE53))
#else
#elif (POWER_DOMAINS_NUMBER == 3U)
#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
@ -592,17 +609,43 @@ typedef enum
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
((LINE) == EXTI_LINE53))
#endif
#else
#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE88))
#endif /*DUAL_CORE*/
#define BDMA_CH6_CLEAR ((uint32_t)0x00000000) /*!< BDMA ch6 event selected as D3 domain pendclear source*/
#define BDMA_CH7_CLEAR ((uint32_t)0x00000001) /*!< BDMA ch7 event selected as D3 domain pendclear source*/
#if defined (LPTIM4)
#define LPTIM4_OUT_CLEAR ((uint32_t)0x00000002) /*!< LPTIM4 out selected as D3 domain pendclear source*/
#else
#define LPTIM2_OUT_CLEAR ((uint32_t)0x00000002) /*!< LPTIM2 out selected as D3 domain pendclear source*/
#endif /* LPTIM4 */
#if defined (LPTIM5)
#define LPTIM5_OUT_CLEAR ((uint32_t)0x00000003) /*!< LPTIM5 out selected as D3 domain pendclear source*/
#else
#define LPTIM3_OUT_CLEAR ((uint32_t)0x00000003) /*!< LPTIM3 out selected as D3 domain pendclear source*/
#endif /* LPTIM5 */
#if defined (LPTIM4) && defined (LPTIM5)
#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR) || \
((SOURCE) == LPTIM4_OUT_CLEAR) || ((SOURCE) == LPTIM5_OUT_CLEAR))
#else
#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR) || \
((SOURCE) == LPTIM2_OUT_CLEAR) || ((SOURCE) == LPTIM3_OUT_CLEAR))
#endif /* LPTIM4 LPTIM5 */
/**
* @}
*/
@ -739,6 +782,23 @@ typedef enum
#define __HAL_SYSCFG_BREAK_CM4_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM4L)
#endif /* DUAL_CORE */
#if !defined(SYSCFG_PMCR_BOOSTEN)
/** @brief Fast-mode Plus driving capability enable/disable macros
* @param __FASTMODEPLUS__ This parameter can be a value of :
* @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
* @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
* @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
* @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
*/
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
SET_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\
}while(0)
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
CLEAR_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\
}while(0)
#endif /* !SYSCFG_PMCR_BOOSTEN */
/**
* @}
*/
@ -935,11 +995,19 @@ uint32_t HAL_GetDEVID(void);
uint32_t HAL_GetUIDw0(void);
uint32_t HAL_GetUIDw1(void);
uint32_t HAL_GetUIDw2(void);
#if defined(SYSCFG_PMCR_EPIS_SEL)
void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface);
#endif /* SYSCFG_PMCR_EPIS_SEL */
void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState );
#if defined(SYSCFG_PMCR_BOOSTEN)
void HAL_SYSCFG_EnableBOOST(void);
void HAL_SYSCFG_DisableBOOST(void);
#endif /* SYSCFG_PMCR_BOOSTEN */
#if defined (SYSCFG_UR2_BOOT_ADD0) || defined (SYSCFG_UR2_BCM7_ADD0)
void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0*/
#if defined(DUAL_CORE)
void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
void HAL_SYSCFG_EnableCM7BOOT(void);
@ -953,6 +1021,9 @@ void HAL_SYSCFG_EnableIOSpeedOptimize(void);
void HAL_SYSCFG_DisableIOSpeedOptimize(void);
void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode);
void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
#if defined(SYSCFG_CCCR_NCC_MMC)
void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
#endif /* SYSCFG_CCCR_NCC_MMC */
void HAL_EnableDBGSleepMode(void);
void HAL_DisableDBGSleepMode(void);
void HAL_EnableDBGStopMode(void);

41
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc.c
View File

@ -500,7 +500,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemD1Clock / (100000UL * 2UL)));
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
@ -574,6 +574,13 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
/* - overrun Init.Overrun */
/* - discontinuous mode Init.DiscontinuousConvMode */
/* - discontinuous mode channel count Init.NbrOfDiscConversion */
#if defined(ADC_VER_V5_3)
tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
hadc->Init.Overrun |
hadc->Init.Resolution |
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode) );
#else
if((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution))
{
/* for STM32H7 silicon rev.B and above , ADC_CFGR_RES value for 8bits resolution is : b111 */
@ -590,6 +597,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode) );
}
#endif /* ADC_VER_V5_3 */
if (hadc->Init.DiscontinuousConvMode == ENABLE)
{
@ -2026,6 +2034,8 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui
ADC_IT_OVR is enabled. */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
/* Enable ADC DMA mode*/
LL_ADC_REG_SetDataTransferMode(hadc->Instance, (uint32_t)hadc->Init.ConversionDataManagement);
/* Start the DMA channel */
tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
@ -2675,11 +2685,13 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
{
assert_param(IS_ADC2_DIFF_CHANNEL(sConfig->Channel));
}
#if defined(ADC3)
/* ADC3 is not available on some STM32H7 products */
if (hadc->Instance == ADC3)
{
assert_param(IS_ADC3_DIFF_CHANNEL(sConfig->Channel));
}
#endif
}
/* Process locked */
@ -2804,7 +2816,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemD1Clock / (100000UL * 2UL)));
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
while(wait_loop_index != 0UL)
{
wait_loop_index--;
@ -3630,6 +3642,26 @@ void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc)
}
}
#if defined(ADC_VER_V5_3)
freq /= 2U;
if (freq <= 6250000UL)
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL);
}
else if(freq <= 12500000UL)
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0);
}
else if(freq <= 25000000UL)
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1);
}
else /* if(freq > 25000000UL) */
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
}
#else
if(HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */
{
if(freq > 20000000UL)
@ -3649,11 +3681,11 @@ void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc)
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL);
}
else if((freq > 6250000UL) && (freq <= 12500000UL))
else if(freq <= 12500000UL)
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0);
}
else if((freq > 12500000UL) && (freq <= 25000000UL))
else if(freq <= 25000000UL)
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1);
}
@ -3662,6 +3694,7 @@ void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc)
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
}
}
#endif /* ADC_VER_V5_3 */
}
/**

16
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc.h
View File

@ -618,6 +618,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, channel specific to ADC3. */
#define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
#define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
#if defined (LL_ADC_CHANNEL_DAC2CH1_ADC2)
#define ADC_CHANNEL_DAC2CH1_ADC2 (LL_ADC_CHANNEL_DAC2CH1_ADC2) /*!< ADC internal channel connected to DAC2 channel 1, channel specific to ADC2 */
#endif
/**
* @}
*/
@ -625,10 +628,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management
* @{
*/
#define ADC_CONVERSIONDATA_DR ((uint32_t)0x00000000) /*!< Regular Conversion data stored in DR register only */
#define ADC_CONVERSIONDATA_DFSDM ((uint32_t)ADC_CFGR_DMNGT_1) /*!< DFSDM mode selected */
#define ADC_CONVERSIONDATA_DMA_ONESHOT ((uint32_t)ADC_CFGR_DMNGT_0) /*!< DMA one shot mode selected */
#define ADC_CONVERSIONDATA_DMA_CIRCULAR ((uint32_t)(ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1)) /*!< DMA circular mode selected */
#define ADC_CONVERSIONDATA_DR (0x00000000UL) /*!< Regular Conversion data stored in DR register only */
#define ADC_CONVERSIONDATA_DFSDM (ADC_CFGR_DMNGT_1) /*!< DFSDM mode selected */
#define ADC_CONVERSIONDATA_DMA_ONESHOT (ADC_CFGR_DMNGT_0) /*!< DMA one shot mode selected */
#define ADC_CONVERSIONDATA_DMA_CIRCULAR (ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1) /*!< DMA circular mode selected */
/**
* @}
*/
@ -832,10 +835,15 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @param __HANDLE__: ADC handle
* @retval SET (clock mode is synchronous) or RESET (clock mode is asynchronous)
*/
#if defined (ADC3)
#define ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__) \
(((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2))? \
((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL) \
:((((ADC3_COMMON)->CCR) & ADC_CCR_CKMODE) != 0UL))
#else
#define ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__) ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL)
#endif
/**
* @brief Simultaneously clear and set specific bits of the handle State.

73
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc_ex.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc_ex.c
View File

@ -226,22 +226,35 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t Single
HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t* LinearCalib_Buffer)
{
uint32_t cnt;
HAL_StatusTypeDef tmp_hal_status;
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t temp_REG_IsConversionOngoing = 0UL;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Enable the ADC ADEN = 1 to be able to read the linear calibration factor */
tmp_hal_status = ADC_Enable(hadc);
if(LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
tmp_hal_status = ADC_Enable(hadc);
}
if (tmp_hal_status == HAL_OK)
{
for(cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL; cnt--)
if(LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
{
LL_ADC_REG_StopConversion(hadc->Instance);
temp_REG_IsConversionOngoing = 1UL;
}
for(cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL; cnt--)
{
LinearCalib_Buffer[cnt-1U]=LL_ADC_GetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT-cnt));
}
if(temp_REG_IsConversionOngoing != 0UL)
{
LL_ADC_REG_StartConversion(hadc->Instance);
}
}
return tmp_hal_status;
}
@ -310,6 +323,7 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc,
{
uint32_t cnt;
__IO uint32_t wait_loop_index = 0;
uint32_t temp_REG_IsConversionOngoing = 0UL;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -335,7 +349,7 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc,
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles. */
wait_loop_index = (ADC_STAB_DELAY_US * (SystemD1Clock / (1000000UL * 2UL)));
wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000UL * 2UL)));
while(wait_loop_index != 0UL)
{
wait_loop_index--;
@ -357,6 +371,8 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc,
return HAL_ERROR;
}
/* Enable the ADC peripheral */
if(LL_ADC_IsEnabled(hadc->Instance) == 0UL) /* Enable the ADC if it is disabled */
{
if (ADC_Enable(hadc) != HAL_OK)
{
return HAL_ERROR;
@ -369,10 +385,25 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc,
}
(void)ADC_Disable(hadc);
}
}else /* ADC is already enabled, so no need to enable it but need to stop conversion */
{
if(LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
{
LL_ADC_REG_StopConversion(hadc->Instance);
temp_REG_IsConversionOngoing = 1UL;
}
for(cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL ; cnt--)
{
LL_ADC_SetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT-cnt), LinearCalib_Buffer[cnt-1U]);
}
if(temp_REG_IsConversionOngoing != 0UL)
{
LL_ADC_REG_StartConversion(hadc->Instance);
}
}
return HAL_OK;
}
/**
* @brief Load the calibration factor from engi bytes
* @param hadc ADC handle
@ -381,18 +412,27 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc,
HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_FactorLoad(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t cnt;
uint32_t cnt, FactorOffset;
uint32_t LinearCalib_Buffer[ADC_LINEAR_CALIB_REG_COUNT];
/* Linearity calibration is retrieved from engi bytes
read values from registers and put them to the CALFACT2 register */
/* If needed linearity calibration can be done in runtime using
LL_ADC_GetCalibrationLinearFactor() */
if(hadc->Instance == ADC1)
{
FactorOffset = 0UL;
}else if(hadc->Instance == ADC2)
{
FactorOffset = 8UL;
}else /*Case ADC3*/
{
FactorOffset = 16UL;
}
for (cnt = 0UL; cnt < ADC_LINEAR_CALIB_REG_COUNT; cnt++)
{
LinearCalib_Buffer[cnt] = *(uint32_t*)(ADC_LINEAR_CALIB_REG_1_ADDR + cnt);
LinearCalib_Buffer[cnt] = *(uint32_t*)(ADC_LINEAR_CALIB_REG_1_ADDR + FactorOffset + cnt);
}
if (HAL_ADCEx_LinearCalibration_SetValue(hadc,(uint32_t*)LinearCalib_Buffer) != HAL_OK)
{
@ -402,7 +442,6 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_FactorLoad(ADC_HandleTypeDef *hadc
return tmp_hal_status;
}
/**
* @brief Enable ADC, start conversion of injected group.
* @note Interruptions enabled in this function: None.
@ -1792,10 +1831,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
{
assert_param(IS_ADC2_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
}
#if defined (ADC3)
if (hadc->Instance == ADC3)
{
assert_param(IS_ADC3_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
}
#endif
}
/* Process locked */
@ -2122,7 +2163,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemD1Clock / (100000UL * 2UL)));
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
while(wait_loop_index != 0UL)
{
wait_loop_index--;

80
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc_ex.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc_ex.h
View File

@ -455,7 +455,7 @@ typedef struct
* @note When multimode feature is not available, the macro always returns SET.
* @retval SET (ADC is independent) or RESET (ADC is not).
*/
#if defined (ADC3)
#define ADC_IS_INDEPENDENT(__HANDLE__) \
( ( ( ((__HANDLE__)->Instance) == ADC3) \
)? \
@ -463,6 +463,7 @@ typedef struct
: \
RESET \
)
#endif
/**
* @brief Set the selected injected Channel rank.
@ -576,6 +577,15 @@ typedef struct
* @param __OFFSET__: Value to be shifted
* @retval None
*/
#if defined(ADC_VER_V5_3)
#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
( \
((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
: \
((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
)
#else
#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
(((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \
? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
@ -585,6 +595,7 @@ typedef struct
: \
((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
)
#endif /* ADC_VER_V5_3 */
/**
* @brief Shift the AWD1 threshold in function of the selected ADC resolution.
@ -599,6 +610,15 @@ typedef struct
* @param __THRESHOLD__: Value to be shifted
* @retval None
*/
#if defined(ADC_VER_V5_3)
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
( \
((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
: \
((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
)
#else
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
(((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \
? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
@ -608,6 +628,7 @@ typedef struct
: \
((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
)
#endif /* ADC_VER_V5_3 */
/**
* @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.
@ -622,6 +643,15 @@ typedef struct
* @param __THRESHOLD__: Value to be shifted
* @retval None
*/
#if defined(ADC_VER_V5_3)
#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
( \
((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
: \
((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
)
#else
#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
(((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \
? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
@ -631,6 +661,7 @@ typedef struct
: \
((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
)
#endif /* ADC_VER_V5_3 */
/**
* @brief Clear Common Control Register.
* @param __HANDLE__ ADC handle.
@ -642,19 +673,21 @@ typedef struct
* @retval Common control register
*/
#define ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON)
#if defined (ADC3)
/**
* @brief Report common register to ADC3
* @param __HANDLE__: ADC handle
* @retval Common control register
*/
#define ADC3_COMMON_REGISTER(__HANDLE__) (ADC3_COMMON)
#endif
/**
* @brief Report Master Instance
* @param __HANDLE__: ADC handle
* @note return same instance if ADC of input handle is independent ADC
* @retval Master Instance
*/
#if defined (ADC3)
#define ADC_MASTER_REGISTER(__HANDLE__) \
( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \
)? \
@ -662,6 +695,9 @@ typedef struct
: \
(ADC1) \
)
#else
#define ADC_MASTER_REGISTER(__HANDLE__) ( (ADC1))
#endif
/**
* @brief Check whether or not dual regular conversions are enabled
@ -690,7 +726,7 @@ typedef struct
: \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
)
#if defined (ADC3)
/**
* @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master
* @param __HANDLE__: ADC handle
@ -703,12 +739,13 @@ typedef struct
: \
((ADC3_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
)
#endif
/**
* @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled
* @param __HANDLE__: ADC handle
* @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)
*/
#if defined (ADC3)
#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \
( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
)? \
@ -717,13 +754,23 @@ typedef struct
( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
#else
#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \
( ( ((__HANDLE__)->Instance == ADC1) \
)? \
SET \
: \
( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
#endif
/**
* @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled
* @param __HANDLE__: ADC handle
* @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)
*/
#if defined (ADC3)
#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \
( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
)? \
@ -732,6 +779,16 @@ typedef struct
( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
#else
#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \
( ( ((__HANDLE__)->Instance == ADC1) \
)? \
SET \
: \
( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
#endif
#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \
ADC_CCR_PRESC | \
@ -758,21 +815,33 @@ typedef struct
* @param __HANDLE__ ADC handle.
* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
*/
#if defined(ADC3)
#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC3)
#else
#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2)
#endif
/**
* @brief Verify the ADC instance connected to the battery voltage VBAT.
* @param __HANDLE__ ADC handle.
* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
*/
#if defined(ADC3)
#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC3)
#else
#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2)
#endif
/**
* @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
* @param __HANDLE__ ADC handle.
* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
*/
#if defined(ADC3)
#define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC3)
#else
#define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2)
#endif
/**
* @brief Verify the length of scheduled injected conversions group.
@ -1101,6 +1170,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc,
HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer);
HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_FactorLoad(ADC_HandleTypeDef *hadc);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);

0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cec.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cec.c
View File

0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cec.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cec.h
View File

95
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_comp.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_comp.c
View File

@ -335,14 +335,22 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
hcomp->Init.Mode );
/* Set parameters in COMP register */
/* Note: Update all bits except read-only, lock and enable bits */
/* Note: Update all bits except read-only, lock and enable bits */
#if defined (COMP_CFGRx_INP2SEL)
MODIFY_REG(hcomp->Instance->CFGR,
COMP_CFGRx_PWRMODE | COMP_CFGRx_INMSEL | COMP_CFGRx_INPSEL |
COMP_CFGRx_PWRMODE | COMP_CFGRx_INMSEL | COMP_CFGRx_INPSEL |
COMP_CFGRx_INP2SEL | COMP_CFGRx_WINMODE | COMP_CFGRx_POLARITY | COMP_CFGRx_HYST |
COMP_CFGRx_BLANKING | COMP_CFGRx_BRGEN | COMP_CFGRx_SCALEN,
tmp_csr
);
#else
MODIFY_REG(hcomp->Instance->CFGR,
COMP_CFGRx_PWRMODE | COMP_CFGRx_INMSEL | COMP_CFGRx_INPSEL |
COMP_CFGRx_WINMODE | COMP_CFGRx_POLARITY | COMP_CFGRx_HYST |
COMP_CFGRx_BLANKING | COMP_CFGRx_BRGEN | COMP_CFGRx_SCALEN,
tmp_csr
);
#endif
/* Set window mode */
/* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */
/* instances. Therefore, this function can update another COMP */
@ -364,7 +372,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles.*/
wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemD1Clock / (1000000UL * 2UL)));
wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000UL * 2UL)));
while(wait_loop_index != 0UL)
{
@ -398,40 +406,71 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
CLEAR_BIT(EXTI->FTSR1, exti_line);
}
#if !defined (DUAL_CORE)
#if !defined (CORE_CM4)
/* Clear COMP EXTI pending bit (if any) */
WRITE_REG(EXTI_D1->PR1, exti_line);
WRITE_REG(EXTI->PR1, exti_line);
/* Configure EXTI event mode */
if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL)
{
SET_BIT(EXTI_D1->EMR1, exti_line);
SET_BIT(EXTI->EMR1, exti_line);
}
else
{
CLEAR_BIT(EXTI_D1->EMR1, exti_line);
CLEAR_BIT(EXTI->EMR1, exti_line);
}
/* Configure EXTI interrupt mode */
if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL)
{
SET_BIT(EXTI_D1->IMR1, exti_line);
SET_BIT(EXTI->IMR1, exti_line);
}
else
{
CLEAR_BIT(EXTI_D1->IMR1, exti_line);
CLEAR_BIT(EXTI->IMR1, exti_line);
}
}
else
{
/* Disable EXTI event mode */
CLEAR_BIT(EXTI_D1->EMR1, exti_line);
CLEAR_BIT(EXTI->EMR1, exti_line);
/* Disable EXTI interrupt mode */
CLEAR_BIT(EXTI_D1->IMR1, exti_line);
#endif
CLEAR_BIT(EXTI->IMR1, exti_line);
}
#else
/* Clear COMP EXTI pending bit (if any) */
WRITE_REG(EXTI->C2PR1, exti_line);
/* Configure EXTI event mode */
if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL)
{
SET_BIT(EXTI->C2EMR1, exti_line);
}
else
{
CLEAR_BIT(EXTI->C2EMR1, exti_line);
}
/* Configure EXTI interrupt mode */
if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL)
{
SET_BIT(EXTI->C2IMR1, exti_line);
}
else
{
CLEAR_BIT(EXTI->C2IMR1, exti_line);
}
}
else
{
/* Disable EXTI event mode */
CLEAR_BIT(EXTI->C2EMR1, exti_line);
/* Disable EXTI interrupt mode */
CLEAR_BIT(EXTI->C2IMR1, exti_line);
}
#endif
/* Set HAL COMP handle state */
/* Note: Transition from state reset to state ready, */
/* otherwise (coming from state ready or busy) no state update. */
@ -743,7 +782,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles. */
wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemD1Clock / (1000000UL * 2UL)));
wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000UL * 2UL)));
while(wait_loop_index != 0UL)
{
wait_loop_index--;
@ -840,7 +879,7 @@ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles. */
wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemD1Clock / (1000000UL * 2UL)));
wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000UL * 2UL)));
while(wait_loop_index != 0UL)
{
wait_loop_index--;
@ -864,9 +903,11 @@ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp)
{
HAL_StatusTypeDef status;
#if !defined (DUAL_CORE)
/* Disable the EXTI Line interrupt mode */
CLEAR_BIT(EXTI_D1->IMR1, COMP_GET_EXTI_LINE(hcomp->Instance));
#if !defined (CORE_CM4)
CLEAR_BIT(EXTI->IMR1, COMP_GET_EXTI_LINE(hcomp->Instance));
#else
CLEAR_BIT(EXTI->C2IMR1, COMP_GET_EXTI_LINE(hcomp->Instance));
#endif
/* Disable the Interrupt comparator */
CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_ITEN);
@ -893,7 +934,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* Check COMP EXTI flag */
if(READ_BIT(EXTI_D1->PR1, exti_line) != 0UL)
if(READ_BIT(EXTI->PR1, exti_line) != 0UL)
{
/* Check whether comparator is in independent or window mode */
if(READ_BIT(COMP12_COMMON->CFGR, COMP_CFGRx_WINMODE) != 0UL)
@ -905,12 +946,12 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
/* (low or high ) to the other "out of window" area (high or low).*/
/* Both flags must be cleared to call comparator trigger */
/* callback is called once. */
WRITE_REG(EXTI_D1->PR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
WRITE_REG(EXTI->PR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
}
else
{
/* Clear COMP EXTI line pending bit */
WRITE_REG(EXTI_D1->PR1, exti_line);
WRITE_REG(EXTI->PR1, exti_line);
}
/* COMP trigger user callback */
@ -926,7 +967,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
else
{
/* Check COMP EXTI flag */
if(READ_BIT(EXTI_D2->PR1, exti_line) != 0UL)
if(READ_BIT(EXTI->C2PR1, exti_line) != 0UL)
{
/* Check whether comparator is in independent or window mode */
if(READ_BIT(COMP12_COMMON->CFGR, COMP_CFGRx_WINMODE) != 0UL)
@ -938,12 +979,12 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
/* (low or high ) to the other "out of window" area (high or low).*/
/* Both flags must be cleared to call comparator trigger */
/* callback is called once. */
WRITE_REG(EXTI_D2->PR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
WRITE_REG(EXTI->C2PR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
}
else
{
/* Clear COMP EXTI line pending bit */
WRITE_REG(EXTI_D2->PR1, exti_line);
WRITE_REG(EXTI->C2PR1, exti_line);
}
/* COMP trigger user callback */
@ -958,7 +999,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
}
#else
/* Check COMP EXTI flag */
if(READ_BIT(EXTI_D1->PR1, exti_line) != 0UL)
if(READ_BIT(EXTI->PR1, exti_line) != 0UL)
{
/* Check whether comparator is in independent or window mode */
if(READ_BIT(COMP12_COMMON->CFGR, COMP_CFGRx_WINMODE) != 0UL)
@ -970,12 +1011,12 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
/* (low or high ) to the other "out of window" area (high or low).*/
/* Both flags must be cleared to call comparator trigger */
/* callback is called once. */
WRITE_REG(EXTI_D1->PR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
WRITE_REG(EXTI->PR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
}
else
{
/* Clear COMP EXTI line pending bit */
WRITE_REG(EXTI_D1->PR1, exti_line);
WRITE_REG(EXTI->PR1, exti_line);
}
/* COMP trigger user callback */

71
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_comp.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_comp.h
View File

@ -178,6 +178,9 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
*/
#define COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000) /*!< Comparator input plus connected to IO1 (pin PB0 for COMP1, pin PE9 for COMP2) */
#define COMP_INPUT_PLUS_IO2 (COMP_CFGRx_INPSEL) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PE11 for COMP2) */
#if defined (COMP_CFGRx_INP2SEL)
#define COMP_INPUT_PLUS_DAC2_CH1 (COMP_CFGRx_INP2SEL) /*!< Comparator input plus 2 connected to (DAC2_CH1 for COMP1) */
#endif
/**
* @}
*/
@ -185,14 +188,18 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/** @defgroup COMP_InputMinus COMP input minus (inverting input)
* @{
*/
#define COMP_INPUT_MINUS_1_4VREFINT ( COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN) /*!< Comparator input minus connected to 1/4 VrefInt */
#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN) /*!< Comparator input minus connected to 1/2 VrefInt */
#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */
#define COMP_INPUT_MINUS_VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN ) /*!< Comparator input minus connected to VrefInt */
#define COMP_INPUT_MINUS_DAC1_CH1 (COMP_CFGRx_INMSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
#define COMP_INPUT_MINUS_DAC1_CH2 (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
#define COMP_INPUT_MINUS_IO1 (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PE10 for COMP2) */
#define COMP_INPUT_MINUS_IO2 (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PE7 for COMP2) */
#define COMP_INPUT_MINUS_1_4VREFINT ( COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN) /*!< Comparator input minus connected to 1/4 VrefInt */
#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN) /*!< Comparator input minus connected to 1/2 VrefInt */
#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */
#define COMP_INPUT_MINUS_VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN ) /*!< Comparator input minus connected to VrefInt */
#define COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CFGRx_INMSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
#define COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_0 ) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
#define COMP_INPUT_MINUS_IO1 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PE10 for COMP2) */
#define COMP_INPUT_MINUS_IO2 ( COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 ) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PE7 for COMP2) */
#if defined (COMP_CFGRx_INMSEL_3)
#define COMP_INPUT_MINUS_TPSENS_DAC2CH1 (COMP_CFGRx_INMSEL_3 ) /*!< Comparator input minus connected to (temp sensor which is exist in ADC for COMP1, DAC2_CH1 for COMP2) */
#define COMP_INPUT_MINUS_VBAT_VDDAP (COMP_CFGRx_INMSEL_3 | COMP_CFGRx_INMSEL_0 ) /*!< Comparator input minus connected to (VBAT/4 for COMP1, VDDAP for COMP2) */
#endif
/**
* @}
*/
@ -212,7 +219,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @{
*/
#define COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
#define COMP_OUTPUTPOL_INVERTED (COMP_CFGRx_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */
#define COMP_OUTPUTPOL_INVERTED (COMP_CFGRx_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */
/**
* @}
*/
@ -314,7 +321,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @retval None
*/
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_COMP_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
@ -400,8 +407,8 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @brief Enable the COMP1 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
__HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
@ -410,8 +417,8 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @brief Disable the COMP1 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
__HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
@ -536,8 +543,8 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @brief Enable the COMP2 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
@ -545,8 +552,8 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @brief Disable the COMP2 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
@ -800,12 +807,28 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) || \
((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER) )
#if defined (COMP_CFGRx_INP2SEL)
#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \
((__INPUT_PLUS__) == COMP_INPUT_PLUS_DAC2_CH1))
#else
#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))
#endif
#if defined (COMP_CFGRx_INMSEL_3)
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_TPSENS_DAC2CH1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_VBAT_VDDAP))
#else
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
@ -813,8 +836,8 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2))
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2))
#endif
#define IS_COMP_HYSTERESIS(__HYSTERESIS__) (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE) || \
((__HYSTERESIS__) == COMP_HYSTERESIS_LOW) || \
@ -824,7 +847,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
#define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
((__POL__) == COMP_OUTPUTPOL_INVERTED))
#define IS_COMP_BLANKINGSRCE(__SOURCE__) (((__SOURCE__) == COMP_BLANKINGSRC_NONE) || \
#define IS_COMP_BLANKINGSRCE(__SOURCE__) (((__SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5) || \
((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3) || \
((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3) || \

0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cortex.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cortex.c
View File

0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cortex.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cortex.h
View File

0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_crc.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc.c
View File

1
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_crc.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc.h
View File

@ -267,7 +267,6 @@ typedef struct
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))

0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_crc_ex.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc_ex.c
View File

0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_crc_ex.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc_ex.h
View File

540
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cryp.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.c
View File

@ -65,7 +65,13 @@
new parametres, finally user can start encryption/decryption.
(#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
(#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
without having to configure again the Key or the Initialization Vector between each API call,
the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA()
or HAL_CRYP_Decrypt_DMA().
[..]
The cryptographic processor supports following standards:
(#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP:
@ -415,6 +421,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip));
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
if (hcryp->State == HAL_CRYP_STATE_RESET)
@ -455,6 +462,9 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
/* Reset Error Code field */
hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
/* Reset peripheral Key and IV configuration flag */
hcryp->KeyIVConfig = 0U;
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
@ -1393,8 +1403,9 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input
*/
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
{
uint32_t algo;
HAL_StatusTypeDef status = HAL_OK;
uint32_t algo;
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->State == HAL_CRYP_STATE_READY)
{
@ -1466,18 +1477,38 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu
case CRYP_AES_CBC:
case CRYP_AES_CTR:
/* Set the Key*/
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
/* Set the Initialization Vector IV */
if (hcryp->Init.Algorithm != CRYP_AES_ECB)
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
DoKeyIVConfig = 0U;
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
}
}
if (DoKeyIVConfig == 1U)
{
/* Set the Key*/
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
/* Set the Initialization Vector*/
if (hcryp->Init.Algorithm != CRYP_AES_ECB)
{
hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
}
} /* if (DoKeyIVConfig == 1U) */
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
@ -1955,19 +1986,40 @@ static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint16_t outcount; /* Temporary CrypOutCount Value */
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
/* Set the Key*/
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
if (hcryp->Init.Algorithm != CRYP_AES_ECB)
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
/* Set the Initialization Vector*/
hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
DoKeyIVConfig = 0U;
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
}
}
if (DoKeyIVConfig == 1U)
{
/* Set the Key*/
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
if (hcryp->Init.Algorithm != CRYP_AES_ECB)
{
/* Set the Initialization Vector*/
hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
}
} /* if (DoKeyIVConfig == 1U) */
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
@ -2002,18 +2054,40 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti
*/
static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
{
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
/* Set the Key*/
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
if (hcryp->Init.Algorithm != CRYP_AES_ECB)
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
/* Set the Initialization Vector*/
hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
DoKeyIVConfig = 0U;
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
}
}
if (DoKeyIVConfig == 1U)
{
/* Set the Key*/
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
if (hcryp->Init.Algorithm != CRYP_AES_ECB)
{
/* Set the Initialization Vector*/
hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
}
} /* if (DoKeyIVConfig == 1U) */
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
@ -2047,7 +2121,27 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint16_t outcount; /* Temporary CrypOutCount Value */
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
DoKeyIVConfig = 0U;
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
}
}
if (DoKeyIVConfig == 1U)
{
/* Key preparation for ECB/CBC */
if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/
{
@ -2092,6 +2186,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti
hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
}
} /* if (DoKeyIVConfig == 1U) */
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
@ -2127,7 +2223,27 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti
static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
{
__IO uint32_t count = 0U;
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
DoKeyIVConfig = 0U;
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
}
}
if (DoKeyIVConfig == 1U)
{
/* Key preparation for ECB/CBC */
if (hcryp->Init.Algorithm != CRYP_AES_CTR)
{
@ -2175,6 +2291,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
}
} /* if (DoKeyIVConfig == 1U) */
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
if (hcryp->Size != 0U)
@ -2205,7 +2323,27 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
{
__IO uint32_t count = 0U;
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
DoKeyIVConfig = 0U;
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
}
}
if (DoKeyIVConfig == 1U)
{
/* Key preparation for ECB/CBC */
if (hcryp->Init.Algorithm != CRYP_AES_CTR)
{
@ -2255,6 +2393,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
}
} /* if (DoKeyIVConfig == 1U) */
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
@ -2313,8 +2453,8 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
uint32_t temp; /* Temporary CrypOutBuff */
uint32_t temp_cr_algodir;
CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable the DMA transfer for output FIFO */
hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
@ -2332,17 +2472,17 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
if (hcryp->Version >= REV_ID_B)
#endif /*End of not defined CRYP_VER_2_2*/
{
/* Case of AES GCM payload encryption or AES CCM payload decryption to get right tag */
/* Case of AES GCM payload encryption or AES CCM payload decryption to get right tag */
temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR;
if (((temp_cr_algodir == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
((temp_cr_algodir == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
{
/* Disable the CRYP */
__HAL_CRYP_DISABLE(hcryp);
/* Specify the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
/* Enable CRYP to start the final phase */
__HAL_CRYP_ENABLE(hcryp);
}
@ -2524,9 +2664,10 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin
static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t temp; /* Temporary CrypOutBuff */
uint32_t temp[4]; /* Temporary CrypOutBuff */
uint16_t incount; /* Temporary CrypInCount Value */
uint16_t outcount; /* Temporary CrypOutCount Value */
uint32_t i;
/*Temporary CrypOutCount Value*/
incount = hcryp->CrypInCount;
@ -2570,18 +2711,17 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < ((hcryp->Size) / 4U)))
{
/* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
temp = hcryp->Instance->DOUT;
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
hcryp->CrypOutCount++;
temp = hcryp->Instance->DOUT;
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
hcryp->CrypOutCount++;
temp = hcryp->Instance->DOUT;
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
hcryp->CrypOutCount++;
temp = hcryp->Instance->DOUT;
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
hcryp->CrypOutCount++;
for (i = 0U; i < 4U; i++)
{
temp[i] = hcryp->Instance->DOUT;
}
i = 0U;
while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U))
{
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
hcryp->CrypOutCount++;
i++;
}
}
}
@ -2595,9 +2735,10 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
*/
static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
{
uint32_t temp; /* Temporary CrypOutBuff */
uint32_t temp[4]; /* Temporary CrypOutBuff */
uint16_t incount; /* Temporary CrypInCount Value */
uint16_t outcount; /* Temporary CrypOutCount Value */
uint32_t i;
if (hcryp->State == HAL_CRYP_STATE_BUSY)
{
@ -2637,18 +2778,17 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
temp = hcryp->Instance->DOUT;
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
hcryp->CrypOutCount++;
temp = hcryp->Instance->DOUT;
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
hcryp->CrypOutCount++;
temp = hcryp->Instance->DOUT;
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
hcryp->CrypOutCount++;
temp = hcryp->Instance->DOUT;
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
hcryp->CrypOutCount++;
for (i = 0U; i < 4U; i++)
{
temp[i] = hcryp->Instance->DOUT;
}
i = 0U;
while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U))
{
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
hcryp->CrypOutCount++;
i++;
}
if (hcryp->CrypOutCount == (hcryp->Size / 4U))
{
/* Disable interrupts */
@ -2743,11 +2883,37 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
uint32_t tickstart;
uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
uint32_t npblb ;
uint32_t temp ; /* Temporary CrypOutBuff */
uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t index ;
uint32_t lastwordsize ;
uint16_t outcount; /* Temporary CrypOutCount Value */
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
DoKeyIVConfig = 0U;
hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
}
}
else
{
hcryp->SizesSum = hcryp->Size;
}
if (DoKeyIVConfig == 1U)
{
/* Reset CrypHeaderCount */
hcryp->CrypHeaderCount = 0U;
@ -2820,7 +2986,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
} /* if (DoKeyIVConfig == 1U) */
if ((hcryp->Size % 16U) != 0U)
{
/* recalculate wordsize */
@ -2933,9 +3100,11 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
for (index = 0U; index < 4U; index++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
temp = hcryp->Instance->DOUT;
*(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
temp[index] = hcryp->Instance->DOUT;
}
for (index=0; index<lastwordsize; index++)
{
*(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index];
hcryp->CrypOutCount++;
}
}
@ -2950,7 +3119,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
#endif /*End of not defined CRYP_VER_2_2*/
}
/* Return function status */
return HAL_OK;
}
@ -2964,7 +3132,34 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
{
__IO uint32_t count = 0U;
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
DoKeyIVConfig = 0U;
hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
}
}
else
{
hcryp->SizesSum = hcryp->Size;
}
/* Configure Key, IV and process message (header and payload) */
if (DoKeyIVConfig == 1U)
{
/* Reset CrypHeaderCount */
hcryp->CrypHeaderCount = 0U;
@ -3008,7 +3203,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
/* Select header phase */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
} /* end of if (DoKeyIVConfig == 1U) */
/* Enable interrupts */
__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
@ -3033,8 +3228,35 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
uint32_t index;
uint32_t npblb;
uint32_t lastwordsize;
uint32_t temp; /* Temporary CrypOutBuff */
/* Reset CrypHeaderCount */
uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
DoKeyIVConfig = 0U;
hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
}
}
else
{
hcryp->SizesSum = hcryp->Size;
}
if (DoKeyIVConfig == 1U)
{
/* Reset CrypHeaderCount */
hcryp->CrypHeaderCount = 0U;
/*************************** Init phase ************************************/
@ -3099,6 +3321,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
/* Select payload phase once the header phase is performed */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
} /* if (DoKeyIVConfig == 1U) */
if (hcryp->Size == 0U)
{
/* Process unLocked */
@ -3191,11 +3415,14 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
for (index = 0U; index < 4U; index++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
temp = hcryp->Instance->DOUT;
*(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
temp[index] = hcryp->Instance->DOUT;
}
for (index=0; index<lastwordsize; index++)
{
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
hcryp->CrypOutCount++;
}
/* Change the CRYP state to ready */
hcryp->State = HAL_CRYP_STATE_READY;
@ -3221,10 +3448,36 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
uint32_t npblb ;
uint32_t lastwordsize ;
uint32_t temp ; /* Temporary CrypOutBuff */
uint32_t temp[4] ; /* Temporary CrypOutBuff */
uint32_t index ;
uint16_t outcount; /* Temporary CrypOutCount Value */
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
DoKeyIVConfig = 0U;
hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
}
}
else
{
hcryp->SizesSum = hcryp->Size;
}
if (DoKeyIVConfig == 1U)
{
/* Reset CrypHeaderCount */
hcryp->CrypHeaderCount = 0U;
@ -3347,6 +3600,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
} /* if (DoKeyIVConfig == 1U) */
if ((hcryp->Size % 16U) != 0U)
{
/* recalculate wordsize */
@ -3458,11 +3713,13 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
for (index = 0U; index < 4U; index++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
temp = hcryp->Instance->DOUT;
*(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
hcryp->CrypOutCount++;
temp[index] = hcryp->Instance->DOUT;
}
for (index=0; index<lastwordsize; index++)
{
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
hcryp->CrypOutCount++;
}
}
}
#if !defined (CRYP_VER_2_2)
@ -3489,7 +3746,34 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
{
__IO uint32_t count = 0U;
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
DoKeyIVConfig = 0U;
hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
}
}
else
{
hcryp->SizesSum = hcryp->Size;
}
/* Configure Key, IV and process message (header and payload) */
if (DoKeyIVConfig == 1U)
{
/* Reset CrypHeaderCount */
hcryp->CrypHeaderCount = 0U;
@ -3575,7 +3859,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
/* Select header phase */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
} /* end of if (DoKeyIVConfig == 1U) */
/* Enable interrupts */
__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
@ -3598,8 +3882,34 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
uint32_t index;
uint32_t npblb;
uint32_t lastwordsize;
uint32_t temp; /* Temporary CrypOutBuff */
uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
DoKeyIVConfig = 0U;
hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
}
}
else
{
hcryp->SizesSum = hcryp->Size;
}
if (DoKeyIVConfig == 1U)
{
/* Reset CrypHeaderCount */
hcryp->CrypHeaderCount = 0U;
@ -3707,6 +4017,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
/* Select payload phase once the header phase is performed */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
} /* if (DoKeyIVConfig == 1U) */
if (hcryp->Size == 0U)
{
@ -3798,11 +4109,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
for (index = 0U; index < 4U; index++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
temp = hcryp->Instance->DOUT;
*(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
temp[index] = hcryp->Instance->DOUT;
}
for (index=0; index<lastwordsize; index++)
{
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
hcryp->CrypOutCount++;
}
/* Change the CRYP state to ready */
hcryp->State = HAL_CRYP_STATE_READY;
@ -3815,7 +4129,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
}
/**
* @brief Sets the payload phase in iterrupt mode
* @brief Sets the payload phase in interrupt mode
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval state
@ -3823,11 +4137,12 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
{
uint32_t loopcounter;
uint32_t temp; /* Temporary CrypOutBuff */
uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t lastwordsize;
uint32_t npblb;
uint32_t temp_cr_algodir;
uint8_t negative = 0U;
uint32_t i;
/***************************** Payload phase *******************************/
@ -3866,7 +4181,6 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
{
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the input data transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
@ -3882,23 +4196,22 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
{
/* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
temp = hcryp->Instance->DOUT;
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
hcryp->CrypOutCount++;
temp = hcryp->Instance->DOUT;
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
hcryp->CrypOutCount++;
temp = hcryp->Instance->DOUT;
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
hcryp->CrypOutCount++;
temp = hcryp->Instance->DOUT;
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
hcryp->CrypOutCount++;
for (i = 0U; i < 4U; i++)
{
temp[i] = hcryp->Instance->DOUT;
}
i = 0U;
while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U))
{
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
hcryp->CrypOutCount++;
i++;
}
if (((hcryp->Size / 4U) == hcryp->CrypOutCount) && ((hcryp->Size % 16U) == 0U))
{
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
@ -3935,16 +4248,16 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
{
/* Set Npblb in case of AES GCM payload encryption and CCM decryption to get right tag */
temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR;
if (((temp_cr_algodir == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
((temp_cr_algodir == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
{
/* Disable the CRYP */
__HAL_CRYP_DISABLE(hcryp);
/* Specify the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
/* Enable CRYP to start the final phase */
__HAL_CRYP_ENABLE(hcryp);
}
@ -3980,18 +4293,29 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
/*Read the output block from the output FIFO */
if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
{
for (loopcounter = 0U; loopcounter < 4U; loopcounter++)
for (i = 0U; i < 4U; i++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
temp = hcryp->Instance->DOUT;
*(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
temp[i] = hcryp->Instance->DOUT;
}
if (( (hcryp->Size)/4U)==0U)
{
for (i = 0U; (uint16_t)i<((hcryp->Size)%4U); i++)
{
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
hcryp->CrypOutCount++;
}
}
i = 0U;
while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U))
{
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
hcryp->CrypOutCount++;
i++;
}
}
/* Disable the output FIFO Interrupt */
if (hcryp->CrypOutCount > ((hcryp->Size) / 4U))
if (hcryp->CrypOutCount >= ((hcryp->Size) / 4U))
{
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI | CRYP_IT_INI);
@ -4591,7 +4915,7 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
__HAL_CRYP_ENABLE(hcryp);
}
/* Last block optionally pad the data with zeros*/
for (index = 0; index < lastwordsize; index ++)
for (index = 0U; index < lastwordsize; index ++)
{
/* Write the last Input block in the IN FIFO */
hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);

23
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cryp.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.h
View File

@ -64,6 +64,9 @@ typedef struct
uint32_t HeaderSize; /*!< The size of header buffer in word */
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
Vector only once and to skip configuration for consecutive processings.
This parameter can be a value of @ref CRYP_Configuration_Skip */
} CRYP_ConfigTypeDef;
@ -121,6 +124,13 @@ typedef struct
uint32_t Version; /*!< CRYP1 IP version*/
uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when
configuration can be skipped */
uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored
for a single signature computation after several
messages processing */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */
void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */
@ -279,6 +289,16 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
* @}
*/
/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
* @{
*/
#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */
#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */
/**
* @}
*/
/**
* @}
@ -461,6 +481,9 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
((DATATYPE) == CRYP_DATATYPE_8B) || \
((DATATYPE) == CRYP_DATATYPE_1B))
#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
/**
* @}
*/

2
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cryp_ex.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp_ex.c
View File

@ -110,7 +110,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
{
uint32_t tickstart;
uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */
uint64_t inputlength = (uint64_t)(hcryp->Size) * 8U; /* input length in bits */
uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */
uint32_t tagaddr = (uint32_t)AuthTag;
if (hcryp->State == HAL_CRYP_STATE_READY)

0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cryp_ex.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp_ex.h
View File

942
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dac.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac.c
View File

File diff suppressed because it is too large Load Diff

395
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dac.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac.h
View File

@ -16,23 +16,24 @@
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7xx_HAL_DAC_H
#define STM32H7xx_HAL_DAC_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
#if defined(DAC1) || defined(DAC2)
/** @addtogroup DAC
* @{
*/
@ -43,9 +44,9 @@
* @{
*/
/**
* @brief HAL State structures definition
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
@ -53,11 +54,11 @@ typedef enum
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
}HAL_DAC_StateTypeDef;
/**
* @brief DAC handle Structure definition
} HAL_DAC_StateTypeDef;
/**
* @brief DAC handle Structure definition
*/
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
typedef struct __DAC_HandleTypeDef
@ -66,80 +67,79 @@ typedef struct
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
{
DAC_TypeDef *Instance; /*!< Register base address */
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
HAL_LockTypeDef Lock; /*!< DAC locking object */
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
__IO uint32_t ErrorCode; /*!< DAC Error code */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
__IO uint32_t ErrorCode; /*!< DAC Error code */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}DAC_HandleTypeDef;
} DAC_HandleTypeDef;
/**
* @brief DAC Configuration sample and hold Channel structure definition
*/
/**
* @brief DAC Configuration sample and hold Channel structure definition
*/
typedef struct
{
uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel.
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
}
DAC_SampleAndHoldConfTypeDef;
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
/**
* @brief DAC Configuration regular Channel structure definition
*/
uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
} DAC_SampleAndHoldConfTypeDef;
/**
* @brief DAC Configuration regular Channel structure definition
*/
typedef struct
{
uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode.
This parameter can be a value of @ref DAC_SampleAndHold */
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection */
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode
This parameter must be a value of @ref DAC_UserTrimming
uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode
This parameter must be a value of @ref DAC_UserTrimming
DAC_UserTrimming is either factory or user trimming */
uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value
i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value
i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */
}DAC_ChannelConfTypeDef;
DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */
} DAC_ChannelConfTypeDef;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/**
@ -155,8 +155,8 @@ typedef enum
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
HAL_DAC_MSP_INIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
HAL_DAC_MSP_DEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
} HAL_DAC_CallbackIDTypeDef;
@ -187,6 +187,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
@ -194,40 +195,93 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
/** @defgroup DAC_trigger_selection DAC trigger selection
* @{
*/
#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
#define DAC_TRIGGER_SOFTWARE (DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
#define DAC_TRIGGER_T1_TRGO (DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T4_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T5_TRGO (DAC_CR_TSEL1_2 |DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T6_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T7_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T8_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_HR1_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_HR1_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LP1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LP1 OUT TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LP2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LP2 OUT TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
#define DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
#define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
#if defined(HRTIM1)
#define DAC_TRIGGER_HR1_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_HR1_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel */
#endif
#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#if defined(TIM23)
#define DAC_TRIGGER_T23_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM23 TRGO selected as external conversion trigger for DAC channel */
#endif
#if defined(TIM24)
#define DAC_TRIGGER_T24_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM24 TRGO selected as external conversion trigger for DAC channel */
#endif
#if defined(DAC2)
#define DAC_TRIGGER_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< LPTIM3 OUT TRGO selected as external conversion trigger for DAC channel */
#endif
/**
* @}
*/
/** @defgroup DAC_output_buffer DAC output buffer
/** @defgroup DAC_output_buffer DAC output buffer
* @{
*/
#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
#define DAC_OUTPUTBUFFER_DISABLE DAC_MCR_MODE1_1
#define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1)
/**
/**
* @}
*/
/** @defgroup DAC_Channel_selection DAC Channel selection
* @{
*/
#define DAC_CHANNEL_1 0x00000000U
#define DAC_CHANNEL_2 0x00000010U
/**
* @}
*/
/** @defgroup DAC_data_alignment DAC data alignment
* @{
*/
#define DAC_ALIGN_12B_R 0x00000000U
#define DAC_ALIGN_12B_L 0x00000004U
#define DAC_ALIGN_8B_R 0x00000008U
/**
* @}
*/
/** @defgroup DAC_flags_definition DAC flags definition
* @{
*/
#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
/**
* @}
*/
/** @defgroup DAC_IT_definition DAC IT definition
* @{
*/
#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
/**
* @}
*/
/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
* @{
*/
#define DAC_CHIPCONNECT_DISABLE 0x00000000U
#define DAC_CHIPCONNECT_ENABLE DAC_MCR_MODE1_0
#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0)
#define DAC_CHIPCONNECT_INTERNAL (1UL << 1)
#define DAC_CHIPCONNECT_BOTH (1UL << 2)
/**
* @}
@ -236,66 +290,21 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
/** @defgroup DAC_UserTrimming DAC User Trimming
* @{
*/
#define DAC_TRIMMING_FACTORY 0x00000000U /*!< Factory trimming */
#define DAC_TRIMMING_USER 0x00000001U /*!< User trimming */
#define DAC_TRIMMING_FACTORY (0x00000000UL) /*!< Factory trimming */
#define DAC_TRIMMING_USER (0x00000001UL) /*!< User trimming */
/**
* @}
*/
*/
/** @defgroup DAC_SampleAndHold DAC Sample and hold
/** @defgroup DAC_SampleAndHold DAC power mode
* @{
*/
#define DAC_SAMPLEANDHOLD_DISABLE 0x00000000U
#define DAC_SAMPLEANDHOLD_ENABLE DAC_MCR_MODE1_2
#define DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL)
#define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2)
/**
* @}
*/
/** @defgroup DAC_Channel_selection DAC Channel selection
* @{
*/
#define DAC_CHANNEL_1 0x00000000U
#define DAC_CHANNEL_2 0x00000010U
/**
* @}
*/
/** @defgroup DAC_data_alignment DAC data alignment
* @{
*/
#define DAC_ALIGN_12B_R 0x00000000U
#define DAC_ALIGN_12B_L 0x00000004U
#define DAC_ALIGN_8B_R 0x00000008U
/**
* @}
*/
/** @defgroup DAC_flags_definition DAC flags definition
* @{
*/
#define DAC_FLAG_DMAUDR1 DAC_SR_DMAUDR1
#define DAC_FLAG_DMAUDR2 DAC_SR_DMAUDR2
/**
* @}
*/
/** @defgroup DAC_IT_definition DAC IT definition
* @{
*/
#define DAC_IT_DMAUDR1 DAC_SR_DMAUDR1
#define DAC_IT_DMAUDR2 DAC_SR_DMAUDR2
/**
* @}
*/
/**
* @}
*/
@ -313,8 +322,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_DAC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
@ -326,7 +335,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
* @retval None
*/
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
/** @brief Disable the DAC channel.
* @param __HANDLE__ specifies the DAC handle
@ -334,32 +343,32 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
* @retval None
*/
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
/** @brief Set DHR12R1 alignment.
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__))
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
/** @brief Set DHR12R2 alignment.
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014U + (__ALIGNMENT__))
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
/** @brief Set DHR12RD alignment.
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__))
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
/** @brief Enable the DAC interrupt.
* @param __HANDLE__ specifies the DAC handle
* @param __INTERRUPT__ specifies the DAC interrupt.
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
* @retval None
*/
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
@ -368,8 +377,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
* @param __HANDLE__ specifies the DAC handle
* @param __INTERRUPT__ specifies the DAC interrupt.
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
* @retval None
*/
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
@ -378,8 +387,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
* @param __HANDLE__ DAC handle
* @param __INTERRUPT__ DAC interrupt source to check
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
* @retval State of interruption (SET or RESET)
*/
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
@ -388,8 +397,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
* @param __HANDLE__ specifies the DAC handle.
* @param __FLAG__ specifies the DAC flag to get.
* This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
* @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
* @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
* @retval None
*/
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
@ -398,8 +407,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
* @param __HANDLE__ specifies the DAC handle.
* @param __FLAG__ specifies the DAC flag to clear.
* This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
* @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
* @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
* @retval None
*/
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
@ -417,24 +426,24 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
((CHANNEL) == DAC_CHANNEL_2))
((CHANNEL) == DAC_CHANNEL_2))
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
((ALIGN) == DAC_ALIGN_12B_L) || \
((ALIGN) == DAC_ALIGN_8B_R))
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFU)
#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL)
/**
* @}
* @}
*/
/* Include DAC HAL Extended module */
#include "stm32h7xx_hal_dac_ex.h"
#include "stm32h7xx_hal_dac_ex.h"
/* Exported functions --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DAC_Exported_Functions
* @{
@ -442,56 +451,60 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
/** @addtogroup DAC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group2
* @{
*/
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* DAC callback registering/unregistering */
HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackId, pDAC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackId);
HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
pDAC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group3
* @{
*/
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group4
* @{
*/
*/
/* Peripheral State and Error functions ***************************************/
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
/**
@ -502,18 +515,30 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
* @}
*/
/** @defgroup DAC_Private_Functions DAC Private Functions
* @{
*/
void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
#endif /* DAC1 || DAC2 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
#endif /*STM32H7xx_HAL_DAC_H */

618
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dac_ex.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac_ex.c
View File

@ -3,28 +3,48 @@
* @file stm32h7xx_hal_dac_ex.c
* @author MCD Application Team
* @brief Extended DAC HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of DAC peripheral.
*
* This file provides firmware functions to manage the extended
* functionalities of the DAC peripheral.
*
@verbatim
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
[..]
*** Dual mode IO operation ***
==============================
(+) Use HAL_DACEx_DualStart() to enable both channel and start conversion
for dual mode operation.
If software trigger is selected, using HAL_DACEx_DualStart() will start
the conversion of the value previously set by HAL_DACEx_DualSetValue().
(+) Use HAL_DACEx_DualStop() to disable both channel and stop conversion
for dual mode operation.
(+) Use HAL_DACEx_DualStart_DMA() to enable both channel and start conversion
for dual mode operation using DMA to feed DAC converters.
First issued trigger will start the conversion of the value previously
set by HAL_DACEx_DualSetValue().
The same callbacks that are used in single mode are called in dual mode to notify
transfer completion (half complete or complete), errors or underrun.
(+) Use HAL_DACEx_DualStop_DMA() to disable both channel and stop conversion
for dual mode operation using DMA to feed DAC converters.
(+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
Channel 1 and Channel 2.
*** Signal generation operation ***
===================================
(+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
(+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
(+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
(+) HAL_DACEx_SetUserTrimming to set user trimming value.
(+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
after reset, user setting if HAL_DACEx_SetUserTrimming have been used
(+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
after reset, user setting if HAL_DACEx_SetUserTrimming have been used
at least one time after reset).
@endverbatim
@endverbatim
******************************************************************************
* @attention
*
@ -47,53 +67,291 @@
* @{
*/
/** @defgroup DACEx DACEx
#ifdef HAL_DAC_MODULE_ENABLED
#if defined(DAC1) || defined(DAC2)
/** @defgroup DACEx DACEx
* @brief DAC Extended HAL module driver
* @{
*/
#ifdef HAL_DAC_MODULE_ENABLED
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
* @{
*/
/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
* @brief Extended IO operation functions
*
@verbatim
* @brief Extended IO operation functions
*
@verbatim
==============================================================================
##### Extended features functions #####
==============================================================================
==============================================================================
[..] This section provides functions allowing to:
(+) Start conversion with triangle wave generation.
(+) Start conversion with noise wave generation.
(+) Start self calibration.
(+) Set user trimming mode.
(+) Start conversion.
(+) Stop conversion.
(+) Start conversion and enable DMA transfer.
(+) Stop conversion and disable DMA transfer.
(+) Get result of conversion.
(+) Get result of dual mode conversion.
@endverbatim
* @{
*/
/**
* @brief Enables DAC and starts conversion of both channels.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
{
uint32_t tmp_swtrig = 0UL;
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
/* Check if software trigger enabled */
if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_CR_TEN1)
{
tmp_swtrig |= DAC_SWTRIGR_SWTRIG1;
}
if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == DAC_CR_TEN2)
{
tmp_swtrig |= DAC_SWTRIGR_SWTRIG2;
}
/* Enable the selected DAC software conversion*/
SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Disables DAC and stop conversion of both channels.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
{
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Enables DAC and starts conversion of both channel 1 and 2 of the same DAC.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The DAC channel that will request data from DMA.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param pData The destination peripheral Buffer address.
* @param Length The length of data to be transferred from memory to DAC peripheral
* @param Alignment Specifies the data alignment for DAC channel.
* This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
uint32_t Alignment)
{
HAL_StatusTypeDef status;
uint32_t tmpreg = 0UL;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_ALIGN(Alignment));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
if (Channel == DAC_CHANNEL_1)
{
/* Set the DMA transfer complete callback for channel1 */
hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
/* Set the DMA half transfer complete callback for channel1 */
hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
/* Set the DMA error callback for channel1 */
hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
/* Enable the selected DAC channel1 DMA request */
SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
}
else
{
/* Set the DMA transfer complete callback for channel2 */
hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
/* Set the DMA half transfer complete callback for channel2 */
hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
/* Set the DMA error callback for channel2 */
hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
/* Enable the selected DAC channel2 DMA request */
SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
}
switch (Alignment)
{
case DAC_ALIGN_12B_R:
/* Get DHR12R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12RD;
break;
case DAC_ALIGN_12B_L:
/* Get DHR12L1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12LD;
break;
case DAC_ALIGN_8B_R:
/* Get DHR8R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR8RD;
break;
default:
break;
}
/* Enable the DMA channel */
if (Channel == DAC_CHANNEL_1)
{
/* Enable the DAC DMA underrun interrupt */
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
/* Enable the DMA channel */
status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
}
else
{
/* Enable the DAC DMA underrun interrupt */
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
/* Enable the DMA channel */
status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
}
/* Process Unlocked */
__HAL_UNLOCK(hdac);
if (status == HAL_OK)
{
/* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
}
else
{
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
}
/* Return function status */
return status;
}
/**
* @brief Disables DAC and stop conversion both channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The DAC channel that requests data from DMA.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
HAL_StatusTypeDef status;
/* Disable the selected DAC channel DMA request */
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2 | DAC_CR_DMAEN1);
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
/* Disable the DMA channel */
/* Channel1 is used */
if (Channel == DAC_CHANNEL_1)
{
/* Disable the DMA channel */
status = HAL_DMA_Abort(hdac->DMA_Handle1);
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
}
else
{
/* Disable the DMA channel */
status = HAL_DMA_Abort(hdac->DMA_Handle2);
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
}
/* Check if DMA Channel effectively disabled */
if (status != HAL_OK)
{
/* Update DAC state machine to error */
hdac->State = HAL_DAC_STATE_ERROR;
}
else
{
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
}
/* Return function status */
return status;
}
/**
* @brief Enable or disable the selected DAC channel wave generation.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param Amplitude Select max triangle amplitude.
* @param Amplitude Select max triangle amplitude.
* This parameter can be one of the following values:
* @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
* @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
@ -106,30 +364,30 @@
* @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
* @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
* @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
* @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
* @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
{
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the triangle wave generation for the selected DAC channel */
MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
@ -137,54 +395,52 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32
/**
* @brief Enable or disable the selected DAC channel wave generation.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param Amplitude Unmask DAC channel LFSR for noise wave generation.
* This parameter can be one of the following values:
* @param Amplitude Unmask DAC channel LFSR for noise wave generation.
* This parameter can be one of the following values:
* @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
* @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
{
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the noise wave generation for the selected DAC channel */
MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Set the specified data holding register value for dual DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
@ -200,42 +456,43 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t
* DAC channels at the same time.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
{
uint32_t data, tmp ;
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
{
uint32_t data;
uint32_t tmp;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(Alignment));
assert_param(IS_DAC_DATA(Data1));
assert_param(IS_DAC_DATA(Data2));
/* Calculate and set dual DAC data holding register value */
if (Alignment == DAC_ALIGN_8B_R)
{
data = ((uint32_t)Data2 << 8U) | Data1;
data = ((uint32_t)Data2 << 8U) | Data1;
}
else
{
data = ((uint32_t)Data2 << 16U) | Data1;
}
tmp = (uint32_t)hdac->Instance;
tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
/* Set the dual DAC selected data holding register */
*(__IO uint32_t *)tmp = data;
/* Return function status */
return HAL_OK;
}
/**
* @brief Conversion complete callback in non-blocking mode for Channel2.
* @brief Conversion complete callback in non-blocking mode for Channel2.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
@ -246,12 +503,12 @@ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
}
/**
* @brief Conversion half DMA transfer callback in non-blocking mode for Channel2.
* @brief Conversion half DMA transfer callback in non-blocking mode for Channel2.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
@ -278,7 +535,7 @@ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
}
/**
* @brief DMA underrun DAC callback for channel2.
* @brief DMA underrun DAC callback for Channel2.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
@ -293,13 +550,12 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
*/
}
/**
* @brief Run the self calibration of one DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param sConfig DAC channel configuration structure.
* @param Channel The selected DAC channel.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
@ -307,22 +563,21 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
* @retval HAL status
* @note Calibration runs about 7 ms.
*/
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
{
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
__IO uint32_t tmp = 0;
uint32_t trimmingvalue ;
__IO uint32_t tmp;
uint32_t trimmingvalue;
uint32_t delta;
/* store/restore channel configuration structure purpose */
uint32_t oldmodeconfiguration ;
uint32_t oldmodeconfiguration;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
/* Check the DAC handle allocation */
/* Check the DAC handle allocation */
/* Check if DAC running */
if (hdac == NULL)
{
@ -333,7 +588,7 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC
status = HAL_ERROR;
}
else
{
{
/* Process locked */
__HAL_LOCK(hdac);
@ -345,11 +600,11 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC
/* Set mode in MCR for calibration */
MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U);
/* Set DAC Channel1 DHR register to the middle value */
tmp = (uint32_t)hdac->Instance;
if(Channel == DAC_CHANNEL_1)
/* Set DAC Channel1 DHR register to the middle value */
tmp = (uint32_t)hdac->Instance;
if (Channel == DAC_CHANNEL_1)
{
tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
}
@ -357,37 +612,37 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC
{
tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
}
*(__IO uint32_t *) tmp = 0x0800U;
*(__IO uint32_t *) tmp = 0x0800UL;
/* Enable the selected DAC channel calibration */
/* i.e. set DAC_CR_CENx bit */
/* i.e. set DAC_CR_CENx bit */
SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
/* Init trimming counter */
/* Init trimming counter */
/* Medium value */
trimmingvalue = 16U;
delta = 8U;
while (delta != 0U)
trimmingvalue = 16UL;
delta = 8UL;
while (delta != 0UL)
{
/* Set candidate trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
/* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
/* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
/* i.e. minimum time needed between two calibration steps */
HAL_Delay(1);
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL)))
{
{
/* DAC_SR_CAL_FLAGx is HIGH try higher trimming */
trimmingvalue -= delta;
}
else
{
/* DAC_SR_CAL_FLAGx is LOW try lower trimming */
trimmingvalue += delta;
}
delta >>= 1U;
/* DAC_SR_CAL_FLAGx is LOW try lower trimming */
trimmingvalue += delta;
}
delta >>= 1UL;
}
/* Still need to check if right calibration is current value or one step below */
@ -395,68 +650,63 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC
/* Set candidate trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
/* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
/* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
/* i.e. minimum time needed between two calibration steps */
HAL_Delay(1U);
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
{
{
/* Trimming is actually one value more */
trimmingvalue ++;
trimmingvalue++;
/* Set right trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
}
/* Disable the selected DAC channel calibration */
/* i.e. clear DAC_CR_CENx bit */
CLEAR_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
sConfig->DAC_TrimmingValue = trimmingvalue;
sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
/* Restore configuration */
MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), oldmodeconfiguration);
/* Process unlocked */
__HAL_UNLOCK(hdac);
}
return status;
}
/**
* @}
*/
/**
* @brief Set the trimming mode and trimming value (user trimming mode applied).
* @brief Set the trimming mode and trimming value (user trimming mode applied).
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param sConfig DAC configuration structure updated with new DAC trimming value.
* @param Channel The selected DAC channel.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param NewTrimmingValue DAC new trimming value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
{
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
uint32_t NewTrimmingValue)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
/* Check the DAC handle allocation */
if(hdac == NULL)
/* Check the DAC handle allocation */
if (hdac == NULL)
{
status = HAL_ERROR;
}
else
{
{
/* Process locked */
__HAL_LOCK(hdac);
@ -466,70 +716,64 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_Channe
/* Update trimming mode */
sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
sConfig->DAC_TrimmingValue = NewTrimmingValue;
/* Process unlocked */
__HAL_UNLOCK(hdac);
}
}
return status;
}
/**
* @brief Return the DAC trimming value.
* @param hdac DAC handle
* @param Channel The selected DAC channel.
* @param hdac DAC handle
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval Trimming value : range: 0->31
*
*
*/
uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
{
uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
/* Check the parameter */
assert_param(IS_DAC_CHANNEL(Channel));
/* Retrieve trimming */
/* Retrieve trimming */
return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL));
}
/**
* @}
*/
/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
* @brief Extended Peripheral Control functions
*
@verbatim
* @brief Extended Peripheral Control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
==============================================================================
[..] This section provides functions allowing to:
(+) Configure channels.
(+) Set the specified data holding register value for DAC channel.
@endverbatim
* @{
*/
/**
* @brief Return the last data output value of the selected DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval The selected DAC channel data output value.
*/
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
{
uint32_t tmp = 0U;
uint32_t tmp = 0UL;
tmp |= hdac->Instance->DOR1;
tmp |= hdac->Instance->DOR2 << 16U;
tmp |= hdac->Instance->DOR2 << 16UL;
/* Returns the DAC channel data output register value */
return tmp;
}
@ -538,80 +782,86 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DACEx_Private_Functions DACEx private functions
* @brief Extended private functions
* @{
* @brief Extended private functions
* @{
*/
/**
* @brief DMA conversion complete callback.
* @brief DMA conversion complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ConvCpltCallbackCh2(hdac);
#else
HAL_DACEx_ConvCpltCallbackCh2(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State= HAL_DAC_STATE_READY;
#else
HAL_DACEx_ConvCpltCallbackCh2(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State = HAL_DAC_STATE_READY;
}
/**
* @brief DMA half transfer complete callback.
* @brief DMA half transfer complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Conversion complete callback */
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Conversion complete callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ConvHalfCpltCallbackCh2(hdac);
#else
HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/**
* @brief DMA error callback.
* @brief DMA error callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Set DAC error code to DMA error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ErrorCallbackCh2(hdac);
#else
HAL_DACEx_ErrorCallbackCh2(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State= HAL_DAC_STATE_READY;
#else
HAL_DACEx_ErrorCallbackCh2(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State = HAL_DAC_STATE_READY;
}
/**
* @}
*/
/**
* @}
*/
#endif /* DAC1 || DAC2 */
#endif /* HAL_DAC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

273
targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac_ex.h Normal file
View File

@ -0,0 +1,273 @@
/**
******************************************************************************
* @file stm32h7xx_hal_dac_ex.h
* @author MCD Application Team
* @brief Header file of DAC HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7xx_HAL_DAC_EX_H
#define STM32H7xx_HAL_DAC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
#if defined(DAC1) || defined(DAC2)
/** @addtogroup DACEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL State structures definition
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
* @{
*/
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
* @{
*/
#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */
#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */
#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */
#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */
#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */
#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */
#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup DACEx_Private_Macros DACEx Private Macros
* @{
*/
#if defined(HRTIM1)
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_HR1_TRGO1) || \
((TRIGGER) == DAC_TRIGGER_HR1_TRGO2) || \
((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \
((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#elif defined(DAC2)
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \
((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_LPTIM3_OUT) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#else
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \
((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_T23_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T24_TRGO) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif
#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
#define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FFU)
#define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_EXTERNAL) || \
((CONNECT) == DAC_CHIPCONNECT_INTERNAL) || \
((CONNECT) == DAC_CHIPCONNECT_BOTH))
#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
((TRIMMING) == DAC_TRIMMING_USER))
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/* Extended features functions ***********************************************/
/** @addtogroup DACEx_Exported_Functions
* @{
*/
/** @addtogroup DACEx_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
uint32_t Alignment);
HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
/**
* @}
*/
/** @addtogroup DACEx_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
uint32_t NewTrimmingValue);
uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DACEx_Private_Functions
* @{
*/
/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
/* are called by HAL_DAC_Start_DMA */
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
#endif /* DAC1 || DAC2 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*STM32H7xx_HAL_DAC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

609
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dcmi.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dcmi.c
View File

@ -131,6 +131,7 @@
*/
#ifdef HAL_DCMI_MODULE_ENABLED
#if defined (DCMI)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@ -167,15 +168,15 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma);
* @brief Initializes the DCMI according to the specified
* parameters in the DCMI_InitTypeDef and create the associated handle.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
{
/* Check the DCMI peripheral state */
if(hdcmi == NULL)
if (hdcmi == NULL)
{
return HAL_ERROR;
return HAL_ERROR;
}
/* Check function parameters */
@ -193,51 +194,56 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));
assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
if(hdcmi->State == HAL_DCMI_STATE_RESET)
if (hdcmi->State == HAL_DCMI_STATE_RESET)
{
/* Init the DCMI Callback settings */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/* Reset callback pointers to the weak predefined callbacks */
hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback;
hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback;
hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback;
hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback;
hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
if(hdcmi->MspInitCallback == NULL)
if (hdcmi->MspInitCallback == NULL)
{
/* Legacy weak MspInit Callback */
hdcmi->MspInitCallback = HAL_DCMI_MspInit;
}
/* Init the low level hardware */
/* Initialize the low level hardware (MSP) */
hdcmi->MspInitCallback(hdcmi);
}
#else
if(hdcmi->State == HAL_DCMI_STATE_RESET)
{
/* Init the low level hardware */
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_DCMI_MspInit(hdcmi);
#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */
}
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
/* Change the DCMI state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Configures the HS, VS, DE and PC polarity */
hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |\
DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |\
DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\
if (hdcmi->Init.ExtendedDataMode != DCMI_EXTEND_DATA_8B)
{
/* Byte select mode must be programmed to the reset value if the extended mode
is not set to 8-bit data capture on every pixel clock */
hdcmi->Init.ByteSelectMode = DCMI_BSM_ALL;
}
/* Configures the HS, VS, DE and PC polarity */
hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 | \
DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG | \
DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS | \
DCMI_CR_LSM | DCMI_CR_OELS);
hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\
hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity |\
hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\
hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode |\
hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\
hdcmi->Init.LineSelectStart);
hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \
hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity | \
hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \
hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode | \
hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode | \
hdcmi->Init.LineSelectStart);
if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
if (hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
{
hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |\
((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_ESCR_LSC_Pos)|\
((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_ESCR_LEC_Pos) |\
hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) | \
((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_ESCR_LSC_Pos) | \
((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_ESCR_LEC_Pos) | \
((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_ESCR_FEC_Pos));
}
@ -258,24 +264,23 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
* @brief Deinitializes the DCMI peripheral registers to their default reset
* values.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
{
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
if(hdcmi->MspDeInitCallback == NULL)
if (hdcmi->MspDeInitCallback == NULL)
{
hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
}
/* DeInit the low level hardware */
/* De-Initialize the low level hardware (MSP) */
hdcmi->MspDeInitCallback(hdcmi);
#else
/* DeInit the low level hardware */
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_DCMI_MspDeInit(hdcmi);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */
/* Update error code */
hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
@ -289,201 +294,13 @@ HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
return HAL_OK;
}
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User DCMI Callback
* To be used instead of the weak predefined callback
* @param hdcmi DCMI handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_DCMI_LINE_EVENT_CB_ID Line Event callback ID
* @arg @ref HAL_DCMI_FRAME_EVENT_CB_ID Frame Event callback ID
* @arg @ref HAL_DCMI_VSYNC_EVENT_CB_ID Vsync Event callback ID
* @arg @ref HAL_DCMI_ERROR_CB_ID Error callback ID
* @arg @ref HAL_DCMI_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_DCMI_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if(pCallback == NULL)
{
/* Update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdcmi);
if(HAL_DCMI_STATE_READY == hdcmi->State)
{
switch (CallbackID)
{
case HAL_DCMI_LINE_EVENT_CB_ID :
hdcmi->LineEventCallback = pCallback;
break;
case HAL_DCMI_FRAME_EVENT_CB_ID :
hdcmi->FrameEventCallback = pCallback;
break;
case HAL_DCMI_VSYNC_EVENT_CB_ID :
hdcmi->VsyncEventCallback = pCallback;
break;
case HAL_DCMI_ERROR_CB_ID :
hdcmi->ErrorCallback = pCallback;
break;
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = pCallback;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if(HAL_DCMI_STATE_RESET == hdcmi->State)
{
switch (CallbackID)
{
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = pCallback;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdcmi);
return status;
}
/**
* @brief Unregister a DCMI Callback
* DCMI callabck is redirected to the weak predefined callback
* @param hdcmi DCMI handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_DCMI_LINE_EVENT_CB_ID Line Event callback ID
* @arg @ref HAL_DCMI_FRAME_EVENT_CB_ID Frame Event callback ID
* @arg @ref HAL_DCMI_VSYNC_EVENT_CB_ID Vsync Event callback ID
* @arg @ref HAL_DCMI_ERROR_CB_ID Error callback ID
* @arg @ref HAL_DCMI_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_DCMI_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdcmi);
if(HAL_DCMI_STATE_READY == hdcmi->State)
{
switch (CallbackID)
{
case HAL_DCMI_LINE_EVENT_CB_ID :
hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback;
break;
case HAL_DCMI_FRAME_EVENT_CB_ID :
hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback;
break;
case HAL_DCMI_VSYNC_EVENT_CB_ID :
hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback;
break;
case HAL_DCMI_ERROR_CB_ID :
hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback;
break;
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = HAL_DCMI_MspInit;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
break;
default :
/* Update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if(HAL_DCMI_STATE_RESET == hdcmi->State)
{
switch (CallbackID)
{
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = HAL_DCMI_MspInit;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
break;
default :
/* Update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdcmi);
return status;
}
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
/**
* @brief Initializes the DCMI MSP.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* the configuration information for DCMI.
* @retval None
*/
__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef *hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
@ -496,10 +313,10 @@ __weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
/**
* @brief DeInitializes the DCMI MSP.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* the configuration information for DCMI.
* @retval None
*/
__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
@ -532,13 +349,13 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
/**
* @brief Enables DCMI DMA request and enables DCMI capture
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* the configuration information for DCMI.
* @param DCMI_Mode DCMI capture mode snapshot or continuous grab.
* @param pData The destination memory Buffer address (LCD Frame buffer).
* @param Length The length of capture to be transferred.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
{
/* Initialize the second memory address */
uint32_t SecondMemAddress;
@ -557,7 +374,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
/* Configure the DCMI Mode */
hdcmi->Instance->CR &= ~(DCMI_CR_CM);
hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode);
hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode);
/* Set the DMA memory0 conversion complete callback */
hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt;
@ -571,8 +388,10 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
/* Reset transfer counters value */
hdcmi->XferCount = 0;
hdcmi->XferTransferNumber = 0;
hdcmi->XferSize = 0;
hdcmi->pBuffPtr = 0;
if(Length <= 0xFFFFU)
if (Length <= 0xFFFFU)
{
/* Enable the DMA Stream */
if (HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length) != HAL_OK)
@ -598,10 +417,10 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
hdcmi->pBuffPtr = pData;
/* Get the number of buffer */
while(hdcmi->XferSize > 0xFFFFU)
while (hdcmi->XferSize > 0xFFFFU)
{
hdcmi->XferSize = (hdcmi->XferSize/2U);
hdcmi->XferCount = hdcmi->XferCount*2U;
hdcmi->XferSize = (hdcmi->XferSize / 2U);
hdcmi->XferCount = hdcmi->XferCount * 2U;
}
/* Update DCMI counter and transfer number*/
@ -609,7 +428,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
hdcmi->XferTransferNumber = hdcmi->XferCount;
/* Update second memory address */
SecondMemAddress = (uint32_t)(pData + (4U*hdcmi->XferSize));
SecondMemAddress = (uint32_t)(pData + (4U * hdcmi->XferSize));
/* Start DMA multi buffer transfer */
if (HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize) != HAL_OK)
@ -638,12 +457,12 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
/**
* @brief Disable DCMI DMA request and Disable DCMI capture
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi)
{
register uint32_t count = HAL_TIMEOUT_DCMI_STOP * ( SystemD1Clock/8U/1000U);
register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
@ -658,7 +477,7 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
/* Check if the DCMI capture effectively disabled */
do
{
count--;
count-- ;
if (count == 0U)
{
/* Update error code */
@ -668,7 +487,7 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
break;
}
}
while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
/* Disable the DCMI */
__HAL_DCMI_DISABLE(hdcmi);
@ -692,18 +511,18 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
/**
* @brief Suspend DCMI capture
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi)
{
register uint32_t count = HAL_TIMEOUT_DCMI_STOP * ( SystemD1Clock/8U/1000U);
register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdcmi);
if(hdcmi->State == HAL_DCMI_STATE_BUSY)
if (hdcmi->State == HAL_DCMI_STATE_BUSY)
{
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_SUSPENDED;
@ -714,7 +533,7 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
/* Check if the DCMI capture effectively disabled */
do
{
count--;
count-- ;
if (count == 0U)
{
/* Update error code */
@ -727,7 +546,7 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
break;
}
}
while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
}
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
@ -739,15 +558,15 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
/**
* @brief Resume DCMI capture
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi)
HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi)
{
/* Process locked */
__HAL_LOCK(hdcmi);
if(hdcmi->State == HAL_DCMI_STATE_SUSPENDED)
if (hdcmi->State == HAL_DCMI_STATE_SUSPENDED)
{
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
@ -765,7 +584,7 @@ HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi)
/**
* @brief Handles DCMI interrupt request.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for the DCMI.
* the configuration information for the DCMI.
* @retval None
*/
void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
@ -773,7 +592,7 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
uint32_t isr_value = READ_REG(hdcmi->Instance->MISR);
/* Synchronization error interrupt management *******************************/
if((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI)
if ((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI)
{
/* Clear the Synchronization error flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
@ -791,7 +610,7 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
(void)HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
}
/* Overflow interrupt management ********************************************/
if((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)
if ((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)
{
/* Clear the Overflow flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI);
@ -809,37 +628,38 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
(void)HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
}
/* Line Interrupt management ************************************************/
if((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)
if ((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)
{
/* Clear the Line interrupt flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
/* Line interrupt Callback */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/*Call registered DCMI line event callback*/
hdcmi->LineEventCallback(hdcmi);
#else
HAL_DCMI_LineEventCallback(hdcmi);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}
/* VSYNC interrupt management ***********************************************/
if((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)
if ((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)
{
/* Clear the VSYNC flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
/* VSYNC Callback */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/*Call registered DCMI vsync event callback*/
hdcmi->VsyncEventCallback(hdcmi);
#else
HAL_DCMI_VsyncEventCallback(hdcmi);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}
/* FRAME interrupt management ***********************************************/
if((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)
if ((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)
{
/* When snapshot mode, disable Vsync, Error and Overrun interrupts */
if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
{
/* Disable the Line, Vsync, Error and Overrun interrupts */
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
@ -853,18 +673,18 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
/* Frame Callback */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/*Call registered DCMI frame event callback*/
hdcmi->FrameEventCallback(hdcmi);
#else
HAL_DCMI_FrameEventCallback(hdcmi);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}
}
/**
* @brief Error DCMI callback.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* the configuration information for DCMI.
* @retval None
*/
__weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
@ -880,7 +700,7 @@ __weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
/**
* @brief Line Event callback.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* the configuration information for DCMI.
* @retval None
*/
__weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
@ -895,7 +715,7 @@ __weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
/**
* @brief VSYNC Event callback.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* the configuration information for DCMI.
* @retval None
*/
__weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
@ -911,7 +731,7 @@ __weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
/**
* @brief Frame Event callback.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* the configuration information for DCMI.
* @retval None
*/
__weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
@ -938,6 +758,7 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
[..] This section provides functions allowing to:
(+) Configure the CROP feature.
(+) Enable/Disable the CROP feature.
(+) Set embedded synchronization delimiters unmasks.
@endverbatim
* @{
@ -946,7 +767,7 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
/**
* @brief Configure the DCMI CROP coordinate.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* the configuration information for DCMI.
* @param YSize DCMI Line number
* @param XSize DCMI Pixel per line
* @param X0 DCMI window X offset
@ -983,7 +804,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui
/**
* @brief Disable the Crop feature.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi)
@ -1009,7 +830,7 @@ HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi)
/**
* @brief Enable the Crop feature.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)
@ -1032,6 +853,37 @@ HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)
return HAL_OK;
}
/**
* @brief Set embedded synchronization delimiters unmasks.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @param SyncUnmask pointer to a DCMI_SyncUnmaskTypeDef structure that contains
* the embedded synchronization delimiters unmasks.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask)
{
/* Process Locked */
__HAL_LOCK(hdcmi);
/* Lock the DCMI peripheral state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Write DCMI embedded synchronization unmask register */
hdcmi->Instance->ESUR = (((uint32_t)SyncUnmask->FrameStartUnmask) | \
((uint32_t)SyncUnmask->LineStartUnmask << DCMI_ESUR_LSU_Pos) | \
((uint32_t)SyncUnmask->LineEndUnmask << DCMI_ESUR_LEU_Pos) | \
((uint32_t)SyncUnmask->FrameEndUnmask << DCMI_ESUR_FEU_Pos));
/* Change the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
return HAL_OK;
}
/**
* @}
*/
@ -1055,7 +907,7 @@ HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)
/**
* @brief Return the DCMI state
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* the configuration information for DCMI.
* @retval HAL state
*/
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
@ -1066,7 +918,7 @@ HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
/**
* @brief Return the DCMI error code
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* the configuration information for DCMI.
* @retval DCMI Error Code
*/
uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
@ -1074,6 +926,187 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
return hdcmi->ErrorCode;
}
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User DCMI Callback
* To be used instead of the weak predefined callback
* @param hdcmi DCMI handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_DCMI_LINE_EVENT_CB_ID Line Event callback ID
* @arg @ref HAL_DCMI_FRAME_EVENT_CB_ID Frame Event callback ID
* @arg @ref HAL_DCMI_VSYNC_EVENT_CB_ID Vsync Event callback ID
* @arg @ref HAL_DCMI_ERROR_CB_ID Error callback ID
* @arg @ref HAL_DCMI_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_DCMI_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
else
{
if (hdcmi->State == HAL_DCMI_STATE_READY)
{
switch (CallbackID)
{
case HAL_DCMI_FRAME_EVENT_CB_ID :
hdcmi->FrameEventCallback = pCallback;
break;
case HAL_DCMI_VSYNC_EVENT_CB_ID :
hdcmi->VsyncEventCallback = pCallback;
break;
case HAL_DCMI_LINE_EVENT_CB_ID :
hdcmi->LineEventCallback = pCallback;
break;
case HAL_DCMI_ERROR_CB_ID :
hdcmi->ErrorCallback = pCallback;
break;
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = pCallback;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = pCallback;
break;
default :
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hdcmi->State == HAL_DCMI_STATE_RESET)
{
switch (CallbackID)
{
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = pCallback;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = pCallback;
break;
default :
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
}
return status;
}
/**
* @brief Unregister a DCMI Callback
* DCMI callabck is redirected to the weak predefined callback
* @param hdcmi DCMI handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_DCMI_LINE_EVENT_CB_ID Line Event callback ID
* @arg @ref HAL_DCMI_FRAME_EVENT_CB_ID Frame Event callback ID
* @arg @ref HAL_DCMI_VSYNC_EVENT_CB_ID Vsync Event callback ID
* @arg @ref HAL_DCMI_ERROR_CB_ID Error callback ID
* @arg @ref HAL_DCMI_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_DCMI_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if (hdcmi->State == HAL_DCMI_STATE_READY)
{
switch (CallbackID)
{
case HAL_DCMI_FRAME_EVENT_CB_ID :
hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
break;
case HAL_DCMI_VSYNC_EVENT_CB_ID :
hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
break;
case HAL_DCMI_LINE_EVENT_CB_ID :
hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
break;
case HAL_DCMI_ERROR_CB_ID :
hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = HAL_DCMI_MspInit;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
break;
default :
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hdcmi->State == HAL_DCMI_STATE_RESET)
{
switch (CallbackID)
{
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = HAL_DCMI_MspInit;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
break;
default :
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
/**
* @}
*/
@ -1081,33 +1114,33 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
/** @defgroup DCMI_Private_Functions DCMI Private Functions
* @{
*/
/**
/**
* @brief DMA conversion complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* the configuration information for the specified DMA module.
* @retval None
*/
static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
{
uint32_t tmp;
uint32_t tmp ;
DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
DCMI_HandleTypeDef *hdcmi = (DCMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
if(hdcmi->XferCount != 0U)
if (hdcmi->XferCount != 0U)
{
/* Update memory 0 address location */
tmp = ((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR) & DMA_SxCR_CT);
if(((hdcmi->XferCount % 2U) == 0U) && (tmp != 0U))
if (((hdcmi->XferCount % 2U) == 0U) && (tmp != 0U))
{
tmp = ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M0AR;
(void) HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8U*hdcmi->XferSize)), MEMORY0);
(void)HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8U * hdcmi->XferSize)), MEMORY0);
hdcmi->XferCount--;
}
/* Update memory 1 address location */
else if((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) == 0U)
else if ((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) == 0U)
{
tmp = ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M1AR;
(void) HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8U*hdcmi->XferSize)), MEMORY1);
(void)HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8U * hdcmi->XferSize)), MEMORY1);
hdcmi->XferCount--;
}
else
@ -1116,15 +1149,15 @@ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
}
}
/* Update memory 0 address location */
else if((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) != 0U)
else if ((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) != 0U)
{
((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M0AR = hdcmi->pBuffPtr;
}
/* Update memory 1 address location */
else if((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) == 0U)
else if ((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) == 0U)
{
tmp = hdcmi->pBuffPtr;
((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M1AR = (tmp + (4U*hdcmi->XferSize));
((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M1AR = (tmp + (4U * hdcmi->XferSize));
hdcmi->XferCount = hdcmi->XferTransferNumber;
}
else
@ -1133,15 +1166,15 @@ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
}
/* Check if the frame is transferred */
if(hdcmi->XferCount == hdcmi->XferTransferNumber)
if (hdcmi->XferCount == hdcmi->XferTransferNumber)
{
/* Enable the Frame interrupt */
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
/* When snapshot mode, set dcmi state to ready */
if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
{
hdcmi->State= HAL_DCMI_STATE_READY;
hdcmi->State = HAL_DCMI_STATE_READY;
}
}
}
@ -1149,14 +1182,14 @@ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA error callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* the configuration information for the specified DMA module.
* @retval None
*/
static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
{
DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
DCMI_HandleTypeDef *hdcmi = (DCMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
if(hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE)
if (hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE)
{
/* Initialize the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
@ -1167,6 +1200,7 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
/* DCMI error Callback */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/*Call registered DCMI error callback*/
hdcmi->ErrorCallback(hdcmi);
#else
HAL_DCMI_ErrorCallback(hdcmi);
@ -1180,6 +1214,7 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
/**
* @}
*/
#endif /* DCMI */
#endif /* HAL_DCMI_MODULE_ENABLED */
/**
* @}

66
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dcmi.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dcmi.h
View File

@ -53,7 +53,7 @@ typedef enum
HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */
HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */
HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */
}HAL_DCMI_StateTypeDef;
} HAL_DCMI_StateTypeDef;
/**
* @brief DCMI Embedded Synchronisation CODE Init structure definition
@ -64,8 +64,18 @@ typedef struct
uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
}DCMI_CodesInitTypeDef;
} DCMI_CodesInitTypeDef;
/**
* @brief DCMI Embedded Synchronisation UNMASK Init structure definition
*/
typedef struct
{
uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */
uint8_t LineStartUnmask; /*!< Specifies the line start delimiter unmask. */
uint8_t LineEndUnmask; /*!< Specifies the line end delimiter unmask. */
uint8_t FrameEndUnmask; /*!< Specifies the frame end delimiter unmask. */
} DCMI_SyncUnmaskTypeDef;
/**
* @brief DCMI Init structure definition
*/
@ -106,7 +116,7 @@ typedef struct
uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd
This parameter can be a value of @ref DCMI_Line_Select_Start */
}DCMI_InitTypeDef;
} DCMI_InitTypeDef;
/**
* @brief DCMI handle Structure definition
@ -138,17 +148,14 @@ typedef struct
__IO uint32_t ErrorCode; /*!< DCMI Error code */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
void (* LineEventCallback) ( struct __DCMI_HandleTypeDef * hdcmi); /*!< DCMI Line Event callback */
void (* FrameEventCallback) ( struct __DCMI_HandleTypeDef * hdcmi); /*!< DCMI Frame Event callback */
void (* VsyncEventCallback) ( struct __DCMI_HandleTypeDef * hdcmi); /*!< DCMI Vsync Event callback */
void (* ErrorCallback) ( struct __DCMI_HandleTypeDef * hdcmi); /*!< DCMI Error callback */
void (* MspInitCallback) ( struct __DCMI_HandleTypeDef * hdcmi); /*!< DCMI Msp Init callback */
void (* MspDeInitCallback) ( struct __DCMI_HandleTypeDef * hdcmi); /*!< DCMI Msp DeInit callback */
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}DCMI_HandleTypeDef;
void (* FrameEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Frame Event Callback */
void (* VsyncEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Vsync Event Callback */
void (* LineEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Line Event Callback */
void (* ErrorCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Error Callback */
void (* MspInitCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp Init callback */
void (* MspDeInitCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp DeInit callback */
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
} DCMI_HandleTypeDef;
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/**
@ -156,14 +163,14 @@ typedef struct
*/
typedef enum
{
HAL_DCMI_FRAME_EVENT_CB_ID = 0x00U, /*!< DCMI Frame event Callback ID */
HAL_DCMI_VSYNC_EVENT_CB_ID = 0x01U, /*!< DCMI Vsync event Callback ID */
HAL_DCMI_LINE_EVENT_CB_ID = 0x02U, /*!< DCMI Line event Callback ID */
HAL_DCMI_ERROR_CB_ID = 0x03U, /*!< DCMI Error Callback ID */
HAL_DCMI_MSPINIT_CB_ID = 0x04U, /*!< DCMI MspInit callback ID */
HAL_DCMI_MSPDEINIT_CB_ID = 0x05U /*!< DCMI MspDeInit callback ID */
HAL_DCMI_FRAME_EVENT_CB_ID = 0x00U, /*!< DCMI Frame Event Callback ID */
HAL_DCMI_VSYNC_EVENT_CB_ID = 0x01U, /*!< DCMI Vsync Event Callback ID */
HAL_DCMI_LINE_EVENT_CB_ID = 0x02U, /*!< DCMI Line Event Callback ID */
HAL_DCMI_ERROR_CB_ID = 0x03U, /*!< DCMI Error Callback ID */
HAL_DCMI_MSPINIT_CB_ID = 0x04U, /*!< DCMI MspInit callback ID */
HAL_DCMI_MSPDEINIT_CB_ID = 0x05U /*!< DCMI MspDeInit callback ID */
}HAL_DCMI_CallbackIDTypeDef;
} HAL_DCMI_CallbackIDTypeDef;
/**
* @brief HAL DCMI Callback pointer definition
@ -183,13 +190,13 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef * hdcmi); /*!< pointer
/** @defgroup DCMI_Error_Code DCMI Error Code
* @{
*/
#define HAL_DCMI_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_DCMI_ERROR_OVR (0x00000001U) /*!< Overrun error */
#define HAL_DCMI_ERROR_SYNC (0x00000002U) /*!< Synchronization error */
#define HAL_DCMI_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_DCMI_ERROR_DMA (0x00000040U) /*!< DMA error */
#define HAL_DCMI_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_DCMI_ERROR_OVR (0x00000001U) /*!< Overrun error */
#define HAL_DCMI_ERROR_SYNC (0x00000002U) /*!< Synchronization error */
#define HAL_DCMI_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_DCMI_ERROR_DMA (0x00000040U) /*!< DMA error */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
#define HAL_DCMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */
#define HAL_DCMI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
/**
* @}
@ -553,6 +560,7 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask);
/**
* @}
@ -578,8 +586,8 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
/** @defgroup DCMI_Private_Constants DCMI Private Constants
* @{
*/
#define DCMI_MIS_INDEX (0x1000) /*!< DCMI MIS register index */
#define DCMI_SR_INDEX (0x2000) /*!< DCMI SR register index */
#define DCMI_MIS_INDEX ((uint32_t)0x1000) /*!< DCMI MIS register index */
#define DCMI_SR_INDEX ((uint32_t)0x2000) /*!< DCMI SR register index */
/**
* @}
*/

2
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_def.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_def.h
View File

@ -28,7 +28,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx.h"
#include "stm32_hal_legacy.h"
#include "Legacy/stm32_hal_legacy.h"
#include <stddef.h>
#include <math.h>

919
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dfsdm.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm.c
View File

File diff suppressed because it is too large Load Diff

248
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dfsdm.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm.h
View File

@ -34,26 +34,26 @@
/** @addtogroup DFSDM
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DFSDM_Exported_Types DFSDM Exported Types
* @{
*/
/**
* @brief HAL DFSDM Channel states definition
*/
/**
* @brief HAL DFSDM Channel states definition
*/
typedef enum
{
HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */
HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */
HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */
}HAL_DFSDM_Channel_StateTypeDef;
} HAL_DFSDM_Channel_StateTypeDef;
/**
* @brief DFSDM channel output clock structure definition
*/
/**
* @brief DFSDM channel output clock structure definition
*/
typedef struct
{
FunctionalState Activation; /*!< Output clock enable/disable */
@ -61,46 +61,46 @@ typedef struct
This parameter can be a value of @ref DFSDM_Channel_OuputClock */
uint32_t Divider; /*!< Output clock divider.
This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
}DFSDM_Channel_OutputClockTypeDef;
} DFSDM_Channel_OutputClockTypeDef;
/**
* @brief DFSDM channel input structure definition
*/
/**
* @brief DFSDM channel input structure definition
*/
typedef struct
{
uint32_t Multiplexer; /*!< Input is external serial inputs ,internal register or ADC output.
uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output.
This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
This parameter can be a value of @ref DFSDM_Channel_DataPacking */
uint32_t Pins; /*!< Input pins are taken from same or following channel.
This parameter can be a value of @ref DFSDM_Channel_InputPins */
}DFSDM_Channel_InputTypeDef;
} DFSDM_Channel_InputTypeDef;
/**
* @brief DFSDM channel serial interface structure definition
*/
/**
* @brief DFSDM channel serial interface structure definition
*/
typedef struct
{
uint32_t Type; /*!< SPI or Manchester modes.
This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
This parameter can be a value of @ref DFSDM_Channel_SpiClock */
}DFSDM_Channel_SerialInterfaceTypeDef;
} DFSDM_Channel_SerialInterfaceTypeDef;
/**
* @brief DFSDM channel analog watchdog structure definition
*/
/**
* @brief DFSDM channel analog watchdog structure definition
*/
typedef struct
{
uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order.
This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
}DFSDM_Channel_AwdTypeDef;
} DFSDM_Channel_AwdTypeDef;
/**
* @brief DFSDM channel init structure definition
*/
/**
* @brief DFSDM channel init structure definition
*/
typedef struct
{
DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */
@ -111,16 +111,16 @@ typedef struct
This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
uint32_t RightBitShift; /*!< DFSDM channel right bit shift.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
}DFSDM_Channel_InitTypeDef;
} DFSDM_Channel_InitTypeDef;
/**
* @brief DFSDM channel handle structure definition
/**
* @brief DFSDM channel handle structure definition
*/
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
typedef struct __DFSDM_Channel_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
{
DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */
DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */
@ -131,7 +131,7 @@ typedef struct
void (*MspInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */
void (*MspDeInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */
#endif
}DFSDM_Channel_HandleTypeDef;
} DFSDM_Channel_HandleTypeDef;
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
/**
@ -143,7 +143,7 @@ typedef enum
HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U, /*!< DFSDM channel short circuit detection callback ID */
HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U, /*!< DFSDM channel MSP init callback ID */
HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U /*!< DFSDM channel MSP de-init callback ID */
}HAL_DFSDM_Channel_CallbackIDTypeDef;
} HAL_DFSDM_Channel_CallbackIDTypeDef;
/**
* @brief DFSDM channel callback pointer definition
@ -151,9 +151,9 @@ typedef enum
typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
#endif
/**
* @brief HAL DFSDM Filter states definition
*/
/**
* @brief HAL DFSDM Filter states definition
*/
typedef enum
{
HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */
@ -162,22 +162,22 @@ typedef enum
HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */
HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */
HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */
}HAL_DFSDM_Filter_StateTypeDef;
} HAL_DFSDM_Filter_StateTypeDef;
/**
* @brief DFSDM filter regular conversion parameters structure definition
*/
/**
* @brief DFSDM filter regular conversion parameters structure definition
*/
typedef struct
{
uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous.
This parameter can be a value of @ref DFSDM_Filter_Trigger */
FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */
FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */
}DFSDM_Filter_RegularParamTypeDef;
} DFSDM_Filter_RegularParamTypeDef;
/**
* @brief DFSDM filter injected conversion parameters structure definition
*/
/**
* @brief DFSDM filter injected conversion parameters structure definition
*/
typedef struct
{
uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous.
@ -188,11 +188,11 @@ typedef struct
This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
}DFSDM_Filter_InjectedParamTypeDef;
} DFSDM_Filter_InjectedParamTypeDef;
/**
* @brief DFSDM filter parameters structure definition
*/
/**
* @brief DFSDM filter parameters structure definition
*/
typedef struct
{
uint32_t SincOrder; /*!< Sinc filter order.
@ -201,26 +201,26 @@ typedef struct
This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
uint32_t IntOversampling; /*!< Integrator oversampling ratio.
This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
}DFSDM_Filter_FilterParamTypeDef;
} DFSDM_Filter_FilterParamTypeDef;
/**
* @brief DFSDM filter init structure definition
*/
/**
* @brief DFSDM filter init structure definition
*/
typedef struct
{
DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */
DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */
DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */
}DFSDM_Filter_InitTypeDef;
} DFSDM_Filter_InitTypeDef;
/**
* @brief DFSDM filter handle structure definition
/**
* @brief DFSDM filter handle structure definition
*/
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
typedef struct __DFSDM_Filter_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
{
DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */
DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */
@ -234,7 +234,7 @@ typedef struct
uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */
uint32_t InjConvRemaining; /*!< Injected conversions remaining */
HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */
uint32_t ErrorCode; /*!< DFSDM filter error code */
uint32_t ErrorCode; /*!< DFSDM filter error code */
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
void (*AwdCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */
@ -248,9 +248,9 @@ typedef struct
#endif
}DFSDM_Filter_HandleTypeDef;
/**
* @brief DFSDM filter analog watchdog parameters structure definition
*/
/**
* @brief DFSDM filter analog watchdog parameters structure definition
*/
typedef struct
{
uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter.
@ -265,7 +265,7 @@ typedef struct
This parameter can be a values combination of @ref DFSDM_BreakSignals */
uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event.
This parameter can be a values combination of @ref DFSDM_BreakSignals */
}DFSDM_Filter_AwdParamTypeDef;
} DFSDM_Filter_AwdParamTypeDef;
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
/**
@ -280,7 +280,7 @@ typedef enum
HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U, /*!< DFSDM filter error callback ID */
HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U, /*!< DFSDM filter MSP init callback ID */
HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U /*!< DFSDM filter MSP de-init callback ID */
}HAL_DFSDM_Filter_CallbackIDTypeDef;
} HAL_DFSDM_Filter_CallbackIDTypeDef;
/**
* @brief DFSDM filter callback pointer definition
@ -291,7 +291,7 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
/**
* @}
*/
*/
/* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
@ -362,10 +362,10 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
* @{
*/
#define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */
#define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
#define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
#define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */
#define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */
#define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
#define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
#define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */
/**
* @}
*/
@ -374,7 +374,7 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
* @{
*/
#define DFSDM_FILTER_SW_TRIGGER 0x00000000U /*!< Software trigger */
#define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */
#define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */
#define DFSDM_FILTER_EXT_TRIGGER 0x00000002U /*!< External trigger (only for injected conversion) */
/**
* @}
@ -383,22 +383,28 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
* @{
*/
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM 0, 1 and 2 */
#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM 0, 1 and 2 */
#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM 0 and 1 */
#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For DFSDM 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)
#define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)
#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3) /*!< For DFSDM 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0) /*!< For DFSDM 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_0) /*!< For DFSDM 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3) /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0) /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_0) /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */
#if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) || defined(STM32H7B0xx) || defined(STM32H7B0xxQ)
#define DFSDM_FILTER_EXT_TRIG_COMP1_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | \
DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_0)
#define DFSDM_FILTER_EXT_TRIG_COMP2_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | \
DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)
#endif /* STM32H7A3xx || STM32H7A3xxQ || STM32H7B3xx || STM32H7B3xxQ || STM32H7B0xx || STM32H7B0xxQ */
/**
* @}
*/
@ -416,11 +422,11 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
* @{
*/
#define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */
#define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */
#define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */
#define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */
#define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */
#define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */
#define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
#define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */
#define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */
#define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
/**
* @}
@ -429,15 +435,15 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
* @{
*/
#define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U /*!< From digital filter */
#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */
#define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U /*!< From digital filter */
#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */
/**
* @}
*/
/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
* @{
*/
*/
#define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */
#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */
#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */
@ -470,7 +476,7 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
- in 16-bit MSB the channel number is set
e.g. for channel 5 definition:
- the channel mask is 0x00000020 (bit 5 is set)
- the channel number 5 is 0x00050000
- the channel number 5 is 0x00050000
--> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
#define DFSDM_CHANNEL_0 0x00000001U
#define DFSDM_CHANNEL_1 0x00010002U
@ -504,10 +510,10 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
/**
* @}
*/
*/
/* End of exported constants -------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
* @{
*/
@ -545,7 +551,12 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
*/
/* End of exported macros ----------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
#if defined(DFSDM_CHDLYR_PLSSKP)
/* Include DFSDM HAL Extension module */
#include "stm32h7xx_hal_dfsdm_ex.h"
#endif /* DFSDM_CHDLYR_PLSSKP */
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
* @{
*/
@ -662,15 +673,15 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
DFSDM_Filter_AwdParamTypeDef* awdParam);
DFSDM_Filter_AwdParamTypeDef *awdParam);
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
@ -701,7 +712,7 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* End of exported functions -------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DFSDM_Private_Macros DFSDM Private Macros
@ -739,6 +750,24 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
#if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) || defined(STM32H7B0xx) || defined(STM32H7B0xxQ)
#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_COMP1_OUT) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_COMP2_OUT))
#else
#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
@ -755,6 +784,7 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT))
#endif /* STM32H7A3xx || STM32H7A3xxQ || STM32H7B3xx || STM32H7B3xxQ || STM32H7B0xx || STM32H7B0xxQ */
#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \
((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \
((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
@ -781,14 +811,32 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))
#define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \
((MODE) == DFSDM_CONTINUOUS_CONV_ON))
#if defined(DFSDM2_Channel0)
#define IS_DFSDM1_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
((INSTANCE) == DFSDM1_Channel1) || \
((INSTANCE) == DFSDM1_Channel2) || \
((INSTANCE) == DFSDM1_Channel3) || \
((INSTANCE) == DFSDM1_Channel4) || \
((INSTANCE) == DFSDM1_Channel5) || \
((INSTANCE) == DFSDM1_Channel6) || \
((INSTANCE) == DFSDM1_Channel7))
#define IS_DFSDM1_FILTER_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
((INSTANCE) == DFSDM1_Filter1) || \
((INSTANCE) == DFSDM1_Filter2) || \
((INSTANCE) == DFSDM1_Filter3) || \
((INSTANCE) == DFSDM1_Filter4) || \
((INSTANCE) == DFSDM1_Filter5) || \
((INSTANCE) == DFSDM1_Filter6) || \
((INSTANCE) == DFSDM1_Filter7))
#endif /* DFSDM2_Channel0 */
/**
* @}
*/
* @}
*/
/* End of private macros -----------------------------------------------------*/
/**
* @}
*/
*/
/**
* @}

135
targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm_ex.c Normal file
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@ -0,0 +1,135 @@
/**
******************************************************************************
* @file stm32h7xx_hal_dfsdm_ex.c
* @author MCD Application Team
* @brief DFSDM Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionality of the DFSDM Peripheral Controller:
* + Set and get pulses skipping on channel.
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#ifdef HAL_DFSDM_MODULE_ENABLED
#if defined(DFSDM_CHDLYR_PLSSKP)
/** @defgroup DFSDMEx DFSDMEx
* @brief DFSDM Extended HAL module driver
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DFSDMEx_Exported_Functions DFSDM Extended Exported Functions
* @{
*/
/** @defgroup DFSDMEx_Exported_Functions_Group1_Channel Extended channel operation functions
* @brief DFSDM extended channel operation functions
*
@verbatim
===============================================================================
##### Extended channel operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Set and get value of pulses skipping on channel
@endverbatim
* @{
*/
/**
* @brief Set value of pulses skipping.
* @param hdfsdm_channel DFSDM channel handle.
* @param PulsesValue Value of pulses to be skipped.
* This parameter must be a number between Min_Data = 0 and Max_Data = 63.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check pulses value */
assert_param(IS_DFSDM_CHANNEL_SKIPPING_VALUE(PulsesValue));
/* Check DFSDM channel state */
if (hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY)
{
/* Set new value of pulses skipping */
hdfsdm_channel->Instance->CHDLYR = (PulsesValue & DFSDM_CHDLYR_PLSSKP);
}
else
{
status = HAL_ERROR;
}
return status;
}
/**
* @brief Get value of pulses skipping.
* @param hdfsdm_channel DFSDM channel handle.
* @param PulsesValue Value of pulses to be skipped.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check DFSDM channel state */
if (hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY)
{
/* Get value of remaining pulses to be skipped */
*PulsesValue = (hdfsdm_channel->Instance->CHDLYR & DFSDM_CHDLYR_PLSSKP);
}
else
{
status = HAL_ERROR;
}
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* DFSDM_CHDLYR_PLSSKP */
#endif /* HAL_DFSDM_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

93
targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm_ex.h Normal file
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@ -0,0 +1,93 @@
/**
******************************************************************************
* @file stm32h7xx_hal_dfsdm_ex.h
* @author MCD Application Team
* @brief Header file of DFSDM HAL extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7xx_HAL_DFSDM_EX_H
#define STM32H7xx_HAL_DFSDM_EX_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(DFSDM_CHDLYR_PLSSKP)
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup DFSDMEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DFSDMEx_Exported_Functions DFSDM Extended Exported Functions
* @{
*/
/** @addtogroup DFSDMEx_Exported_Functions_Group1_Channel Extended channel operation functions
* @{
*/
HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue);
HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup DFSDMEx_Private_Macros DFSDM Extended Private Macros
* @{
*/
#define IS_DFSDM_CHANNEL_SKIPPING_VALUE(VALUE) ((VALUE) < 64U)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* DFSDM_CHDLYR_PLSSKP */
#ifdef __cplusplus
}
#endif
#endif /* STM32H7xx_HAL_DFSDM_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

316
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dma.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma.c
View File

@ -146,6 +146,19 @@ typedef struct
#define DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U)
#if defined(UART9)
#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \
(((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \
(((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \
(((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX )) || \
(((__REQUEST__) >= DMA_REQUEST_UART9_RX) && ((__REQUEST__) <= DMA_REQUEST_USART10_TX )))
#else
#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \
(((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \
(((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \
(((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX )))
#endif
/**
* @}
*/
@ -278,6 +291,20 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
}
/* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be
lock when transfering data to/from USART/UART */
#if (STM32H7_DEV_ID == 0x450UL)
if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U)
{
#endif /* STM32H7_DEV_ID == 0x450UL */
if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U)
{
registerValue |= DMA_SxCR_TRBUFF;
}
#if (STM32H7_DEV_ID == 0x450UL)
}
#endif /* STM32H7_DEV_ID == 0x450UL */
/* Write to DMA Stream CR register */
((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue;
@ -325,8 +352,11 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
}
else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
{
/* Check the request parameter */
assert_param(IS_BDMA_REQUEST(hdma->Init.Request));
if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
{
/* Check the request parameter */
assert_param(IS_BDMA_REQUEST(hdma->Init.Request));
}
/* Allocate lock resource */
__HAL_UNLOCK(hdma);
@ -344,12 +374,12 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
BDMA_CCR_CT));
/* Prepare the DMA Channel configuration */
registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | \
DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | \
DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | \
DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | \
DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | \
DMA_TO_BDMA_MODE(hdma->Init.Mode) | \
registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) |
DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) |
DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) |
DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) |
DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) |
DMA_TO_BDMA_MODE(hdma->Init.Mode) |
DMA_TO_BDMA_PRIORITY(hdma->Init.Priority);
/* Write to DMA Channel CR register */
@ -373,43 +403,46 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
return HAL_ERROR;
}
/* Initialize parameters for DMAMUX channel :
DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
*/
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* if memory to memory force the request to 0*/
hdma->Init.Request = DMA_REQUEST_MEM2MEM;
}
/* Initialize parameters for DMAMUX channel :
DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
*/
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
/* Set peripheral request to DMAMUX channel */
hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
{
/* if memory to memory force the request to 0*/
hdma->Init.Request = DMA_REQUEST_MEM2MEM;
}
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
/* Set peripheral request to DMAMUX channel */
hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
/* Initialize parameters for DMAMUX request generator :
if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7
*/
if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
{
/* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7
*/
if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
{
/* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
/* Reset the DMAMUX request generator register */
hdma->DMAmuxRequestGen->RGCR = 0U;
/* Reset the DMAMUX request generator register */
hdma->DMAmuxRequestGen->RGCR = 0U;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
else
{
hdma->DMAmuxRequestGen = 0U;
hdma->DMAmuxRequestGenStatus = 0U;
hdma->DMAmuxRequestGenStatusMask = 0U;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
else
{
hdma->DMAmuxRequestGen = 0U;
hdma->DMAmuxRequestGenStatus = 0U;
hdma->DMAmuxRequestGenStatusMask = 0U;
}
}
/* Initialize the error code */
@ -496,35 +529,39 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
return HAL_ERROR;
}
/* Initialize parameters for DMAMUX channel :
DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
if(hdma->DMAmuxChannel != 0U)
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* Resett he DMAMUX channel that corresponds to the DMA stream */
hdma->DMAmuxChannel->CCR = 0U;
/* Initialize parameters for DMAMUX channel :
DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxChannel != 0U)
{
/* Resett he DMAMUX channel that corresponds to the DMA stream */
hdma->DMAmuxChannel->CCR = 0U;
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
}
if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
{
/* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
/* Reset the DMAMUX request generator register */
hdma->DMAmuxRequestGen->RGCR = 0U;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
hdma->DMAmuxRequestGen = 0U;
hdma->DMAmuxRequestGenStatus = 0U;
hdma->DMAmuxRequestGenStatusMask = 0U;
}
if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
{
/* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
/* Reset the DMAMUX request generator register */
hdma->DMAmuxRequestGen->RGCR = 0U;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
hdma->DMAmuxRequestGen = 0U;
hdma->DMAmuxRequestGenStatus = 0U;
hdma->DMAmuxRequestGenStatusMask = 0U;
/* Clean callbacks */
hdma->XferCpltCallback = NULL;
@ -687,18 +724,21 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
}
}
/* Check if DMAMUX Synchronization is enabled */
if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* Enable DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
}
/* Check if DMAMUX Synchronization is enabled */
if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
{
/* Enable DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
}
if(hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
/* enable the request gen overrun IT */
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
if(hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
/* enable the request gen overrun IT */
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
}
}
/* Enable the Peripheral */
@ -775,8 +815,11 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR));
}
/* disable the DMAMUX sync overrun IT */
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* disable the DMAMUX sync overrun IT */
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
}
/* Disable the stream */
__HAL_DMA_DISABLE(hdma);
@ -812,17 +855,20 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
}
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */
/* disable the request gen overrun IT */
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */
/* disable the request gen overrun IT */
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
}
/* Process Unlocked */
@ -874,24 +920,27 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
/* disable the DMAMUX sync overrun IT */
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
/* Clear all flags */
regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT */
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
/* disable the DMAMUX sync overrun IT */
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
/* Clear all flags */
regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT */
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
}
/* Process Unlocked */
@ -1069,42 +1118,46 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
/* if timeout then abort the current transfer */
/* No need to check return value: as in this case we will return HAL_ERROR with HAL_DMA_ERROR_TIMEOUT error code */
(void) HAL_DMA_Abort(hdma);
/*
Note that the Abort function will
- Clear the transfer error flags
- Unlock
- Set the State
*/
/*
Note that the Abort function will
- Clear the transfer error flags
- Unlock
- Set the State
*/
return HAL_ERROR;
}
}
/* Check for DMAMUX Request generator (if used) overrun status */
if(hdma->DMAmuxRequestGen != 0U)
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* if using DMAMUX request generator Check for DMAMUX request generator overrun */
if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
/* Check for DMAMUX Request generator (if used) overrun status */
if(hdma->DMAmuxRequestGen != 0U)
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
/* if using DMAMUX request generator Check for DMAMUX request generator overrun */
if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
}
}
/* Check for DMAMUX Synchronization overrun */
if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
{
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
}
}
/* Check for DMAMUX Synchronization overrun */
if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
{
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
}
}
/* Get the level transfer complete flag */
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
{
@ -1150,7 +1203,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
uint32_t tmpisr_dma, tmpisr_bdma;
uint32_t ccr_reg;
__IO uint32_t count = 0U;
uint32_t timeout = SystemD1Clock / 9600U;
uint32_t timeout = SystemCoreClock / 9600U;
/* calculate DMA base and stream number */
DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress;
@ -1715,13 +1768,16 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress;
BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
}
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */

191
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dma.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma.h
View File

@ -308,7 +308,12 @@ typedef struct __DMA_HandleTypeDef
#define DMA_REQUEST_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */
#define DMA_REQUEST_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */
#define DMA_REQUEST_DCMI 75U /*!< DMAMUX1 DCMI request */
#if defined (PSSI)
#define DMA_REQUEST_DCMI_PSSI 75U /*!< DMAMUX1 DCMI/PSSI request */
#define DMA_REQUEST_DCMI DMA_REQUEST_DCMI_PSSI /* Legacy define */
#else
#define DMA_REQUEST_DCMI 75U /*!< DMAMUX1 DCMI request */
#endif /* PSSI */
#define DMA_REQUEST_CRYP_IN 76U /*!< DMAMUX1 CRYP IN request */
#define DMA_REQUEST_CRYP_OUT 77U /*!< DMAMUX1 CRYP OUT request */
@ -336,12 +341,14 @@ typedef struct __DMA_HandleTypeDef
#define DMA_REQUEST_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request*/
#define DMA_REQUEST_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request*/
#if defined(HRTIM1)
#define DMA_REQUEST_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */
#define DMA_REQUEST_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 TimerA request 2 */
#define DMA_REQUEST_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 TimerB request 3 */
#define DMA_REQUEST_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 TimerC request 4 */
#define DMA_REQUEST_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 TimerD request 5 */
#define DMA_REQUEST_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 TimerE request 6 */
#endif /* HRTIM1 */
#define DMA_REQUEST_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */
#define DMA_REQUEST_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM Filter1 request */
@ -359,10 +366,24 @@ typedef struct __DMA_HandleTypeDef
#define DMA_REQUEST_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */
#define DMA_REQUEST_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */
#if defined(SAI3)
#define DMA_REQUEST_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */
#define DMA_REQUEST_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */
#endif /* SAI3 */
#if defined(ADC3)
#define DMA_REQUEST_ADC3 115U /*!< DMAMUX1 ADC3 request */
#endif /* ADC3 */
#if defined(UART9)
#define DMA_REQUEST_UART9_RX 116U /*!< DMAMUX1 UART9 request */
#define DMA_REQUEST_UART9_TX 117U /*!< DMAMUX1 UART9 request */
#endif /* UART9 */
#if defined(USART10)
#define DMA_REQUEST_USART10_RX 118U /*!< DMAMUX1 USART10 request */
#define DMA_REQUEST_USART10_TX 119U /*!< DMAMUX1 USART10 request */
#endif /* USART10 */
/* DMAMUX2 requests */
@ -381,9 +402,19 @@ typedef struct __DMA_HandleTypeDef
#define BDMA_REQUEST_SPI6_TX 12U /*!< DMAMUX2 SPI6 TX request */
#define BDMA_REQUEST_I2C4_RX 13U /*!< DMAMUX2 I2C4 RX request */
#define BDMA_REQUEST_I2C4_TX 14U /*!< DMAMUX2 I2C4 TX request */
#if defined(SAI4)
#define BDMA_REQUEST_SAI4_A 15U /*!< DMAMUX2 SAI4 A request */
#define BDMA_REQUEST_SAI4_B 16U /*!< DMAMUX2 SAI4 B request */
#endif /* SAI4 */
#if defined(ADC3)
#define BDMA_REQUEST_ADC3 17U /*!< DMAMUX2 ADC3 request */
#endif /* ADC3 */
#if defined(DAC2)
#define BDMA_REQUEST_DAC2_CH1 17U /*!< DMAMUX2 DAC2 CH1 request */
#endif /* DAC2 */
#if defined(DFSDM2_Channel0)
#define BDMA_REQUEST_DFSDM2_FLT0 18U /*!< DMAMUX2 DFSDM2 request */
#endif /* DFSDM1_Channel0 */
/**
* @}
@ -649,6 +680,42 @@ typedef struct __DMA_HandleTypeDef
* @param __HANDLE__: DMA handle
* @retval The specified transfer complete flag index.
*/
#if defined(BDMA1)
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TC0 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TC0 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TC6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TC6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TC7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TC7 :\
(uint32_t)0x00000000)
#else
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
@ -675,12 +742,49 @@ typedef struct __DMA_HandleTypeDef
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7 :\
(uint32_t)0x00000000)
#endif /* BDMA1 */
/**
* @brief Return the current DMA Stream half transfer complete flag.
* @param __HANDLE__: DMA handle
* @retval The specified half transfer complete flag index.
*/
#if defined(BDMA1)
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_HT0 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_HT0 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_HT6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_HT6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_HT7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_HT7 :\
(uint32_t)0x00000000)
#else
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
@ -707,12 +811,49 @@ typedef struct __DMA_HandleTypeDef
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7 :\
(uint32_t)0x00000000)
#endif /* BDMA1 */
/**
* @brief Return the current DMA Stream transfer error flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#if defined(BDMA1)
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TE0 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TE0 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TE6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TE6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TE7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TE7 :\
(uint32_t)0x00000000)
#else
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
@ -739,6 +880,7 @@ typedef struct __DMA_HandleTypeDef
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7 :\
(uint32_t)0x00000000)
#endif /* BDMA1 */
/**
* @brief Return the current DMA Stream FIFO error flag.
@ -793,6 +935,26 @@ typedef struct __DMA_HandleTypeDef
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#if defined(BDMA1)
#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_ISR_GIF0 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_ISR_GIF0 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_ISR_GIF6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_ISR_GIF6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_ISR_GIF7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_ISR_GIF7 :\
(uint32_t)0x00000000)
#else
#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\
@ -803,6 +965,7 @@ typedef struct __DMA_HandleTypeDef
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\
(uint32_t)0x00000000)
#endif /* BDMA1 */
/**
* @brief Get the DMA Stream pending flags.
@ -817,11 +980,20 @@ typedef struct __DMA_HandleTypeDef
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
* @retval The state of FLAG (SET or RESET).
*/
#if defined(BDMA1)
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->ISR & (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7 )? (BDMA1->ISR & (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3 )? (DMA2->HISR & (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7 )? (DMA2->LISR & (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3 )? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
#else
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
#endif /* BDMA1 */
/**
* @brief Clear the DMA Stream pending flags.
@ -836,11 +1008,20 @@ typedef struct __DMA_HandleTypeDef
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
* @retval None
*/
#if defined(BDMA1)
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->IFCR = (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA1->IFCR = (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
#else
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
#endif /* BDMA1 */
#define DMA_TO_BDMA_IT(__DMA_IT__) \
((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
@ -1019,9 +1200,17 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
* @{
*/
#if defined(ADC3)
#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3))
#else
#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX))
#endif /* ADC3 */
#if defined(ADC3)
#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3))
#else
#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2_FLT0))
#endif /* ADC3 */
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \

184
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dma2d.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma2d.c
View File

@ -249,6 +249,8 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->Init.AlphaInverted));
assert_param(IS_DMA2D_RB_SWAP(hdma2d->Init.RedBlueSwap));
assert_param(IS_DMA2D_LOM_MODE(hdma2d->Init.LineOffsetMode));
assert_param(IS_DMA2D_BYTES_SWAP(hdma2d->Init.BytesSwap));
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
if (hdma2d->State == HAL_DMA2D_STATE_RESET)
@ -278,10 +280,10 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* DMA2D CR register configuration -------------------------------------------*/
MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE | DMA2D_CR_LOM, hdma2d->Init.Mode | hdma2d->Init.LineOffsetMode);
/* DMA2D OPFCCR register configuration ---------------------------------------*/
MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB, hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap);
/* DMA2D OOR register configuration ------------------------------------------*/
MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
@ -747,11 +749,28 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure DMA2D Stream source2 address */
WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
{
/*blending & fixed FG*/
WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
/* Configure the source, destination address and the data size */
DMA2D_SetConfig(hdma2d, SrcAddress2, DstAddress, Width, Height);
}
else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_BG)
{
/*blending & fixed BG*/
WRITE_REG(hdma2d->Instance->BGCOLR, SrcAddress2);
/* Configure the source, destination address and the data size */
DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
}
else
{
/* Configure DMA2D Stream source2 address */
WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
/* Configure the source, destination address and the data size */
DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
/* Configure the source, destination address and the data size */
DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
}
/* Enable the Peripheral */
__HAL_DMA2D_ENABLE(hdma2d);
@ -782,11 +801,27 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure DMA2D Stream source2 address */
WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
{
/*blending & fixed FG*/
WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
/* Configure the source, destination address and the data size */
DMA2D_SetConfig(hdma2d, SrcAddress2, DstAddress, Width, Height);
}
else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_BG)
{
/*blending & fixed BG*/
WRITE_REG(hdma2d->Instance->BGCOLR, SrcAddress2);
/* Configure the source, destination address and the data size */
DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
}
else
{
WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
/* Configure the source, destination address and the data size */
DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
/* Configure the source, destination address and the data size */
DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
}
/* Enable the transfer complete, transfer error and configuration error interrupts */
__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
@ -954,6 +989,119 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay
return HAL_OK;
}
/**
* @brief Start DMA2D CLUT Loading.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
* the configuration information for the color look up table.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
/* Process locked */
__HAL_LOCK(hdma2d);
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
if(LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
/* Enable the CLUT loading for the background */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
}
/* Configure the CLUT of the foreground DMA2D layer */
else
{
/* Write foreground CLUT memory address */
WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
/* Enable the CLUT loading for the foreground */
SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
}
return HAL_OK;
}
/**
* @brief Start DMA2D CLUT Loading with interrupt enabled.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
* the configuration information for the color look up table.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
/* Process locked */
__HAL_LOCK(hdma2d);
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
if(LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
/* Enable the CLUT loading for the background */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
}
/* Configure the CLUT of the foreground DMA2D layer */
else
{
/* Write foreground CLUT memory address */
WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
/* Enable the CLUT loading for the foreground */
SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
}
return HAL_OK;
}
/**
* @brief Start DMA2D CLUT Loading.
@ -964,7 +1112,9 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
* @note API obsolete and maintained for compatibility with legacy. User is
* invited to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from
* code compactness, code size and improved heap usage.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
@ -1019,6 +1169,9 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgT
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @note API obsolete and maintained for compatibility with legacy. User is
* invited to resort to HAL_DMA2D_CLUTStartLoad_IT() instead to benefit
* from code compactness, code size and improved heap usage.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
@ -1699,6 +1852,9 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @note API obsolete and maintained for compatibility with legacy. User is invited
* to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from code compactness,
* code size and improved heap usage.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
@ -1983,7 +2139,11 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_
/* Write to DMA2D OCOLR register */
WRITE_REG(hdma2d->Instance->OCOLR, tmp);
}
else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
else if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) /*M2M_blending with fixed color FG DMA2D Mode selected*/
{
WRITE_REG(hdma2d->Instance->BGMAR , pdata);
}
else /* M2M, M2M_PFC,M2M_Blending or M2M_blending with fixed color BG DMA2D Mode */
{
/* Configure DMA2D source address */
WRITE_REG(hdma2d->Instance->FGMAR, pdata);

40
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dma2d.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma2d.h
View File

@ -32,6 +32,8 @@
* @{
*/
#if defined (DMA2D)
/** @addtogroup DMA2D DMA2D
* @brief DMA2D HAL module driver
* @{
@ -78,7 +80,11 @@ typedef struct
This parameter can be one value of @ref DMA2D_RB_Swap. */
uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two).
This parameter can be one value of @ref DMA2D_Bytes_Swap. */
uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output.
This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */
} DMA2D_InitTypeDef;
@ -199,7 +205,9 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Poin
#define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
#define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
#define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */
#define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */
#define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */
/**
* @}
*/
@ -266,7 +274,23 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Poin
/** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode
* @{
*/
#define DMA2D_LOM_PIXELS 0x00000000U /*!< Line offsets expressed in pixels */
#define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */
/**
* @}
*/
/** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap
* @{
*/
#define DMA2D_BYTES_REGULAR 0x00000000U /*!< Bytes in regular order in output FIFO */
#define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */
/**
* @}
*/
/** @defgroup DMA2D_Chroma_Sub_Sampling DMA2D Chroma Sub Sampling
* @{
@ -486,6 +510,8 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
@ -607,8 +633,9 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
*/
#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER))
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \
((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG))
#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
@ -636,7 +663,11 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
((RB_Swap) == DMA2D_RB_SWAP))
#define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \
((LOM) == DMA2D_LOM_BYTES))
#define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \
((BYTES_SWAP) == DMA2D_BYTES_SWAP))
#define IS_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == DMA2D_NO_CSS) || \
((CSS) == DMA2D_CSS_422) || \
@ -659,11 +690,12 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
* @}
*/
#endif /* defined (DMA2D) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif

59
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dma_ex.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma_ex.c
View File

@ -175,16 +175,19 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t S
*ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
}
/* Configure the source, destination address and the data length */
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
/* Configure the source, destination address and the data length */
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
}
/* Enable the peripheral */
@ -271,13 +274,16 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_
/* Configure the source, destination address and the data length */
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
}
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
@ -304,18 +310,21 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_
}
}
/* Check if DMAMUX Synchronization is enabled*/
if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* Enable DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
}
/* Check if DMAMUX Synchronization is enabled*/
if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
{
/* Enable DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
}
if(hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
/* enable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
if(hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
/* enable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
}
}
/* Enable the peripheral */

6
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dma_ex.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma_ex.h
View File

@ -177,8 +177,12 @@ typedef struct
#define HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT */
#define HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup */
#define HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT */
#if defined(LPTIM4)
#define HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup */
#endif /* LPTIM4 */
#if defined(LPTIM5)
#define HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup */
#endif /* LPTIM5 */
#define HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup */
#define HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup */
#define HAL_DMAMUX2_REQ_GEN_COMP1_OUT 17U /*!< DMAMUX2 Request generator Signal is Comparator 1 output */
@ -190,8 +194,10 @@ typedef struct
#define HAL_DMAMUX2_REQ_GEN_SPI6_IT 23U /*!< DMAMUX2 Request generator Signal is SPI6 IT */
#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT */
#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT */
#if defined(ADC3)
#define HAL_DMAMUX2_REQ_GEN_ADC3_IT 26U /*!< DMAMUX2 Request generator Signal is ADC3 IT */
#define HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */
#endif /* ADC3 */
#define HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT */
#define HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT */

0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dsi.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.c
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0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dsi.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.h
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823
targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dts.c Normal file
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/**
******************************************************************************
* @file stm32h7xx_hal_dts.c
* @author MCD Application Team
* @brief DTS HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the DTS peripheral:
* + Initialization and de-initialization functions
* + Start/Stop operation functions in polling mode.
* + Start/Stop operation functions in interrupt mode.
* + Peripheral Control functions
* + Peripheral State functions
*
@verbatim
================================================================================
##### DTS Peripheral features #####
================================================================================
[..]
The STM32h7xx device family integrate one DTS sensor interface :
##### How to use this driver #####
================================================================================
[..]
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#ifdef HAL_DTS_MODULE_ENABLED
#if defined(DTS)
/** @defgroup DTS DTS
* @brief DTS HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup DTS_Private_Constants
* @{
*/
/* @brief Delay for DTS startup time
* @note Delay required to get ready for DTS Block.
* @note Unit: ms
*/
#define DTS_DELAY_STARTUP (1UL)
/* @brief DTS measure ready flag time out value.
* @note Maximal measurement time is when LSE is selected as ref_clock and
* maximal sampling time is used, taking calibration into account this
* is equivalent to ~620 us. Use 5 ms as arbitrary timeout
* @note Unit: ms
*/
#define TS_TIMEOUT_MS (5UL)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
static void DTS_ResetCallback(DTS_HandleTypeDef *hdts);
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
/* Exported functions --------------------------------------------------------*/
/** @defgroup DTS_Exported_Functions DTS Exported Functions
* @{
*/
/** @defgroup DTS_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and de-initialization functions.
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions to initialize and de-initialize comparators
@endverbatim
* @{
*/
/**
* @brief Initialize the DTS according to the specified
* parameters in the DTS_InitTypeDef and initialize the associated handle.
* @param hdts DTS handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts)
{
/* Check the DTS handle allocation */
if (hdts == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
assert_param(IS_DTS_QUICKMEAS(hdts->Init.QuickMeasure));
assert_param(IS_DTS_REFCLK(hdts->Init.RefClock));
assert_param(IS_DTS_TRIGGERINPUT(hdts->Init.TriggerInput));
assert_param(IS_DTS_SAMPLINGTIME(hdts->Init.SamplingTime));
assert_param(IS_DTS_THRESHOLD(hdts->Init.HighThreshold));
assert_param(IS_DTS_THRESHOLD(hdts->Init.LowThreshold));
if (hdts->State == HAL_DTS_STATE_RESET)
{
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
/* Reset interrupt callbacks to legacy weak callbacks */
DTS_ResetCallback(hdts);
if (hdts->MspInitCallback == NULL)
{
hdts->MspInitCallback = HAL_DTS_MspInit;
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
hdts->MspInitCallback(hdts);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_DTS_MspInit(hdts);
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
}
/* Change the DTS state */
hdts->State = HAL_DTS_STATE_BUSY;
/* Check ramp coefficient */
if (hdts->Instance->RAMPVALR == 0UL)
{
return HAL_ERROR;
}
/* Check factory calibration temperature */
if (hdts->Instance->T0VALR1 == 0UL)
{
return HAL_ERROR;
}
/* Check Quick Measure option is enabled or disabled */
if (hdts->Init.QuickMeasure == DTS_QUICKMEAS_DISABLE)
{
/* Check Reference clock selection */
if (hdts->Init.RefClock == DTS_REFCLKSEL_PCLK)
{
assert_param(IS_DTS_DIVIDER_RATIO_NUMBER(hdts->Init.Divider));
}
/* Quick measurement mode disabled */
CLEAR_BIT(hdts->Instance->CFGR1, DTS_CFGR1_Q_MEAS_OPT);
}
else
{
/* DTS_QUICKMEAS_ENABLE shall be used only when the LSE clock is
selected as reference clock */
if (hdts->Init.RefClock != DTS_REFCLKSEL_LSE)
{
return HAL_ERROR;
}
/* Quick measurement mode enabled - no calibration needed */
SET_BIT(hdts->Instance->CFGR1, DTS_CFGR1_Q_MEAS_OPT);
}
/* set the DTS clk source */
if (hdts->Init.RefClock == DTS_REFCLKSEL_LSE)
{
SET_BIT(hdts->Instance->CFGR1, DTS_CFGR1_REFCLK_SEL);
}
else
{
CLEAR_BIT(hdts->Instance->CFGR1, DTS_CFGR1_REFCLK_SEL);
}
MODIFY_REG(hdts->Instance->CFGR1, DTS_CFGR1_HSREF_CLK_DIV, (hdts->Init.Divider << DTS_CFGR1_HSREF_CLK_DIV_Pos));
MODIFY_REG(hdts->Instance->CFGR1, DTS_CFGR1_TS1_SMP_TIME, hdts->Init.SamplingTime);
MODIFY_REG(hdts->Instance->CFGR1, DTS_CFGR1_TS1_INTRIG_SEL, hdts->Init.TriggerInput);
MODIFY_REG(hdts->Instance->ITR1, DTS_ITR1_TS1_HITTHD, (hdts->Init.HighThreshold << DTS_ITR1_TS1_HITTHD_Pos));
MODIFY_REG(hdts->Instance->ITR1, DTS_ITR1_TS1_LITTHD, hdts->Init.LowThreshold);
/* Change the DTS state */
hdts->State = HAL_DTS_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitialize the DTS peripheral.
* @note Deinitialization cannot be performed if the DTS configuration is locked.
* To unlock the configuration, perform a system reset.
* @param hdts DTS handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DTS_DeInit(DTS_HandleTypeDef *hdts)
{
/* Check the DTS handle allocation */
if (hdts == NULL)
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
/* Set DTS_CFGR register to reset value */
CLEAR_REG(hdts->Instance->CFGR1);
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
if (hdts->MspDeInitCallback == NULL)
{
hdts->MspDeInitCallback = HAL_DTS_MspDeInit;
}
/* DeInit the low level hardware: CLOCK, NVIC.*/
hdts->MspDeInitCallback(hdts);
#else
/* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_DTS_MspDeInit(hdts);
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
hdts->State = HAL_DTS_STATE_RESET;
return HAL_OK;
}
/**
* @brief Initialize the DTS MSP.
* @param hdts DTS handle
* @retval None
*/
__weak void HAL_DTS_MspInit(DTS_HandleTypeDef *hdts)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdts);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DTS_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitialize the DTS MSP.
* @param hdts DTS handle
* @retval None
*/
__weak void HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdts);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DTS_MspDeInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup DTS_Exported_Functions_Group2 Start-Stop operation functions
* @brief Start-Stop operation functions.
*
@verbatim
===============================================================================
##### DTS Start Stop operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Start a DTS Sensor without interrupt.
(+) Stop a DTS Sensor without interrupt.
(+) Start a DTS Sensor with interrupt generation.
(+) Stop a DTS Sensor with interrupt generation.
@endverbatim
* @{
*/
/**
* @brief Start the DTS sensor.
* @param hdts DTS handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DTS_Start(DTS_HandleTypeDef *hdts)
{
uint32_t Ref_Time;
/* Check the DTS handle allocation */
if (hdts == NULL)
{
return HAL_ERROR;
}
if (hdts->State == HAL_DTS_STATE_READY)
{
hdts->State = HAL_DTS_STATE_BUSY;
/* Enable DTS sensor */
__HAL_DTS_ENABLE(hdts);
/* Get Start Tick*/
Ref_Time = HAL_GetTick();
/* Wait till TS1_RDY flag is set */
while (__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_RDY) == RESET)
{
if ((HAL_GetTick() - Ref_Time) > DTS_DELAY_STARTUP)
{
return HAL_TIMEOUT;
}
}
if (__HAL_DTS_GET_TRIGGER(hdts) == DTS_TRIGGER_HW_NONE)
{
/* Start continuous measures */
SET_BIT(hdts->Instance->CFGR1, DTS_CFGR1_TS1_START);
/* Ensure start is taken into account */
HAL_Delay(TS_TIMEOUT_MS);
}
hdts->State = HAL_DTS_STATE_READY;
}
else
{
return HAL_BUSY;
}
return HAL_OK;
}
/**
* @brief Stop the DTS Sensor.
* @param hdts DTS handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DTS_Stop(DTS_HandleTypeDef *hdts)
{
/* Check the DTS handle allocation */
if (hdts == NULL)
{
return HAL_ERROR;
}
if (hdts->State == HAL_DTS_STATE_READY)
{
hdts->State = HAL_DTS_STATE_BUSY;
if (__HAL_DTS_GET_TRIGGER(hdts) == DTS_TRIGGER_HW_NONE)
{
CLEAR_BIT(hdts->Instance->CFGR1, DTS_CFGR1_TS1_START);
}
/* Disable the selected DTS sensor */
__HAL_DTS_DISABLE(hdts);
hdts->State = HAL_DTS_STATE_READY;
}
else
{
return HAL_BUSY;
}
return HAL_OK;
}
/**
* @brief Enable the interrupt(s) and start the DTS sensor
* @param hdts DTS handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DTS_Start_IT(DTS_HandleTypeDef *hdts)
{
uint32_t Ref_Time;
/* Check the DTS handle allocation */
if (hdts == NULL)
{
return HAL_ERROR;
}
if (hdts->State == HAL_DTS_STATE_READY)
{
hdts->State = HAL_DTS_STATE_BUSY;
/* On Asynchronous mode enable the asynchronous IT */
if (hdts->Init.RefClock == DTS_REFCLKSEL_LSE)
{
__HAL_DTS_ENABLE_IT(hdts, DTS_IT_TS1_AITE | DTS_IT_TS1_AITL | DTS_IT_TS1_AITH);
}
else
{
/* Enable the IT(s) */
__HAL_DTS_ENABLE_IT(hdts, DTS_IT_TS1_ITE | DTS_IT_TS1_ITL | DTS_IT_TS1_ITH);
}
/* Enable the selected DTS sensor */
__HAL_DTS_ENABLE(hdts);
/* Get Start Tick*/
Ref_Time = HAL_GetTick();
/* Wait till TS1_RDY flag is set */
while (__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_RDY) == RESET)
{
if ((HAL_GetTick() - Ref_Time) > DTS_DELAY_STARTUP)
{
return HAL_TIMEOUT;
}
}
if (__HAL_DTS_GET_TRIGGER(hdts) == DTS_TRIGGER_HW_NONE)
{
/* Start continuous measures */
SET_BIT(hdts->Instance->CFGR1, DTS_CFGR1_TS1_START);
/* Ensure start is taken into account */
HAL_Delay(TS_TIMEOUT_MS);
}
hdts->State = HAL_DTS_STATE_READY;
}
else
{
return HAL_BUSY;
}
return HAL_OK;
}
/**
* @brief Disable the interrupt(s) and stop the DTS sensor.
* @param hdts DTS handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DTS_Stop_IT(DTS_HandleTypeDef *hdts)
{
/* Check the DTS handle allocation */
if (hdts == NULL)
{
return HAL_ERROR;
}
if (hdts->State == HAL_DTS_STATE_READY)
{
hdts->State = HAL_DTS_STATE_BUSY;
/* On Asynchronous mode disable the asynchronous IT */
if (hdts->Init.RefClock == DTS_REFCLKSEL_LSE)
{
__HAL_DTS_DISABLE_IT(hdts, DTS_IT_TS1_AITE | DTS_IT_TS1_AITL | DTS_IT_TS1_AITH);
}
else
{
/* Disable the IT(s) */
__HAL_DTS_DISABLE_IT(hdts, DTS_IT_TS1_ITE | DTS_IT_TS1_ITL | DTS_IT_TS1_ITH);
}
if (__HAL_DTS_GET_TRIGGER(hdts) == DTS_TRIGGER_HW_NONE)
{
CLEAR_BIT(hdts->Instance->CFGR1, DTS_CFGR1_TS1_START);
}
/* Disable the selected DTS sensor */
__HAL_DTS_DISABLE(hdts);
hdts->State = HAL_DTS_STATE_READY;
}
else
{
return HAL_BUSY;
}
return HAL_OK;
}
/**
* @brief Get temperature from DTS
* @param hdts DTS handle
* @param Temperature Temperature in deg C
* @note This function retrieves latest available measure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts, int32_t *Temperature)
{
uint32_t freq_meas;
uint32_t samples;
uint32_t t0_temp;
uint32_t t0_freq;
uint32_t ramp_coeff;
if (hdts->State == HAL_DTS_STATE_READY)
{
hdts->State = HAL_DTS_STATE_BUSY;
/* Get the total number of samples */
samples = (hdts->Instance->DR & DTS_DR_TS1_MFREQ);
if ((hdts->Init.SamplingTime == 0UL) || (samples == 0UL))
{
hdts->State = HAL_DTS_STATE_READY;
return HAL_ERROR;
}
if ((hdts->Init.RefClock) == DTS_REFCLKSEL_LSE)
{
freq_meas = (LSE_VALUE * samples) / (hdts->Init.SamplingTime >> DTS_CFGR1_TS1_SMP_TIME_Pos); /* On Hz */
}
else
{
freq_meas = (HAL_RCCEx_GetD3PCLK1Freq() * (hdts->Init.SamplingTime >> DTS_CFGR1_TS1_SMP_TIME_Pos)) / samples; /* On Hz */
}
/* Read factory settings */
t0_temp = hdts->Instance->T0VALR1 >> DTS_T0VALR1_TS1_T0_Pos;
if (t0_temp == 0UL)
{
t0_temp = 30UL; /* 30 deg C */
}
else if (t0_temp == 1UL)
{
t0_temp = 110UL; /* 110 deg C */
}
else
{
hdts->State = HAL_DTS_STATE_READY;
return HAL_ERROR;
}
t0_freq = (hdts->Instance->T0VALR1 & DTS_T0VALR1_TS1_FMT0) * 100UL; /* Hz */
ramp_coeff = hdts->Instance->RAMPVALR & DTS_RAMPVALR_TS1_RAMP_COEFF; /* deg C/Hz */
if (ramp_coeff == 0UL)
{
hdts->State = HAL_DTS_STATE_READY;
return HAL_ERROR;
}
/* Figure out the temperature deg C */
*Temperature = (int32_t)t0_temp + (((int32_t)freq_meas - (int32_t)t0_freq) / (int32_t)ramp_coeff);
hdts->State = HAL_DTS_STATE_READY;
}
else
{
return HAL_BUSY;
}
return HAL_OK;
}
/**
* @brief DTS sensor IRQ Handler.
* @param hdts DTS handle
* @retval None
*/
void HAL_DTS_IRQHandler(DTS_HandleTypeDef *hdts)
{
/* Check end of measure Asynchronous IT */
if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_AITE)) != RESET)
{
__HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_AITE);
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
hdts->AsyncEndCallback(hdts);
#else
HAL_DTS_AsyncEndCallback(hdts);
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
}
/* Check low threshold Asynchronous IT */
if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_AITL)) != RESET)
{
__HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_AITL);
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
hdts->AsyncLowCallback(hdts);
#else
HAL_DTS_AsyncLowCallback(hdts);
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
}
/* Check high threshold Asynchronous IT */
if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_AITH)) != RESET)
{
__HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_AITH);
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
hdts->AsyncHighCallback(hdts);
#else
HAL_DTS_AsyncHighCallback(hdts);
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
}
/* Check end of measure IT */
if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_ITE)) != RESET)
{
__HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_ITE);
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
hdts->EndCallback(hdts);
#else
HAL_DTS_EndCallback(hdts);
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
}
/* Check low threshold IT */
if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_ITL)) != RESET)
{
__HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_ITL);
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
hdts->LowCallback(hdts);
#else
HAL_DTS_LowCallback(hdts);
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
}
/* Check high threshold IT */
if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_ITH)) != RESET)
{
__HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_ITH);
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
hdts->HighCallback(hdts);
#else
HAL_DTS_HighCallback(hdts);
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
}
}
/**
* @brief DTS Sensor End measure callback.
* @param hdts DTS handle
* @retval None
*/
__weak void HAL_DTS_EndCallback(DTS_HandleTypeDef *hdts)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdts);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DTS_EndCallback should be implemented in the user file
*/
}
/**
* @brief DTS Sensor low threshold measure callback.
* @param hdts DTS handle
* @retval None
*/
__weak void HAL_DTS_LowCallback(DTS_HandleTypeDef *hdts)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdts);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DTS_LowCallback should be implemented in the user file
*/
}
/**
* @brief DTS Sensor high threshold measure callback.
* @param hdts DTS handle
* @retval None
*/
__weak void HAL_DTS_HighCallback(DTS_HandleTypeDef *hdts)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdts);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DTS_HighCallback should be implemented in the user file
*/
}
/**
* @brief DTS Sensor asynchronous end measure callback.
* @param hdts DTS handle
* @retval None
*/
__weak void HAL_DTS_AsyncEndCallback(DTS_HandleTypeDef *hdts)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdts);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DTS_AsyncEndCallback should be implemented in the user file
*/
}
/**
* @brief DTS Sensor asynchronous low threshold measure callback.
* @param hdts DTS handle
* @retval None
*/
__weak void HAL_DTS_AsyncLowCallback(DTS_HandleTypeDef *hdts)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdts);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DTS_AsyncLowCallback should be implemented in the user file
*/
}
/**
* @brief DTS Sensor asynchronous high threshold measure callback.
* @param hdts DTS handle
* @retval None
*/
__weak void HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdts);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DTS_AsyncHighCallback should be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup DTS_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral.
@endverbatim
* @{
*/
/**
* @brief Return the DTS handle state.
* @param hdts DTS handle
* @retval HAL state
*/
HAL_DTS_StateTypeDef HAL_DTS_GetState(DTS_HandleTypeDef *hdts)
{
/* Check the DTS handle allocation */
if (hdts == NULL)
{
return HAL_DTS_STATE_RESET;
}
/* Return DTS handle state */
return hdts->State;
}
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DTS_Private_Functions DTS Private Functions
* @{
*/
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
/**
* @brief Reset interrupt callbacks to the legacy weak callbacks.
* @param hdts pointer to a DTS_HandleTypeDef structure that contains
* the configuration information for DTS module.
* @retval None
*/
static void DTS_ResetCallback(DTS_HandleTypeDef *hdts)
{
/* Reset the DTS callback to the legacy weak callbacks */
hdts->DTS_EndCallback = HAL_DTS_EndCallback; /* End measure Callback */
hdts->DTS_LowCallback = HAL_DTS_LowCallback; /* low threshold Callback */
hdts->DTS_HighCallback = HAL_DTS_HighCallback; /* high threshold Callback */
hdts->DTS_AsyncEndCallback = HAL_DTS_AsyncEndCallback; /* Asynchronous end of measure Callback */
hdts->DTS_AsyncLowCallback = HAL_DTS_AsyncLowCallback; /* Asynchronous low threshold Callback */
hdts->DTS_AsyncHighCallback = HAL_DTS_AsyncHighCallback; /* Asynchronous high threshold Callback */
}
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
#endif /* DTS */
#endif /* HAL_DTS_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dts.h Normal file
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@ -0,0 +1,483 @@
/**
******************************************************************************
* @file stm32h7xx_hal_dts.h
* @author MCD Application Team
* @brief Header file of DTS HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_DTS_H
#define __STM32H7xx_HAL_DTS_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(DTS)
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup DTS
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DTS_Exported_Types DTS Exported Types
* @{
*/
/**
* @brief DTS Init structure definition
*/
typedef struct
{
uint32_t QuickMeasure; /*!< Specifies the quick measure option selection of the DTS sensor.
This parameter can be a value of @ref DTS_Quick_Measurement */
uint32_t RefClock; /*!< Specifies the reference clock selection of the DTS sensor.
This parameter can be a value of @ref DTS_Reference_Clock_Selection */
uint32_t TriggerInput; /*!< Specifies the trigger input of the DTS sensor.
This parameter can be a value of @ref DTS_TriggerConfig */
uint32_t SamplingTime; /*!< Specifies the sampling time configuration.
This parameter can be a value of @ref DTS_Sampling_Time */
uint32_t Divider; /*!< Specifies the high speed clock divider ratio.
This parameter can be a value from 0 to 127 */
uint32_t HighThreshold; /*!< Specifies the high threshold of the DTS sensor */
uint32_t LowThreshold; /*!< Specifies the low threshold of the DTS sensor */
} DTS_InitTypeDef;
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_DTS_STATE_RESET = 0x00UL, /*!< DTS not yet initialized or disabled */
HAL_DTS_STATE_READY = 0x01UL, /*!< DTS initialized and ready for use */
HAL_DTS_STATE_BUSY = 0x02UL, /*!< DTS is running */
HAL_DTS_STATE_TIMEOUT = 0x03UL, /*!< Timeout state */
HAL_DTS_STATE_ERROR = 0x04UL /*!< Internal Process error */
} HAL_DTS_StateTypeDef;
/**
* @brief DTS Handle Structure definition
*/
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
typedef struct __DTS_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
{
DTS_TypeDef *Instance; /*!< Register base address */
DTS_InitTypeDef Init; /*!< DTS required parameters */
HAL_LockTypeDef Lock; /*!< DTS Locking object */
__IO HAL_DTS_StateTypeDef State; /*!< DTS peripheral state */
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __DTS_HandleTypeDef *hdts); /*!< DTS Base Msp Init Callback */
void (* MspDeInitCallback)(struct __DTS_HandleTypeDef *hdts); /*!< DTS Base Msp DeInit Callback */
void (* DTS_EndCallback)(struct __DTS_HandleTypeDef *hdts); /*!< End measure Callback */
void (* DTS_LowCallback)(struct __DTS_HandleTypeDef *hdts); /*!< low threshold Callback */
void (* DTS_HighCallback)(struct __DTS_HandleTypeDef *hdts); /*!< high threshold Callback */
void (* DTS_AsyncEndCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous end of measure Callback */
void (* DTS_AsyncLowCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous low threshold Callback */
void (* DTS_AsyncHighCallback(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous high threshold Callback */
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
} DTS_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DTS_Exported_Constants DTS Exported Constants
* @{
*/
/** @defgroup DTS_TriggerConfig DTS Trigger Configuration
* @{
*/
/* @brief No Hardware trigger detection */
#define DTS_TRIGGER_HW_NONE (0UL)
/* @brief External Interrupt Mode with LPTIMER1 trigger detection */
#define DTS_TRIGGER_LPTIMER1 DTS_CFGR1_TS1_INTRIG_SEL_0
/* @brief External Interrupt Mode with LPTIMER2 trigger detection */
#define DTS_TRIGGER_LPTIMER2 DTS_CFGR1_TS1_INTRIG_SEL_1
/* @brief External Interrupt Mode with LPTIMER3 trigger detection */
#define DTS_TRIGGER_LPTIMER3 (DTS_CFGR1_TS1_INTRIG_SEL_0 | DTS_CFGR1_TS1_INTRIG_SEL_1)
/* @brief External Interrupt Mode with EXTI13 trigger detection */
#define DTS_TRIGGER_EXTI13 DTS_CFGR1_TS1_INTRIG_SEL_2
/**
* @}
*/
/** @defgroup DTS_Quick_Measurement DTS Quick Measurement
* @{
*/
#define DTS_QUICKMEAS_ENABLE DTS_CFGR1_Q_MEAS_OPT /*!< Enable the Quick Measure (Measure without calibration) */
#define DTS_QUICKMEAS_DISABLE (0x0UL) /*!< Disable the Quick Measure (Measure with calibration) */
/**
* @}
*/
/** @defgroup DTS_Reference_Clock_Selection DTS Reference Clock Selection
* @{
*/
#define DTS_REFCLKSEL_LSE DTS_CFGR1_REFCLK_SEL /*!< Low speed REF clock (LSE) */
#define DTS_REFCLKSEL_PCLK (0UL) /*!< High speed REF clock (PCLK) */
/**
* @}
*/
/** @defgroup DTS_Sampling_Time DTS Sampling Time
* @{
*/
#define DTS_SMP_TIME_1_CYCLE DTS_CFGR1_TS1_SMP_TIME_0 /*!< 1 clock cycle for the sampling time */
#define DTS_SMP_TIME_2_CYCLE DTS_CFGR1_TS1_SMP_TIME_1 /*!< 2 clock cycle for the sampling time */
#define DTS_SMP_TIME_3_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_1) /*!< 3 clock cycle for the sampling time */
#define DTS_SMP_TIME_4_CYCLE (DTS_CFGR1_TS1_SMP_TIME_2) /*!< 4 clock cycle for the sampling time */
#define DTS_SMP_TIME_5_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_2) /*!< 5 clock cycle for the sampling time */
#define DTS_SMP_TIME_6_CYCLE (DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_2) /*!< 6 clock cycle for the sampling time */
#define DTS_SMP_TIME_7_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_2) /*!< 7 clock cycle for the sampling time */
#define DTS_SMP_TIME_8_CYCLE (DTS_CFGR1_TS1_SMP_TIME_3) /*!< 8 clock cycle for the sampling time */
#define DTS_SMP_TIME_9_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_3) /*!< 9 clock cycle for the sampling time */
#define DTS_SMP_TIME_10_CYCLE (DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_3) /*!< 10 clock cycle for the sampling time */
#define DTS_SMP_TIME_11_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_3) /*!< 11 clock cycle for the sampling time */
#define DTS_SMP_TIME_12_CYCLE (DTS_CFGR1_TS1_SMP_TIME_2 | DTS_CFGR1_TS1_SMP_TIME_3) /*!< 12 clock cycle for the sampling time */
#define DTS_SMP_TIME_13_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_2 | DTS_CFGR1_TS1_SMP_TIME_3) /*!< 13 clock cycle for the sampling time */
#define DTS_SMP_TIME_14_CYCLE (DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_2 | DTS_CFGR1_TS1_SMP_TIME_3) /*!< 14 clock cycle for the sampling time */
#define DTS_SMP_TIME_15_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_2 | DTS_CFGR1_TS1_SMP_TIME_3) /*!< 15 clock cycle for the sampling time */
/**
* @}
*/
/** @defgroup DTS_Flag_Definitions DTS Flag Definitions
* @{
*/
#define DTS_FLAG_TS1_ITE DTS_SR_TS1_ITEF /*!< Interrupt flag for end of measure for DTS1 */
#define DTS_FLAG_TS1_ITL DTS_SR_TS1_ITLF /*!< Interrupt flag for low threshold for DTS1 */
#define DTS_FLAG_TS1_ITH DTS_SR_TS1_ITHF /*!< Interrupt flag for high threshold for DTS1 */
#define DTS_FLAG_TS1_AITE DTS_SR_TS1_AITEF /*!< Asynchronous Interrupt flag for end of measure for DTS1 */
#define DTS_FLAG_TS1_AITL DTS_SR_TS1_AITLF /*!< Asynchronous Interrupt flag for low threshold for DTS1 */
#define DTS_FLAG_TS1_AITH DTS_SR_TS1_AITHF /*!< Asynchronous Interrupt flag for high threshold for DTS1 */
#define DTS_FLAG_TS1_RDY DTS_SR_TS1_RDY /*!< Ready flag for DTS1 */
/**
* @}
*/
/** @defgroup DTS_Interrupts_Definitions DTS Interrupts Definitions
* @{
*/
#define DTS_IT_TS1_ITE DTS_ITENR_TS1_ITEEN /*!< Enable interrupt flag for end of measure for DTS1 */
#define DTS_IT_TS1_ITL DTS_ITENR_TS1_ITLEN /*!< Enable interrupt flag for low threshold for DTS1 */
#define DTS_IT_TS1_ITH DTS_ITENR_TS1_ITHEN /*!< Enable interrupt flag for high threshold for DTS1 */
#define DTS_IT_TS1_AITE DTS_ITENR_TS1_AITEEN /*!< Enable asynchronous interrupt flag for end of measure for DTS1 */
#define DTS_IT_TS1_AITL DTS_ITENR_TS1_AITLEN /*!< Enable asynchronous interrupt flag for low threshold for DTS1 */
#define DTS_IT_TS1_AITH DTS_ITENR_TS1_AITHEN /*!< Enable asynchronous interrupt flag for high threshold for DTS1 */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup DTS_Exported_Macros DTS Exported Macros
* @{
*/
/** @brief Reset DTS handle state
* @param __HANDLE__ DTS handle.
* @retval None
*/
#define __HAL_DTS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DTS_STATE_RESET)
/**
* @brief Enable the specified DTS sensor
* @param __HANDLE__ DTS handle.
* @retval None
*/
#define __HAL_DTS_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR1, DTS_CFGR1_TS1_EN)
/**
* @brief Disable the specified DTS sensor
* @param __HANDLE__ DTS handle.
* @retval None
*/
#define __HAL_DTS_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR1, DTS_CFGR1_TS1_EN)
/**
* @brief Enable the DTS EXTI line in interrupt mode
* @retval None
*/
#define __HAL_DTS_EXTI_WAKEUP_ENABLE_IT() SET_BIT(EXTI->IMR3, DTS_EXTI_LINE_DTS1)
/**
* @brief Disable the DTS EXTI line in interrupt mode
* @retval None
*/
#define __HAL_DTS_EXTI_WAKEUP_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, DTS_EXTI_LINE_DTS1)
/**
* @brief Enable the DTS EXTI Line in event mode
* @retval None
*/
#define __HAL_DTS_EXTI_WAKEUP_ENABLE_EVENT() SET_BIT(EXTI->EMR3, DTS_EXTI_LINE_DTS1)
/**
* @brief Disable the DTS EXTI Line in event mode
* @retval None
*/
#define __HAL_DTS_EXTI_WAKEUP_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, DTS_EXTI_LINE_DTS1)
/** @brief Checks whether the specified DTS flag is set or not.
* @param __HANDLE__ specifies the DTS Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg DTS_FLAG_TS1_ITE : interrupt flag for end of measure for DTS1
* @arg DTS_FLAG_TS1_ITL : interrupt flag for low threshold for DTS1
* @arg DTS_FLAG_TS1_ITH : interrupt flag for high threshold for DTS1
* @arg DTS_FLAG_TS1_AITE: asynchronous interrupt flag for end of measure for DTS1
* @arg DTS_FLAG_TS1_AITL: asynchronous interrupt flag for low threshold for DTS1
* @arg DTS_FLAG_TS1_AITH: asynchronous interrupt flag for high threshold for DTS1
* @arg DTS_FLAG_TS1_RDY : Ready flag for DTS1
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define __HAL_DTS_GET_FLAG(__HANDLE__, __FLAG__) \
(((((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)))? SET : RESET)
/** @brief Clears the specified DTS pending flag.
* @param __HANDLE__ specifies the DTS Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg DTS_FLAG_TS1_ITE : interrupt flag for end of measure for DTS1
* @arg DTS_FLAG_TS1_ITL : interrupt flag for low threshold for DTS1
* @arg DTS_FLAG_TS1_ITH : interrupt flag for high threshold for DTS1
* @arg DTS_FLAG_TS1_AITE: asynchronous interrupt flag for end of measure for DTS1
* @arg DTS_FLAG_TS1_AITL: asynchronous interrupt flag for low threshold for DTS1
* @arg DTS_FLAG_TS1_AITH: asynchronous interrupt flag for high threshold for DTS1
* @retval None
*/
#define __HAL_DTS_CLEAR_FLAG(__HANDLE__, __FLAG__) \
((__HANDLE__)->Instance->ICIFR = (__FLAG__))
/** @brief Enable the specified DTS interrupt.
* @param __HANDLE__ specifies the DTS Handle.
* @param __INTERRUPT__ specifies the DTS interrupt source to enable.
* This parameter can be one of the following values:
* @arg DTS_IT_TS1_ITE : interrupt flag for end of measure for DTS1
* @arg DTS_IT_TS1_ITL : interrupt flag for low of measure for DTS1
* @arg DTS_IT_TS1_ITH : interrupt flag for high of measure for DTS1
* @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1
* @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1
* @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1
* @retval None
*/
#define __HAL_DTS_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
SET_BIT((__HANDLE__)->Instance->ITENR, __INTERRUPT__)
/** @brief Disable the specified DTS interrupt.
* @param __HANDLE__ specifies the DTS Handle.
* @param __INTERRUPT__ specifies the DTS interrupt source to enable.
* This parameter can be one of the following values:
* @arg DTS_IT_TS1_ITE : interrupt flag for end of measure for DTS1
* @arg DTS_IT_TS1_ITL : interrupt flag for low of measure for DTS1
* @arg DTS_IT_TS1_ITH : interrupt flag for high of measure for DTS1
* @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1
* @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1
* @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1
* @retval None
*/
#define __HAL_DTS_DISABLE_IT(__HANDLE__,__INTERRUPT__) \
CLEAR_BIT((__HANDLE__)->Instance->ITENR, __INTERRUPT__)
/** @brief Check whether the specified DTS interrupt source is enabled or not.
* @param __HANDLE__ DTS handle.
* @param __INTERRUPT__ DTS interrupt source to check
* This parameter can be one of the following values:
* @arg DTS_IT_TS1_ITE : interrupt flag for end of measure for DTS1
* @arg DTS_IT_TS1_ITL : interrupt flag for low of measure for DTS1
* @arg DTS_IT_TS1_ITH : interrupt flag for high of measure for DTS1
* @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1
* @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1
* @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1
* @retval State of interruption (SET or RESET)
*/
#define __HAL_DTS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
(( ((__HANDLE__)->Instance->ITENR & (__INTERRUPT__)) == (__INTERRUPT__) \
)? SET : RESET)
/** @brief Check whether the specified DTS REFCLK is selected
* @param __HANDLE__ DTS handle.
* @param __REFCLK__ DTS reference clock to check
* This parameter can be one of the following values:
* @arg DTS_REFCLKSEL_LSE: Low speed REF clock
* @arg DTS_REFCLKSEL_PCLK: High speed REF clock
* @retval State of the REF clock tested (SET or RESET)
*/
#define __HAL_DTS_GET_REFCLK(__HANDLE__, __REFCLK__) ((((__HANDLE__)->Instance->CFGR1 & (__REFCLK__)) == (__REFCLK__))? SET : RESET)
/** @brief Get Trigger
* @param __HANDLE__ DTS handle.
* @retval One of the following trigger
* DTS_TRIGGER_HW_NONE : No HW trigger (SW trigger)
* DTS_TRIGGER_LPTIMER1: LPTIMER1 trigger
* DTS_TRIGGER_LPTIMER2: LPTIMER2 trigger
* DTS_TRIGGER_LPTIMER3: LPTIMER3 trigger
* DTS_TRIGGER_EXTI13 : EXTI13 trigger
*/
#define __HAL_DTS_GET_TRIGGER(__HANDLE__) ((__HANDLE__)->Instance->CFGR1 & (DTS_CFGR1_TS1_INTRIG_SEL))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DTS_Exported_Functions
* @{
*/
/** @addtogroup DTS_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions **********************************/
HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts);
HAL_StatusTypeDef HAL_DTS_DeInit(DTS_HandleTypeDef *hdts);
void HAL_DTS_MspInit(DTS_HandleTypeDef *hdts);
void HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts);
/**
* @}
*/
/* IO operation functions *****************************************************/
/** @addtogroup DTS_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_DTS_Start(DTS_HandleTypeDef *hdts);
HAL_StatusTypeDef HAL_DTS_Stop(DTS_HandleTypeDef *hdts);
HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts, int32_t *Temperature);
HAL_StatusTypeDef HAL_DTS_Start_IT(DTS_HandleTypeDef *hdts);
HAL_StatusTypeDef HAL_DTS_Stop_IT(DTS_HandleTypeDef *hdts);
void HAL_DTS_IRQHandler(DTS_HandleTypeDef *hdts);
HAL_DTS_StateTypeDef HAL_DTS_GetState(DTS_HandleTypeDef *hdts);
/* Callback in Interrupt mode */
void HAL_DTS_EndCallback(DTS_HandleTypeDef *hdts);
void HAL_DTS_LowCallback(DTS_HandleTypeDef *hdts);
void HAL_DTS_HighCallback(DTS_HandleTypeDef *hdts);
void HAL_DTS_AsyncEndCallback(DTS_HandleTypeDef *hdts);
void HAL_DTS_AsyncLowCallback(DTS_HandleTypeDef *hdts);
void HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts);
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup DTS_Private_Constants DTS Private Constants
* @{
*/
/** @defgroup DTS_ExtiLine DTS EXTI Lines
* @{
*/
#define DTS_EXTI_LINE_DTS1 (EXTI_IMR3_IM88) /*!< EXTI line 88 connected to DTS1 output */
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DTS_Private_Macros DTS Private Macros
* @{
*/
/** @defgroup DTS_IS_DTS_Definitions DTS Private macros to check input parameters
* @{
*/
#define IS_DTS_QUICKMEAS(__SEL__) (((__SEL__) == DTS_QUICKMEAS_DISABLE) || \
((__SEL__) == DTS_QUICKMEAS_ENABLE))
#define IS_DTS_REFCLK(__SEL__) (((__SEL__) == DTS_REFCLKSEL_LSE) || \
((__SEL__) == DTS_REFCLKSEL_PCLK))
#define IS_DTS_TRIGGERINPUT(__INPUT__) (((__INPUT__) == DTS_TRIGGER_HW_NONE) || \
((__INPUT__) == DTS_TRIGGER_LPTIMER1) || \
((__INPUT__) == DTS_TRIGGER_LPTIMER2) || \
((__INPUT__) == DTS_TRIGGER_LPTIMER3) || \
((__INPUT__) == DTS_TRIGGER_EXTI13))
#define IS_DTS_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= 0xFFFFUL)
#define IS_DTS_DIVIDER_RATIO_NUMBER(__NUMBER__) (((__NUMBER__) >= (2UL)) && ((__NUMBER__) <= (127UL)))
#define IS_DTS_SAMPLINGTIME(__CYCLE__) (((__CYCLE__) == DTS_SMP_TIME_1_CYCLE) || \
((__CYCLE__) == DTS_SMP_TIME_2_CYCLE) || \
((__CYCLE__) == DTS_SMP_TIME_3_CYCLE) || \
((__CYCLE__) == DTS_SMP_TIME_4_CYCLE) || \
((__CYCLE__) == DTS_SMP_TIME_5_CYCLE) || \
((__CYCLE__) == DTS_SMP_TIME_6_CYCLE) || \
((__CYCLE__) == DTS_SMP_TIME_7_CYCLE) || \
((__CYCLE__) == DTS_SMP_TIME_8_CYCLE) || \
((__CYCLE__) == DTS_SMP_TIME_9_CYCLE) || \
((__CYCLE__) == DTS_SMP_TIME_10_CYCLE) || \
((__CYCLE__) == DTS_SMP_TIME_11_CYCLE) || \
((__CYCLE__) == DTS_SMP_TIME_12_CYCLE) || \
((__CYCLE__) == DTS_SMP_TIME_13_CYCLE) || \
((__CYCLE__) == DTS_SMP_TIME_14_CYCLE) || \
((__CYCLE__) == DTS_SMP_TIME_15_CYCLE))
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#endif /* DTS */
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_DTS_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

10
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_eth.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.c
View File

@ -149,12 +149,14 @@
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#ifdef HAL_ETH_MODULE_ENABLED
#if defined(ETH)
/** @defgroup ETH ETH
* @brief ETH HAL module driver
* @{
*/
#ifdef HAL_ETH_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@ -2980,11 +2982,15 @@ static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
}
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
#endif /* HAL_ETH_MODULE_ENABLED */
/**
* @}
*/
#endif /* ETH */
#endif /* HAL_ETH_MODULE_ENABLED */
/**
* @}
*/

5
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_eth.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.h
View File

@ -25,6 +25,7 @@
extern "C" {
#endif
#if defined(ETH)
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
@ -1665,7 +1666,9 @@ uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
/**
* @}
*/
#endif /* ETH */
#ifdef __cplusplus
}
#endif

10
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_eth_ex.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth_ex.c
View File

@ -25,12 +25,15 @@
* @{
*/
#ifdef HAL_ETH_MODULE_ENABLED
#if defined(ETH)
/** @defgroup ETHEx ETHEx
* @brief ETH HAL Extended module driver
* @{
*/
#ifdef HAL_ETH_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@ -541,11 +544,14 @@ uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth)
* @}
*/
#endif /* HAL_ETH_MODULE_ENABLED */
/**
* @}
*/
#endif /* ETH */
#endif /* HAL_ETH_MODULE_ENABLED */
/**
* @}
*/

4
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_eth_ex.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth_ex.h
View File

@ -25,6 +25,8 @@
extern "C" {
#endif
#if defined(ETH)
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
@ -344,6 +346,8 @@ uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth);
* @}
*/
#endif /* ETH */
#ifdef __cplusplus
}
#endif

0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_exti.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_exti.c
View File

74
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_exti.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_exti.h
View File

@ -134,16 +134,32 @@ typedef struct
#define EXTI_LINE_41 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x09U)
#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)
#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)
#if !defined(USB2_OTG_FS)
#define EXTI_LINE_44 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0CU)
#else
#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)
#endif /* USB2_OTG_FS */
#define EXTI_LINE_45 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0DU)
#if defined(DSI)
#define EXTI_LINE_46 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0EU)
#else
#define EXTI_LINE_46 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0EU)
#endif /* DSI */
#define EXTI_LINE_47 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0FU)
#define EXTI_LINE_48 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x10U)
#define EXTI_LINE_49 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x11U)
#define EXTI_LINE_50 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x12U)
#define EXTI_LINE_51 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x13U)
#if !defined(UART9)
#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x14U)
#else
#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x14U)
#endif /* UART9 */
#if !defined(USART10)
#define EXTI_LINE_53 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x15U)
#else
#define EXTI_LINE_53 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
#endif /* USART10 */
#define EXTI_LINE_54 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
#define EXTI_LINE_55 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
#define EXTI_LINE_56 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)
@ -165,21 +181,25 @@ typedef struct
#define EXTI_LINE_72 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)
#define EXTI_LINE_73 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x09U)
#define EXTI_LINE_74 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)
#if defined(ADC3)
#define EXTI_LINE_75 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)
#define EXTI_LINE_76 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)
#define EXTI_LINE_77 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0DU)
#if defined (DUAL_CORE)
#define EXTI_LINE_78 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x0EU)
#else
#define EXTI_LINE_78 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU)
#endif /* DUAL_CORE */
#define EXTI_LINE_79 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0FU)
#define EXTI_LINE_75 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE | 0x0BU)
#endif /* ADC3 */
#if defined(SAI4)
#define EXTI_LINE_76 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)
#else
#define EXTI_LINE_76 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE | 0x0CU)
#endif /* SAI4 */
#if defined (DUAL_CORE)
#define EXTI_LINE_77 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0DU)
#define EXTI_LINE_78 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x0EU)
#define EXTI_LINE_79 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0FU)
#define EXTI_LINE_80 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x10U)
#else
#define EXTI_LINE_77 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0DU)
#define EXTI_LINE_78 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU)
#define EXTI_LINE_79 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0FU)
#define EXTI_LINE_80 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x10U)
#endif /* DUAL_CORE */
@ -192,10 +212,21 @@ typedef struct
#endif /* DUAL_CORE */
#define EXTI_LINE_83 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x13U)
#if defined (DUAL_CORE)
#define EXTI_LINE_84 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x14U)
#else
#define EXTI_LINE_84 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x14U)
#endif /* DUAL_CORE */
#define EXTI_LINE_85 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
#if defined(ETH)
#define EXTI_LINE_86 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
#else
#define EXTI_LINE_86 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x16U)
#endif /* ETH */
#define EXTI_LINE_87 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
#if defined(DTS)
#define EXTI_LINE_88 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL | 0x18U)
#endif /* DTS */
/**
* @}
@ -255,8 +286,16 @@ typedef struct
#define EXTI_D3_PENDCLR_SRC_NONE 0x00000000U /*!< No D3 domain pendclear source , PMRx register to be set to zero */
#define EXTI_D3_PENDCLR_SRC_DMACH6 0x00000001U /*!< DMA ch6 event selected as D3 domain pendclear source, PMRx register to be set to 1 */
#define EXTI_D3_PENDCLR_SRC_DMACH7 0x00000002U /*!< DMA ch7 event selected as D3 domain pendclear source, PMRx register to be set to 1*/
#if defined (LPTIM4)
#define EXTI_D3_PENDCLR_SRC_LPTIM4 0x00000003U /*!< LPTIM4 out selected as D3 domain pendclear source, PMRx register to be set to 1 */
#define EXTI_D3_PENDCLR_SRC_LPTIM5 0x00000004U /*!< LPTIM4 out selected as D3 domain pendclear source, PMRx register to be set to 1 */
#else
#define EXTI_D3_PENDCLR_SRC_LPTIM2 0x00000003U /*!< LPTIM2 out selected as D3 domain pendclear source, PMRx register to be set to 1 */
#endif
#if defined (LPTIM5)
#define EXTI_D3_PENDCLR_SRC_LPTIM5 0x00000004U /*!< LPTIM5 out selected as D3 domain pendclear source, PMRx register to be set to 1 */
#else
#define EXTI_D3_PENDCLR_SRC_LPTIM3 0x00000004U /*!< LPTIM3 out selected as D3 domain pendclear source, PMRx register to be set to 1 */
#endif
/**
* @}
*/
@ -339,7 +378,11 @@ typedef struct
/**
* @brief EXTI Line number
*/
#if defined (EXTI_LINE_88)
#define EXTI_LINE_NB 89UL
#else
#define EXTI_LINE_NB 88UL
#endif /* EXTI_LINE_88 */
/**
* @}
@ -390,12 +433,19 @@ typedef struct
((__PORT__) == EXTI_GPIOK))
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16UL)
#if defined (LPTIM4) && defined (LPTIM5)
#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \
((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \
((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \
((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM4) || \
((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM5))
#else
#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \
((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \
((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \
((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM2) || \
((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM3))
#endif /* LPTIM4 && LPTIM5 */
/**
* @}

0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_fdcan.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fdcan.c
View File

0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_fdcan.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fdcan.h
View File

146
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash.c
View File

@ -105,6 +105,7 @@
* @{
*/
#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
/**
* @}
*/
@ -134,11 +135,11 @@ FLASH_ProcessTypeDef pFlash;
*/
/**
* @brief Program flash word of 256 bits at a specified address
* @brief Program flash word at a specified address
* @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @param FlashAddress specifies the address to be programmed.
* @param DataAddress specifies the address of data (256 bits) to be programmed
* @param DataAddress specifies the address of data to be programmed
*
* @retval HAL_StatusTypeDef HAL Status
*/
@ -157,7 +158,11 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress,
/* Process Locked */
__HAL_LOCK(&pFlash);
#if defined (FLASH_OPTCR_PG_OTP)
if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress)))
#else
if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress))
#endif /* FLASH_OPTCR_PG_OTP */
{
bank = FLASH_BANK_1;
}
@ -176,8 +181,18 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress,
{
if(bank == FLASH_BANK_1)
{
/* Set PG bit */
SET_BIT(FLASH->CR1, FLASH_CR_PG);
#if defined (FLASH_OPTCR_PG_OTP)
if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
{
/* Set OTP_PG bit */
SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
}
else
#endif /* FLASH_OPTCR_PG_OTP */
{
/* Set PG bit */
SET_BIT(FLASH->CR1, FLASH_CR_PG);
}
}
else
{
@ -188,14 +203,24 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress,
__ISB();
__DSB();
/* Program the 256 bits flash word */
do
#if defined (FLASH_OPTCR_PG_OTP)
if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
{
*dest_addr = *src_addr;
dest_addr++;
src_addr++;
row_index--;
} while (row_index != 0U);
/* Program an OTP word (16 bits) */
*(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress;
}
else
#endif /* FLASH_OPTCR_PG_OTP */
{
/* Program the flash word */
do
{
*dest_addr = *src_addr;
dest_addr++;
src_addr++;
row_index--;
} while (row_index != 0U);
}
__ISB();
__DSB();
@ -203,15 +228,25 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress,
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
if(bank == FLASH_BANK_1)
#if defined (FLASH_OPTCR_PG_OTP)
if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
{
/* If the program operation is completed, disable the PG */
CLEAR_BIT(FLASH->CR1, FLASH_CR_PG);
/* If the program operation is completed, disable the OTP_PG */
CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
}
else
#endif /* FLASH_OPTCR_PG_OTP */
{
/* If the program operation is completed, disable the PG */
CLEAR_BIT(FLASH->CR2, FLASH_CR_PG);
if(bank == FLASH_BANK_1)
{
/* If the program operation is completed, disable the PG */
CLEAR_BIT(FLASH->CR1, FLASH_CR_PG);
}
else
{
/* If the program operation is completed, disable the PG */
CLEAR_BIT(FLASH->CR2, FLASH_CR_PG);
}
}
}
@ -248,7 +283,11 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre
/* Reset error code */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
#if defined (FLASH_OPTCR_PG_OTP)
if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress)))
#else
if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress))
#endif /* FLASH_OPTCR_PG_OTP */
{
bank = FLASH_BANK_1;
}
@ -274,12 +313,27 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre
/* Set internal variables used by the IRQ handler */
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1;
/* Set PG bit */
SET_BIT(FLASH->CR1, FLASH_CR_PG);
#if defined (FLASH_OPTCR_PG_OTP)
if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
{
/* Set OTP_PG bit */
SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
}
else
#endif /* FLASH_OPTCR_PG_OTP */
{
/* Set PG bit */
SET_BIT(FLASH->CR1, FLASH_CR_PG);
}
/* Enable End of Operation and Error interrupts for Bank 1 */
#if defined (FLASH_CR_OPERRIE)
__HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
#else
__HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
#endif /* FLASH_CR_OPERRIE */
}
else
{
@ -290,21 +344,36 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre
SET_BIT(FLASH->CR2, FLASH_CR_PG);
/* Enable End of Operation and Error interrupts for Bank2 */
#if defined (FLASH_CR_OPERRIE)
__HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
#else
__HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
#endif /* FLASH_CR_OPERRIE */
}
__ISB();
__DSB();
/* Program the 256 bits flash word */
do
#if defined (FLASH_OPTCR_PG_OTP)
if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
{
*dest_addr = *src_addr;
dest_addr++;
src_addr++;
row_index--;
} while (row_index != 0U);
/* Program an OTP word (16 bits) */
*(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress;
}
else
#endif /* FLASH_OPTCR_PG_OTP */
{
/* Program the flash word */
do
{
*dest_addr = *src_addr;
dest_addr++;
src_addr++;
row_index--;
} while (row_index != 0U);
}
__ISB();
__DSB();
@ -391,7 +460,7 @@ void HAL_FLASH_IRQHandler(void)
}
}
/* Check FLASH Bank2 End of Operation flag */
/* Check FLASH Bank2 End of Operation flag */
if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_SR_EOP) != RESET)
{
if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK2)
@ -460,8 +529,13 @@ void HAL_FLASH_IRQHandler(void)
}
/* Check FLASH Bank1 operation error flags */
#if defined (FLASH_SR_OPERR)
errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \
FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1);
#else
errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \
FLASH_FLAG_INCERR_BANK1);
#endif /* FLASH_SR_OPERR */
if(errorflag != 0U)
{
@ -498,10 +572,14 @@ void HAL_FLASH_IRQHandler(void)
}
/* Check FLASH Bank2 operation error flags */
#if defined (FLASH_SR_OPERR)
errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \
FLASH_FLAG_INCERR_BANK2 | FLASH_FLAG_OPERR_BANK2) & 0x7FFFFFFFU);
#else
errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \
FLASH_FLAG_INCERR_BANK2) & 0x7FFFFFFFU);
#endif /* FLASH_SR_OPERR */
/* Check FLASH Bank2 operation error flags */
if(errorflag != 0U)
{
/* Save the error code */
@ -538,6 +616,7 @@ void HAL_FLASH_IRQHandler(void)
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
{
#if defined (FLASH_CR_OPERRIE)
/* Disable Bank1 Operation and Error source interrupt */
__HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
@ -545,6 +624,15 @@ void HAL_FLASH_IRQHandler(void)
/* Disable Bank2 Operation and Error source interrupt */
__HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
#else
/* Disable Bank1 Operation and Error source interrupt */
__HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
/* Disable Bank2 Operation and Error source interrupt */
__HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
#endif /* FLASH_CR_OPERRIE */
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
@ -856,8 +944,8 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U;
}
/* In case of error reported in Flash SR1 or SR2 register */
if((errorflag & 0x7FFFFFFFU) != 0U)
/* In case of error reported in Flash SR1 or SR2 registers (ECCC not managed as an error) */
if((errorflag & 0x7DFFFFFFU) != 0U)
{
/*Save the error code*/
pFlash.ErrorCode |= errorflag;

367
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash.h
View File

@ -91,24 +91,28 @@ typedef struct
* @brief FLASH Error Code
* @{
*/
#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR /*!< Write Protection Error */
#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR /*!< Program Sequence Error */
#define HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR /*!< Strobe Error */
#define HAL_FLASH_ERROR_INC FLASH_FLAG_INCERR /*!< Inconsistency Error */
#define HAL_FLASH_ERROR_OPE FLASH_FLAG_OPERR /*!< Operation Error */
#define HAL_FLASH_ERROR_RDP FLASH_FLAG_RDPERR /*!< Read Protection Error */
#define HAL_FLASH_ERROR_RDS FLASH_FLAG_RDSERR /*!< Read Secured Error */
#define HAL_FLASH_ERROR_SNECC FLASH_FLAG_SNECCERR /*!< ECC Single Correction Error */
#define HAL_FLASH_ERROR_DBECC FLASH_FLAG_DBECCERR /*!< ECC Double Detection Error */
#define HAL_FLASH_ERROR_CRCRD FLASH_FLAG_CRCRDERR /*!< CRC Read Error */
#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR /*!< Write Protection Error */
#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR /*!< Program Sequence Error */
#define HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR /*!< Strobe Error */
#define HAL_FLASH_ERROR_INC FLASH_FLAG_INCERR /*!< Inconsistency Error */
#if defined (FLASH_SR_OPERR)
#define HAL_FLASH_ERROR_OPE FLASH_FLAG_OPERR /*!< Operation Error */
#endif /* FLASH_SR_OPERR */
#define HAL_FLASH_ERROR_RDP FLASH_FLAG_RDPERR /*!< Read Protection Error */
#define HAL_FLASH_ERROR_RDS FLASH_FLAG_RDSERR /*!< Read Secured Error */
#define HAL_FLASH_ERROR_SNECC FLASH_FLAG_SNECCERR /*!< ECC Single Correction Error */
#define HAL_FLASH_ERROR_DBECC FLASH_FLAG_DBECCERR /*!< ECC Double Detection Error */
#define HAL_FLASH_ERROR_CRCRD FLASH_FLAG_CRCRDERR /*!< CRC Read Error */
#define HAL_FLASH_ERROR_WRP_BANK1 FLASH_FLAG_WRPERR_BANK1 /*!< Write Protection Error on Bank 1 */
#define HAL_FLASH_ERROR_PGS_BANK1 FLASH_FLAG_PGSERR_BANK1 /*!< Program Sequence Error on Bank 1 */
#define HAL_FLASH_ERROR_STRB_BANK1 FLASH_FLAG_STRBERR_BANK1 /*!< Strobe Error on Bank 1 */
#define HAL_FLASH_ERROR_INC_BANK1 FLASH_FLAG_INCERR_BANK1 /*!< Inconsistency Error on Bank 1 */
#if defined (FLASH_SR_OPERR)
#define HAL_FLASH_ERROR_OPE_BANK1 FLASH_FLAG_OPERR_BANK1 /*!< Operation Error on Bank 1 */
#endif /* FLASH_SR_OPERR */
#define HAL_FLASH_ERROR_RDP_BANK1 FLASH_FLAG_RDPERR_BANK1 /*!< Read Protection Error on Bank 1 */
#define HAL_FLASH_ERROR_RDS_BANK1 FLASH_FLAG_RDSERR_BANK1 /*!< Read Secured Error on Bank 1 */
#define HAL_FLASH_ERROR_SNECC_BANK1 FLASH_FLAG_SNECCERR_BANK1 /*!< ECC Single Correction Error on Bank 1 */
@ -119,7 +123,9 @@ typedef struct
#define HAL_FLASH_ERROR_PGS_BANK2 FLASH_FLAG_PGSERR_BANK2 /*!< Program Sequence Error on Bank 2 */
#define HAL_FLASH_ERROR_STRB_BANK2 FLASH_FLAG_STRBERR_BANK2 /*!< Strobe Error on Bank 2 */
#define HAL_FLASH_ERROR_INC_BANK2 FLASH_FLAG_INCERR_BANK2 /*!< Inconsistency Error on Bank 2 */
#if defined (FLASH_SR_OPERR)
#define HAL_FLASH_ERROR_OPE_BANK2 FLASH_FLAG_OPERR_BANK2 /*!< Operation Error on Bank 2 */
#endif /* FLASH_SR_OPERR */
#define HAL_FLASH_ERROR_RDP_BANK2 FLASH_FLAG_RDPERR_BANK2 /*!< Read Protection Error on Bank 2 */
#define HAL_FLASH_ERROR_RDS_BANK2 FLASH_FLAG_RDSERR_BANK2 /*!< Read Secured Error on Bank 2 */
#define HAL_FLASH_ERROR_SNECC_BANK2 FLASH_FLAG_SNECCERR_BANK2 /*!< ECC Single Correction Error on Bank 2 */
@ -134,7 +140,10 @@ typedef struct
/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
#define FLASH_TYPEPROGRAM_FLASHWORD 0x01U /*!< Program a flash word (256-bit) at a specified address */
#define FLASH_TYPEPROGRAM_FLASHWORD 0x01U /*!< Program a flash word at a specified address */
#if defined (FLASH_OPTCR_PG_OTP)
#define FLASH_TYPEPROGRAM_OTPWORD 0x02U /*!< Program an OTP word at a specified address */
#endif /* FLASH_OPTCR_PG_OTP */
/**
* @}
*/
@ -144,77 +153,99 @@ typedef struct
* @{
*/
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
#define FLASH_FLAG_WDW FLASH_SR_WDW /*!< Waiting for Data to Write on flag */
#define FLASH_FLAG_QW FLASH_SR_QW /*!< Write Waiting in Operation Queue on flag */
#define FLASH_FLAG_CRC_BUSY FLASH_SR_CRC_BUSY /*!< CRC module is working on flag */
#define FLASH_FLAG_WBNE FLASH_SR_WBNE /*!< Write Buffer Not Empty flag */
#define FLASH_FLAG_QW FLASH_SR_QW /*!< Wait Queue on flag */
#define FLASH_FLAG_CRC_BUSY FLASH_SR_CRC_BUSY /*!< CRC Busy flag */
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< End Of Program on flag */
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< Write Protection Error on flag */
#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< Program Sequence Error on flag */
#define FLASH_FLAG_STRBERR FLASH_SR_STRBERR /*!< strobe Error on flag */
#define FLASH_FLAG_STRBERR FLASH_SR_STRBERR /*!< Strobe Error flag */
#define FLASH_FLAG_INCERR FLASH_SR_INCERR /*!< Inconsistency Error on flag */
#if defined (FLASH_SR_OPERR)
#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< Operation Error on flag */
#endif /* FLASH_SR_OPERR */
#define FLASH_FLAG_RDPERR FLASH_SR_RDPERR /*!< Read Protection Error on flag */
#define FLASH_FLAG_RDSERR FLASH_SR_RDSERR /*!< Read Secured Error on flag */
#define FLASH_FLAG_SNECCERR FLASH_SR_SNECCERR /*!< Single ECC Error Correction on flag */
#define FLASH_FLAG_DBECCERR FLASH_SR_DBECCERR /*!< Double Detection ECC Error on flag */
#define FLASH_FLAG_CRCEND FLASH_SR_CRCEND /*!< CRC module completes on bank flag */
#define FLASH_FLAG_CRCEND FLASH_SR_CRCEND /*!< CRC End of Calculation flag */
#define FLASH_FLAG_CRCRDERR FLASH_SR_CRCRDERR /*!< CRC Read Error on bank flag */
#define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank 1 Busy flag */
#define FLASH_FLAG_WBNE_BANK1 FLASH_SR_WBNE /*!< Waiting for Data to Write on Bank 1 flag */
#define FLASH_FLAG_QW_BANK1 FLASH_SR_QW /*!< Write Waiting in Operation Queue on Bank 1 flag */
#define FLASH_FLAG_CRC_BUSY_BANK1 FLASH_SR_CRC_BUSY /*!< CRC module is working on Bank 1 flag */
#define FLASH_FLAG_WBNE_BANK1 FLASH_SR_WBNE /*!< Write Buffer Not Empty on Bank 1 flag */
#define FLASH_FLAG_QW_BANK1 FLASH_SR_QW /*!< Wait Queue on Bank 1 flag */
#define FLASH_FLAG_CRC_BUSY_BANK1 FLASH_SR_CRC_BUSY /*!< CRC Busy on Bank 1 flag */
#define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< End Of Program on Bank 1 flag */
#define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPERR /*!< Write Protection Error on Bank 1 flag */
#define FLASH_FLAG_PGSERR_BANK1 FLASH_SR_PGSERR /*!< Program Sequence Error on Bank 1 flag */
#define FLASH_FLAG_STRBERR_BANK1 FLASH_SR_STRBERR /*!< strobe Error on Bank 1 flag */
#define FLASH_FLAG_STRBERR_BANK1 FLASH_SR_STRBERR /*!< Strobe Error on Bank 1 flag */
#define FLASH_FLAG_INCERR_BANK1 FLASH_SR_INCERR /*!< Inconsistency Error on Bank 1 flag */
#if defined (FLASH_SR_OPERR)
#define FLASH_FLAG_OPERR_BANK1 FLASH_SR_OPERR /*!< Operation Error on Bank 1 flag */
#endif /* FLASH_SR_OPERR */
#define FLASH_FLAG_RDPERR_BANK1 FLASH_SR_RDPERR /*!< Read Protection Error on Bank 1 flag */
#define FLASH_FLAG_RDSERR_BANK1 FLASH_SR_RDSERR /*!< Read Secured Error on Bank 1 flag */
#define FLASH_FLAG_SNECCERR_BANK1 FLASH_SR_SNECCERR /*!< Single ECC Error Correction on Bank 1 flag */
#define FLASH_FLAG_DBECCERR_BANK1 FLASH_SR_DBECCERR /*!< Double Detection ECC Error on Bank 1 flag */
#define FLASH_FLAG_CRCEND_BANK1 FLASH_SR_CRCEND /*!< CRC module completes on bank Bank 1 flag */
#define FLASH_FLAG_CRCEND_BANK1 FLASH_SR_CRCEND /*!< CRC End of Calculation on Bank 1 flag */
#define FLASH_FLAG_CRCRDERR_BANK1 FLASH_SR_CRCRDERR /*!< CRC Read error on Bank 1 flag */
#if defined (FLASH_SR_OPERR)
#define FLASH_FLAG_ALL_ERRORS_BANK1 (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | \
FLASH_FLAG_STRBERR_BANK1 | FLASH_FLAG_INCERR_BANK1 | \
FLASH_FLAG_OPERR_BANK1 | FLASH_FLAG_RDPERR_BANK1 | \
FLASH_FLAG_RDSERR_BANK1 | FLASH_FLAG_SNECCERR_BANK1 | \
FLASH_FLAG_DBECCERR_BANK1 | FLASH_FLAG_CRCRDERR_BANK1)
FLASH_FLAG_DBECCERR_BANK1 | FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */
#else
#define FLASH_FLAG_ALL_ERRORS_BANK1 (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | \
FLASH_FLAG_STRBERR_BANK1 | FLASH_FLAG_INCERR_BANK1 | \
FLASH_FLAG_RDPERR_BANK1 | FLASH_FLAG_RDSERR_BANK1 | \
FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1 | \
FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */
#endif /* FLASH_SR_OPERR */
#define FLASH_FLAG_ALL_BANK1 (FLASH_FLAG_BSY_BANK1 | FLASH_FLAG_WBNE_BANK1 | \
FLASH_FLAG_QW_BANK1 | FLASH_FLAG_CRC_BUSY_BANK1 | \
FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_CRCEND_BANK1 | \
FLASH_FLAG_ALL_ERRORS_BANK1)
FLASH_FLAG_ALL_ERRORS_BANK1) /*!< All Bank 1 flags */
#define FLASH_FLAG_BSY_BANK2 (FLASH_SR_BSY | 0x80000000U) /*!< FLASH Bank 2 Busy flag */
#define FLASH_FLAG_WBNE_BANK2 (FLASH_SR_WBNE | 0x80000000U) /*!< Waiting for Data to Write on Bank 2 flag */
#define FLASH_FLAG_QW_BANK2 (FLASH_SR_QW | 0x80000000U) /*!< Write Waiting in Operation Queue on Bank 2 flag */
#define FLASH_FLAG_CRC_BUSY_BANK2 (FLASH_SR_CRC_BUSY | 0x80000000U) /*!< CRC module is working on Bank 2 flag */
#define FLASH_FLAG_WBNE_BANK2 (FLASH_SR_WBNE | 0x80000000U) /*!< Write Buffer Not Empty on Bank 2 flag */
#define FLASH_FLAG_QW_BANK2 (FLASH_SR_QW | 0x80000000U) /*!< Wait Queue on Bank 2 flag */
#define FLASH_FLAG_CRC_BUSY_BANK2 (FLASH_SR_CRC_BUSY | 0x80000000U) /*!< CRC Busy on Bank 2 flag */
#define FLASH_FLAG_EOP_BANK2 (FLASH_SR_EOP | 0x80000000U) /*!< End Of Program on Bank 2 flag */
#define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR_WRPERR | 0x80000000U) /*!< Write Protection Error on Bank 2 flag */
#define FLASH_FLAG_PGSERR_BANK2 (FLASH_SR_PGSERR | 0x80000000U) /*!< Program Sequence Error on Bank 2 flag */
#define FLASH_FLAG_STRBERR_BANK2 (FLASH_SR_STRBERR | 0x80000000U) /*!< Strobe Error on Bank 2 flag */
#define FLASH_FLAG_INCERR_BANK2 (FLASH_SR_INCERR | 0x80000000U) /*!< Inconsistency Error on Bank 2 flag */
#if defined (FLASH_SR_OPERR)
#define FLASH_FLAG_OPERR_BANK2 (FLASH_SR_OPERR | 0x80000000U) /*!< Operation Error on Bank 2 flag */
#endif /* FLASH_SR_OPERR */
#define FLASH_FLAG_RDPERR_BANK2 (FLASH_SR_RDPERR | 0x80000000U) /*!< Read Protection Error on Bank 2 flag */
#define FLASH_FLAG_RDSERR_BANK2 (FLASH_SR_RDSERR | 0x80000000U) /*!< Read Secured Error on Bank 2 flag */
#define FLASH_FLAG_SNECCERR_BANK2 (FLASH_SR_SNECCERR | 0x80000000U) /*!< Single ECC Error Correction on Bank 2 flag */
#define FLASH_FLAG_DBECCERR_BANK2 (FLASH_SR_DBECCERR | 0x80000000U) /*!< Double Detection ECC Error on Bank 2 flag */
#define FLASH_FLAG_CRCEND_BANK2 (FLASH_SR_CRCEND | 0x80000000U) /*!< CRC module completes on bank Bank 2 flag */
#define FLASH_FLAG_CRCEND_BANK2 (FLASH_SR_CRCEND | 0x80000000U) /*!< CRC End of Calculation on Bank 2 flag */
#define FLASH_FLAG_CRCRDERR_BANK2 (FLASH_SR_CRCRDERR | 0x80000000U) /*!< CRC Read error on Bank 2 flag */
#if defined (FLASH_SR_OPERR)
#define FLASH_FLAG_ALL_ERRORS_BANK2 (FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | \
FLASH_FLAG_STRBERR_BANK2 | FLASH_FLAG_INCERR_BANK2 | \
FLASH_FLAG_OPERR_BANK2 | FLASH_FLAG_RDPERR_BANK2 | \
FLASH_FLAG_RDSERR_BANK2 | FLASH_FLAG_SNECCERR_BANK2 | \
FLASH_FLAG_DBECCERR_BANK2 | FLASH_FLAG_CRCRDERR_BANK2)
FLASH_FLAG_DBECCERR_BANK2 | FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */
#else
#define FLASH_FLAG_ALL_ERRORS_BANK2 (FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | \
FLASH_FLAG_STRBERR_BANK2 | FLASH_FLAG_INCERR_BANK2 | \
FLASH_FLAG_RDPERR_BANK2 | FLASH_FLAG_RDSERR_BANK2 | \
FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2 | \
FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */
#endif /* FLASH_SR_OPERR */
#define FLASH_FLAG_ALL_BANK2 (FLASH_FLAG_BSY_BANK2 | FLASH_FLAG_WBNE_BANK2 | \
FLASH_FLAG_QW_BANK2 | FLASH_FLAG_CRC_BUSY_BANK2 | \
FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_CRCEND_BANK2 | \
FLASH_FLAG_ALL_ERRORS_BANK2)
FLASH_FLAG_ALL_ERRORS_BANK2) /*!< All Bank 2 flags */
/**
* @}
*/
@ -228,7 +259,9 @@ typedef struct
#define FLASH_IT_PGSERR_BANK1 FLASH_CR_PGSERRIE /*!< Program Sequence Error on Bank 1 Interrupt source */
#define FLASH_IT_STRBERR_BANK1 FLASH_CR_STRBERRIE /*!< Strobe Error on Bank 1 Interrupt source */
#define FLASH_IT_INCERR_BANK1 FLASH_CR_INCERRIE /*!< Inconsistency Error on Bank 1 Interrupt source */
#if defined (FLASH_CR_OPERRIE)
#define FLASH_IT_OPERR_BANK1 FLASH_CR_OPERRIE /*!< Operation Error on Bank 1 Interrupt source */
#endif /* FLASH_CR_OPERRIE */
#define FLASH_IT_RDPERR_BANK1 FLASH_CR_RDPERRIE /*!< Read protection Error on Bank 1 Interrupt source */
#define FLASH_IT_RDSERR_BANK1 FLASH_CR_RDSERRIE /*!< Read Secured Error on Bank 1 Interrupt source */
#define FLASH_IT_SNECCERR_BANK1 FLASH_CR_SNECCERRIE /*!< Single ECC Error Correction on Bank 1 Interrupt source */
@ -236,19 +269,30 @@ typedef struct
#define FLASH_IT_CRCEND_BANK1 FLASH_CR_CRCENDIE /*!< CRC End on Bank 1 Interrupt source */
#define FLASH_IT_CRCRDERR_BANK1 FLASH_CR_CRCRDERRIE /*!< CRC Read error on Bank 1 Interrupt source */
#if defined (FLASH_CR_OPERRIE)
#define FLASH_IT_ALL_BANK1 (FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | \
FLASH_IT_PGSERR_BANK1 | FLASH_IT_STRBERR_BANK1 | \
FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1 | \
FLASH_IT_RDPERR_BANK1 | FLASH_IT_RDSERR_BANK1 | \
FLASH_IT_SNECCERR_BANK1 | FLASH_IT_DBECCERR_BANK1 | \
FLASH_IT_CRCEND_BANK1 | FLASH_IT_CRCRDERR_BANK1)
FLASH_IT_CRCEND_BANK1 | FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */
#else
#define FLASH_IT_ALL_BANK1 (FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | \
FLASH_IT_PGSERR_BANK1 | FLASH_IT_STRBERR_BANK1 | \
FLASH_IT_INCERR_BANK1 | FLASH_IT_RDPERR_BANK1 | \
FLASH_IT_RDSERR_BANK1 | FLASH_IT_SNECCERR_BANK1 | \
FLASH_IT_DBECCERR_BANK1 | FLASH_IT_CRCEND_BANK1 | \
FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */
#endif /* FLASH_CR_OPERRIE */
#define FLASH_IT_EOP_BANK2 (FLASH_CR_EOPIE | 0x80000000U) /*!< End of FLASH Bank 2 Operation Interrupt source */
#define FLASH_IT_WRPERR_BANK2 (FLASH_CR_WRPERRIE | 0x80000000U) /*!< Write Protection Error on Bank 2 Interrupt source */
#define FLASH_IT_PGSERR_BANK2 (FLASH_CR_PGSERRIE | 0x80000000U) /*!< Program Sequence Error on Bank 2 Interrupt source */
#define FLASH_IT_STRBERR_BANK2 (FLASH_CR_STRBERRIE | 0x80000000U) /*!< Strobe Error on Bank 2 Interrupt source */
#define FLASH_IT_INCERR_BANK2 (FLASH_CR_INCERRIE | 0x80000000U) /*!< Inconsistency Error on Bank 2 Interrupt source */
#if defined (FLASH_CR_OPERRIE)
#define FLASH_IT_OPERR_BANK2 (FLASH_CR_OPERRIE | 0x80000000U) /*!< Operation Error on Bank 2 Interrupt source */
#endif /* FLASH_CR_OPERRIE */
#define FLASH_IT_RDPERR_BANK2 (FLASH_CR_RDPERRIE | 0x80000000U) /*!< Read protection Error on Bank 2 Interrupt source */
#define FLASH_IT_RDSERR_BANK2 (FLASH_CR_RDSERRIE | 0x80000000U) /*!< Read Secured Error on Bank 2 Interrupt source */
#define FLASH_IT_SNECCERR_BANK2 (FLASH_CR_SNECCERRIE | 0x80000000U) /*!< Single ECC Error Correction on Bank 2 Interrupt source */
@ -256,16 +300,26 @@ typedef struct
#define FLASH_IT_CRCEND_BANK2 (FLASH_CR_CRCENDIE | 0x80000000U) /*!< CRC End on Bank 2 Interrupt source */
#define FLASH_IT_CRCRDERR_BANK2 (FLASH_CR_CRCRDERRIE | 0x80000000U) /*!< CRC Read Error on Bank 2 Interrupt source */
#if defined (FLASH_CR_OPERRIE)
#define FLASH_IT_ALL_BANK2 (FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | \
FLASH_IT_PGSERR_BANK2 | FLASH_IT_STRBERR_BANK2 | \
FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2 | \
FLASH_IT_RDPERR_BANK2 | FLASH_IT_RDSERR_BANK2 | \
FLASH_IT_SNECCERR_BANK2 | FLASH_IT_DBECCERR_BANK2 | \
FLASH_IT_CRCEND_BANK2 | FLASH_IT_CRCRDERR_BANK2)
FLASH_IT_CRCEND_BANK2 | FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */
#else
#define FLASH_IT_ALL_BANK2 (FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | \
FLASH_IT_PGSERR_BANK2 | FLASH_IT_STRBERR_BANK2 | \
FLASH_IT_INCERR_BANK2 | FLASH_IT_RDPERR_BANK2 | \
FLASH_IT_RDSERR_BANK2 | FLASH_IT_SNECCERR_BANK2 | \
FLASH_IT_DBECCERR_BANK2 | FLASH_IT_CRCEND_BANK2 | \
FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */
#endif /* FLASH_CR_OPERRIE */
/**
* @}
*/
#if defined (FLASH_CR_PSIZE)
/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
* @{
*/
@ -276,6 +330,7 @@ typedef struct
/**
* @}
*/
#endif /* FLASH_CR_PSIZE */
/** @defgroup FLASH_Keys FLASH Keys
@ -300,6 +355,128 @@ typedef struct
#define FLASH_SECTOR_5 5U /*!< Sector Number 5 */
#define FLASH_SECTOR_6 6U /*!< Sector Number 6 */
#define FLASH_SECTOR_7 7U /*!< Sector Number 7 */
#if (FLASH_SECTOR_TOTAL == 128)
#define FLASH_SECTOR_8 8U /*!< Sector Number 8 */
#define FLASH_SECTOR_9 9U /*!< Sector Number 9 */
#define FLASH_SECTOR_10 10U /*!< Sector Number 10 */
#define FLASH_SECTOR_11 11U /*!< Sector Number 11 */
#define FLASH_SECTOR_12 12U /*!< Sector Number 12 */
#define FLASH_SECTOR_13 13U /*!< Sector Number 13 */
#define FLASH_SECTOR_14 14U /*!< Sector Number 14 */
#define FLASH_SECTOR_15 15U /*!< Sector Number 15 */
#define FLASH_SECTOR_16 16U /*!< Sector Number 16 */
#define FLASH_SECTOR_17 17U /*!< Sector Number 17 */
#define FLASH_SECTOR_18 18U /*!< Sector Number 18 */
#define FLASH_SECTOR_19 19U /*!< Sector Number 19 */
#define FLASH_SECTOR_20 20U /*!< Sector Number 20 */
#define FLASH_SECTOR_21 21U /*!< Sector Number 21 */
#define FLASH_SECTOR_22 22U /*!< Sector Number 22 */
#define FLASH_SECTOR_23 23U /*!< Sector Number 23 */
#define FLASH_SECTOR_24 24U /*!< Sector Number 24 */
#define FLASH_SECTOR_25 25U /*!< Sector Number 25 */
#define FLASH_SECTOR_26 26U /*!< Sector Number 26 */
#define FLASH_SECTOR_27 27U /*!< Sector Number 27 */
#define FLASH_SECTOR_28 28U /*!< Sector Number 28 */
#define FLASH_SECTOR_29 29U /*!< Sector Number 29 */
#define FLASH_SECTOR_30 30U /*!< Sector Number 30 */
#define FLASH_SECTOR_31 31U /*!< Sector Number 31 */
#define FLASH_SECTOR_32 32U /*!< Sector Number 32 */
#define FLASH_SECTOR_33 33U /*!< Sector Number 33 */
#define FLASH_SECTOR_34 34U /*!< Sector Number 34 */
#define FLASH_SECTOR_35 35U /*!< Sector Number 35 */
#define FLASH_SECTOR_36 36U /*!< Sector Number 36 */
#define FLASH_SECTOR_37 37U /*!< Sector Number 37 */
#define FLASH_SECTOR_38 38U /*!< Sector Number 38 */
#define FLASH_SECTOR_39 39U /*!< Sector Number 39 */
#define FLASH_SECTOR_40 40U /*!< Sector Number 40 */
#define FLASH_SECTOR_41 41U /*!< Sector Number 41 */
#define FLASH_SECTOR_42 42U /*!< Sector Number 42 */
#define FLASH_SECTOR_43 43U /*!< Sector Number 43 */
#define FLASH_SECTOR_44 44U /*!< Sector Number 44 */
#define FLASH_SECTOR_45 45U /*!< Sector Number 45 */
#define FLASH_SECTOR_46 46U /*!< Sector Number 46 */
#define FLASH_SECTOR_47 47U /*!< Sector Number 47 */
#define FLASH_SECTOR_48 48U /*!< Sector Number 48 */
#define FLASH_SECTOR_49 49U /*!< Sector Number 49 */
#define FLASH_SECTOR_50 50U /*!< Sector Number 50 */
#define FLASH_SECTOR_51 51U /*!< Sector Number 51 */
#define FLASH_SECTOR_52 52U /*!< Sector Number 52 */
#define FLASH_SECTOR_53 53U /*!< Sector Number 53 */
#define FLASH_SECTOR_54 54U /*!< Sector Number 54 */
#define FLASH_SECTOR_55 55U /*!< Sector Number 55 */
#define FLASH_SECTOR_56 56U /*!< Sector Number 56 */
#define FLASH_SECTOR_57 57U /*!< Sector Number 57 */
#define FLASH_SECTOR_58 58U /*!< Sector Number 58 */
#define FLASH_SECTOR_59 59U /*!< Sector Number 59 */
#define FLASH_SECTOR_60 60U /*!< Sector Number 60 */
#define FLASH_SECTOR_61 61U /*!< Sector Number 61 */
#define FLASH_SECTOR_62 62U /*!< Sector Number 62 */
#define FLASH_SECTOR_63 63U /*!< Sector Number 63 */
#define FLASH_SECTOR_64 64U /*!< Sector Number 64 */
#define FLASH_SECTOR_65 65U /*!< Sector Number 65 */
#define FLASH_SECTOR_66 66U /*!< Sector Number 66 */
#define FLASH_SECTOR_67 67U /*!< Sector Number 67 */
#define FLASH_SECTOR_68 68U /*!< Sector Number 68 */
#define FLASH_SECTOR_69 69U /*!< Sector Number 69 */
#define FLASH_SECTOR_70 70U /*!< Sector Number 70 */
#define FLASH_SECTOR_71 71U /*!< Sector Number 71 */
#define FLASH_SECTOR_72 72U /*!< Sector Number 72 */
#define FLASH_SECTOR_73 73U /*!< Sector Number 73 */
#define FLASH_SECTOR_74 74U /*!< Sector Number 74 */
#define FLASH_SECTOR_75 75U /*!< Sector Number 75 */
#define FLASH_SECTOR_76 76U /*!< Sector Number 76 */
#define FLASH_SECTOR_77 77U /*!< Sector Number 77 */
#define FLASH_SECTOR_78 78U /*!< Sector Number 78 */
#define FLASH_SECTOR_79 79U /*!< Sector Number 79 */
#define FLASH_SECTOR_80 80U /*!< Sector Number 80 */
#define FLASH_SECTOR_81 81U /*!< Sector Number 81 */
#define FLASH_SECTOR_82 82U /*!< Sector Number 82 */
#define FLASH_SECTOR_83 83U /*!< Sector Number 83 */
#define FLASH_SECTOR_84 84U /*!< Sector Number 84 */
#define FLASH_SECTOR_85 85U /*!< Sector Number 85 */
#define FLASH_SECTOR_86 86U /*!< Sector Number 86 */
#define FLASH_SECTOR_87 87U /*!< Sector Number 87 */
#define FLASH_SECTOR_88 88U /*!< Sector Number 88 */
#define FLASH_SECTOR_89 89U /*!< Sector Number 89 */
#define FLASH_SECTOR_90 90U /*!< Sector Number 90 */
#define FLASH_SECTOR_91 91U /*!< Sector Number 91 */
#define FLASH_SECTOR_92 92U /*!< Sector Number 92 */
#define FLASH_SECTOR_93 93U /*!< Sector Number 93 */
#define FLASH_SECTOR_94 94U /*!< Sector Number 94 */
#define FLASH_SECTOR_95 95U /*!< Sector Number 95 */
#define FLASH_SECTOR_96 96U /*!< Sector Number 96 */
#define FLASH_SECTOR_97 97U /*!< Sector Number 97 */
#define FLASH_SECTOR_98 98U /*!< Sector Number 98 */
#define FLASH_SECTOR_99 99U /*!< Sector Number 99 */
#define FLASH_SECTOR_100 100U /*!< Sector Number 100 */
#define FLASH_SECTOR_101 101U /*!< Sector Number 101 */
#define FLASH_SECTOR_102 102U /*!< Sector Number 102 */
#define FLASH_SECTOR_103 103U /*!< Sector Number 103 */
#define FLASH_SECTOR_104 104U /*!< Sector Number 104 */
#define FLASH_SECTOR_105 105U /*!< Sector Number 105 */
#define FLASH_SECTOR_106 106U /*!< Sector Number 106 */
#define FLASH_SECTOR_107 107U /*!< Sector Number 107 */
#define FLASH_SECTOR_108 108U /*!< Sector Number 108 */
#define FLASH_SECTOR_109 109U /*!< Sector Number 109 */
#define FLASH_SECTOR_110 110U /*!< Sector Number 110 */
#define FLASH_SECTOR_111 111U /*!< Sector Number 111 */
#define FLASH_SECTOR_112 112U /*!< Sector Number 112 */
#define FLASH_SECTOR_113 113U /*!< Sector Number 113 */
#define FLASH_SECTOR_114 114U /*!< Sector Number 114 */
#define FLASH_SECTOR_115 115U /*!< Sector Number 115 */
#define FLASH_SECTOR_116 116U /*!< Sector Number 116 */
#define FLASH_SECTOR_117 117U /*!< Sector Number 117 */
#define FLASH_SECTOR_118 118U /*!< Sector Number 118 */
#define FLASH_SECTOR_119 119U /*!< Sector Number 119 */
#define FLASH_SECTOR_120 120U /*!< Sector Number 120 */
#define FLASH_SECTOR_121 121U /*!< Sector Number 121 */
#define FLASH_SECTOR_122 122U /*!< Sector Number 122 */
#define FLASH_SECTOR_123 123U /*!< Sector Number 123 */
#define FLASH_SECTOR_124 124U /*!< Sector Number 124 */
#define FLASH_SECTOR_125 125U /*!< Sector Number 125 */
#define FLASH_SECTOR_126 126U /*!< Sector Number 126 */
#define FLASH_SECTOR_127 127U /*!< Sector Number 127 */
#endif /* FLASH_SECTOR_TOTAL == 128 */
/**
* @}
*/
@ -344,8 +521,9 @@ typedef struct
* @arg FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source
* @arg FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source
* @arg FLASH_IT_CRCRDERR_BANK1 : CRC Read error on Bank 1 Interrupt source
* In case of Bank 2, this parameter can be any combination of the following values: *
* @arg FLASH_IT_ALL_BANK1 : All Bank 1 Interrupt sources
*
* In case of Bank 2, this parameter can be any combination of the following values:
* @arg FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source
* @arg FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source
* @arg FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source
@ -358,6 +536,7 @@ typedef struct
* @arg FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source
* @arg FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source
* @arg FLASH_IT_CRCRDERR_BANK2 : CRC Read error on Bank 2 Interrupt source
* @arg FLASH_IT_ALL_BANK2 : All Bank 2 Interrupt sources
* @retval none
*/
@ -386,8 +565,9 @@ typedef struct
* @arg FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source
* @arg FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source
* @arg FLASH_IT_CRCRDERR_BANK1 : CRC Read error on Bank 1 Interrupt source
* In case of Bank 2, this parameter can be any combination of the following values: *
* @arg FLASH_IT_ALL_BANK1 : All Bank 1 Interrupt sources
*
* In case of Bank 2, this parameter can be any combination of the following values:
* @arg FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source
* @arg FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source
* @arg FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source
@ -400,6 +580,7 @@ typedef struct
* @arg FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source
* @arg FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source
* @arg FLASH_IT_CRCRDERR_BANK2 : CRC Read error on Bank 2 Interrupt source
* @arg FLASH_IT_ALL_BANK2 : All Bank 2 Interrupt sources
* @retval none
*/
@ -415,10 +596,10 @@ typedef struct
/**
* @brief Checks whether the specified FLASH flag is set or not.
* @param __FLAG__: specifies the FLASH flag to check.
* In case of Bank 1 This parameter can be any combination of the following values :
* In case of Bank 1 This parameter can be one of the following values :
* @arg FLASH_FLAG_BSY_BANK1 : FLASH Bank 1 Busy flag
* @arg FLASH_FLAG_WBNE_BANK1 : Waiting for Data to Write on Bank 1 flag
* @arg FLASH_FLAG_QW_BANK1 : Write Waiting in Operation Queue on Bank 1 flag
* @arg FLASH_FLAG_WBNE_BANK1 : Write Buffer Not Empty on Bank 1 flag
* @arg FLASH_FLAG_QW_BANK1 : Wait Queue on Bank 1 flag
* @arg FLASH_FLAG_CRC_BUSY_BANK1 : CRC module is working on Bank 1 flag
* @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag
* @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag
@ -433,10 +614,10 @@ typedef struct
* @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag
* @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag
*
* In case of Bank 2 This parameter can be any combination of the following values :
* In case of Bank 2 This parameter can be one of the following values :
* @arg FLASH_FLAG_BSY_BANK2 : FLASH Bank 2 Busy flag
* @arg FLASH_FLAG_WBNE_BANK2 : Waiting for Data to Write on Bank 2 flag
* @arg FLASH_FLAG_QW_BANK2 : Write Waiting in Operation Queue on Bank 2 flag
* @arg FLASH_FLAG_WBNE_BANK2 : Write Buffer Not Empty on Bank 2 flag
* @arg FLASH_FLAG_QW_BANK2 : Wait Queue on Bank 2 flag
* @arg FLASH_FLAG_CRC_BUSY_BANK2 : CRC module is working on Bank 2 flag
* @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag
* @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag
@ -463,33 +644,37 @@ typedef struct
/**
* @brief Clear the specified FLASH flag.
* @param __FLAG__: specifies the FLASH flags to clear.
* This parameter can be any combination of the following values:
* @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag
* @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag
* @arg FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag
* @arg FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag
* @arg FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag
* @arg FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag
* @arg FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag
* @arg FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag
* @arg FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag
* @arg FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag
* @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag
* @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag
* In case of Bank 1, this parameter can be any combination of the following values:
* @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag
* @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag
* @arg FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag
* @arg FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag
* @arg FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag
* @arg FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag
* @arg FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag
* @arg FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag
* @arg FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag
* @arg FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag
* @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag
* @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag
* @arg FLASH_FLAG_ALL_ERRORS_BANK1 : All Bank 1 error flags
* @arg FLASH_FLAG_ALL_BANK1 : All Bank 1 flags
*
* In case of Bank 2 This parameter can be any combination of the following values :
* @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag
* @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag
* @arg FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag
* @arg FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag
* @arg FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag
* @arg FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag
* @arg FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag
* @arg FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag
* @arg FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag
* @arg FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag
* @arg FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag
* @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag
* In case of Bank 2, this parameter can be any combination of the following values :
* @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag
* @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag
* @arg FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag
* @arg FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag
* @arg FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag
* @arg FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag
* @arg FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag
* @arg FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag
* @arg FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag
* @arg FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag
* @arg FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag
* @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag
* @arg FLASH_FLAG_ALL_ERRORS_BANK2 : All Bank 2 error flags
* @arg FLASH_FLAG_ALL_BANK2 : All Bank 2 flags
* @retval none
*/
@ -575,36 +760,33 @@ extern FLASH_ProcessTypeDef pFlash;
* @{
*/
/** @defgroup FLASH_IS_FLASH_Definitions FLASH Definitions
* @{
*/
#define IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD)
/**
* @}
*/
/** @defgroup FLASH_IS_BANK_IT_Definitions FLASH BANK IT Definitions
* @{
*/
#if defined (FLASH_OPTCR_PG_OTP)
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD) || \
((VALUE) == FLASH_TYPEPROGRAM_OTPWORD))
#else
#define IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD)
#endif /* FLASH_OPTCR_PG_OTP */
#define IS_FLASH_IT_BANK1(IT) (((IT) & FLASH_IT_ALL_BANK1) == (IT))
#define IS_FLASH_IT_BANK1(IT) (((IT) & FLASH_IT_ALL_BANK1) == (IT))
#define IS_FLASH_IT_BANK2(IT) (((IT) & FLASH_IT_ALL_BANK2) == (IT))
#define IS_FLASH_IT_BANK2(IT) (((IT) & FLASH_IT_ALL_BANK2) == (IT))
/**
* @}
*/
#define IS_FLASH_FLAG_BANK1(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))
#define IS_FLASH_FLAG_BANK1(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))
#define IS_FLASH_FLAG_BANK2(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))
/** @defgroup FLASH_Address FLASH Address
* @{
*/
#define IS_FLASH_FLAG_BANK2(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))
#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < FLASH_BANK2_BASE))
#define IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) <= FLASH_END))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))
#if defined (FLASH_OPTCR_PG_OTP)
#define IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS) (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) || \
IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS))
#else
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))
#endif /* FLASH_OPTCR_PG_OTP */
#define IS_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= (0x3FFF0000U))
@ -615,9 +797,6 @@ extern FLASH_ProcessTypeDef pFlash;
#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \
((BANK) == FLASH_BANK_2))
/**
* @}
*/
/**
* @}

135
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash_ex.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash_ex.c
View File

@ -120,10 +120,15 @@ static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureA
static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank);
static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank);
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1);
static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1);
#endif /*DUAL_CORE*/
#endif /* DUAL_CORE */
#if defined (FLASH_OTPBL_LOCKBL)
static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block);
static uint32_t FLASH_OB_OTP_GetLock(void);
#endif /* FLASH_OTPBL_LOCKBL */
/**
* @}
*/
@ -309,14 +314,24 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
{
/* Enable End of Operation and Error interrupts for Bank 1 */
#if defined (FLASH_CR_OPERRIE)
__HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
#else
__HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
#endif /* FLASH_CR_OPERRIE */
}
if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
/* Enable End of Operation and Error interrupts for Bank 2 */
#if defined (FLASH_CR_OPERRIE)
__HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
#else
__HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
#endif /* FLASH_CR_OPERRIE */
}
if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
@ -444,30 +459,38 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
}
#if defined(DUAL_CORE)
/*CM7 Boot Address configuration*/
/* CM7 Boot Address configuration */
if((pOBInit->OptionType & OPTIONBYTE_CM7_BOOTADD) == OPTIONBYTE_CM7_BOOTADD)
{
FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
}
/*CM4 Boot Address configuration*/
/* CM4 Boot Address configuration */
if((pOBInit->OptionType & OPTIONBYTE_CM4_BOOTADD) == OPTIONBYTE_CM4_BOOTADD)
{
FLASH_OB_CM4BootAddConfig(pOBInit->CM4BootConfig, pOBInit->CM4BootAddr0, pOBInit->CM4BootAddr1);
}
#else /* Single Core*/
/*Boot Address configuration*/
/* Boot Address configuration */
if((pOBInit->OptionType & OPTIONBYTE_BOOTADD) == OPTIONBYTE_BOOTADD)
{
FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
}
#endif /*DUAL_CORE*/
/*Bank1 secure area configuration*/
/* Secure area configuration */
if((pOBInit->OptionType & OPTIONBYTE_SECURE_AREA) == OPTIONBYTE_SECURE_AREA)
{
FLASH_OB_SecureAreaConfig(pOBInit->SecureAreaConfig, pOBInit->SecureAreaStartAddr, pOBInit->SecureAreaEndAddr,pOBInit->Banks);
}
#if defined(FLASH_OTPBL_LOCKBL)
/* OTP Block Lock configuration */
if((pOBInit->OptionType & OPTIONBYTE_OTP_LOCK) == OPTIONBYTE_OTP_LOCK)
{
FLASH_OB_OTP_LockConfig(pOBInit->OTPBlockLock);
}
#endif /* FLASH_OTPBL_LOCKBL */
}
/* Process Unlocked */
@ -522,6 +545,13 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
#else
pOBInit->OptionType |= OPTIONBYTE_BOOTADD;
#endif /*DUAL_CORE*/
#if defined (FLASH_OTPBL_LOCKBL)
pOBInit->OptionType |= OPTIONBYTE_OTP_LOCK;
/* Get OTP Block Lock */
pOBInit->OTPBlockLock = FLASH_OB_OTP_GetLock();
#endif /* FLASH_OTPBL_LOCKBL */
}
/**
@ -750,12 +780,17 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks)
{
/* Check the parameters */
#if defined (FLASH_CR_PSIZE)
assert_param(IS_VOLTAGERANGE(VoltageRange));
#else
UNUSED(VoltageRange);
#endif /* FLASH_CR_PSIZE */
assert_param(IS_FLASH_BANK(Banks));
/* Flash Mass Erase */
if((Banks & FLASH_BANK_BOTH) == FLASH_BANK_BOTH)
{
#if defined (FLASH_CR_PSIZE)
/* Reset Program/erase VoltageRange for Bank1 and Bank2 */
FLASH->CR1 &= (~FLASH_CR_PSIZE);
FLASH->CR2 &= (~FLASH_CR_PSIZE);
@ -763,6 +798,7 @@ static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks)
/* Set voltage range */
FLASH->CR1 |= VoltageRange;
FLASH->CR2 |= VoltageRange;
#endif /* FLASH_CR_PSIZE */
/* Set Mass Erase Bit */
FLASH->OPTCR |= FLASH_OPTCR_MER;
@ -772,21 +808,25 @@ static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks)
/* Proceed to erase Flash Bank */
if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
{
/* Reset Program/erase VoltageRange for Bank1 */
#if defined (FLASH_CR_PSIZE)
/* Set Program/erase VoltageRange for Bank1 */
FLASH->CR1 &= (~FLASH_CR_PSIZE);
FLASH->CR1 |= VoltageRange;
#endif /* FLASH_CR_PSIZE */
/* Bank1 will be erased, and set voltage range */
FLASH->CR1 |= FLASH_CR_BER | VoltageRange;
FLASH->CR1 |= FLASH_CR_START;
/* Erase Bank1 */
FLASH->CR1 |= (FLASH_CR_BER | FLASH_CR_START);
}
if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
/* Reset Program/erase VoltageRange for Bank2 */
#if defined (FLASH_CR_PSIZE)
/* Set Program/erase VoltageRange for Bank2 */
FLASH->CR2 &= (~FLASH_CR_PSIZE);
FLASH->CR2 |= VoltageRange;
#endif /* FLASH_CR_PSIZE */
/* Bank2 will be erased, and set voltage range */
FLASH->CR2 |= FLASH_CR_BER | VoltageRange;
FLASH->CR2 |= FLASH_CR_START;
/* Erase Bank2 */
FLASH->CR2 |= (FLASH_CR_BER | FLASH_CR_START);
}
}
}
@ -813,26 +853,40 @@ void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)
{
assert_param(IS_FLASH_SECTOR(Sector));
assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
#if defined (FLASH_CR_PSIZE)
assert_param(IS_VOLTAGERANGE(VoltageRange));
#else
UNUSED(VoltageRange);
#endif /* FLASH_CR_PSIZE */
if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
{
/* reset Program/erase VoltageRange for Bank1 */
#if defined (FLASH_CR_PSIZE)
/* Reset Program/erase VoltageRange and Sector Number for Bank1 */
FLASH->CR1 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
FLASH->CR1 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos));
FLASH->CR1 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
#else
/* Reset Sector Number for Bank1 */
FLASH->CR1 &= ~(FLASH_CR_SNB);
FLASH->CR1 |= FLASH_CR_START;
FLASH->CR1 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
#endif /* FLASH_CR_PSIZE */
}
if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
/* reset Program/erase VoltageRange for Bank2 */
#if defined (FLASH_CR_PSIZE)
/* Reset Program/erase VoltageRange and Sector Number for Bank2 */
FLASH->CR2 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
FLASH->CR2 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos));
FLASH->CR2 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
#else
/* Reset Sector Number for Bank2 */
FLASH->CR2 &= ~(FLASH_CR_SNB);
FLASH->CR2 |= FLASH_CR_START;
FLASH->CR2 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
#endif /* FLASH_CR_PSIZE */
}
}
@ -1165,7 +1219,7 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D2);
optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D2;
}
#endif /*DUAL_CORE*/
#endif /* DUAL_CORE */
if((UserType & OB_USER_SWAP_BANK) != 0U)
{
/* SWAP_BANK_OPT option byte should be modified */
@ -1186,6 +1240,18 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
optr_reg_mask |= FLASH_OPTSR_IO_HSLV;
}
#if defined (FLASH_OPTSR_VDDMMC_HSLV)
if((UserType & OB_USER_VDDMMC_HSLV) != 0U)
{
/* VDDMMC_HSLV option byte should be modified */
assert_param(IS_OB_USER_VDDMMC_HSLV(UserConfig & FLASH_OPTSR_VDDMMC_HSLV));
/* Set value and mask for VDDMMC_HSLV option byte */
optr_reg_val |= (UserConfig & FLASH_OPTSR_VDDMMC_HSLV);
optr_reg_mask |= FLASH_OPTSR_VDDMMC_HSLV;
}
#endif /* FLASH_OPTSR_VDDMMC_HSLV */
/* Configure the option bytes register */
MODIFY_REG(FLASH->OPTSR_PRG, optr_reg_mask, optr_reg_val);
}
@ -1603,6 +1669,33 @@ static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr,
* @}
*/
#if defined (FLASH_OTPBL_LOCKBL)
/**
* @brief Configure the OTP Block Lock.
* @param OTP_Block specifies the OTP Block to lock.
* This parameter can be a value of @ref FLASHEx_OTP_Blocks
* @retval None
*/
static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block)
{
/* Check the parameters */
assert_param(IS_OTP_BLOCK(OTP_Block));
/* Configure the OTP Block lock in the option bytes register */
FLASH->OTPBL_PRG |= (OTP_Block & FLASH_OTPBL_LOCKBL);
}
/**
* @brief Get the OTP Block Lock.
* @retval OTP_Block specifies the OTP Block to lock.
* This return value can be a value of @ref FLASHEx_OTP_Blocks
*/
static uint32_t FLASH_OB_OTP_GetLock(void)
{
return (FLASH->OTPBL_CUR);
}
#endif /* FLASH_OTPBL_LOCKBL */
#endif /* HAL_FLASH_MODULE_ENABLED */
/**

350
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash_ex.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash_ex.h
View File

@ -69,26 +69,26 @@ typedef struct
*/
typedef struct
{
uint32_t OptionType; /*!< Option byte to be configured.
This parameter can be a value of @ref FLASHEx_Option_Type */
uint32_t OptionType; /*!< Option byte to be configured.
This parameter can be a value of @ref FLASHEx_Option_Type */
uint32_t WRPState; /*!< Write protection activation or deactivation.
This parameter can be a value of @ref FLASHEx_WRP_State */
uint32_t WRPState; /*!< Write protection activation or deactivation.
This parameter can be a value of @ref FLASHEx_WRP_State */
uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
The value of this parameter depend on device used within the same series */
uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
The value of this parameter depend on device used within the same series */
uint32_t RDPLevel; /*!< Set the read protection level.
This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
uint32_t RDPLevel; /*!< Set the read protection level.
This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
uint32_t BORLevel; /*!< Set the BOR Level.
This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
uint32_t BORLevel; /*!< Set the BOR Level.
This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
This parameter can be a combination of @ref FLASHEx_OB_USER_Type */
uint32_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY /
IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */
uint32_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY /
IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */
uint32_t Banks; /*!< Select banks for WRP , PCROP and secure area config .
This parameter must be a value of @ref FLASHEx_Banks */
@ -103,13 +103,13 @@ typedef struct
uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP).
This parameter must be a value between PCROP Start address and end of a bank */
uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1
uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1
or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
uint32_t BootAddr0; /*!< Boot Address 0.
uint32_t BootAddr0; /*!< Boot Address 0.
This parameter must be a value between begin and end of a bank */
uint32_t BootAddr1; /*!< Boot Address 1.
uint32_t BootAddr1; /*!< Boot Address 1.
This parameter must be a value between begin and end of a bank */
#if defined(DUAL_CORE)
uint32_t CM4BootConfig; /*!< specifies if the CM4 boot Address to be configured BOOT_ADD0, BOOT_ADD1
@ -123,9 +123,9 @@ typedef struct
This parameter must be a value between begin and end of a bank */
#endif /*DUAL_CORE*/
uint32_t SecureAreaConfig; /*!< specifies if the bank secured area shall be erased or not
when RDP level decreased from Level 1 to Level 0 or during a mass erase.
This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */
uint32_t SecureAreaConfig; /*!< specifies if the bank secured area shall be erased or not
when RDP level decreased from Level 1 to Level 0 or during a mass erase.
This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */
uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address.
This parameter must be a value between begin address and end address of bank1 */
@ -133,6 +133,11 @@ typedef struct
uint32_t SecureAreaEndAddr; /*!< Bank Secure area End address.
This parameter must be a value between Secure Area Start address and end address of a bank1 */
#if defined (FLASH_OTPBL_LOCKBL)
uint32_t OTPBlockLock; /*!< Specifies the OTP block(s) to be locked.
This parameter must be a value of @ref FLASHEx_OTP_Blocks */
#endif /* FLASH_OTPBL_LOCKBL */
} FLASH_OBProgramInitTypeDef;
/**
@ -140,20 +145,20 @@ typedef struct
*/
typedef struct
{
uint32_t TypeCRC; /*!< CRC Selection Type.
This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */
uint32_t TypeCRC; /*!< CRC Selection Type.
This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */
uint32_t BurstSize; /*!< CRC Burst Size.
This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */
uint32_t BurstSize; /*!< CRC Burst Size.
This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */
uint32_t Bank; /*!< Select bank where CRC computation is enabled.
This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */
uint32_t Bank; /*!< Select bank where CRC computation is enabled.
This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */
uint32_t Sector; /*!< Initial FLASH sector from which starts the CRC computation
This parameter must be a value of @ref FLASH_Sectors */
uint32_t Sector; /*!< Initial FLASH sector from which starts the CRC computation
This parameter must be a value of @ref FLASH_Sectors */
uint32_t NbSectors; /*!< Number of sectors to be computed.
This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
uint32_t NbSectors; /*!< Number of sectors to be computed.
This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
uint32_t CRCStartAddr; /*!< CRC Start address.
This parameter must be a value between begin address and end address of a bank */
@ -181,6 +186,7 @@ typedef struct
* @}
*/
#if defined (FLASH_CR_PSIZE)
/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
* @{
*/
@ -191,6 +197,7 @@ typedef struct
/**
* @}
*/
#endif /* FLASH_CR_PSIZE */
/** @defgroup FLASHEx_WRP_State FLASH WRP State
* @{
@ -210,13 +217,16 @@ typedef struct
#define OPTIONBYTE_PCROP 0x08U /*!< PCROP option byte configuration */
#define OPTIONBYTE_BOR 0x10U /*!< BOR option byte configuration */
#define OPTIONBYTE_SECURE_AREA 0x20U /*!< secure area option byte configuration */
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
#define OPTIONBYTE_CM7_BOOTADD 0x40U /*!< CM7 BOOT ADD option byte configuration */
#define OPTIONBYTE_CM4_BOOTADD 0x80U /*!< CM4 BOOT ADD option byte configuration */
#define OPTIONBYTE_BOOTADD OPTIONBYTE_CM7_BOOTADD /*!< BOOT ADD option byte configuration */
#else /* Single core*/
#else /* Single core */
#define OPTIONBYTE_BOOTADD 0x40U /*!< BOOT ADD option byte configuration */
#endif /*DUAL_CORE*/
#if defined (FLASH_OTPBL_LOCKBL)
#define OPTIONBYTE_OTP_LOCK 0x80U /*!< OTP Lock option byte configuration */
#endif /* FLASH_OTPBL_LOCKBL */
/**
* @}
*/
@ -272,8 +282,8 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
* @{
*/
#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Freeze IWDG counter in STOP mode */
#define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */
#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Freeze IWDG counter in STOP mode */
#define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */
/**
* @}
*/
@ -281,8 +291,8 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
* @{
*/
#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */
#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY /*!< IWDG counter active in STANDBY mode */
#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */
#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY /*!< IWDG counter active in STANDBY mode */
/**
* @}
*/
@ -290,10 +300,10 @@ typedef struct
/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
* @{
*/
#define OB_BOR_LEVEL0 0x00000000U /*!< Reset level threshold is set to 1.6V */
#define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level threshold is set to 2.1V */
#define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level threshold is set to 2.4V */
#define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V */
#define OB_BOR_LEVEL0 0x00000000U /*!< Reset level threshold is set to 1.6V */
#define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level threshold is set to 2.1V */
#define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level threshold is set to 2.4V */
#define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V */
/**
* @}
*/
@ -303,13 +313,13 @@ typedef struct
/** @defgroup FLASHEx_Boot_Address FLASH Boot Address
* @{
*/
#define OB_BOOTADDR_ITCM_RAM 0x0000U /*!< Boot from ITCM RAM (0x00000000) */
#define OB_BOOTADDR_SYSTEM 0x0040U /*!< Boot from System memory bootloader (0x00100000) */
#define OB_BOOTADDR_ITCM_FLASH 0x0080U /*!< Boot from Flash on ITCM interface (0x00200000) */
#define OB_BOOTADDR_AXIM_FLASH 0x2000U /*!< Boot from Flash on AXIM interface (0x08000000) */
#define OB_BOOTADDR_DTCM_RAM 0x8000U /*!< Boot from DTCM RAM (0x20000000) */
#define OB_BOOTADDR_SRAM1 0x8004U /*!< Boot from SRAM1 (0x20010000) */
#define OB_BOOTADDR_SRAM2 0x8013U /*!< Boot from SRAM2 (0x2004C000) */
#define OB_BOOTADDR_ITCM_RAM 0x0000U /*!< Boot from ITCM RAM (0x00000000) */
#define OB_BOOTADDR_SYSTEM 0x0040U /*!< Boot from System memory bootloader (0x00100000) */
#define OB_BOOTADDR_ITCM_FLASH 0x0080U /*!< Boot from Flash on ITCM interface (0x00200000) */
#define OB_BOOTADDR_AXIM_FLASH 0x2000U /*!< Boot from Flash on AXIM interface (0x08000000) */
#define OB_BOOTADDR_DTCM_RAM 0x8000U /*!< Boot from DTCM RAM (0x20000000) */
#define OB_BOOTADDR_SRAM1 0x8004U /*!< Boot from SRAM1 (0x20010000) */
#define OB_BOOTADDR_SRAM2 0x8013U /*!< Boot from SRAM2 (0x2004C000) */
/**
* @}
*/
@ -340,9 +350,9 @@ typedef struct
/** @defgroup FLASHEx_Banks FLASH Banks
* @{
*/
#define FLASH_BANK_1 0x01U /*!< Bank 1 */
#define FLASH_BANK_2 0x02U /*!< Bank 2 */
#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
#define FLASH_BANK_1 0x01U /*!< Bank 1 */
#define FLASH_BANK_2 0x02U /*!< Bank 2 */
#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
/**
* @}
*/
@ -350,10 +360,10 @@ typedef struct
/** @defgroup FLASHEx_OB_PCROP_RDP FLASHEx OB PCROP RDP
* @{
*/
#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level
is decreased from Level 1 to Level 0 or during a mass erase */
#define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is
decreased from Level 1 to Level 0 (full mass erase) */
#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level
is decreased from Level 1 to Level 0 or during a mass erase */
#define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is
decreased from Level 1 to Level 0 (full mass erase) */
/**
* @}
@ -362,15 +372,51 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
* @{
*/
#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */
#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */
#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */
#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */
#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */
#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */
#define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */
#define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */
#define OB_WRP_SECTOR_All 0x000000FFU /*!< Write protection of all Sectors */
#if (FLASH_SECTOR_TOTAL == 128)
#define OB_WRP_SECTOR_0TO3 0x00000001U /*!< Write protection of Sector0 to Sector3 */
#define OB_WRP_SECTOR_4TO7 0x00000002U /*!< Write protection of Sector4 to Sector7 */
#define OB_WRP_SECTOR_8TO11 0x00000004U /*!< Write protection of Sector8 to Sector11 */
#define OB_WRP_SECTOR_12TO15 0x00000008U /*!< Write protection of Sector12 to Sector15 */
#define OB_WRP_SECTOR_16TO19 0x00000010U /*!< Write protection of Sector16 to Sector19 */
#define OB_WRP_SECTOR_20TO23 0x00000020U /*!< Write protection of Sector20 to Sector23 */
#define OB_WRP_SECTOR_24TO27 0x00000040U /*!< Write protection of Sector24 to Sector27 */
#define OB_WRP_SECTOR_28TO31 0x00000080U /*!< Write protection of Sector28 to Sector31 */
#define OB_WRP_SECTOR_32TO35 0x00000100U /*!< Write protection of Sector32 to Sector35 */
#define OB_WRP_SECTOR_36TO39 0x00000200U /*!< Write protection of Sector36 to Sector39 */
#define OB_WRP_SECTOR_40TO43 0x00000400U /*!< Write protection of Sector40 to Sector43 */
#define OB_WRP_SECTOR_44TO47 0x00000800U /*!< Write protection of Sector44 to Sector47 */
#define OB_WRP_SECTOR_48TO51 0x00001000U /*!< Write protection of Sector48 to Sector51 */
#define OB_WRP_SECTOR_52TO55 0x00002000U /*!< Write protection of Sector52 to Sector55 */
#define OB_WRP_SECTOR_56TO59 0x00004000U /*!< Write protection of Sector56 to Sector59 */
#define OB_WRP_SECTOR_60TO63 0x00008000U /*!< Write protection of Sector60 to Sector63 */
#define OB_WRP_SECTOR_64TO67 0x00010000U /*!< Write protection of Sector64 to Sector67 */
#define OB_WRP_SECTOR_68TO71 0x00020000U /*!< Write protection of Sector68 to Sector71 */
#define OB_WRP_SECTOR_72TO75 0x00040000U /*!< Write protection of Sector72 to Sector75 */
#define OB_WRP_SECTOR_76TO79 0x00080000U /*!< Write protection of Sector76 to Sector79 */
#define OB_WRP_SECTOR_80TO83 0x00100000U /*!< Write protection of Sector80 to Sector83 */
#define OB_WRP_SECTOR_84TO87 0x00200000U /*!< Write protection of Sector84 to Sector87 */
#define OB_WRP_SECTOR_88TO91 0x00400000U /*!< Write protection of Sector88 to Sector91 */
#define OB_WRP_SECTOR_92TO95 0x00800000U /*!< Write protection of Sector92 to Sector95 */
#define OB_WRP_SECTOR_96TO99 0x01000000U /*!< Write protection of Sector96 to Sector99 */
#define OB_WRP_SECTOR_100TO103 0x02000000U /*!< Write protection of Sector100 to Sector103 */
#define OB_WRP_SECTOR_104TO107 0x04000000U /*!< Write protection of Sector104 to Sector107 */
#define OB_WRP_SECTOR_108TO111 0x08000000U /*!< Write protection of Sector108 to Sector111 */
#define OB_WRP_SECTOR_112TO115 0x10000000U /*!< Write protection of Sector112 to Sector115 */
#define OB_WRP_SECTOR_116TO119 0x20000000U /*!< Write protection of Sector116 to Sector119 */
#define OB_WRP_SECTOR_120TO123 0x40000000U /*!< Write protection of Sector120 to Sector123 */
#define OB_WRP_SECTOR_124TO127 0x80000000U /*!< Write protection of Sector124 to Sector127 */
#define OB_WRP_SECTOR_ALL 0xFFFFFFFFU /*!< Write protection of all Sectors */
#else
#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */
#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */
#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */
#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */
#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */
#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */
#define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */
#define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */
#define OB_WRP_SECTOR_ALL 0x000000FFU /*!< Write protection of all Sectors */
#endif /* FLASH_SECTOR_TOTAL == 128 */
/**
* @}
*/
@ -387,10 +433,10 @@ typedef struct
/** @defgroup FLASHEx_OB_ST_RAM_SIZE FLASHEx OB ST RAM SIZE
* @{
*/
#define OB_ST_RAM_SIZE_2KB 0x00000000U /*!< 2 Kbytes reserved to ST code */
#define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */
#define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */
#define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE /*!< 16 Kbytes reserved to ST code */
#define OB_ST_RAM_SIZE_2KB 0x00000000U /*!< 2 Kbytes reserved to ST code */
#define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */
#define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */
#define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE /*!< 16 Kbytes reserved to ST code */
/**
* @}
*/
@ -414,7 +460,7 @@ typedef struct
/**
* @}
*/
#endif /*DUAL_CORE*/
#endif /* DUAL_CORE */
/** @defgroup FLASHEx_OB_IWDG1_SW FLASHEx OB IWDG1 SW
* @{
@ -454,7 +500,7 @@ typedef struct
* @}
*/
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
/** @defgroup FLASHEx_OB_NRST_STOP_D2 FLASHEx OB NRST STOP D2
* @{
*/
@ -472,7 +518,7 @@ typedef struct
/**
* @}
*/
#endif
#endif /* DUAL_CORE */
/** @defgroup FLASHEx_OB_SWAP_BANK FLASHEx OB SWAP BANK
* @{
@ -486,18 +532,29 @@ typedef struct
/** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV
* @{
*/
#define OB_IOHSLV_DISABLE 0x00000000U /*!< IOHSLV disabled */
#define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */
#define OB_IOHSLV_DISABLE 0x00000000U /*!< IOHSLV disabled */
#define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */
/**
* @}
*/
#if defined (FLASH_OPTSR_VDDMMC_HSLV)
/** @defgroup FLASHEx_OB_VDDMMC_HSLV FLASHEx OB VDDMMC HSLV
* @{
*/
#define OB_VDDMMC_HSLV_DISABLE 0x00000000U /*!< VDDMMC HSLV disabled */
#define OB_VDDMMC_HSLV_ENABLE FLASH_OPTSR_VDDMMC_HSLV /*!< VDDMMC HSLV enabled */
/**
* @}
*/
#endif /* FLASH_OPTSR_VDDMMC_HSLV */
/** @defgroup FLASHEx_OB_BOOT_OPTION FLASHEx OB BOOT OPTION
* @{
*/
#define OB_BOOT_ADD0 0x01U /*!< Select Boot Address 0 */
#define OB_BOOT_ADD1 0x02U /*!< Select Boot Address 1 */
#define OB_BOOT_ADD_BOTH 0x03U /*!< Select Boot Address 0 and 1 */
#define OB_BOOT_ADD0 0x01U /*!< Select Boot Address 0 */
#define OB_BOOT_ADD1 0x02U /*!< Select Boot Address 1 */
#define OB_BOOT_ADD_BOTH 0x03U /*!< Select Boot Address 0 and 1 */
/**
* @}
*/
@ -514,6 +571,9 @@ typedef struct
#define OB_USER_SECURITY 0x0040U /*!< security selection */
#define OB_USER_IOHSLV 0x0080U /*!< IO HSLV selection */
#define OB_USER_SWAP_BANK 0x0100U /*!< Bank swap selection */
#if defined (FLASH_OPTSR_VDDMMC_HSLV)
#define OB_USER_VDDMMC_HSLV 0x0200U /*!< VDDMMC HSLV selection */
#endif /* FLASH_OPTSR_VDDMMC_HSLV */
#if defined (DUAL_CORE)
#define OB_USER_IWDG2_SW 0x0200U /*!< Window watchdog selection */
#define OB_USER_BCM4 0x0400U /*!< CM4 boot selection */
@ -533,7 +593,6 @@ typedef struct
is decreased from Level 1 to Level 0 or during a mass erase */
#define OB_SECURE_RDP_ERASE FLASH_SCAR_DMES /*!< Secure area is erased when the RDP level is
decreased from Level 1 to Level 0 (full mass erase) */
/**
* @}
*/
@ -570,6 +629,32 @@ typedef struct
* @}
*/
#if defined (FLASH_OTPBL_LOCKBL)
/** @defgroup FLASHEx_OTP_Blocks FLASH OTP blocks
* @{
*/
#define FLASH_OTP_BLOCK_0 0x00000001U /*!< OTP Block0 */
#define FLASH_OTP_BLOCK_1 0x00000002U /*!< OTP Block1 */
#define FLASH_OTP_BLOCK_2 0x00000004U /*!< OTP Block2 */
#define FLASH_OTP_BLOCK_3 0x00000008U /*!< OTP Block3 */
#define FLASH_OTP_BLOCK_4 0x00000010U /*!< OTP Block4 */
#define FLASH_OTP_BLOCK_5 0x00000020U /*!< OTP Block5 */
#define FLASH_OTP_BLOCK_6 0x00000040U /*!< OTP Block6 */
#define FLASH_OTP_BLOCK_7 0x00000080U /*!< OTP Block7 */
#define FLASH_OTP_BLOCK_8 0x00000100U /*!< OTP Block8 */
#define FLASH_OTP_BLOCK_9 0x00000200U /*!< OTP Block9 */
#define FLASH_OTP_BLOCK_10 0x00000400U /*!< OTP Block10 */
#define FLASH_OTP_BLOCK_11 0x00000800U /*!< OTP Block11 */
#define FLASH_OTP_BLOCK_12 0x00001000U /*!< OTP Block12 */
#define FLASH_OTP_BLOCK_13 0x00002000U /*!< OTP Block13 */
#define FLASH_OTP_BLOCK_14 0x00004000U /*!< OTP Block14 */
#define FLASH_OTP_BLOCK_15 0x00008000U /*!< OTP Block15 */
#define FLASH_OTP_BLOCK_ALL 0x0000FFFFU /*!< OTP All Blocks */
/**
* @}
*/
#endif /* FLASH_OTPBL_LOCKBL */
/* Exported macro ------------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros
* @{
@ -585,6 +670,7 @@ typedef struct
* @}
*/
#if defined (FLASH_CR_PSIZE)
/**
* @brief Set the FLASH Program/Erase parallelism.
* @param __PSIZE__ FLASH Program/Erase parallelism
@ -605,6 +691,7 @@ typedef struct
#define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \
READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) : \
READ_BIT((FLASH->CR2), FLASH_CR_PSIZE))
#endif /* FLASH_CR_PSIZE */
/**
* @brief Set the FLASH Programming Delay.
@ -661,66 +748,75 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
* @{
*/
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
((VALUE) == FLASH_TYPEERASE_MASSERASE))
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
((VALUE) == FLASH_TYPEERASE_MASSERASE))
#define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
((RANGE) == FLASH_VOLTAGE_RANGE_4))
#if defined (FLASH_CR_PSIZE)
#define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
((RANGE) == FLASH_VOLTAGE_RANGE_4))
#endif /* FLASH_CR_PSIZE */
#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
((VALUE) == OB_WRPSTATE_ENABLE))
#if defined(DUAL_CORE)
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x3FFFU) && ((VALUE) != 0U))
#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
((VALUE) == OB_WRPSTATE_ENABLE))
#if defined (FLASH_OPTSR_VDDMMC_HSLV)
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x03FFU) && ((VALUE) != 0U))
#elif defined (DUAL_CORE)
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x3FFFU) && ((VALUE) != 0U))
#else
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x01FFU) && ((VALUE) != 0U))
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x01FFU) && ((VALUE) != 0U))
#endif /*DUAL_CORE*/
#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U)
#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U)
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
((LEVEL) == OB_RDP_LEVEL_1) ||\
((LEVEL) == OB_RDP_LEVEL_2))
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
((LEVEL) == OB_RDP_LEVEL_1) ||\
((LEVEL) == OB_RDP_LEVEL_2))
#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \
((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3))
#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \
((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3))
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
((LATENCY) == FLASH_LATENCY_1) || \
((LATENCY) == FLASH_LATENCY_2) || \
((LATENCY) == FLASH_LATENCY_3) || \
((LATENCY) == FLASH_LATENCY_4) || \
((LATENCY) == FLASH_LATENCY_5) || \
((LATENCY) == FLASH_LATENCY_6) || \
((LATENCY) == FLASH_LATENCY_7) || \
((LATENCY) == FLASH_LATENCY_8) || \
((LATENCY) == FLASH_LATENCY_9) || \
((LATENCY) == FLASH_LATENCY_10) || \
((LATENCY) == FLASH_LATENCY_11) || \
((LATENCY) == FLASH_LATENCY_12) || \
((LATENCY) == FLASH_LATENCY_13) || \
((LATENCY) == FLASH_LATENCY_14) || \
((LATENCY) == FLASH_LATENCY_15))
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
((LATENCY) == FLASH_LATENCY_1) || \
((LATENCY) == FLASH_LATENCY_2) || \
((LATENCY) == FLASH_LATENCY_3) || \
((LATENCY) == FLASH_LATENCY_4) || \
((LATENCY) == FLASH_LATENCY_5) || \
((LATENCY) == FLASH_LATENCY_6) || \
((LATENCY) == FLASH_LATENCY_7) || \
((LATENCY) == FLASH_LATENCY_8) || \
((LATENCY) == FLASH_LATENCY_9) || \
((LATENCY) == FLASH_LATENCY_10) || \
((LATENCY) == FLASH_LATENCY_11) || \
((LATENCY) == FLASH_LATENCY_12) || \
((LATENCY) == FLASH_LATENCY_13) || \
((LATENCY) == FLASH_LATENCY_14) || \
((LATENCY) == FLASH_LATENCY_15))
#define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL)
#define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL)
#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#if (FLASH_SECTOR_TOTAL == 8U)
#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#else
#define IS_OB_WRP_SECTOR(SECTOR) ((SECTOR) != 0x00000000U)
#endif /* FLASH_SECTOR_TOTAL == 8U */
#define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
((CONFIG) == OB_PCROP_RDP_ERASE))
#define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
((CONFIG) == OB_PCROP_RDP_ERASE))
#define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \
((CONFIG) == OB_SECURE_RDP_ERASE))
@ -729,10 +825,14 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
#define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
#if defined (FLASH_OPTSR_VDDMMC_HSLV)
#define IS_OB_USER_VDDMMC_HSLV(VALUE) (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE))
#endif /* FLASH_OPTSR_VDDMMC_HSLV */
#define IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
#define IS_OB_IWDG2_SOURCE(SOURCE) (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW))
#endif /*DUAL_CORE*/
#endif /* DUAL_CORE */
#define IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
#define IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
@ -746,7 +846,7 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
#define IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))
#if defined(DUAL_CORE)
#if defined (DUAL_CORE)
#define IS_OB_USER_BCM4(VALUE) (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE))
#define IS_OB_USER_BCM7(VALUE) (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE))
@ -754,12 +854,12 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
#define IS_OB_STOP_D2_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2))
#define IS_OB_STDBY_D2_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2))
#endif /*DUAL_CORE*/
#if defined(DUAL_CORE)
#endif /* DUAL_CORE */
#if defined (DUAL_CORE)
#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x3FFFU) && ((TYPE) != 0U))
#else
#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x73FU) && ((TYPE) != 0U))
#endif
#endif /* DUAL_CORE */
#define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \
((VALUE) == OB_BOOT_ADD1) || \
@ -768,6 +868,10 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
#define IS_FLASH_TYPECRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || \
((VALUE) == FLASH_CRC_SECTORS) || \
((VALUE) == FLASH_CRC_BANK))
#if defined (FLASH_OTPBL_LOCKBL)
#define IS_OTP_BLOCK(VALUE) ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U))
#endif /* FLASH_OTPBL_LOCKBL */
/**
* @}
*/

893
targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gfxmmu.c Normal file
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@ -0,0 +1,893 @@
/**
******************************************************************************
* @file stm32h7xx_hal_gfxmmu.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
* functionalities of the Graphic MMU (GFXMMU) peripheral:
* + Initialization and De-initialization.
* + LUT configuration.
* + Force flush and/or invalidate of cache.
* + Modify physical buffer adresses.
* + Modify cache and pre-fetch parameters.
* + Error management.
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** Initialization ***
======================
[..]
(#) As prerequisite, fill in the HAL_GFXMMU_MspInit() :
(++) Enable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE().
(++) If interrupts are used, enable and configure GFXMMU global
interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
(#) Configure the number of blocks per line, default value, physical
buffer addresses, cache and pre-fetch parameters and interrupts
using the HAL_GFXMMU_Init() function.
*** LUT configuration ***
=========================
[..]
(#) Use HAL_GFXMMU_DisableLutLines() to deactivate all LUT lines (or a
range of lines).
(#) Use HAL_GFXMMU_ConfigLut() to copy LUT from flash to look up RAM.
(#) Use HAL_GFXMMU_ConfigLutLine() to configure one line of LUT.
*** Force flush and/or invalidate of cache ***
==============================================
[..]
(#) Use HAL_GFXMMU_ConfigForceCache() to flush and/or invalidate cache.
*** Modify physical buffer adresses ***
=======================================
[..]
(#) Use HAL_GFXMMU_ModifyBuffers() to modify physical buffer addresses.
*** Modify cache and pre-fetch parameters ***
=============================================
[..]
(#) Use HAL_GFXMMU_ModifyCachePrefetch() to modify cache and pre-fetch
parameters.
*** Error management ***
========================
[..]
(#) If interrupts are used, HAL_GFXMMU_IRQHandler() will be called when
an error occurs. This function will call HAL_GFXMMU_ErrorCallback().
Use HAL_GFXMMU_GetError() to get the error code.
*** De-initialization ***
=========================
[..]
(#) As prerequisite, fill in the HAL_GFXMMU_MspDeInit() :
(++) Disable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE().
(++) If interrupts has been used, disable GFXMMU global interrupt with
HAL_NVIC_DisableIRQ().
(#) De-initialize GFXMMU using the HAL_GFXMMU_DeInit() function.
*** Callback registration ***
=============================
[..]
The compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use functions HAL_GFXMMU_RegisterCallback() to register a user callback.
[..]
Function HAL_GFXMMU_RegisterCallback() allows to register following callbacks:
(+) ErrorCallback : GFXMMU error.
(+) MspInitCallback : GFXMMU MspInit.
(+) MspDeInitCallback : GFXMMU MspDeInit.
[..]
This function takes as parameters the HAL peripheral handle, the callback ID
and a pointer to the user callback function.
[..]
Use function HAL_GFXMMU_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
HAL_GFXMMU_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the callback ID.
[..]
This function allows to reset following callbacks:
(+) ErrorCallback : GFXMMU error.
(+) MspInitCallback : GFXMMU MspInit.
(+) MspDeInitCallback : GFXMMU MspDeInit.
[..]
By default, after the HAL_GFXMMU_Init and if the state is HAL_GFXMMU_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
examples HAL_GFXMMU_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_GFXMMU_Init
and HAL_GFXMMU_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_GFXMMU_Init and HAL_GFXMMU_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_GFXMMU_RegisterCallback before calling HAL_GFXMMU_DeInit
or HAL_GFXMMU_Init function.
[..]
When the compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#ifdef HAL_GFXMMU_MODULE_ENABLED
#if defined(GFXMMU)
/** @defgroup GFXMMU GFXMMU
* @brief GFXMMU HAL driver module
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define GFXMMU_LUTXL_FVB_OFFSET 8U
#define GFXMMU_LUTXL_LVB_OFFSET 16U
#define GFXMMU_CR_ITS_MASK 0x1FU
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GFXMMU_Exported_Functions GFXMMU Exported Functions
* @{
*/
/** @defgroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Initialize the GFXMMU.
(+) De-initialize the GFXMMU.
@endverbatim
* @{
*/
/**
* @brief Initialize the GFXMMU according to the specified parameters in the
* GFXMMU_InitTypeDef structure and initialize the associated handle.
* @param hgfxmmu GFXMMU handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check GFXMMU handle */
if(hgfxmmu == NULL)
{
status = HAL_ERROR;
}
else
{
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_BLOCKS_PER_LINE(hgfxmmu->Init.BlocksPerLine));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf0Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf1Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf2Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf3Address));
assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.CachePrefetch.Activation));
assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.Interrupts.Activation));
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
/* Reset callback pointers to the weak predefined callbacks */
hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback;
/* Call GFXMMU MSP init function */
if(hgfxmmu->MspInitCallback == NULL)
{
hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
}
hgfxmmu->MspInitCallback(hgfxmmu);
#else
/* Call GFXMMU MSP init function */
HAL_GFXMMU_MspInit(hgfxmmu);
#endif
/* Configure blocks per line, cache and interrupts parameters on GFXMMU_CR register */
hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE |
GFXMMU_CR_AMEIE | GFXMMU_CR_192BM | GFXMMU_CR_CE | GFXMMU_CR_CL |
GFXMMU_CR_CLB | GFXMMU_CR_FC | GFXMMU_CR_PD | GFXMMU_CR_OC |
GFXMMU_CR_OB);
hgfxmmu->Instance->CR |= (hgfxmmu->Init.BlocksPerLine);
if(hgfxmmu->Init.CachePrefetch.Activation == ENABLE)
{
assert_param(IS_GFXMMU_CACHE_LOCK(hgfxmmu->Init.CachePrefetch.CacheLock));
assert_param(IS_GFXMMU_PREFETCH(hgfxmmu->Init.CachePrefetch.Prefetch));
assert_param(IS_GFXMMU_OUTTER_BUFFERABILITY(hgfxmmu->Init.CachePrefetch.OutterBufferability));
assert_param(IS_GFXMMU_OUTTER_CACHABILITY(hgfxmmu->Init.CachePrefetch.OutterCachability));
hgfxmmu->Instance->CR |= (GFXMMU_CR_CE |
hgfxmmu->Init.CachePrefetch.CacheLock |
hgfxmmu->Init.CachePrefetch.Prefetch |
hgfxmmu->Init.CachePrefetch.OutterBufferability |
hgfxmmu->Init.CachePrefetch.OutterCachability);
if(hgfxmmu->Init.CachePrefetch.CacheLock == GFXMMU_CACHE_LOCK_ENABLE)
{
assert_param(IS_GFXMMU_CACHE_LOCK_BUFFER(hgfxmmu->Init.CachePrefetch.CacheLockBuffer));
assert_param(IS_GFXMMU_CACHE_FORCE(hgfxmmu->Init.CachePrefetch.CacheForce));
hgfxmmu->Instance->CR |= (hgfxmmu->Init.CachePrefetch.CacheLockBuffer |
hgfxmmu->Init.CachePrefetch.CacheForce);
}
}
if(hgfxmmu->Init.Interrupts.Activation == ENABLE)
{
assert_param(IS_GFXMMU_INTERRUPTS(hgfxmmu->Init.Interrupts.UsedInterrupts));
hgfxmmu->Instance->CR |= hgfxmmu->Init.Interrupts.UsedInterrupts;
}
/* Configure default value on GFXMMU_DVR register */
hgfxmmu->Instance->DVR = hgfxmmu->Init.DefaultValue;
/* Configure physical buffer adresses on GFXMMU_BxCR registers */
hgfxmmu->Instance->B0CR = hgfxmmu->Init.Buffers.Buf0Address;
hgfxmmu->Instance->B1CR = hgfxmmu->Init.Buffers.Buf1Address;
hgfxmmu->Instance->B2CR = hgfxmmu->Init.Buffers.Buf2Address;
hgfxmmu->Instance->B3CR = hgfxmmu->Init.Buffers.Buf3Address;
/* Force invalidate cache if cache is enabled */
if(hgfxmmu->Init.CachePrefetch.Activation == ENABLE)
{
hgfxmmu->Instance->CCR |= GFXMMU_CACHE_FORCE_INVALIDATE;
}
/* Reset GFXMMU error code */
hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE;
/* Set GFXMMU to ready state */
hgfxmmu->State = HAL_GFXMMU_STATE_READY;
}
/* Return function status */
return status;
}
/**
* @brief De-initialize the GFXMMU.
* @param hgfxmmu GFXMMU handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check GFXMMU handle */
if(hgfxmmu == NULL)
{
status = HAL_ERROR;
}
else
{
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
/* Disable all interrupts on GFXMMU_CR register */
hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE |
GFXMMU_CR_AMEIE);
/* Call GFXMMU MSP de-init function */
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
if(hgfxmmu->MspDeInitCallback == NULL)
{
hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
}
hgfxmmu->MspDeInitCallback(hgfxmmu);
#else
HAL_GFXMMU_MspDeInit(hgfxmmu);
#endif
/* Set GFXMMU to reset state */
hgfxmmu->State = HAL_GFXMMU_STATE_RESET;
}
/* Return function status */
return status;
}
/**
* @brief Initialize the GFXMMU MSP.
* @param hgfxmmu GFXMMU handle.
* @retval None.
*/
__weak void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgfxmmu);
/* NOTE : This function should not be modified, when the function is needed,
the HAL_GFXMMU_MspInit could be implemented in the user file.
*/
}
/**
* @brief De-initialize the GFXMMU MSP.
* @param hgfxmmu GFXMMU handle.
* @retval None.
*/
__weak void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgfxmmu);
/* NOTE : This function should not be modified, when the function is needed,
the HAL_GFXMMU_MspDeInit could be implemented in the user file.
*/
}
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
/**
* @brief Register a user GFXMMU callback
* to be used instead of the weak predefined callback.
* @param hgfxmmu GFXMMU handle.
* @param CallbackID ID of the callback to be registered.
* This parameter can be one of the following values:
* @arg @ref HAL_GFXMMU_ERROR_CB_ID error callback ID.
* @arg @ref HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID.
* @arg @ref HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID.
* @param pCallback pointer to the callback function.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu,
HAL_GFXMMU_CallbackIDTypeDef CallbackID,
pGFXMMU_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if(pCallback == NULL)
{
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
else
{
if(HAL_GFXMMU_STATE_READY == hgfxmmu->State)
{
switch (CallbackID)
{
case HAL_GFXMMU_ERROR_CB_ID :
hgfxmmu->ErrorCallback = pCallback;
break;
case HAL_GFXMMU_MSPINIT_CB_ID :
hgfxmmu->MspInitCallback = pCallback;
break;
case HAL_GFXMMU_MSPDEINIT_CB_ID :
hgfxmmu->MspDeInitCallback = pCallback;
break;
default :
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if(HAL_GFXMMU_STATE_RESET == hgfxmmu->State)
{
switch (CallbackID)
{
case HAL_GFXMMU_MSPINIT_CB_ID :
hgfxmmu->MspInitCallback = pCallback;
break;
case HAL_GFXMMU_MSPDEINIT_CB_ID :
hgfxmmu->MspDeInitCallback = pCallback;
break;
default :
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
}
return status;
}
/**
* @brief Unregister a user GFXMMU callback.
* GFXMMU callback is redirected to the weak predefined callback.
* @param hgfxmmu GFXMMU handle.
* @param CallbackID ID of the callback to be unregistered.
* This parameter can be one of the following values:
* @arg @ref HAL_GFXMMU_ERROR_CB_ID error callback ID.
* @arg @ref HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID.
* @arg @ref HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu,
HAL_GFXMMU_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if(HAL_GFXMMU_STATE_READY == hgfxmmu->State)
{
switch (CallbackID)
{
case HAL_GFXMMU_ERROR_CB_ID :
hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback;
break;
case HAL_GFXMMU_MSPINIT_CB_ID :
hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
break;
case HAL_GFXMMU_MSPDEINIT_CB_ID :
hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
break;
default :
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if(HAL_GFXMMU_STATE_RESET == hgfxmmu->State)
{
switch (CallbackID)
{
case HAL_GFXMMU_MSPINIT_CB_ID :
hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
break;
case HAL_GFXMMU_MSPDEINIT_CB_ID :
hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
break;
default :
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup GFXMMU_Exported_Functions_Group2 Operations functions
* @brief GFXMMU operation functions
*
@verbatim
==============================================================================
##### Operation functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Configure LUT.
(+) Force flush and/or invalidate of cache.
(+) Modify physical buffer adresses.
(+) Modify cache and pre-fetch parameters.
(+) Manage error.
@endverbatim
* @{
*/
/**
* @brief This function allows to copy LUT from flash to look up RAM.
* @param hgfxmmu GFXMMU handle.
* @param FirstLine First line enabled on LUT.
* This parameter must be a number between Min_Data = 0 and Max_Data = 1023.
* @param LinesNumber Number of lines enabled on LUT.
* This parameter must be a number between Min_Data = 1 and Max_Data = 1024.
* @param Address Start address of LUT in flash.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu,
uint32_t FirstLine,
uint32_t LinesNumber,
uint32_t Address)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_LUT_LINE(FirstLine));
assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber));
/* Check GFXMMU state and coherent parameters */
if((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U))
{
status = HAL_ERROR;
}
else
{
uint32_t current_address, current_line, lutxl_address, lutxh_address;
/* Initialize local variables */
current_address = Address;
current_line = 0U;
lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]);
lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]);
/* Copy LUT from flash to look up RAM */
while(current_line < LinesNumber)
{
*((uint32_t *)lutxl_address) = *((uint32_t *)current_address);
current_address += 4U;
*((uint32_t *)lutxh_address) = *((uint32_t *)current_address);
current_address += 4U;
lutxl_address += 8U;
lutxh_address += 8U;
current_line++;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to disable a range of LUT lines.
* @param hgfxmmu GFXMMU handle.
* @param FirstLine First line to disable on LUT.
* This parameter must be a number between Min_Data = 0 and Max_Data = 1023.
* @param LinesNumber Number of lines to disable on LUT.
* This parameter must be a number between Min_Data = 1 and Max_Data = 1024.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu,
uint32_t FirstLine,
uint32_t LinesNumber)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_LUT_LINE(FirstLine));
assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber));
/* Check GFXMMU state and coherent parameters */
if((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U))
{
status = HAL_ERROR;
}
else
{
uint32_t current_line, lutxl_address, lutxh_address;
/* Initialize local variables */
current_line = 0U;
lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]);
lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]);
/* Disable LUT lines */
while(current_line < LinesNumber)
{
*((uint32_t *)lutxl_address) = 0U;
*((uint32_t *)lutxh_address) = 0U;
lutxl_address += 8U;
lutxh_address += 8U;
current_line++;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to configure one line of LUT.
* @param hgfxmmu GFXMMU handle.
* @param lutLine LUT line parameters.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_LUT_LINE(lutLine->LineNumber));
assert_param(IS_GFXMMU_LUT_LINE_STATUS(lutLine->LineStatus));
assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->FirstVisibleBlock));
assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->LastVisibleBlock));
assert_param(IS_GFXMMU_LUT_LINE_OFFSET(lutLine->LineOffset));
/* Check GFXMMU state */
if(hgfxmmu->State != HAL_GFXMMU_STATE_READY)
{
status = HAL_ERROR;
}
else
{
uint32_t lutxl_address, lutxh_address;
/* Initialize local variables */
lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * lutLine->LineNumber]);
lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * lutLine->LineNumber) + 1U]);
/* Configure LUT line */
if(lutLine->LineStatus == GFXMMU_LUT_LINE_ENABLE)
{
/* Enable and configure LUT line */
*((uint32_t *)lutxl_address) = (lutLine->LineStatus |
(lutLine->FirstVisibleBlock << GFXMMU_LUTXL_FVB_OFFSET) |
(lutLine->LastVisibleBlock << GFXMMU_LUTXL_LVB_OFFSET));
*((uint32_t *)lutxh_address) = (uint32_t) lutLine->LineOffset;
}
else
{
/* Disable LUT line */
*((uint32_t *)lutxl_address) = 0U;
*((uint32_t *)lutxh_address) = 0U;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to force flush and/or invalidate of cache.
* @param hgfxmmu GFXMMU handle.
* @param ForceParam Force cache parameter.
* This parameter can be a values combination of @ref GFXMMU_CacheForceParam.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_CACHE_FORCE_ACTION(ForceParam));
/* Check GFXMMU state and cache status */
if(((hgfxmmu->Instance->CR & GFXMMU_CR_CE) != GFXMMU_CR_CE) || (hgfxmmu->State != HAL_GFXMMU_STATE_READY))
{
status = HAL_ERROR;
}
else
{
/* Force flush and/or invalidate cache on GFXMMU_CCR register */
hgfxmmu->Instance->CCR |= ForceParam;
}
/* Return function status */
return status;
}
/**
* @brief This function allows to modify physical buffer addresses.
* @param hgfxmmu GFXMMU handle.
* @param Buffers Buffers parameters.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf0Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf1Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf2Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf3Address));
/* Check GFXMMU state */
if(hgfxmmu->State != HAL_GFXMMU_STATE_READY)
{
status = HAL_ERROR;
}
else
{
/* Modify physical buffer adresses on GFXMMU_BxCR registers */
hgfxmmu->Instance->B0CR = Buffers->Buf0Address;
hgfxmmu->Instance->B1CR = Buffers->Buf1Address;
hgfxmmu->Instance->B2CR = Buffers->Buf2Address;
hgfxmmu->Instance->B3CR = Buffers->Buf3Address;
}
/* Return function status */
return status;
}
/**
* @brief This function allows to modify cache and pre-fetch parameters.
* @param hgfxmmu GFXMMU handle.
* @param CachePrefetch Cache and pre-fetch parameters.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu,
GFXMMU_CachePrefetchTypeDef *CachePrefetch)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_FUNCTIONAL_STATE(CachePrefetch->Activation));
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
/* Check GFXMMU state */
if(hgfxmmu->State != HAL_GFXMMU_STATE_READY)
{
status = HAL_ERROR;
}
else
{
/* Modify cache and pre-fetch parameters on GFXMMU_CR register */
hgfxmmu->Instance->CR &= ~(GFXMMU_CR_CE | GFXMMU_CR_CL | GFXMMU_CR_CLB | GFXMMU_CR_FC |
GFXMMU_CR_PD | GFXMMU_CR_OC | GFXMMU_CR_OB);
if(CachePrefetch->Activation == ENABLE)
{
assert_param(IS_GFXMMU_CACHE_LOCK(CachePrefetch->CacheLock));
assert_param(IS_GFXMMU_PREFETCH(CachePrefetch->Prefetch));
assert_param(IS_GFXMMU_OUTTER_BUFFERABILITY(CachePrefetch->OutterBufferability));
assert_param(IS_GFXMMU_OUTTER_CACHABILITY(CachePrefetch->OutterCachability));
hgfxmmu->Instance->CR |= (GFXMMU_CR_CE |
CachePrefetch->CacheLock |
CachePrefetch->Prefetch |
CachePrefetch->OutterBufferability |
CachePrefetch->OutterCachability);
if(CachePrefetch->CacheLock == GFXMMU_CACHE_LOCK_ENABLE)
{
assert_param(IS_GFXMMU_CACHE_LOCK_BUFFER(CachePrefetch->CacheLockBuffer));
assert_param(IS_GFXMMU_CACHE_FORCE(CachePrefetch->CacheForce));
hgfxmmu->Instance->CR |= (CachePrefetch->CacheLockBuffer |
CachePrefetch->CacheForce);
}
}
}
/* Return function status */
return status;
}
/**
* @brief This function handles the GFXMMU interrupts.
* @param hgfxmmu GFXMMU handle.
* @retval None.
*/
void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu)
{
uint32_t flags, interrupts, error;
/* Read current flags and interrupts and determine which error occurs */
flags = hgfxmmu->Instance->SR;
interrupts = (hgfxmmu->Instance->CR & GFXMMU_CR_ITS_MASK);
error = (flags & interrupts);
if(error != 0U)
{
/* Clear flags on GFXMMU_FCR register */
hgfxmmu->Instance->FCR = error;
/* Update GFXMMU error code */
hgfxmmu->ErrorCode |= error;
/* Call GFXMMU error callback */
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
hgfxmmu->ErrorCallback(hgfxmmu);
#else
HAL_GFXMMU_ErrorCallback(hgfxmmu);
#endif
}
}
/**
* @brief Error callback.
* @param hgfxmmu GFXMMU handle.
* @retval None.
*/
__weak void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgfxmmu);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_GFXMMU_ErrorCallback could be implemented in the user file.
*/
}
/**
* @}
*/
/** @defgroup GFXMMU_Exported_Functions_Group3 State functions
* @brief GFXMMU state functions
*
@verbatim
==============================================================================
##### State functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Get GFXMMU handle state.
(+) Get GFXMMU error code.
@endverbatim
* @{
*/
/**
* @brief This function allows to get the current GFXMMU handle state.
* @param hgfxmmu GFXMMU handle.
* @retval GFXMMU state.
*/
HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu)
{
/* Return GFXMMU handle state */
return hgfxmmu->State;
}
/**
* @brief This function allows to get the current GFXMMU error code.
* @param hgfxmmu GFXMMU handle.
* @retval GFXMMU error code.
*/
uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu)
{
uint32_t error_code;
/* Enter in critical section */
__disable_irq();
/* Store and reset GFXMMU error code */
error_code = hgfxmmu->ErrorCode;
hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE;
/* Exit from critical section */
__enable_irq();
/* Return GFXMMU error code */
return error_code;
}
/**
* @}
*/
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* End of private functions --------------------------------------------------*/
/**
* @}
*/
#endif /* GFXMMU */
#endif /* HAL_GFXMMU_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gfxmmu.h Normal file
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@ -0,0 +1,453 @@
/**
******************************************************************************
* @file stm32h7xx_hal_gfxmmu.h
* @author MCD Application Team
* @brief Header file of GFXMMU HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7xx_HAL_GFXMMU_H
#define STM32H7xx_HAL_GFXMMU_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
#if defined(GFXMMU)
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup GFXMMU
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup GFXMMU_Exported_Types GFXMMU Exported Types
* @{
*/
/**
* @brief HAL GFXMMU states definition
*/
typedef enum
{
HAL_GFXMMU_STATE_RESET = 0x00U, /*!< GFXMMU not initialized */
HAL_GFXMMU_STATE_READY = 0x01U, /*!< GFXMMU initialized and ready for use */
}HAL_GFXMMU_StateTypeDef;
/**
* @brief GFXMMU buffers structure definition
*/
typedef struct
{
uint32_t Buf0Address; /*!< Physical address of buffer 0. */
uint32_t Buf1Address; /*!< Physical address of buffer 1. */
uint32_t Buf2Address; /*!< Physical address of buffer 2. */
uint32_t Buf3Address; /*!< Physical address of buffer 3. */
}GFXMMU_BuffersTypeDef;
/**
* @brief GFXMMU cache and pre-fetch structure definition
*/
typedef struct
{
FunctionalState Activation; /*!< Cache and pre-fetch enable/disable.
@note: All following parameters are usefull only if cache and pre-fetch are enabled. */
uint32_t CacheLock; /*!< Locking the cache to a buffer.
This parameter can be a value of @ref GFXMMU_CacheLock. */
uint32_t CacheLockBuffer; /*!< Buffer on which the cache is locked.
This parameter can be a value of @ref GFXMMU_CacheLockBuffer.
@note: Usefull only when lock of the cache is enabled. */
uint32_t CacheForce; /*!< Forcing the cache regardless MPU attributes.
This parameter can be a value of @ref GFXMMU_CacheForce.
@note: Usefull only when lock of the cache is enabled. */
uint32_t OutterBufferability; /*!< Bufferability of an access generated by the GFXMMU cache.
This parameter can be a value of @ref GFXMMU_OutterBufferability. */
uint32_t OutterCachability; /*!< Cachability of an access generated by the GFXMMU cache.
This parameter can be a value of @ref GFXMMU_OutterCachability. */
uint32_t Prefetch; /*!< Pre-fetch enable/disable.
This parameter can be a value of @ref GFXMMU_Prefetch. */
}GFXMMU_CachePrefetchTypeDef;
/**
* @brief GFXMMU interrupts structure definition
*/
typedef struct
{
FunctionalState Activation; /*!< Interrupts enable/disable */
uint32_t UsedInterrupts; /*!< Interrupts used.
This parameter can be a values combination of @ref GFXMMU_Interrupts.
@note: Usefull only when interrupts are enabled. */
}GFXMMU_InterruptsTypeDef;
/**
* @brief GFXMMU init structure definition
*/
typedef struct
{
uint32_t BlocksPerLine; /*!< Number of blocks of 16 bytes per line.
This parameter can be a value of @ref GFXMMU_BlocksPerLine. */
uint32_t DefaultValue; /*!< Value returned when virtual memory location not physically mapped. */
GFXMMU_BuffersTypeDef Buffers; /*!< Physical buffers addresses. */
GFXMMU_CachePrefetchTypeDef CachePrefetch; /*!< Cache and pre-fetch parameters. */
GFXMMU_InterruptsTypeDef Interrupts; /*!< Interrupts parameters. */
}GFXMMU_InitTypeDef;
/**
* @brief GFXMMU handle structure definition
*/
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
typedef struct __GFXMMU_HandleTypeDef
#else
typedef struct
#endif
{
GFXMMU_TypeDef *Instance; /*!< GFXMMU instance */
GFXMMU_InitTypeDef Init; /*!< GFXMMU init parameters */
HAL_GFXMMU_StateTypeDef State; /*!< GFXMMU state */
__IO uint32_t ErrorCode; /*!< GFXMMU error code */
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
void (*ErrorCallback) (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU error callback */
void (*MspInitCallback) (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP init callback */
void (*MspDeInitCallback) (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP de-init callback */
#endif
}GFXMMU_HandleTypeDef;
/**
* @brief GFXMMU LUT line structure definition
*/
typedef struct
{
uint32_t LineNumber; /*!< LUT line number.
This parameter must be a number between Min_Data = 0 and Max_Data = 1023. */
uint32_t LineStatus; /*!< LUT line enable/disable.
This parameter can be a value of @ref GFXMMU_LutLineStatus. */
uint32_t FirstVisibleBlock; /*!< First visible block on this line.
This parameter must be a number between Min_Data = 0 and Max_Data = 255. */
uint32_t LastVisibleBlock; /*!< Last visible block on this line.
This parameter must be a number between Min_Data = 0 and Max_Data = 255. */
int32_t LineOffset; /*!< Offset of block 0 of the current line in physical buffer.
This parameter must be a number between Min_Data = -4080 and Max_Data = 4190208.
@note: Line offset has to be computed with the following formula:
LineOffset = [(Blocks already used) - (1st visible block)]*BlockSize. */
}GFXMMU_LutLineTypeDef;
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
/**
* @brief GFXMMU callback ID enumeration definition
*/
typedef enum
{
HAL_GFXMMU_ERROR_CB_ID = 0x00U, /*!< GFXMMU error callback ID */
HAL_GFXMMU_MSPINIT_CB_ID = 0x01U, /*!< GFXMMU MSP init callback ID */
HAL_GFXMMU_MSPDEINIT_CB_ID = 0x02U /*!< GFXMMU MSP de-init callback ID */
}HAL_GFXMMU_CallbackIDTypeDef;
/**
* @brief GFXMMU callback pointer definition
*/
typedef void (*pGFXMMU_CallbackTypeDef)(GFXMMU_HandleTypeDef *hgfxmmu);
#endif
/**
* @}
*/
/* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GFXMMU_Exported_Constants GFXMMU Exported Constants
* @{
*/
/** @defgroup GFXMMU_BlocksPerLine GFXMMU blocks per line
* @{
*/
#define GFXMMU_256BLOCKS 0x00000000U /*!< 256 blocks of 16 bytes per line */
#define GFXMMU_192BLOCKS GFXMMU_CR_192BM /*!< 192 blocks of 16 bytes per line */
/**
* @}
*/
/** @defgroup GFXMMU_CacheLock GFXMMU cache lock
* @{
*/
#define GFXMMU_CACHE_LOCK_DISABLE 0x00000000U /*!< Cache not locked to a buffer */
#define GFXMMU_CACHE_LOCK_ENABLE GFXMMU_CR_CL /*!< Cache locked to a buffer */
/**
* @}
*/
/** @defgroup GFXMMU_CacheLockBuffer GFXMMU cache lock buffer
* @{
*/
#define GFXMMU_CACHE_LOCK_BUFFER0 0x00000000U /*!< Cache locked to buffer 0 */
#define GFXMMU_CACHE_LOCK_BUFFER1 GFXMMU_CR_CLB_0 /*!< Cache locked to buffer 1 */
#define GFXMMU_CACHE_LOCK_BUFFER2 GFXMMU_CR_CLB_1 /*!< Cache locked to buffer 2 */
#define GFXMMU_CACHE_LOCK_BUFFER3 GFXMMU_CR_CLB /*!< Cache locked to buffer 3 */
/**
* @}
*/
/** @defgroup GFXMMU_CacheForce GFXMMU cache force
* @{
*/
#define GFXMMU_CACHE_FORCE_DISABLE 0x00000000U /*!< Caching not forced */
#define GFXMMU_CACHE_FORCE_ENABLE GFXMMU_CR_FC /*!< Caching forced */
/**
* @}
*/
/** @defgroup GFXMMU_OutterBufferability GFXMMU outter bufferability
* @{
*/
#define GFXMMU_OUTTER_BUFFERABILITY_DISABLE 0x00000000U /*!< No bufferable */
#define GFXMMU_OUTTER_BUFFERABILITY_ENABLE GFXMMU_CR_OB /*!< Bufferable */
/**
* @}
*/
/** @defgroup GFXMMU_OutterCachability GFXMMU outter cachability
* @{
*/
#define GFXMMU_OUTTER_CACHABILITY_DISABLE 0x00000000U /*!< No cachable */
#define GFXMMU_OUTTER_CACHABILITY_ENABLE GFXMMU_CR_OC /*!< Cachable */
/**
* @}
*/
/** @defgroup GFXMMU_Prefetch GFXMMU pre-fetch
* @{
*/
#define GFXMMU_PREFETCH_DISABLE GFXMMU_CR_PD /*!< Pre-fetch disable */
#define GFXMMU_PREFETCH_ENABLE 0x00000000U /*!< Pre-fetch enable */
/**
* @}
*/
/** @defgroup GFXMMU_Interrupts GFXMMU interrupts
* @{
*/
#define GFXMMU_AHB_MASTER_ERROR_IT GFXMMU_CR_AMEIE /*!< AHB master error interrupt */
#define GFXMMU_BUFFER0_OVERFLOW_IT GFXMMU_CR_B0OIE /*!< Buffer 0 overflow interrupt */
#define GFXMMU_BUFFER1_OVERFLOW_IT GFXMMU_CR_B1OIE /*!< Buffer 1 overflow interrupt */
#define GFXMMU_BUFFER2_OVERFLOW_IT GFXMMU_CR_B2OIE /*!< Buffer 2 overflow interrupt */
#define GFXMMU_BUFFER3_OVERFLOW_IT GFXMMU_CR_B3OIE /*!< Buffer 3 overflow interrupt */
/**
* @}
*/
/** @defgroup GFXMMU_Error_Code GFXMMU Error Code
* @{
*/
#define GFXMMU_ERROR_NONE 0x00000000U /*!< No error */
#define GFXMMU_ERROR_BUFFER0_OVERFLOW GFXMMU_SR_B0OF /*!< Buffer 0 overflow */
#define GFXMMU_ERROR_BUFFER1_OVERFLOW GFXMMU_SR_B1OF /*!< Buffer 1 overflow */
#define GFXMMU_ERROR_BUFFER2_OVERFLOW GFXMMU_SR_B2OF /*!< Buffer 2 overflow */
#define GFXMMU_ERROR_BUFFER3_OVERFLOW GFXMMU_SR_B3OF /*!< Buffer 3 overflow */
#define GFXMMU_ERROR_AHB_MASTER GFXMMU_SR_AMEF /*!< AHB master error */
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
#define GFXMMU_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */
#endif
/**
* @}
*/
/** @defgroup GFXMMU_LutLineStatus GFXMMU LUT line status
* @{
*/
#define GFXMMU_LUT_LINE_DISABLE 0x00000000U /*!< LUT line disabled */
#define GFXMMU_LUT_LINE_ENABLE GFXMMU_LUTxL_EN /*!< LUT line enabled */
/**
* @}
*/
/** @defgroup GFXMMU_CacheForceParam GFXMMU cache force parameter
* @{
*/
#define GFXMMU_CACHE_FORCE_FLUSH GFXMMU_CCR_FF /*!< Force cache flush */
#define GFXMMU_CACHE_FORCE_INVALIDATE GFXMMU_CCR_FI /*!< Force cache invalidate */
/**
* @}
*/
/**
* @}
*/
/* End of exported constants -------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup GFXMMU_Exported_Macros GFXMMU Exported Macros
* @{
*/
/** @brief Reset GFXMMU handle state.
* @param __HANDLE__ GFXMMU handle.
* @retval None
*/
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_GFXMMU_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GFXMMU_STATE_RESET)
#endif
/**
* @}
*/
/* End of exported macros ----------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GFXMMU_Exported_Functions GFXMMU Exported Functions
* @{
*/
/** @addtogroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu);
HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu);
void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu);
void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu);
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
/* GFXMMU callbacks register/unregister functions *****************************/
HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu,
HAL_GFXMMU_CallbackIDTypeDef CallbackID,
pGFXMMU_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu,
HAL_GFXMMU_CallbackIDTypeDef CallbackID);
#endif
/**
* @}
*/
/** @addtogroup GFXMMU_Exported_Functions_Group2 Operations functions
* @{
*/
/* Operation functions ********************************************************/
HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu,
uint32_t FirstLine,
uint32_t LinesNumber,
uint32_t Address);
HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu,
uint32_t FirstLine,
uint32_t LinesNumber);
HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine);
HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam);
HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers);
HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu,
GFXMMU_CachePrefetchTypeDef *CachePrefetch);
void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu);
void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu);
/**
* @}
*/
/** @defgroup GFXMMU_Exported_Functions_Group3 State functions
* @{
*/
/* State function *************************************************************/
HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu);
uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu);
/**
* @}
*/
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup GFXMMU_Private_Macros GFXMMU Private Macros
* @{
*/
#define IS_GFXMMU_BLOCKS_PER_LINE(VALUE) (((VALUE) == GFXMMU_256BLOCKS) || \
((VALUE) == GFXMMU_192BLOCKS))
#define IS_GFXMMU_BUFFER_ADDRESS(VALUE) (((VALUE) & 0xFU) == 0U)
#define IS_GFXMMU_CACHE_LOCK(VALUE) (((VALUE) == GFXMMU_CACHE_LOCK_DISABLE) || \
((VALUE) == GFXMMU_CACHE_LOCK_ENABLE))
#define IS_GFXMMU_CACHE_LOCK_BUFFER(VALUE) (((VALUE) == GFXMMU_CACHE_LOCK_BUFFER0) || \
((VALUE) == GFXMMU_CACHE_LOCK_BUFFER1) || \
((VALUE) == GFXMMU_CACHE_LOCK_BUFFER2) || \
((VALUE) == GFXMMU_CACHE_LOCK_BUFFER3))
#define IS_GFXMMU_CACHE_FORCE(VALUE) (((VALUE) == GFXMMU_CACHE_FORCE_DISABLE) || \
((VALUE) == GFXMMU_CACHE_FORCE_ENABLE))
#define IS_GFXMMU_OUTTER_BUFFERABILITY(VALUE) (((VALUE) == GFXMMU_OUTTER_BUFFERABILITY_DISABLE) || \
((VALUE) == GFXMMU_OUTTER_BUFFERABILITY_ENABLE))
#define IS_GFXMMU_OUTTER_CACHABILITY(VALUE) (((VALUE) == GFXMMU_OUTTER_CACHABILITY_DISABLE) || \
((VALUE) == GFXMMU_OUTTER_CACHABILITY_ENABLE))
#define IS_GFXMMU_PREFETCH(VALUE) (((VALUE) == GFXMMU_PREFETCH_DISABLE) || \
((VALUE) == GFXMMU_PREFETCH_ENABLE))
#define IS_GFXMMU_INTERRUPTS(VALUE) (((VALUE) & 0x1FU) != 0U)
#define IS_GFXMMU_LUT_LINE(VALUE) ((VALUE) < 1024U)
#define IS_GFXMMU_LUT_LINES_NUMBER(VALUE) (((VALUE) > 0U) && ((VALUE) <= 1024U))
#define IS_GFXMMU_LUT_LINE_STATUS(VALUE) (((VALUE) == GFXMMU_LUT_LINE_DISABLE) || \
((VALUE) == GFXMMU_LUT_LINE_ENABLE))
#define IS_GFXMMU_LUT_BLOCK(VALUE) ((VALUE) < 256U)
#define IS_GFXMMU_LUT_LINE_OFFSET(VALUE) (((VALUE) >= -4080) && ((VALUE) <= 4190208))
#define IS_GFXMMU_CACHE_FORCE_ACTION(VALUE) (((VALUE) == GFXMMU_CACHE_FORCE_FLUSH) || \
((VALUE) == GFXMMU_CACHE_FORCE_INVALIDATE) || \
((VALUE) == (GFXMMU_CACHE_FORCE_FLUSH | GFXMMU_CACHE_FORCE_INVALIDATE)))
/**
* @}
*/
/* End of private macros -----------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#endif /* GFXMMU */
#ifdef __cplusplus
}
#endif
#endif /* STM32H7xx_HAL_GFXMMU_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

54
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_gpio.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio.c
View File

@ -198,26 +198,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
if (iocurrent != 0x00U)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
temp &= ~(0xFU << ((position & 0x07U) * 4U));
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
GPIOx->AFR[position >> 3U] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
GPIOx->MODER = temp;
/* In case of Output or Alternate function mode selection */
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
@ -243,6 +223,26 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
temp |= ((GPIO_Init->Pull) << (position * 2U));
GPIOx->PUPDR = temp;
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
temp &= ~(0xFU << ((position & 0x07U) * 4U));
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
GPIOx->AFR[position >> 3U] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
GPIOx->MODER = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
@ -333,9 +333,6 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
tmp &= (0x0FUL << (4U * (position & 0x03U)));
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
{
tmp = 0x0FUL << (4U * (position & 0x03U));
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
/* Clear EXTI line configuration for Current CPU */
EXTI_CurrentCPU->IMR1 &= ~(iocurrent);
EXTI_CurrentCPU->EMR1 &= ~(iocurrent);
@ -343,6 +340,9 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/* Clear Rising Falling edge configuration */
EXTI->RTSR1 &= ~(iocurrent);
EXTI->FTSR1 &= ~(iocurrent);
tmp = 0x0FUL << (4U * (position & 0x03U));
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
}
/*------------------------- GPIO Mode Configuration --------------------*/
@ -352,14 +352,14 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ;
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
}
position++;

30
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_gpio.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio.h
View File

@ -173,11 +173,7 @@ typedef enum
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#if defined(DUAL_CORE) && defined(CORE_CM4)
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D2->PR1 & (__EXTI_LINE__))
#else
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__))
#endif
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
/**
* @brief Clears the EXTI's line pending flags.
@ -185,11 +181,7 @@ typedef enum
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#if defined(DUAL_CORE) && defined(CORE_CM4)
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR1 = (__EXTI_LINE__))
#else
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))
#endif
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
/**
* @brief Checks whether the specified EXTI line is asserted or not.
@ -197,7 +189,7 @@ typedef enum
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__))
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
/**
* @brief Clears the EXTI's line pending bits.
@ -205,7 +197,7 @@ typedef enum
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
#if defined(DUAL_CORE)
/**
@ -214,7 +206,7 @@ typedef enum
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI_D2->PR1 & (__EXTI_LINE__))
#define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__))
/**
* @brief Clears the EXTI's line pending flags.
@ -222,7 +214,7 @@ typedef enum
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR1 = (__EXTI_LINE__))
#define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__))
/**
* @brief Checks whether the specified EXTI line is asserted or not.
@ -230,7 +222,7 @@ typedef enum
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI_D2->PR1 & (__EXTI_LINE__))
#define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__))
/**
* @brief Clears the EXTI's line pending bits.
@ -238,9 +230,9 @@ typedef enum
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI_D2->PR1 = (__EXTI_LINE__))
#define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__))
#endif
/**
* @brief Generates a Software interrupt on selected EXTI line.
* @param __EXTI_LINE__: specifies the EXTI line to check.
@ -304,8 +296,8 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
(((__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
((MODE) == GPIO_MODE_OUTPUT_OD) ||\

235
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_gpio_ex.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio_ex.h
View File

@ -46,14 +46,16 @@ extern "C" {
/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
* @{
*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
#if defined (PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */
#define GPIO_AF0_C1DSLEEP ((uint8_t)0x00) /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
#define GPIO_AF0_C1SLEEP ((uint8_t)0x00) /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
#define GPIO_AF0_D1PWREN ((uint8_t)0x00) /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */
@ -62,26 +64,32 @@ extern "C" {
#define GPIO_AF0_C2DSLEEP ((uint8_t)0x00) /* Cortex-M4 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
#define GPIO_AF0_C2SLEEP ((uint8_t)0x00) /* Cortex-M4 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
#endif /* DUAL_CORE */
#endif /* PWR_CPUCR_PDDS_D2 */
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
#if defined(HRTIM1)
#define GPIO_AF1_HRTIM1 ((uint8_t)0x01) /* HRTIM1 Alternate Function mapping */
#endif /* HRTIM1 */
/**
* @brief AF 2 selection
*/
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */
#define GPIO_AF2_HRTIM1 ((uint8_t)0x02) /* HRTIM2 Alternate Function mapping */
#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */
#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */
#if defined(HRTIM1)
#define GPIO_AF2_HRTIM1 ((uint8_t)0x02) /* HRTIM1 Alternate Function mapping */
#endif /* HRTIM1 */
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
/**
* @brief AF 3 selection
@ -89,11 +97,17 @@ extern "C" {
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF3_DFSDM1 ((uint8_t)0x03) /* DFSDM Alternate Function mapping */
#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM3 Alternate Function mapping */
#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */
#define GPIO_AF3_LPTIM4 ((uint8_t)0x03) /* LPTIM4 Alternate Function mapping */
#define GPIO_AF3_LPTIM5 ((uint8_t)0x03) /* LPTIM5 Alternate Function mapping */
#define GPIO_AF3_LPUART ((uint8_t)0x03) /* LPUART Alternate Function mapping */
#if defined(OCTOSPIM)
#define GPIO_AF3_OCTOSPIM_P1 ((uint8_t)0x03) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#define GPIO_AF3_OCTOSPIM_P2 ((uint8_t)0x03) /* OCTOSPI Manager Port 2 Alternate Function mapping */
#endif /* OCTOSPIM */
#if defined(HRTIM1)
#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM1 Alternate Function mapping */
#endif /* HRTIM1 */
/**
* @brief AF 4 selection
@ -106,7 +120,13 @@ extern "C" {
#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
#define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
#define GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */
#define GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */
#if defined(DFSDM2_BASE)
#define GPIO_AF4_DFSDM2 ((uint8_t)0x04) /* DFSDM2 Alternate Function mapping */
#endif /* DFSDM2_BASE */
#if defined(PSSI)
#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */
#endif /* PSSI */
/**
* @brief AF 5 selection
@ -119,17 +139,24 @@ extern "C" {
#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
#define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
#define GPIO_AF6_SAI3 ((uint8_t)0x06) /* SAI3 Alternate Function mapping */
#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */
#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */
#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */
#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */
#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
#if defined(DFSDM2_BASE)
#define GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */
#endif /* DFSDM2_BASE */
#if defined(SAI3)
#define GPIO_AF6_SAI3 ((uint8_t)0x06) /* SAI3 Alternate Function mapping */
#endif /* SAI3 */
#if defined(OCTOSPIM)
#define GPIO_AF6_OCTOSPIM_P1 ((uint8_t)0x06) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#endif /* OCTOSPIM */
/**
* @brief AF 7 selection
@ -148,83 +175,139 @@ extern "C" {
/**
* @brief AF 8 selection
*/
#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */
#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
#define GPIO_AF8_SAI4 ((uint8_t)0x08) /* SAI4 Alternate Function mapping */
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
#define GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */
#define GPIO_AF8_LPUART ((uint8_t)0x08) /* LPUART Alternate Function mapping */
#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */
#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */
#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
#define GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */
#define GPIO_AF8_LPUART ((uint8_t)0x08) /* LPUART Alternate Function mapping */
#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */
#if defined(SAI4)
#define GPIO_AF8_SAI4 ((uint8_t)0x08) /* SAI4 Alternate Function mapping */
#endif /* SAI4 */
/**
* @brief AF 9 selection
*/
#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */
#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
#define GPIO_AF9_SDMMC2 ((uint8_t)0x09) /* SDMMC2 Alternate Function mapping */
#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */
#define GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */
#define GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */
#define GPIO_AF9_SAI4 ((uint8_t)0x09) /* SAI4 Alternate Function mapping */
#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */
#define GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */
#define GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */
#if defined(QUADSPI)
#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */
#endif /* QUADSPI */
#if defined(SAI4)
#define GPIO_AF9_SAI4 ((uint8_t)0x09) /* SAI4 Alternate Function mapping */
#endif /* SAI4 */
#if defined(OCTOSPIM)
#define GPIO_AF9_OCTOSPIM_P1 ((uint8_t)0x09) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#define GPIO_AF9_OCTOSPIM_P2 ((uint8_t)0x09) /* OCTOSPI Manager Port 2 Alternate Function mapping */
#endif /* OCTOSPIM */
/**
* @brief AF 10 selection
*/
#define GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */
#define GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */
#define GPIO_AF10_SAI4 ((uint8_t)0xA) /* SAI4 Alternate Function mapping */
#define GPIO_AF10_SDMMC2 ((uint8_t)0xA) /* SDMMC2 Alternate Function mapping */
#define GPIO_AF10_OTG2_HS ((uint8_t)0xA) /* OTG2_HS Alternate Function mapping */
#define GPIO_AF10_OTG1_FS ((uint8_t)0xA) /* OTG1_FS Alternate Function mapping */
#define GPIO_AF10_COMP1 ((uint8_t)0xA) /* COMP1 Alternate Function mapping */
#define GPIO_AF10_COMP2 ((uint8_t)0xA) /* COMP2 Alternate Function mapping */
#define GPIO_AF10_LTDC ((uint8_t)0xA) /* LTDC Alternate Function mapping */
#define GPIO_AF10_CRS_SYNC ((uint8_t)0xA) /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above */
#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */
#define GPIO_AF10_SDMMC2 ((uint8_t)0x0A) /* SDMMC2 Alternate Function mapping */
#if defined(USB2_OTG_FS)
#define GPIO_AF10_OTG2_FS ((uint8_t)0x0A) /* OTG2_FS Alternate Function mapping */
#endif /*USB2_OTG_FS*/
#define GPIO_AF10_COMP1 ((uint8_t)0x0A) /* COMP1 Alternate Function mapping */
#define GPIO_AF10_COMP2 ((uint8_t)0x0A) /* COMP2 Alternate Function mapping */
#if defined(LTDC)
#define GPIO_AF10_LTDC ((uint8_t)0x0A) /* LTDC Alternate Function mapping */
#endif /*LTDC*/
#define GPIO_AF10_CRS_SYNC ((uint8_t)0x0A) /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above */
#if defined(QUADSPI)
#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */
#endif /* QUADSPI */
#if defined(SAI4)
#define GPIO_AF10_SAI4 ((uint8_t)0x0A) /* SAI4 Alternate Function mapping */
#endif /* SAI4 */
#if !defined(USB2_OTG_FS)
#define GPIO_AF10_OTG1_FS ((uint8_t)0x0A) /* OTG1_FS Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
#endif /* !USB2_OTG_FS */
#define GPIO_AF10_OTG1_HS ((uint8_t)0x0A) /* OTG1_HS Alternate Function mapping */
#if defined(OCTOSPIM)
#define GPIO_AF10_OCTOSPIM_P1 ((uint8_t)0x0A) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#endif /* OCTOSPIM */
#define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */
/**
* @brief AF 11 selection
*/
#define GPIO_AF11_SWP ((uint8_t)0x0B) /* SWP Alternate Function mapping */
#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */
#define GPIO_AF11_MDIOS ((uint8_t)0x0B) /* MDIOS Alternate Function mapping */
#define GPIO_AF11_OTG1_HS ((uint8_t)0x0B) /* OTG1_HS Alternate Function mapping */
#define GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */
#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */
#define GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM Alternate Function mapping */
#define GPIO_AF11_COMP1 ((uint8_t)0x0B) /* COMP1 Alternate Function mapping */
#define GPIO_AF11_COMP2 ((uint8_t)0x0B) /* COMP2 Alternate Function mapping */
#define GPIO_AF11_I2C4 ((uint8_t)0x0B) /* I2C4 Alternate Function mapping */
#define GPIO_AF11_SWP ((uint8_t)0x0B) /* SWP Alternate Function mapping */
#define GPIO_AF11_MDIOS ((uint8_t)0x0B) /* MDIOS Alternate Function mapping */
#define GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */
#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */
#define GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM1 Alternate Function mapping */
#define GPIO_AF11_COMP1 ((uint8_t)0x0B) /* COMP1 Alternate Function mapping */
#define GPIO_AF11_COMP2 ((uint8_t)0x0B) /* COMP2 Alternate Function mapping */
#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
#define GPIO_AF11_I2C4 ((uint8_t)0x0B) /* I2C4 Alternate Function mapping */
#if defined(DFSDM2_BASE)
#define GPIO_AF11_DFSDM2 ((uint8_t)0x0B) /* DFSDM2 Alternate Function mapping */
#endif /* DFSDM2_BASE */
#if defined(USART10)
#define GPIO_AF11_USART10 ((uint8_t)0x0B) /* USART10 Alternate Function mapping */
#endif /* USART10 */
#if defined(UART9)
#define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */
#endif /* UART9 */
#if defined(ETH)
#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */
#endif /* ETH */
#if defined(LTDC)
#define GPIO_AF11_LTDC ((uint8_t)0x0B) /* LTDC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
#endif /*LTDC*/
#if defined(OCTOSPIM)
#define GPIO_AF11_OCTOSPIM_P1 ((uint8_t)0x0B) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#endif /* OCTOSPIM */
/**
* @brief AF 12 selection
*/
#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
#define GPIO_AF12_SDMMC1 ((uint8_t)0xC) /* SDMMC1 Alternate Function mapping */
#define GPIO_AF12_MDIOS ((uint8_t)0xC) /* MDIOS Alternate Function mapping */
#define GPIO_AF12_OTG2_FS ((uint8_t)0xC) /* OTG2_FS Alternate Function mapping */
#define GPIO_AF12_COMP1 ((uint8_t)0xC) /* COMP1 Alternate Function mapping */
#define GPIO_AF12_COMP2 ((uint8_t)0xC) /* COMP2 Alternate Function mapping */
#define GPIO_AF12_LTDC ((uint8_t)0xC) /* LTDC Alternate Function mapping */
#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
#define GPIO_AF12_MDIOS ((uint8_t)0x0C) /* MDIOS Alternate Function mapping */
#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
#define GPIO_AF12_TIM8 ((uint8_t)0x0C) /* TIM8 Alternate Function mapping */
#if defined(LTDC)
#define GPIO_AF12_LTDC ((uint8_t)0x0C) /* LTDC Alternate Function mapping */
#endif /*LTDC*/
#if defined(USB2_OTG_FS)
#define GPIO_AF12_OTG1_FS ((uint8_t)0x0C) /* OTG1_FS Alternate Function mapping */
#endif /* USB2_OTG_FS */
/**
* @brief AF 13 selection
*/
#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */
#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
#define GPIO_AF13_COMP1 ((uint8_t)0x0D) /* COMP1 Alternate Function mapping */
#define GPIO_AF13_COMP2 ((uint8_t)0x0D) /* COMP2 Alternate Function mapping */
#define GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */
#if defined(LTDC)
#define GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */
#endif /*LTDC*/
#if defined(DSI)
#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */
#endif /* DSI */
#if defined(PSSI)
#define GPIO_AF13_PSSI ((uint8_t)0x0D) /* PSSI Alternate Function mapping */
#endif /* PSSI */
#define GPIO_AF13_TIM1 ((uint8_t)0x0D) /* TIM1 Alternate Function mapping */
/**
* @brief AF 14 selection
*/
#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */
#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */
#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
/**
@ -280,7 +363,7 @@ extern "C" {
#define GPIOI_PIN_AVAILABLE GPIO_PIN_All
#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All
#define GPIOH_PIN_AVAILABLE GPIO_PIN_All
#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \
#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \
GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
/**

951
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hash.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash.c
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File diff suppressed because it is too large Load Diff

60
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hash.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash.h
View File

@ -152,6 +152,8 @@ typedef struct
__IO uint32_t ErrorCode; /*!< HASH Error code */
__IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */
@ -226,11 +228,11 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/** @defgroup HASH_flags_definition HASH flags definitions
* @{
*/
#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the IP */
#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */
#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the Peripheral */
#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */
/**
* @}
@ -276,7 +278,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
*/
/** @brief Check whether or not the specified HASH flag is set.
* @param __FLAG__: specifies the flag to check.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
* @arg @ref HASH_FLAG_DCIS Digest calculation complete.
@ -291,7 +293,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/** @brief Clear the specified HASH flag.
* @param __FLAG__: specifies the flag to clear.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
* @arg @ref HASH_FLAG_DCIS Digest calculation complete
@ -301,7 +303,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/** @brief Enable the specified HASH interrupt.
* @param __INTERRUPT__: specifies the HASH interrupt source to enable.
* @param __INTERRUPT__ specifies the HASH interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
* @arg @ref HASH_IT_DCI Digest calculation complete
@ -310,7 +312,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
#define __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__))
/** @brief Disable the specified HASH interrupt.
* @param __INTERRUPT__: specifies the HASH interrupt source to disable.
* @param __INTERRUPT__ specifies the HASH interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
* @arg @ref HASH_IT_DCI Digest calculation complete
@ -319,7 +321,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
#define __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
/** @brief Reset HASH handle state.
* @param __HANDLE__: HASH handle.
* @param __HANDLE__ HASH handle.
* @retval None
*/
@ -335,7 +337,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/** @brief Reset HASH handle status.
* @param __HANDLE__: HASH handle.
* @param __HANDLE__ HASH handle.
* @retval None
*/
#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
@ -362,7 +364,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/**
* @brief Set the number of valid bits in the last word written in data register DIN.
* @param __SIZE__: size in bytes of last data written in Data register.
* @param __SIZE__ size in bytes of last data written in Data register.
* @retval None
*/
#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
@ -397,7 +399,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
/**
* @brief Ensure that HASH input data type is valid.
* @param __DATATYPE__: HASH input data type.
* @param __DATATYPE__ HASH input data type.
* @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
*/
#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
@ -405,21 +407,11 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
((__DATATYPE__) == HASH_DATATYPE_8B) || \
((__DATATYPE__) == HASH_DATATYPE_1B))
/**
* @brief Ensure that input data buffer size is valid for multi-buffer HASH
* processing in polling mode.
* @note This check is valid only for multi-buffer HASH processing in polling mode.
* @param __SIZE__: input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4U) == 0U)
/**
* @brief Ensure that input data buffer size is valid for multi-buffer HASH
* processing in DMA mode.
* @note This check is valid only for multi-buffer HASH processing in DMA mode.
* @param __SIZE__: input data buffer size.
* @param __SIZE__ input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U))
@ -428,21 +420,21 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
* @brief Ensure that input data buffer size is valid for multi-buffer HMAC
* processing in DMA mode.
* @note This check is valid only for multi-buffer HMAC processing in DMA mode.
* @param __HANDLE__: HASH handle.
* @param __SIZE__: input data buffer size.
* @param __HANDLE__ HASH handle.
* @param __SIZE__ input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))
/**
* @brief Ensure that handle phase is set to HASH processing.
* @param __HANDLE__: HASH handle.
* @param __HANDLE__ HASH handle.
* @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
*/
#define IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
/**
* @brief Ensure that handle phase is set to HMAC processing.
* @param __HANDLE__: HASH handle.
* @param __HANDLE__ HASH handle.
* @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
*/
#define IS_HMAC_PROCESSING(__HANDLE__) (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
@ -492,8 +484,11 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS
/* HASH processing using polling *********************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
/**
* @}
@ -505,7 +500,11 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p
/* HASH processing using IT **************************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
/**
* @}
@ -591,6 +590,7 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
/* Private functions */
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);

402
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hash_ex.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash_ex.c
View File

@ -33,16 +33,21 @@
e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to
HAL_HASHEx_xxx_Finish() is then required to retrieve the digest.
(#)Multi-buffer processing is possible in polling and DMA mode.
(#)Multi-buffer processing is possible in polling, interrupt and DMA modes.
(##) In polling mode, only multi-buffer HASH processing is possible.
API HAL_HASHEx_xxx_Accumulate() must be called for each input buffer, except for the last one.
User must resort to HAL_HASHEx_xxx_Start() to enter the last one and retrieve as
User must resort to HAL_HASHEx_xxx_Accumulate_End() to enter the last one and retrieve as
well the computed digest.
(##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer,
except for the last one.
User must resort to HAL_HASHEx_xxx_Accumulate_End_IT() to enter the last one and retrieve as
well the computed digest.
(##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
(+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
From that point, each buffer can be fed to the IP thru HAL_HASHEx_xxx_Start_DMA() API.
From that point, each buffer can be fed to the Peripheral thru HAL_HASHEx_xxx_Start_DMA() API.
Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
macro then wrap-up the HASH processing in feeding the last input buffer thru the
same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to
@ -50,7 +55,7 @@
(+++) HMAC processing (MD-5, SHA-1, SHA-224 and SHA-256 must all resort to
extended functions): after initialization, the key and the first input buffer are entered
in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
in the Peripheral with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
starts step 2.
The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this
point, the HMAC processing is still carrying out step 2.
@ -112,17 +117,19 @@
the hash value using one of the following algorithms:
(+) SHA224
(++) HAL_HASHEx_SHA224_Start()
(++) HAL_HASHEx_SHA224_Accumulate()
(++) HAL_HASHEx_SHA224_Accmlt()
(++) HAL_HASHEx_SHA224_Accmlt_End()
(+) SHA256
(++) HAL_HASHEx_SHA256_Start()
(++) HAL_HASHEx_SHA256_Accumulate()
(++) HAL_HASHEx_SHA256_Accmlt()
(++) HAL_HASHEx_SHA256_Accmlt_End()
[..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
[..] In case of multi-buffer HASH processing (a single digest is computed while
several buffers are fed to the IP), the user can resort to successive calls
several buffers are fed to the Peripheral), the user can resort to successive calls
to HAL_HASHEx_xxx_Accumulate() and wrap-up the digest computation by a call
to HAL_HASHEx_xxx_Start().
to HAL_HASHEx_xxx_Accumulate_End().
@endverbatim
* @{
@ -133,11 +140,11 @@
* @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout: Timeout value
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@ -148,37 +155,52 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
/**
* @brief If not already done, initialize the HASH peripheral in SHA224 mode then
* processes pInBuffer.
* @note Consecutive calls to HAL_HASHEx_SHA224_Accumulate() can be used to feed
* several input buffers back-to-back to the IP that will yield a single
* @note Consecutive calls to HAL_HASHEx_SHA224_Accmlt() can be used to feed
* several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
* HAL_HASHEx_SHA224_Start().
* HAL_HASHEx_SHA224_Accmlt_End().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
* the IP has already been initialized.
* @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Start()
* to read it, feeding at the same time the last input buffer to the IP.
* the Peripheral has already been initialized.
* @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Accmlt_End()
* to read it, feeding at the same time the last input buffer to the Peripheral.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Start() is able
* HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Accmlt_End() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes, must be a multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
}
/**
* @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA224_Accmlt() API.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout: Timeout value
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@ -189,28 +211,42 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
/**
* @brief If not already done, initialize the HASH peripheral in SHA256 mode then
* processes pInBuffer.
* @note Consecutive calls to HAL_HASHEx_SHA256_Accumulate() can be used to feed
* several input buffers back-to-back to the IP that will yield a single
* @note Consecutive calls to HAL_HASHEx_SHA256_Accmlt() can be used to feed
* several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
* HAL_HASHEx_SHA256_Start().
* HAL_HASHEx_SHA256_Accmlt_End().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
* the IP has already been initialized.
* @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Start()
* to read it, feeding at the same time the last input buffer to the IP.
* the Peripheral has already been initialized.
* @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Accmlt_End()
* to read it, feeding at the same time the last input buffer to the Peripheral.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Start() is able
* HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Accmlt_End() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes, must be a multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
}
/**
* @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA256_Accmlt() API.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
}
/**
* @}
@ -227,8 +263,12 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_
the hash value using one of the following algorithms:
(+) SHA224
(++) HAL_HASHEx_SHA224_Start_IT()
(++) HAL_HASHEx_SHA224_Accmlt_IT()
(++) HAL_HASHEx_SHA224_Accmlt_End_IT()
(+) SHA256
(++) HAL_HASHEx_SHA256_Start_IT()
(++) HAL_HASHEx_SHA256_Accmlt_IT()
(++) HAL_HASHEx_SHA256_Accmlt_End_IT()
@endverbatim
* @{
@ -239,10 +279,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_
* @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@ -250,14 +290,51 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
}
/**
* @brief If not already done, initialize the HASH peripheral in SHA224 mode then
* processes pInBuffer in interruption mode.
* @note Consecutive calls to HAL_HASHEx_SHA224_Accmlt_IT() can be used to feed
* several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
* HAL_HASHEx_SHA224_Accmlt_End_IT().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
* the Peripheral has already been initialized.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Accmlt_End_IT() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
}
/**
* @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA224_Accmlt_IT() API.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
}
/**
* @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@ -265,6 +342,43 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
}
/**
* @brief If not already done, initialize the HASH peripheral in SHA256 mode then
* processes pInBuffer in interruption mode.
* @note Consecutive calls to HAL_HASHEx_SHA256_Accmlt_IT() can be used to feed
* several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
* HAL_HASHEx_SHA256_Accmlt_End_IT().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
* the Peripheral has already been initialized.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Accmlt_End_IT() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
}
/**
* @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA256_Accmlt_IT() API.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
}
/**
* @}
*/
@ -285,7 +399,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
(++) HAL_HASHEx_SHA256_Start_DMA()
(++) HAL_HASHEx_SHA256_Finish()
[..] When resorting to DMA mode to enter the data in the IP, user must resort
[..] When resorting to DMA mode to enter the data in the Peripheral, user must resort
to HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with
HAL_HASHEx_xxx_Finish().
@ -303,12 +417,12 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer
* to feed the input buffer to the IP.
* to feed the input buffer to the Peripheral.
* @note Once the DMA transfer is finished, HAL_HASHEx_SHA224_Finish() API must
* be called to retrieve the computed digest.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -321,9 +435,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
* @note The API waits for DCIS to be set then reads the computed digest.
* @note HAL_HASHEx_SHA224_Finish() can be used as well to retrieve the digest in
* HMAC SHA224 mode.
* @param hhash: HASH handle.
* @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout: Timeout value.
* @param hhash HASH handle.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@ -333,12 +447,12 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
/**
* @brief Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer
* to feed the input buffer to the IP.
* to feed the input buffer to the Peripheral.
* @note Once the DMA transfer is finished, HAL_HASHEx_SHA256_Finish() API must
* be called to retrieve the computed digest.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -351,9 +465,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
* @note The API waits for DCIS to be set then reads the computed digest.
* @note HAL_HASHEx_SHA256_Finish() can be used as well to retrieve the digest in
* HMAC SHA256 mode.
* @param hhash: HASH handle.
* @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout: Timeout value.
* @param hhash HASH handle.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@ -391,11 +505,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout: Timeout value.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@ -409,11 +523,11 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout: Timeout value.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@ -452,10 +566,10 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@ -469,10 +583,10 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@ -502,7 +616,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
(+) SHA256
(++) HAL_HMACEx_SHA256_Start_DMA()
[..] When resorting to DMA mode to enter the data in the IP for HMAC processing,
[..] When resorting to DMA mode to enter the data in the Peripheral for HMAC processing,
user must resort to HAL_HMACEx_xxx_Start_DMA() then read the resulting digest
with HAL_HASHEx_xxx_Finish().
@ -515,7 +629,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
* DMA transfers to feed the key and the input buffer to the IP.
* DMA transfers to feed the key and the input buffer to the Peripheral.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve
* the computed digest.
@ -527,9 +641,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -539,7 +653,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
* DMA transfers to feed the key and the input buffer to the IP.
* DMA transfers to feed the key and the input buffer to the Peripheral.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
@ -551,9 +665,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (buffer to be hashed).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -597,13 +711,13 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
calling HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
intiates step 2 with the first input buffer.
[..] The following buffers are next fed to the IP with a call to the API
[..] The following buffers are next fed to the Peripheral with a call to the API
HAL_HMACEx_xxx_Step2_DMA(). There may be several consecutive calls
to this API.
[..] Multi-buffer DMA-based HMAC computation is wrapped up by a call to
HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input
buffer to the IP then carries out step 3.
buffer to the Peripheral then carries out step 3.
[..] Digest is retrieved by a call to HAL_HASH_xxx_Finish() for MD-5 or
SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256.
@ -618,18 +732,18 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
* @note Step 1 consists in writing the inner hash function key in the IP,
* @note Step 1 consists in writing the inner hash function key in the Peripheral,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
* the first buffer entered to the IP. DCAL bit is not automatically set after
* the first buffer entered to the Peripheral. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -640,7 +754,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief MD5 HMAC step 2 in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP.
* @note Step 2 consists in writing the message text in the Peripheral.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
@ -648,9 +762,9 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -664,7 +778,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *p
/**
* @brief MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP,
* @note Step 2 consists in writing the message text in the Peripheral,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
@ -674,9 +788,9 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *p
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -688,18 +802,18 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
* @note Step 1 consists in writing the inner hash function key in the IP,
* @note Step 1 consists in writing the inner hash function key in the Peripheral,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
* the first buffer entered to the IP. DCAL bit is not automatically set after
* the first buffer entered to the Peripheral. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -710,7 +824,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief SHA1 HMAC step 2 in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP.
* @note Step 2 consists in writing the message text in the Peripheral.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
@ -718,9 +832,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -734,7 +848,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *
/**
* @brief SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP,
* @note Step 2 consists in writing the message text in the Peripheral,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
@ -744,9 +858,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -757,18 +871,18 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
* @note Step 1 consists in writing the inner hash function key in the IP,
* @note Step 1 consists in writing the inner hash function key in the Peripheral,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
* the first buffer entered to the IP. DCAL bit is not automatically set after
* the first buffer entered to the Peripheral. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -779,7 +893,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8
/**
* @brief SHA224 HMAC step 2 in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP.
* @note Step 2 consists in writing the message text in the Peripheral.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
@ -787,9 +901,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -803,7 +917,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP,
* @note Step 2 consists in writing the message text in the Peripheral,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
@ -813,9 +927,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -826,18 +940,18 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8
/**
* @brief SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
* @note Step 1 consists in writing the inner hash function key in the IP,
* @note Step 1 consists in writing the inner hash function key in the Peripheral,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
* the first buffer entered to the IP. DCAL bit is not automatically set after
* the first buffer entered to the Peripheral. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -848,7 +962,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8
/**
* @brief SHA256 HMAC step 2 in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP.
* @note Step 2 consists in writing the message text in the Peripheral.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
@ -856,9 +970,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@ -872,7 +986,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @brief SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the IP,
* @note Step 2 consists in writing the message text in the Peripheral,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
@ -882,9 +996,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
* @param hhash: HASH handle.
* @param pInBuffer: pointer to the input buffer (message buffer).
* @param Size: length of the input buffer in bytes.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)

10
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hash_ex.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash_ex.h
View File

@ -52,9 +52,11 @@
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
/**
* @}
@ -65,7 +67,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
/**
* @}

10
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hcd.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hcd.c
View File

@ -1225,6 +1225,16 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
hhcd->hc[ch_num].urb_state = URB_DONE;
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else if (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC)
{
hhcd->hc[ch_num].urb_state = URB_DONE;
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
#else

0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hcd.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hcd.h
View File

27
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hrtim.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.c
View File

@ -363,6 +363,7 @@
#ifdef HAL_HRTIM_MODULE_ENABLED
#if defined(HRTIM1)
/** @defgroup HRTIM HRTIM
* @brief HRTIM HAL module driver
@ -1315,6 +1316,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
default:
{
OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
hhrtim->State = HAL_HRTIM_STATE_ERROR;
/* Process Unlocked */
@ -1608,11 +1612,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
/* Check the parameters */
assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
{
return HAL_BUSY;
}
if(hhrtim->State == HAL_HRTIM_STATE_READY)
if (hhrtim->State == HAL_HRTIM_STATE_READY)
{
if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
{
@ -1860,6 +1864,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
}
default:
{
OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
hhrtim->State = HAL_HRTIM_STATE_ERROR;
/* Process Unlocked */
@ -2222,11 +2229,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
/* Check the parameters */
assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
{
return HAL_BUSY;
}
if(hhrtim->State == HAL_HRTIM_STATE_READY)
if (hhrtim->State == HAL_HRTIM_STATE_READY)
{
if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
{
@ -3185,6 +3192,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh
default:
{
OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
hhrtim->State = HAL_HRTIM_STATE_ERROR;
/* Process Unlocked */
@ -3634,8 +3644,8 @@ HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
HRTIM_EventCfgTypeDef* pEventCfg)
{
/* Check parameters */
assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
assert_param(IS_HRTIM_EVENT(Event));
assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
@ -5313,7 +5323,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim,
/* Check the parameters */
assert_param(IS_HRTIM_TIMERID(Timers));
if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
{
return HAL_BUSY;
}
@ -5748,11 +5758,11 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
/* Check the parameters */
assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
{
return HAL_BUSY;
}
if(hhrtim->State == HAL_HRTIM_STATE_READY)
if (hhrtim->State == HAL_HRTIM_STATE_READY)
{
if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U))
{
@ -9256,6 +9266,7 @@ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
* @}
*/
#endif /* HRTIM1 */
#endif /* HAL_HRTIM_MODULE_ENABLED */

41
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hrtim.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.h
View File

@ -28,6 +28,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
#if defined(HRTIM1)
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
@ -653,11 +654,6 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
* @{
* @brief Constants defining timer high-resolution clock prescaler ratio.
*/
#define HRTIM_PRESCALERRATIO_MUL32 (0x00000000U) /*!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_MUL16 (0x00000001U) /*!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_MUL8 (0x00000002U) /*!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_MUL4 (0x00000003U) /*!< fHRCK: fHRTIM x 4U = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_MUL2 (0x00000004U) /*!< fHRCK: fHRTIM x 2U = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
@ -1134,9 +1130,6 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
/**
* @}
*/
/**
* @}
*/
/** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter
* @{
@ -2085,12 +2078,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
((FAULT) == HRTIM_FAULT_5))
#define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
(((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
(((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
@ -2726,18 +2714,13 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \
((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000U) == 0x00000000U)) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)))
#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \
|| (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
|| (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
|| (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
|| (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
|| (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)))
#define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
(((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \
@ -3124,11 +3107,6 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
* @arg 0x0 to 0x4 for timers A to E
* @param __PRESCALER__ specifies the clock prescaler new value.
* This parameter can be one of the following values:
* @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
@ -3657,6 +3635,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * h
* @}
*/
#endif /* HRTIM1 */
#ifdef __cplusplus
}

0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hsem.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hsem.c
View File

0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hsem.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hsem.h
View File

250
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_i2c.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c.c
View File

@ -351,13 +351,13 @@
/* Private define to centralize the enable/disable of Interrupts */
#define I2C_XFER_TX_IT (0x00000001U)
#define I2C_XFER_RX_IT (0x00000002U)
#define I2C_XFER_LISTEN_IT (0x00000004U)
#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */
#define I2C_XFER_ERROR_IT (0x00000011U)
#define I2C_XFER_CPLT_IT (0x00000012U)
#define I2C_XFER_RELOAD_IT (0x00000012U)
#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */
#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */
#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */
/* Private define Sequential Transfer Options default/reset value */
#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
@ -410,6 +410,9 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32
static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
/* Private function to treat different error callback */
static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
/* Private function to flush TXDR register */
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
@ -4251,9 +4254,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA
/* Process Locked */
__HAL_LOCK(hi2c);
/* Disable Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
/* Disable Interrupts and Store Previous state */
if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
}
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
}
else
{
/* Do nothing */
}
/* Set State at HAL_I2C_STATE_ABORT */
hi2c->State = HAL_I2C_STATE_ABORT;
@ -4737,6 +4752,13 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
/* Process locked */
__HAL_LOCK(hi2c);
/* Check if STOPF is set */
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, tmpITFlags);
}
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
@ -4788,9 +4810,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
{
if (hi2c->XferCount > 0U)
{
/* Remove RXNE flag on temporary variable as read done */
tmpITFlags &= ~I2C_FLAG_RXNE;
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
@ -4844,13 +4863,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
/* Nothing to do */
}
/* Check if STOPF is set */
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, tmpITFlags);
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -5004,10 +5016,18 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
{
uint32_t tmpoptions = hi2c->XferOptions;
uint32_t treatdmanack = 0U;
HAL_I2C_StateTypeDef tmpstate;
/* Process locked */
__HAL_LOCK(hi2c);
/* Check if STOPF is set */
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
}
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
@ -5075,8 +5095,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
/* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
tmpstate = hi2c->State;
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
{
if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
{
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
}
else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
{
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
}
else
{
/* Do nothing */
}
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
}
@ -5092,11 +5128,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
{
I2C_ITAddrCplt(hi2c, ITFlags);
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
}
else
{
/* Nothing to do */
@ -5370,9 +5401,27 @@ static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
*/
static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
{
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
/* If a DMA is ongoing, Update handle size context */
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
}
else
{
/* Do nothing */
}
if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
{
/* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
@ -5427,19 +5476,36 @@ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
uint32_t tmperror;
uint32_t tmpITFlags = ITFlags;
uint32_t tmp;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Disable Interrupts and Store Previous state */
if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
}
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
}
else
{
/* Do nothing */
}
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
/* Reset handle parameters */
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = NULL;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET)
if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@ -5448,12 +5514,18 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
/* Fetch Last receive data if any */
if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
{
/* Read data from RXDR */
tmp = (uint8_t)hi2c->Instance->RXDR;
UNUSED(tmp);
}
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
/* Disable Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);
/* Store current volatile hi2c->ErrorCode, misra rule */
tmperror = hi2c->ErrorCode;
@ -5467,6 +5539,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
@ -5501,6 +5574,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
@ -5547,12 +5621,26 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
uint32_t tmpITFlags = ITFlags;
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Disable all interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
/* Disable Interrupts and Store Previous state */
if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
{
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
}
else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
{
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
}
else
{
/* Do nothing */
}
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@ -5566,6 +5654,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
/* If a DMA is ongoing, Update handle size context */
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
if (hi2c->hdmatx != NULL)
{
hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
@ -5573,6 +5664,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
if (hi2c->hdmarx != NULL)
{
hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
@ -5609,7 +5703,6 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferISR = NULL;
@ -5632,6 +5725,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -5647,6 +5741,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -5661,6 +5756,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
else
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -5734,6 +5830,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
uint32_t tmppreviousstate;
/* Reset handle parameters */
hi2c->Mode = HAL_I2C_MODE_NONE;
@ -5753,7 +5850,6 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
/* keep HAL_I2C_STATE_LISTEN if set */
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = I2C_Slave_ISR_IT;
}
else
@ -5768,16 +5864,19 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
/* Set HAL_I2C_STATE_READY */
hi2c->State = HAL_I2C_STATE_READY;
}
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = NULL;
}
/* Abort DMA TX transfer if any */
if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
tmppreviousstate = hi2c->PreviousState;
if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
{
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
{
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
}
if (hi2c->hdmatx != NULL)
if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
@ -5793,13 +5892,20 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
}
}
else
{
I2C_TreatErrorCallback(hi2c);
}
}
/* Abort DMA RX transfer if any */
else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
{
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
{
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
}
if (hi2c->hdmarx != NULL)
if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
@ -5815,10 +5921,28 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
}
}
else
{
I2C_TreatErrorCallback(hi2c);
}
}
else if (hi2c->State == HAL_I2C_STATE_ABORT)
else
{
I2C_TreatErrorCallback(hi2c);
}
}
/**
* @brief I2C Error callback treatment.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
{
if (hi2c->State == HAL_I2C_STATE_ABORT)
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -5832,6 +5956,8 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
}
else
{
hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -6063,30 +6189,16 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Reset AbortCpltCallback */
hi2c->hdmatx->XferAbortCallback = NULL;
hi2c->hdmarx->XferAbortCallback = NULL;
/* Check if come from abort from user */
if (hi2c->State == HAL_I2C_STATE_ABORT)
if (hi2c->hdmatx != NULL)
{
hi2c->State = HAL_I2C_STATE_READY;
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->AbortCpltCallback(hi2c);
#else
HAL_I2C_AbortCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
hi2c->hdmatx->XferAbortCallback = NULL;
}
else
if (hi2c->hdmarx != NULL)
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->ErrorCallback(hi2c);
#else
HAL_I2C_ErrorCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
hi2c->hdmarx->XferAbortCallback = NULL;
}
I2C_TreatErrorCallback(hi2c);
}
/**
@ -6363,19 +6475,19 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
}
if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
if (InterruptRequest == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
@ -6401,7 +6513,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
@ -6455,19 +6567,19 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
}
if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
if (InterruptRequest == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;

0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_i2c.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c.h
View File

0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_i2c_ex.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c_ex.c
View File

0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_i2c_ex.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c_ex.h
View File

157
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_i2s.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s.c
View File

@ -189,6 +189,8 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define I2S_TIMEOUT 0xFFFFUL
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@ -347,8 +349,21 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
}
/* Get the source clock value: based on System Clock value */
#if defined (SPI_SPI6I2S_SUPPORT)
if (hi2s->Instance == SPI6)
{
/* SPI6 source clock */
i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI6);
}
else
{
/* SPI1,SPI2 and SPI3 share the same source clock */
i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123);
}
#else
/* SPI1,SPI2 and SPI3 share the same source clock */
i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123);
#endif
/* Compute the Real divider depending on the MCLK output state, with a floating point */
if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
@ -761,6 +776,10 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca
*/
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
#if defined (__GNUC__)
__IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR));
#endif /* __GNUC__ */
if ((pData == NULL) || (Size == 0UL))
{
return HAL_ERROR;
@ -820,7 +839,12 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
else
{
/* Transmit data in 16 Bit mode */
#if defined (__GNUC__)
*ptxdr_16bits = *((uint16_t *)hi2s->pTxBuffPtr);
#else
*((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr);
#endif /* __GNUC__ */
hi2s->pTxBuffPtr++;
hi2s->TxXferCount--;
}
@ -870,6 +894,10 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
*/
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
#if defined (__GNUC__)
__IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR));
#endif /* __GNUC__ */
if ((pData == NULL) || (Size == 0UL))
{
return HAL_ERROR;
@ -929,7 +957,11 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
else
{
/* Receive data in 16 Bit mode */
#if defined (__GNUC__)
*((uint16_t *)hi2s->pRxBuffPtr) = *prxdr_16bits;
#else
*((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
#endif /* __GNUC__ */
hi2s->pRxBuffPtr++;
hi2s->RxXferCount--;
}
@ -1278,26 +1310,66 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
{
/* Process Locked */
__HAL_LOCK(hi2s);
uint32_t tickstart;
if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
/* Get tick */
tickstart = HAL_GetTick();
/* Check if the I2S peripheral is in master mode */
if (IS_I2S_MASTER(hi2s->Init.Mode))
{
/* Disable the I2S DMA Tx request */
CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
}
else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
/* Disable the I2S DMA Rx request */
CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
}
else
{
/* nothing to do */
}
/* Check if there is a transfer on-going */
if (HAL_IS_BIT_SET(hi2s->Instance->CR1, SPI_CR1_CSTART) == 0UL)
{
/* Set error code to no on going transfer */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_NO_OGT);
hi2s->State = HAL_I2S_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
__HAL_UNLOCK(hi2s);
return HAL_ERROR;
}
SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSUSP);
return HAL_OK;
while (HAL_IS_BIT_SET(hi2s->Instance->CR1, SPI_CR1_CSTART) != 0UL)
{
if ((((HAL_GetTick() - tickstart) >= I2S_TIMEOUT) && (I2S_TIMEOUT != HAL_MAX_DELAY)) || (I2S_TIMEOUT == 0U))
{
/* Set the I2S State ready */
hi2s->State = HAL_I2S_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
hi2s->State = HAL_I2S_STATE_READY;
return HAL_TIMEOUT;
}
}
/* Disable I2S peripheral */
__HAL_I2S_DISABLE(hi2s);
hi2s->State = HAL_I2S_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
else
{
/* Set error code to not supported */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_NOT_SUPPORTED);
hi2s->State = HAL_I2S_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_ERROR;
}
}
/**
@ -1311,27 +1383,23 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
/* Process Locked */
__HAL_LOCK(hi2s);
if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
if (hi2s->State != HAL_I2S_STATE_READY)
{
/* Enable the I2S DMA Tx request */
SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
}
else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
/* Enable the I2S DMA Rx request */
SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
}
else
{
/* nothing to do */
}
hi2s->State = HAL_I2S_STATE_READY;
/* If the I2S peripheral is still not enabled, enable it */
if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE))
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
__HAL_UNLOCK(hi2s);
return HAL_ERROR;
}
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
/* Start the transfer */
SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
@ -1413,26 +1481,28 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
}
/* I2S interrupt error ----------------------------------------------------*/
if (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_ERR) != RESET)
if ((trigger & (I2S_FLAG_OVR| I2S_FLAG_UDR | I2S_FLAG_FRE)) != 0UL)
{
/* I2S Overrun error interrupt occurred ---------------------------------*/
if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET)
{
/* Disable RXNE and ERR interrupt */
/* Disable RXP and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
/* Set the error code and execute error callback*/
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
}
/* I2S Underrun error interrupt occurred --------------------------------*/
if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET)
{
/* Disable TXE and ERR interrupt */
/* Disable TXP and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
/* Set the error code and execute error callback*/
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
__HAL_I2S_CLEAR_UDRFLAG(hi2s);
}
/* I2S Frame error interrupt occurred -----------------------------------*/
@ -1443,6 +1513,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
/* Set the error code and execute error callback*/
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_FRE);
__HAL_I2S_CLEAR_FREFLAG(hi2s);
}
/* Set the I2S State ready */
@ -1707,7 +1778,13 @@ static void I2S_DMAError(DMA_HandleTypeDef *hdma)
static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s)
{
/* Transmit data */
#if defined (__GNUC__)
__IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR));
*ptxdr_16bits = *((uint16_t *)hi2s->pTxBuffPtr);
#else
*((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr);
#endif /* __GNUC__ */
hi2s->pTxBuffPtr++;
hi2s->TxXferCount--;
@ -1763,7 +1840,13 @@ static void I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s)
static void I2S_Receive_16Bit_IT(I2S_HandleTypeDef *hi2s)
{
/* Receive data */
#if defined (__GNUC__)
__IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR));
*((uint16_t *)hi2s->pRxBuffPtr) = *prxdr_16bits;
#else
*((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
#endif /* __GNUC__ */
hi2s->pRxBuffPtr++;
hi2s->RxXferCount--;

24
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_i2s.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s.h
View File

@ -178,16 +178,18 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
*/
/** @defgroup I2S_Error I2S Error
* @{
*/
#define HAL_I2S_ERROR_NONE (0x00000000UL) /*!< No error */
#define HAL_I2S_ERROR_TIMEOUT (0x00000001UL) /*!< Timeout error */
#define HAL_I2S_ERROR_OVR (0x00000002UL) /*!< OVR error */
#define HAL_I2S_ERROR_UDR (0x00000004UL) /*!< UDR error */
#define HAL_I2S_ERROR_DMA (0x00000008UL) /*!< DMA transfer error */
#define HAL_I2S_ERROR_PRESCALER (0x00000010UL) /*!< Prescaler Calculation error */
#define HAL_I2S_ERROR_FRE (0x00000020UL) /*!< FRE error */
*/
#define HAL_I2S_ERROR_NONE (0x00000000UL) /*!< No error */
#define HAL_I2S_ERROR_TIMEOUT (0x00000001UL) /*!< Timeout error */
#define HAL_I2S_ERROR_OVR (0x00000002UL) /*!< OVR error */
#define HAL_I2S_ERROR_UDR (0x00000004UL) /*!< UDR error */
#define HAL_I2S_ERROR_DMA (0x00000008UL) /*!< DMA transfer error */
#define HAL_I2S_ERROR_PRESCALER (0x00000010UL) /*!< Prescaler Calculation error */
#define HAL_I2S_ERROR_FRE (0x00000020UL) /*!< FRE error */
#define HAL_I2S_ERROR_NO_OGT (0x00000040UL) /*!< No On Going Transfer error */
#define HAL_I2S_ERROR_NOT_SUPPORTED (0x00000080UL) /*!< Requested operation not supported */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000040UL) /*!< Invalid Callback error */
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000100UL) /*!< Invalid Callback error */
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
@ -375,7 +377,7 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
* @arg I2S_IT_ERR : Error interrupt enable
* @retval None
*/
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->IER,(__INTERRUPT__)))
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/** @brief Disable the specified I2S interrupts.
* @param __HANDLE__ specifies the I2S Handle.
@ -390,7 +392,7 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
* @arg I2S_IT_ERR : Error interrupt enable
* @retval None
*/
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->IER,(__INTERRUPT__)))
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
/** @brief Check if the specified I2S interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the I2S Handle.

28
targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s_ex.c Normal file
View File

@ -0,0 +1,28 @@
/**
******************************************************************************
* @file stm32h7xx_hal_i2s_ex.c
* @author MCD Application Team
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2S extension peripheral:
* + Extension features Functions
*
@verbatim
==============================================================================
##### I2S Extension features #####
==============================================================================
The I2S Full duplex feature is not supported by this HAL Driver
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

20
targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s_ex.h Normal file
View File

@ -0,0 +1,20 @@
/**
******************************************************************************
* @file stm32h7xx_hal_i2s_ex.h
* @author MCD Application Team
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* The I2S Full duplex feature is not supported by this HAL Driver */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_irda.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda.c
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0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_irda.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda.h
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0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_irda_ex.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda_ex.h
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0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_iwdg.c → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_iwdg.c
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0
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_iwdg.h → targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_iwdg.h
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