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[MAX32620HSP] Cleanup with formatting script.

pull/2832/head
Kevin Gillespie 2016-09-09 10:53:44 -05:00 committed by Jeremy Brodt
parent 8e70018ec1
commit 0611885832
24 changed files with 182 additions and 216 deletions
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60
targets/TARGET_Maxim/TARGET_MAX32620/PeripheralPins.c
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@ -68,14 +68,14 @@ const PinMap PinMap_I2C_SCL[] = {
/* /*
*/ */
const PinMap PinMap_UART_TX[] = { const PinMap PinMap_UART_TX[] = {
{ P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, { P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, { P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, { P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, { P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, { P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) }, { P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ NC, NC, 0 } { NC, NC, 0 }
}; };
@ -157,30 +157,30 @@ const PinMap PinMap_SPI_QUAD[] = {
/************PWM***************/ /************PWM***************/
const PinMap PinMap_PWM[] = { const PinMap PinMap_PWM[] = {
{ P0_0, PWM_0, 1 }, { P2_0, PWM_0, 1 }, { P4_0, PWM_0, 1 }, {P6_0, PWM_0, 1}, { P0_0, PWM_0, 1 }, { P2_0, PWM_0, 1 }, { P4_0, PWM_0, 1 }, {P6_0, PWM_0, 1},
{ P0_1, PWM_1, 1 }, { P2_1, PWM_1, 1 }, { P4_1, PWM_1, 1 }, { P0_1, PWM_1, 1 }, { P2_1, PWM_1, 1 }, { P4_1, PWM_1, 1 },
{ P0_2, PWM_2, 1 }, { P2_2, PWM_2, 1 }, { P4_2, PWM_2, 1 }, { P0_2, PWM_2, 1 }, { P2_2, PWM_2, 1 }, { P4_2, PWM_2, 1 },
{ P0_3, PWM_3, 1 }, { P2_3, PWM_3, 1 }, { P4_3, PWM_3, 1 }, { P0_3, PWM_3, 1 }, { P2_3, PWM_3, 1 }, { P4_3, PWM_3, 1 },
{ P0_4, PWM_4, 1 }, { P2_4, PWM_4, 1 }, { P4_4, PWM_4, 1 }, { P0_4, PWM_4, 1 }, { P2_4, PWM_4, 1 }, { P4_4, PWM_4, 1 },
{ P0_5, PWM_5, 1 }, { P2_5, PWM_5, 1 }, { P4_5, PWM_5, 1 }, { P0_5, PWM_5, 1 }, { P2_5, PWM_5, 1 }, { P4_5, PWM_5, 1 },
{ P0_6, PWM_6, 1 }, { P2_6, PWM_6, 1 }, { P4_6, PWM_6, 1 }, { P0_6, PWM_6, 1 }, { P2_6, PWM_6, 1 }, { P4_6, PWM_6, 1 },
{ P0_7, PWM_7, 1 }, { P2_7, PWM_7, 1 }, { P4_7, PWM_7, 1 }, { P0_7, PWM_7, 1 }, { P2_7, PWM_7, 1 }, { P4_7, PWM_7, 1 },
{ P1_0, PWM_8, 1 }, { P3_0, PWM_8, 1 }, { P5_0, PWM_8, 1 }, { P1_0, PWM_8, 1 }, { P3_0, PWM_8, 1 }, { P5_0, PWM_8, 1 },
{ P1_1, PWM_9, 1 }, { P3_1, PWM_9, 1 }, { P5_1, PWM_9, 1 }, { P1_1, PWM_9, 1 }, { P3_1, PWM_9, 1 }, { P5_1, PWM_9, 1 },
{ P1_2, PWM_10, 1 }, { P3_2, PWM_10, 1 }, { P5_2, PWM_10, 1 }, { P1_2, PWM_10, 1 }, { P3_2, PWM_10, 1 }, { P5_2, PWM_10, 1 },
{ P1_3, PWM_11, 1 }, { P3_3, PWM_11, 1 }, { P5_3, PWM_11, 1 }, { P1_3, PWM_11, 1 }, { P3_3, PWM_11, 1 }, { P5_3, PWM_11, 1 },
{ P1_4, PWM_12, 1 }, { P3_4, PWM_12, 1 }, { P5_4, PWM_12, 1 }, { P1_4, PWM_12, 1 }, { P3_4, PWM_12, 1 }, { P5_4, PWM_12, 1 },
{ P1_5, PWM_13, 1 }, { P3_5, PWM_13, 1 }, { P5_5, PWM_13, 1 }, { P1_5, PWM_13, 1 }, { P3_5, PWM_13, 1 }, { P5_5, PWM_13, 1 },
{ P1_6, PWM_14, 1 }, { P3_6, PWM_14, 1 }, { P5_6, PWM_14, 1 }, { P1_6, PWM_14, 1 }, { P3_6, PWM_14, 1 }, { P5_6, PWM_14, 1 },
{ P1_7, PWM_15, 1 }, { P3_7, PWM_15, 1 }, { P5_7, PWM_15, 1 }, { P1_7, PWM_15, 1 }, { P3_7, PWM_15, 1 }, { P5_7, PWM_15, 1 },
{ NC, NC, 0 } { NC, NC, 0 }
}; };
/************ADC***************/ /************ADC***************/
const PinMap PinMap_ADC[] = { const PinMap PinMap_ADC[] = {
{ AIN_0, ADC, 0 }, { AIN_0, ADC, 0 },
{ AIN_1, ADC, 0 }, { AIN_1, ADC, 0 },
{ AIN_2, ADC, 0 }, { AIN_2, ADC, 0 },
{ AIN_3, ADC, 0 }, { AIN_3, ADC, 0 },
{ NC, NC, 0 } { NC, NC, 0 }
}; };

2
targets/TARGET_Maxim/TARGET_MAX32620/TARGET_MAX32620HSP/PinNames.h
View File

@ -116,7 +116,7 @@ typedef enum {
AIN_3 = (0xA << PORT_SHIFT) | 3, AIN_3 = (0xA << PORT_SHIFT) | 3,
// LEDs // LEDs
LED_RED = P2_0, LED_RED = P2_0,
LED1 = LED_RED, LED1 = LED_RED,
LED2 = NOT_CONNECTED, LED2 = NOT_CONNECTED,
LED3 = NOT_CONNECTED, LED3 = NOT_CONNECTED,

2
targets/TARGET_Maxim/TARGET_MAX32620/analogin_api.c
View File

@ -86,7 +86,7 @@ void analogin_init(analogin_t *obj, PinName pin)
// Enable ADC power bypass the buffer // Enable ADC power bypass the buffer
obj->adc->ctrl |= (MXC_F_ADC_CTRL_ADC_PU | MXC_F_ADC_CTRL_ADC_REFBUF_PU | obj->adc->ctrl |= (MXC_F_ADC_CTRL_ADC_PU | MXC_F_ADC_CTRL_ADC_REFBUF_PU |
MXC_F_ADC_CTRL_ADC_CHGPUMP_PU | MXC_F_ADC_CTRL_BUF_BYPASS); MXC_F_ADC_CTRL_ADC_CHGPUMP_PU | MXC_F_ADC_CTRL_BUF_BYPASS);
// Wait for ADC ready // Wait for ADC ready
while (!(obj->adc->intr & MXC_F_ADC_INTR_ADC_REF_READY_IF)); while (!(obj->adc->intr & MXC_F_ADC_INTR_ADC_REF_READY_IF));

2
targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/MAX32620.sct
View File

@ -14,7 +14,7 @@ LR_IROM1 0x00000000 0x200000 { ; load region size_region
} }
; [RAM] Vector table dynamic copy: 65 vectors * 4 bytes = 260 (0x104) + 4 ; [RAM] Vector table dynamic copy: 65 vectors * 4 bytes = 260 (0x104) + 4
; for 8 byte alignment ; for 8 byte alignment
RW_IRAM1 (0x20000000+0x108) (0x40000-0x108) { ; RW data RW_IRAM1 (0x20000000+0x108) (0x40000-0x108) { ; RW data
.ANY (+RW +ZI) .ANY (+RW +ZI)
} }

3
targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/sys.cpp
View File

@ -40,7 +40,8 @@ extern "C" {
extern char Image$$RW_IRAM1$$ZI$$Limit[]; extern char Image$$RW_IRAM1$$ZI$$Limit[];
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
{
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp(); uint32_t sp_limit = __current_sp();

108
targets/TARGET_Maxim/TARGET_MAX32620/device/ioman_regs.h
View File

@ -72,72 +72,63 @@ typedef enum {
Bitfield structs for registers in this module Bitfield structs for registers in this module
*/ */
typedef struct typedef struct {
{
uint32_t wud_req_p0 : 8; uint32_t wud_req_p0 : 8;
uint32_t wud_req_p1 : 8; uint32_t wud_req_p1 : 8;
uint32_t wud_req_p2 : 8; uint32_t wud_req_p2 : 8;
uint32_t wud_req_p3 : 8; uint32_t wud_req_p3 : 8;
} mxc_ioman_wud_req0_t; } mxc_ioman_wud_req0_t;
typedef struct typedef struct {
{
uint32_t wud_req_p4 : 8; uint32_t wud_req_p4 : 8;
uint32_t wud_req_p5 : 8; uint32_t wud_req_p5 : 8;
uint32_t wud_req_p6 : 1; uint32_t wud_req_p6 : 1;
uint32_t : 15; uint32_t : 15;
} mxc_ioman_wud_req1_t; } mxc_ioman_wud_req1_t;
typedef struct typedef struct {
{
uint32_t wud_ack_p0 : 8; uint32_t wud_ack_p0 : 8;
uint32_t wud_ack_p1 : 8; uint32_t wud_ack_p1 : 8;
uint32_t wud_ack_p2 : 8; uint32_t wud_ack_p2 : 8;
uint32_t wud_ack_p3 : 8; uint32_t wud_ack_p3 : 8;
} mxc_ioman_wud_ack0_t; } mxc_ioman_wud_ack0_t;
typedef struct typedef struct {
{
uint32_t wud_ack_p4 : 8; uint32_t wud_ack_p4 : 8;
uint32_t wud_ack_p5 : 8; uint32_t wud_ack_p5 : 8;
uint32_t wud_ack_p6 : 1; uint32_t wud_ack_p6 : 1;
uint32_t : 15; uint32_t : 15;
} mxc_ioman_wud_ack1_t; } mxc_ioman_wud_ack1_t;
typedef struct typedef struct {
{
uint32_t ali_req_p0 : 8; uint32_t ali_req_p0 : 8;
uint32_t ali_req_p1 : 8; uint32_t ali_req_p1 : 8;
uint32_t ali_req_p2 : 8; uint32_t ali_req_p2 : 8;
uint32_t ali_req_p3 : 8; uint32_t ali_req_p3 : 8;
} mxc_ioman_ali_req0_t; } mxc_ioman_ali_req0_t;
typedef struct typedef struct {
{
uint32_t ali_req_p4 : 8; uint32_t ali_req_p4 : 8;
uint32_t ali_req_p5 : 8; uint32_t ali_req_p5 : 8;
uint32_t ali_req_p6 : 1; uint32_t ali_req_p6 : 1;
uint32_t : 15; uint32_t : 15;
} mxc_ioman_ali_req1_t; } mxc_ioman_ali_req1_t;
typedef struct typedef struct {
{
uint32_t ali_ack_p0 : 8; uint32_t ali_ack_p0 : 8;
uint32_t ali_ack_p1 : 8; uint32_t ali_ack_p1 : 8;
uint32_t ali_ack_p2 : 8; uint32_t ali_ack_p2 : 8;
uint32_t ali_ack_p3 : 8; uint32_t ali_ack_p3 : 8;
} mxc_ioman_ali_ack0_t; } mxc_ioman_ali_ack0_t;
typedef struct typedef struct {
{
uint32_t ali_ack_p4 : 8; uint32_t ali_ack_p4 : 8;
uint32_t ali_ack_p5 : 8; uint32_t ali_ack_p5 : 8;
uint32_t ali_ack_p6 : 1; uint32_t ali_ack_p6 : 1;
uint32_t : 15; uint32_t : 15;
} mxc_ioman_ali_ack1_t; } mxc_ioman_ali_ack1_t;
typedef struct typedef struct {
{
uint32_t : 4; uint32_t : 4;
uint32_t core_io_req : 1; uint32_t core_io_req : 1;
uint32_t : 3; uint32_t : 3;
@ -151,8 +142,7 @@ typedef struct
uint32_t : 15; uint32_t : 15;
} mxc_ioman_spix_req_t; } mxc_ioman_spix_req_t;
typedef struct typedef struct {
{
uint32_t : 4; uint32_t : 4;
uint32_t core_io_ack : 1; uint32_t core_io_ack : 1;
uint32_t : 3; uint32_t : 3;
@ -166,8 +156,7 @@ typedef struct
uint32_t : 15; uint32_t : 15;
} mxc_ioman_spix_ack_t; } mxc_ioman_spix_ack_t;
typedef struct typedef struct {
{
uint32_t io_map : 1; uint32_t io_map : 1;
uint32_t cts_map : 1; uint32_t cts_map : 1;
uint32_t rts_map : 1; uint32_t rts_map : 1;
@ -178,8 +167,7 @@ typedef struct
uint32_t : 25; uint32_t : 25;
} mxc_ioman_uart0_req_t; } mxc_ioman_uart0_req_t;
typedef struct typedef struct {
{
uint32_t io_map : 1; uint32_t io_map : 1;
uint32_t cts_map : 1; uint32_t cts_map : 1;
uint32_t rts_map : 1; uint32_t rts_map : 1;
@ -190,8 +178,7 @@ typedef struct
uint32_t : 25; uint32_t : 25;
} mxc_ioman_uart0_ack_t; } mxc_ioman_uart0_ack_t;
typedef struct typedef struct {
{
uint32_t io_map : 1; uint32_t io_map : 1;
uint32_t cts_map : 1; uint32_t cts_map : 1;
uint32_t rts_map : 1; uint32_t rts_map : 1;
@ -202,8 +189,7 @@ typedef struct
uint32_t : 25; uint32_t : 25;
} mxc_ioman_uart1_req_t; } mxc_ioman_uart1_req_t;
typedef struct typedef struct {
{
uint32_t io_map : 1; uint32_t io_map : 1;
uint32_t cts_map : 1; uint32_t cts_map : 1;
uint32_t rts_map : 1; uint32_t rts_map : 1;
@ -214,8 +200,7 @@ typedef struct
uint32_t : 25; uint32_t : 25;
} mxc_ioman_uart1_ack_t; } mxc_ioman_uart1_ack_t;
typedef struct typedef struct {
{
uint32_t io_map : 1; uint32_t io_map : 1;
uint32_t cts_map : 1; uint32_t cts_map : 1;
uint32_t rts_map : 1; uint32_t rts_map : 1;
@ -226,8 +211,7 @@ typedef struct
uint32_t : 25; uint32_t : 25;
} mxc_ioman_uart2_req_t; } mxc_ioman_uart2_req_t;
typedef struct typedef struct {
{
uint32_t io_map : 1; uint32_t io_map : 1;
uint32_t cts_map : 1; uint32_t cts_map : 1;
uint32_t rts_map : 1; uint32_t rts_map : 1;
@ -238,8 +222,7 @@ typedef struct
uint32_t : 25; uint32_t : 25;
} mxc_ioman_uart2_ack_t; } mxc_ioman_uart2_ack_t;
typedef struct typedef struct {
{
uint32_t io_map : 1; uint32_t io_map : 1;
uint32_t cts_map : 1; uint32_t cts_map : 1;
uint32_t rts_map : 1; uint32_t rts_map : 1;
@ -250,8 +233,7 @@ typedef struct
uint32_t : 25; uint32_t : 25;
} mxc_ioman_uart3_req_t; } mxc_ioman_uart3_req_t;
typedef struct typedef struct {
{
uint32_t io_map : 1; uint32_t io_map : 1;
uint32_t cts_map : 1; uint32_t cts_map : 1;
uint32_t rts_map : 1; uint32_t rts_map : 1;
@ -262,66 +244,57 @@ typedef struct
uint32_t : 25; uint32_t : 25;
} mxc_ioman_uart3_ack_t; } mxc_ioman_uart3_ack_t;
typedef struct typedef struct {
{
uint32_t : 4; uint32_t : 4;
uint32_t mapping_req : 1; uint32_t mapping_req : 1;
uint32_t : 27; uint32_t : 27;
} mxc_ioman_i2cm0_req_t; } mxc_ioman_i2cm0_req_t;
typedef struct typedef struct {
{
uint32_t : 4; uint32_t : 4;
uint32_t mapping_ack : 1; uint32_t mapping_ack : 1;
uint32_t : 27; uint32_t : 27;
} mxc_ioman_i2cm0_ack_t; } mxc_ioman_i2cm0_ack_t;
typedef struct typedef struct {
{
uint32_t : 4; uint32_t : 4;
uint32_t mapping_req : 1; uint32_t mapping_req : 1;
uint32_t : 27; uint32_t : 27;
} mxc_ioman_i2cm1_req_t; } mxc_ioman_i2cm1_req_t;
typedef struct typedef struct {
{
uint32_t : 4; uint32_t : 4;
uint32_t mapping_ack : 1; uint32_t mapping_ack : 1;
uint32_t : 27; uint32_t : 27;
} mxc_ioman_i2cm1_ack_t; } mxc_ioman_i2cm1_ack_t;
typedef struct typedef struct {
{
uint32_t : 4; uint32_t : 4;
uint32_t mapping_req : 1; uint32_t mapping_req : 1;
uint32_t : 27; uint32_t : 27;
} mxc_ioman_i2cm2_req_t; } mxc_ioman_i2cm2_req_t;
typedef struct typedef struct {
{
uint32_t : 4; uint32_t : 4;
uint32_t mapping_ack : 1; uint32_t mapping_ack : 1;
uint32_t : 27; uint32_t : 27;
} mxc_ioman_i2cm2_ack_t; } mxc_ioman_i2cm2_ack_t;
typedef struct typedef struct {
{
uint32_t io_sel : 2; uint32_t io_sel : 2;
uint32_t : 2; uint32_t : 2;
uint32_t mapping_req : 1; uint32_t mapping_req : 1;
uint32_t : 27; uint32_t : 27;
} mxc_ioman_i2cs_req_t; } mxc_ioman_i2cs_req_t;
typedef struct typedef struct {
{
uint32_t io_sel : 2; uint32_t io_sel : 2;
uint32_t : 2; uint32_t : 2;
uint32_t mapping_ack : 1; uint32_t mapping_ack : 1;
uint32_t : 27; uint32_t : 27;
} mxc_ioman_i2cs_ack_t; } mxc_ioman_i2cs_ack_t;
typedef struct typedef struct {
{
uint32_t : 4; uint32_t : 4;
uint32_t core_io_req : 1; uint32_t core_io_req : 1;
uint32_t : 3; uint32_t : 3;
@ -337,8 +310,7 @@ typedef struct
uint32_t : 7; uint32_t : 7;
} mxc_ioman_spim0_req_t; } mxc_ioman_spim0_req_t;
typedef struct typedef struct {
{
uint32_t : 4; uint32_t : 4;
uint32_t core_io_ack : 1; uint32_t core_io_ack : 1;
uint32_t : 3; uint32_t : 3;
@ -354,8 +326,7 @@ typedef struct
uint32_t : 7; uint32_t : 7;
} mxc_ioman_spim0_ack_t; } mxc_ioman_spim0_ack_t;
typedef struct typedef struct {
{
uint32_t : 4; uint32_t : 4;
uint32_t core_io_req : 1; uint32_t core_io_req : 1;
uint32_t : 3; uint32_t : 3;
@ -369,8 +340,7 @@ typedef struct
uint32_t : 7; uint32_t : 7;
} mxc_ioman_spim1_req_t; } mxc_ioman_spim1_req_t;
typedef struct typedef struct {
{
uint32_t : 4; uint32_t : 4;
uint32_t core_io_ack : 1; uint32_t core_io_ack : 1;
uint32_t : 3; uint32_t : 3;
@ -384,8 +354,7 @@ typedef struct
uint32_t : 7; uint32_t : 7;
} mxc_ioman_spim1_ack_t; } mxc_ioman_spim1_ack_t;
typedef struct typedef struct {
{
uint32_t mapping_req : 1; uint32_t mapping_req : 1;
uint32_t : 3; uint32_t : 3;
uint32_t core_io_req : 1; uint32_t core_io_req : 1;
@ -403,8 +372,7 @@ typedef struct
uint32_t : 7; uint32_t : 7;
} mxc_ioman_spim2_req_t; } mxc_ioman_spim2_req_t;
typedef struct typedef struct {
{
uint32_t mapping_ack : 1; uint32_t mapping_ack : 1;
uint32_t : 3; uint32_t : 3;
uint32_t core_io_ack : 1; uint32_t core_io_ack : 1;
@ -422,8 +390,7 @@ typedef struct
uint32_t : 7; uint32_t : 7;
} mxc_ioman_spim2_ack_t; } mxc_ioman_spim2_ack_t;
typedef struct typedef struct {
{
uint32_t : 4; uint32_t : 4;
uint32_t core_io_req : 1; uint32_t core_io_req : 1;
uint32_t : 3; uint32_t : 3;
@ -433,8 +400,7 @@ typedef struct
uint32_t : 19; uint32_t : 19;
} mxc_ioman_spib_req_t; } mxc_ioman_spib_req_t;
typedef struct typedef struct {
{
uint32_t : 4; uint32_t : 4;
uint32_t core_io_ack : 1; uint32_t core_io_ack : 1;
uint32_t : 3; uint32_t : 3;
@ -444,16 +410,14 @@ typedef struct
uint32_t : 19; uint32_t : 19;
} mxc_ioman_spib_ack_t; } mxc_ioman_spib_ack_t;
typedef struct typedef struct {
{
uint32_t : 4; uint32_t : 4;
uint32_t mapping_req : 1; uint32_t mapping_req : 1;
uint32_t epu_io_req : 1; uint32_t epu_io_req : 1;
uint32_t : 26; uint32_t : 26;
} mxc_ioman_owm_req_t; } mxc_ioman_owm_req_t;
typedef struct typedef struct {
{
uint32_t : 4; uint32_t : 4;
uint32_t mapping_ack : 1; uint32_t mapping_ack : 1;
uint32_t epu_io_ack : 1; uint32_t epu_io_ack : 1;

4
targets/TARGET_Maxim/TARGET_MAX32620/device/system_max32620.c
View File

@ -187,11 +187,11 @@ void SystemInit(void)
// Clear all unused wakeup sources // Clear all unused wakeup sources
// Beware! Do not change any flag not mentioned here, as they will gate important power sequencer signals // Beware! Do not change any flag not mentioned here, as they will gate important power sequencer signals
MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP | MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP |
MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP); MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP);
// RTC sources are inverted, so a 1 will disable them // RTC sources are inverted, so a 1 will disable them
MXC_PWRSEQ->msk_flags |= (MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 | MXC_PWRSEQ->msk_flags |= (MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 |
MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP); MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP);
/* Enable RTOS Mode: Enable 32kHz clock synchronizer to SysTick external clock input */ /* Enable RTOS Mode: Enable 32kHz clock synchronizer to SysTick external clock input */
MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE; MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE;

5
targets/TARGET_Maxim/TARGET_MAX32620/gpio_api.c
View File

@ -88,8 +88,7 @@ void pin_dir(PinName name, PinDirection direction)
/* Enable default input weak pull-up by setting corresponding output */ /* Enable default input weak pull-up by setting corresponding output */
MXC_GPIO->out_val[port] |= 1 << pin; MXC_GPIO->out_val[port] |= 1 << pin;
} } else {
else {
/* Set requested output mode */ /* Set requested output mode */
MXC_GPIO->out_mode[port] = (MXC_GPIO->out_mode[port] & ~(0xF << (4 * pin))) | (MXC_V_GPIO_OUT_MODE_NORMAL << (4 * pin)); MXC_GPIO->out_mode[port] = (MXC_GPIO->out_mode[port] & ~(0xF << (4 * pin))) | (MXC_V_GPIO_OUT_MODE_NORMAL << (4 * pin));
} }
@ -97,5 +96,5 @@ void pin_dir(PinName name, PinDirection direction)
void gpio_dir(gpio_t *obj, PinDirection direction) void gpio_dir(gpio_t *obj, PinDirection direction)
{ {
pin_dir(obj->name, direction); pin_dir(obj->name, direction);
} }

2
targets/TARGET_Maxim/TARGET_MAX32620/gpio_irq_api.c
View File

@ -233,7 +233,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint3
void gpio_irq_free(gpio_irq_t *obj) void gpio_irq_free(gpio_irq_t *obj)
{ {
/* disable interrupt */ /* disable interrupt */
MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin); MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
MXC_GPIO->int_mode[obj->port] &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4)); MXC_GPIO->int_mode[obj->port] &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
objs[obj->port][obj->pin] = NULL; objs[obj->port][obj->pin] = NULL;

3
targets/TARGET_Maxim/TARGET_MAX32620/gpio_object.h
View File

@ -60,7 +60,8 @@ static inline int gpio_read(gpio_t *obj)
void pin_dir(PinName name, PinDirection direction); void pin_dir(PinName name, PinDirection direction);
static inline int gpio_is_connected(const gpio_t *obj) { static inline int gpio_is_connected(const gpio_t *obj)
{
return obj->name != (PinName)NC; return obj->name != (PinName)NC;
} }

84
targets/TARGET_Maxim/TARGET_MAX32620/i2c_api.c
View File

@ -60,42 +60,42 @@ typedef enum {
static const uint32_t clk_div_table[2][8] = { static const uint32_t clk_div_table[2][8] = {
/* MXC_E_I2CM_SPEED_100KHZ */ /* MXC_E_I2CM_SPEED_100KHZ */
{ {
/* 0: 12MHz */ ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | /* 0: 12MHz */ ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(17 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | (17 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), (72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
/* 1: 24MHz */ ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | /* 1: 24MHz */ ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(38 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | (38 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), (144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
/* 2: */ 0, /* not supported */ /* 2: */ 0, /* not supported */
/* 3: 48MHz */ ((24 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | /* 3: 48MHz */ ((24 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(80 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | (80 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(288 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), (288 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
/* 4: */ 0, /* not supported */ /* 4: */ 0, /* not supported */
/* 5: */ 0, /* not supported */ /* 5: */ 0, /* not supported */
/* 6: */ 0, /* not supported */ /* 6: */ 0, /* not supported */
/* 7: 96MHz */ ((48 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | /* 7: 96MHz */ ((48 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(164 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | (164 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(576 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), (576 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
}, },
/* MXC_E_I2CM_SPEED_400KHZ */ /* MXC_E_I2CM_SPEED_400KHZ */
{ {
/* 0: 12MHz */ ((2 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | /* 0: 12MHz */ ((2 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(1 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | (1 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(18 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), (18 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
/* 1: 24MHz */ ((3 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | /* 1: 24MHz */ ((3 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(5 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | (5 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(36 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), (36 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
/* 2: */ 0, /* not supported */ /* 2: */ 0, /* not supported */
/* 3: 48MHz */ ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | /* 3: 48MHz */ ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(15 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | (15 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), (72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
/* 4: */ 0, /* not supported */ /* 4: */ 0, /* not supported */
/* 5: */ 0, /* not supported */ /* 5: */ 0, /* not supported */
/* 6: */ 0, /* not supported */ /* 6: */ 0, /* not supported */
/* 7: 96MHz */ ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) | /* 7: 96MHz */ ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(33 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) | (33 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)), (144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
}, },
}; };
void i2c_init(i2c_t *obj, PinName sda, PinName scl) void i2c_init(i2c_t *obj, PinName sda, PinName scl)
@ -109,7 +109,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
obj->i2c = i2c; obj->i2c = i2c;
obj->fifos = (mxc_i2cm_fifo_regs_t*)MXC_I2CM_GET_BASE_FIFO(MXC_I2CM_GET_IDX(i2c)); obj->fifos = (mxc_i2cm_fifo_regs_t*)MXC_I2CM_GET_BASE_FIFO(MXC_I2CM_GET_IDX(i2c));
obj->start_pending = 0; obj->start_pending = 0;
obj->stop_pending = 0; obj->stop_pending = 0;
// configure the pins // configure the pins
pinmap_pinout(sda, PinMap_I2C_SDA); pinmap_pinout(sda, PinMap_I2C_SDA);
@ -135,10 +135,10 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
void i2c_frequency(i2c_t *obj, int hz) void i2c_frequency(i2c_t *obj, int hz)
{ {
// compute clock array index // compute clock array index
// (96Mhz/12M) -1 = 7 // (96Mhz/12M) -1 = 7
// (48Mhz/12M) -1 = 3 // (48Mhz/12M) -1 = 3
// (24Mhz/12M) -1 = 1 // (24Mhz/12M) -1 = 1
// (12Mhz/12M) -1 = 0 // (12Mhz/12M) -1 = 0
int clki = (SystemCoreClock / 12000000) - 1; int clki = (SystemCoreClock / 12000000) - 1;
// get clock divider settings from lookup table // get clock divider settings from lookup table
@ -318,7 +318,7 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
} }
if (stop) { if (stop) {
obj->stop_pending = 0; obj->stop_pending = 0;
if ((err = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition if ((err = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
retval = (retval ? retval : err); retval = (retval ? retval : err);
} }

2
targets/TARGET_Maxim/TARGET_MAX32620/port_api.c
View File

@ -50,7 +50,7 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
obj->reg_in = &MXC_GPIO->in_val[port]; obj->reg_in = &MXC_GPIO->in_val[port];
/* Ensure that the GPIO clock is enabled */ /* Ensure that the GPIO clock is enabled */
MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_S_CLKMAN_CLK_SCALE_DIV_1; MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_S_CLKMAN_CLK_SCALE_DIV_1;
uint32_t i; uint32_t i;
// The function is set per pin: reuse gpio logic // The function is set per pin: reuse gpio logic

4
targets/TARGET_Maxim/TARGET_MAX32620/pwmout_api.c
View File

@ -114,7 +114,7 @@ static void pwmout_update(pwmout_t* obj)
{ {
// Calculate and set the divider ratio // Calculate and set the divider ratio
int div = (obj->period * (SystemCoreClock/1000000))/32; int div = (obj->period * (SystemCoreClock/1000000))/32;
if (div < 2){ if (div < 2) {
div = 2; div = 2;
} }
MXC_SET_FIELD(&obj->pwm->rate_length, MXC_F_PT_RATE_LENGTH_RATE_CONTROL, div); MXC_SET_FIELD(&obj->pwm->rate_length, MXC_F_PT_RATE_LENGTH_RATE_CONTROL, div);
@ -142,7 +142,7 @@ void pwmout_write(pwmout_t* obj, float percent)
float pwmout_read(pwmout_t* obj) float pwmout_read(pwmout_t* obj)
{ {
// Check for when pulsewidth or period equals 0 // Check for when pulsewidth or period equals 0
if ((obj->pulse_width == 0) || (obj->period == 0)){ if ((obj->pulse_width == 0) || (obj->period == 0)) {
return 0; return 0;
} }

8
targets/TARGET_Maxim/TARGET_MAX32620/serial_api.c
View File

@ -311,7 +311,7 @@ void serial_putc(serial_t *obj, int c)
{ {
// Wait for TXFIFO to not be full // Wait for TXFIFO to not be full
while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
>> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)
>= MXC_UART_FIFO_DEPTH ); >= MXC_UART_FIFO_DEPTH );
// Must clear before every write to the buffer to know that the fifo // Must clear before every write to the buffer to know that the fifo
@ -330,8 +330,8 @@ int serial_readable(serial_t *obj)
int serial_writable(serial_t *obj) int serial_writable(serial_t *obj)
{ {
return ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) return ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
>> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)
< MXC_UART_FIFO_DEPTH ); < MXC_UART_FIFO_DEPTH );
} }
//****************************************************************************** //******************************************************************************
@ -348,7 +348,7 @@ void serial_break_set(serial_t *obj)
{ {
// Make sure that nothing is being sent // Make sure that nothing is being sent
while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
>> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) > 0); >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) > 0);
while (!(obj->uart->intfl & MXC_F_UART_INTFL_TX_DONE)); while (!(obj->uart->intfl & MXC_F_UART_INTFL_TX_DONE));
// Configure the GPIO to output 0 // Configure the GPIO to output 0

8
targets/TARGET_Maxim/TARGET_MAX32620/sleep.c
View File

@ -86,8 +86,7 @@ static void usb_sleep(void)
MXC_USB->dev_cn = 0; MXC_USB->dev_cn = 0;
MXC_USB->cn = 0; MXC_USB->cn = 0;
restore_usb = 1; // USB should be restored upon wakeup restore_usb = 1; // USB should be restored upon wakeup
} } else {
else {
restore_usb = 0; restore_usb = 0;
} }
} }
@ -124,7 +123,7 @@ void deepsleep(void)
// Wait for all STDIO characters to be sent. The UART clock will stop. // Wait for all STDIO characters to be sent. The UART clock will stop.
while ((stdio_uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) || while ((stdio_uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) ||
!(stdio_uart->intfl & MXC_F_UART_INTFL_TX_DONE)); !(stdio_uart->intfl & MXC_F_UART_INTFL_TX_DONE));
__disable_irq(); __disable_irq();
@ -187,8 +186,7 @@ void deepsleep(void)
__SEV(); __SEV();
__WFE(); __WFE();
__WFI(); __WFI();
} } else {
else {
// Note: ARM deep-sleep requires a specific sequence to clear event latches, // Note: ARM deep-sleep requires a specific sequence to clear event latches,
// otherwise the CPU will not enter sleep. // otherwise the CPU will not enter sleep.
__SEV(); __SEV();

4
targets/TARGET_Maxim/TARGET_MAX32620/spi_api.c
View File

@ -451,7 +451,7 @@ static uint32_t spi_master_transfer_handler(spi_t *obj)
// Check to see if we've finished reading and writing // Check to see if we've finished reading and writing
if (((read && (req->read_num == req->len)) || !read) && if (((read && (req->read_num == req->len)) || !read) &&
((req->write_num == req->len) || !write)) { ((req->write_num == req->len) || !write)) {
// Disable interrupts // Disable interrupts
spim->inten = 0; spim->inten = 0;
@ -516,7 +516,7 @@ uint8_t spi_active(spi_t *obj)
// Check to see if there are any ongoing transactions // Check to see if there are any ongoing transactions
if ((state[obj->spi.index] == NULL) && if ((state[obj->spi.index] == NULL) &&
!(spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED)) { !(spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED)) {
return 0; return 0;
} }

13
targets/TARGET_Maxim/TARGET_MAX32620/us_ticker.c
View File

@ -72,7 +72,8 @@ static volatile uint64_t event_cnt; // Holds the value of the next event
#define MAX_TICK_VAL ((uint64_t)0xFFFFFFFF * ticks_per_us) #define MAX_TICK_VAL ((uint64_t)0xFFFFFFFF * ticks_per_us)
//****************************************************************************** //******************************************************************************
static inline void inc_current_cnt(uint32_t inc) { static inline void inc_current_cnt(uint32_t inc)
{
// Overflow the ticker when the us ticker overflows // Overflow the ticker when the us ticker overflows
current_cnt += inc; current_cnt += inc;
@ -82,14 +83,15 @@ static inline void inc_current_cnt(uint32_t inc) {
} }
//****************************************************************************** //******************************************************************************
static inline int event_passed(uint64_t current, uint64_t event) { static inline int event_passed(uint64_t current, uint64_t event)
{
// Determine if the event has already happened. // Determine if the event has already happened.
// If the event is behind the current ticker, within a window, // If the event is behind the current ticker, within a window,
// then the event has already happened. // then the event has already happened.
if (((current < tick_win) && ((event < current) || if (((current < tick_win) && ((event < current) ||
(event > (MAX_TICK_VAL - (tick_win - current))))) || (event > (MAX_TICK_VAL - (tick_win - current))))) ||
((event < current) && (event > (current - tick_win)))) { ((event < current) && (event > (current - tick_win)))) {
return 1; return 1;
} }
@ -97,7 +99,8 @@ static inline int event_passed(uint64_t current, uint64_t event) {
} }
//****************************************************************************** //******************************************************************************
static inline uint64_t event_diff(uint64_t current, uint64_t event) { static inline uint64_t event_diff(uint64_t current, uint64_t event)
{
// Check to see if the ticker will overflow before the event // Check to see if the ticker will overflow before the event
if(current <= event) { if(current <= event) {