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[MAX32620HSP] Cleanup with formatting script.

pull/2832/head
Kevin Gillespie 2016-09-09 10:53:44 -05:00 committed by Jeremy Brodt
parent 8e70018ec1
commit 0611885832
24 changed files with 182 additions and 216 deletions
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60
targets/TARGET_Maxim/TARGET_MAX32620/PeripheralPins.c
View File

@ -68,14 +68,14 @@ const PinMap PinMap_I2C_SCL[] = {
/*
*/
const PinMap PinMap_UART_TX[] = {
{ P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
{ NC, NC, 0 }
};
@ -157,30 +157,30 @@ const PinMap PinMap_SPI_QUAD[] = {
/************PWM***************/
const PinMap PinMap_PWM[] = {
{ P0_0, PWM_0, 1 }, { P2_0, PWM_0, 1 }, { P4_0, PWM_0, 1 }, {P6_0, PWM_0, 1},
{ P0_1, PWM_1, 1 }, { P2_1, PWM_1, 1 }, { P4_1, PWM_1, 1 },
{ P0_2, PWM_2, 1 }, { P2_2, PWM_2, 1 }, { P4_2, PWM_2, 1 },
{ P0_3, PWM_3, 1 }, { P2_3, PWM_3, 1 }, { P4_3, PWM_3, 1 },
{ P0_4, PWM_4, 1 }, { P2_4, PWM_4, 1 }, { P4_4, PWM_4, 1 },
{ P0_5, PWM_5, 1 }, { P2_5, PWM_5, 1 }, { P4_5, PWM_5, 1 },
{ P0_6, PWM_6, 1 }, { P2_6, PWM_6, 1 }, { P4_6, PWM_6, 1 },
{ P0_7, PWM_7, 1 }, { P2_7, PWM_7, 1 }, { P4_7, PWM_7, 1 },
{ P1_0, PWM_8, 1 }, { P3_0, PWM_8, 1 }, { P5_0, PWM_8, 1 },
{ P1_1, PWM_9, 1 }, { P3_1, PWM_9, 1 }, { P5_1, PWM_9, 1 },
{ P1_2, PWM_10, 1 }, { P3_2, PWM_10, 1 }, { P5_2, PWM_10, 1 },
{ P1_3, PWM_11, 1 }, { P3_3, PWM_11, 1 }, { P5_3, PWM_11, 1 },
{ P1_4, PWM_12, 1 }, { P3_4, PWM_12, 1 }, { P5_4, PWM_12, 1 },
{ P1_5, PWM_13, 1 }, { P3_5, PWM_13, 1 }, { P5_5, PWM_13, 1 },
{ P1_6, PWM_14, 1 }, { P3_6, PWM_14, 1 }, { P5_6, PWM_14, 1 },
{ P1_7, PWM_15, 1 }, { P3_7, PWM_15, 1 }, { P5_7, PWM_15, 1 },
{ NC, NC, 0 }
{ P0_0, PWM_0, 1 }, { P2_0, PWM_0, 1 }, { P4_0, PWM_0, 1 }, {P6_0, PWM_0, 1},
{ P0_1, PWM_1, 1 }, { P2_1, PWM_1, 1 }, { P4_1, PWM_1, 1 },
{ P0_2, PWM_2, 1 }, { P2_2, PWM_2, 1 }, { P4_2, PWM_2, 1 },
{ P0_3, PWM_3, 1 }, { P2_3, PWM_3, 1 }, { P4_3, PWM_3, 1 },
{ P0_4, PWM_4, 1 }, { P2_4, PWM_4, 1 }, { P4_4, PWM_4, 1 },
{ P0_5, PWM_5, 1 }, { P2_5, PWM_5, 1 }, { P4_5, PWM_5, 1 },
{ P0_6, PWM_6, 1 }, { P2_6, PWM_6, 1 }, { P4_6, PWM_6, 1 },
{ P0_7, PWM_7, 1 }, { P2_7, PWM_7, 1 }, { P4_7, PWM_7, 1 },
{ P1_0, PWM_8, 1 }, { P3_0, PWM_8, 1 }, { P5_0, PWM_8, 1 },
{ P1_1, PWM_9, 1 }, { P3_1, PWM_9, 1 }, { P5_1, PWM_9, 1 },
{ P1_2, PWM_10, 1 }, { P3_2, PWM_10, 1 }, { P5_2, PWM_10, 1 },
{ P1_3, PWM_11, 1 }, { P3_3, PWM_11, 1 }, { P5_3, PWM_11, 1 },
{ P1_4, PWM_12, 1 }, { P3_4, PWM_12, 1 }, { P5_4, PWM_12, 1 },
{ P1_5, PWM_13, 1 }, { P3_5, PWM_13, 1 }, { P5_5, PWM_13, 1 },
{ P1_6, PWM_14, 1 }, { P3_6, PWM_14, 1 }, { P5_6, PWM_14, 1 },
{ P1_7, PWM_15, 1 }, { P3_7, PWM_15, 1 }, { P5_7, PWM_15, 1 },
{ NC, NC, 0 }
};
/************ADC***************/
const PinMap PinMap_ADC[] = {
{ AIN_0, ADC, 0 },
{ AIN_1, ADC, 0 },
{ AIN_2, ADC, 0 },
{ AIN_3, ADC, 0 },
{ NC, NC, 0 }
{ AIN_0, ADC, 0 },
{ AIN_1, ADC, 0 },
{ AIN_2, ADC, 0 },
{ AIN_3, ADC, 0 },
{ NC, NC, 0 }
};

2
targets/TARGET_Maxim/TARGET_MAX32620/PortNames.h
View File

@ -30,7 +30,7 @@
* ownership rights.
*******************************************************************************
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H

2
targets/TARGET_Maxim/TARGET_MAX32620/TARGET_MAX32620HSP/PinNames.h
View File

@ -116,7 +116,7 @@ typedef enum {
AIN_3 = (0xA << PORT_SHIFT) | 3,
// LEDs
LED_RED = P2_0,
LED_RED = P2_0,
LED1 = LED_RED,
LED2 = NOT_CONNECTED,
LED3 = NOT_CONNECTED,

4
targets/TARGET_Maxim/TARGET_MAX32620/analogin_api.c
View File

@ -49,7 +49,7 @@
// Only allow initialization once
static int initialized = 0;
//******************************************************************************
void analogin_init(analogin_t *obj, PinName pin)
{
@ -86,7 +86,7 @@ void analogin_init(analogin_t *obj, PinName pin)
// Enable ADC power bypass the buffer
obj->adc->ctrl |= (MXC_F_ADC_CTRL_ADC_PU | MXC_F_ADC_CTRL_ADC_REFBUF_PU |
MXC_F_ADC_CTRL_ADC_CHGPUMP_PU | MXC_F_ADC_CTRL_BUF_BYPASS);
MXC_F_ADC_CTRL_ADC_CHGPUMP_PU | MXC_F_ADC_CTRL_BUF_BYPASS);
// Wait for ADC ready
while (!(obj->adc->intr & MXC_F_ADC_INTR_ADC_REF_READY_IF));

2
targets/TARGET_Maxim/TARGET_MAX32620/device.h
View File

@ -32,7 +32,7 @@
* ownership rights.
*******************************************************************************
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"

2
targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/MAX32620.sct
View File

@ -14,7 +14,7 @@ LR_IROM1 0x00000000 0x200000 { ; load region size_region
}
; [RAM] Vector table dynamic copy: 65 vectors * 4 bytes = 260 (0x104) + 4
; for 8 byte alignment
; for 8 byte alignment
RW_IRAM1 (0x20000000+0x108) (0x40000-0x108) { ; RW data
.ANY (+RW +ZI)
}

7
targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/sys.cpp
View File

@ -36,11 +36,12 @@
#ifdef __cplusplus
extern "C" {
#endif
#endif
extern char Image$$RW_IRAM1$$ZI$$Limit[];
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
{
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
@ -54,4 +55,4 @@ extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_
#ifdef __cplusplus
}
#endif
#endif

2
targets/TARGET_Maxim/TARGET_MAX32620/device/cmsis.h
View File

@ -30,7 +30,7 @@
* ownership rights.
*******************************************************************************
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H

2
targets/TARGET_Maxim/TARGET_MAX32620/device/cmsis_nvic.c
View File

@ -30,7 +30,7 @@
* ownership rights.
*******************************************************************************
*/
#include "cmsis_nvic.h"
#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_ARM_STD)

108
targets/TARGET_Maxim/TARGET_MAX32620/device/ioman_regs.h
View File

@ -72,72 +72,63 @@ typedef enum {
Bitfield structs for registers in this module
*/
typedef struct
{
typedef struct {
uint32_t wud_req_p0 : 8;
uint32_t wud_req_p1 : 8;
uint32_t wud_req_p2 : 8;
uint32_t wud_req_p3 : 8;
} mxc_ioman_wud_req0_t;
typedef struct
{
typedef struct {
uint32_t wud_req_p4 : 8;
uint32_t wud_req_p5 : 8;
uint32_t wud_req_p6 : 1;
uint32_t : 15;
} mxc_ioman_wud_req1_t;
typedef struct
{
typedef struct {
uint32_t wud_ack_p0 : 8;
uint32_t wud_ack_p1 : 8;
uint32_t wud_ack_p2 : 8;
uint32_t wud_ack_p3 : 8;
} mxc_ioman_wud_ack0_t;
typedef struct
{
typedef struct {
uint32_t wud_ack_p4 : 8;
uint32_t wud_ack_p5 : 8;
uint32_t wud_ack_p6 : 1;
uint32_t : 15;
} mxc_ioman_wud_ack1_t;
typedef struct
{
typedef struct {
uint32_t ali_req_p0 : 8;
uint32_t ali_req_p1 : 8;
uint32_t ali_req_p2 : 8;
uint32_t ali_req_p3 : 8;
} mxc_ioman_ali_req0_t;
typedef struct
{
typedef struct {
uint32_t ali_req_p4 : 8;
uint32_t ali_req_p5 : 8;
uint32_t ali_req_p6 : 1;
uint32_t : 15;
} mxc_ioman_ali_req1_t;
typedef struct
{
typedef struct {
uint32_t ali_ack_p0 : 8;
uint32_t ali_ack_p1 : 8;
uint32_t ali_ack_p2 : 8;
uint32_t ali_ack_p3 : 8;
} mxc_ioman_ali_ack0_t;
typedef struct
{
typedef struct {
uint32_t ali_ack_p4 : 8;
uint32_t ali_ack_p5 : 8;
uint32_t ali_ack_p6 : 1;
uint32_t : 15;
} mxc_ioman_ali_ack1_t;
typedef struct
{
typedef struct {
uint32_t : 4;
uint32_t core_io_req : 1;
uint32_t : 3;
@ -151,8 +142,7 @@ typedef struct
uint32_t : 15;
} mxc_ioman_spix_req_t;
typedef struct
{
typedef struct {
uint32_t : 4;
uint32_t core_io_ack : 1;
uint32_t : 3;
@ -166,8 +156,7 @@ typedef struct
uint32_t : 15;
} mxc_ioman_spix_ack_t;
typedef struct
{
typedef struct {
uint32_t io_map : 1;
uint32_t cts_map : 1;
uint32_t rts_map : 1;
@ -178,8 +167,7 @@ typedef struct
uint32_t : 25;
} mxc_ioman_uart0_req_t;
typedef struct
{
typedef struct {
uint32_t io_map : 1;
uint32_t cts_map : 1;
uint32_t rts_map : 1;
@ -190,8 +178,7 @@ typedef struct
uint32_t : 25;
} mxc_ioman_uart0_ack_t;
typedef struct
{
typedef struct {
uint32_t io_map : 1;
uint32_t cts_map : 1;
uint32_t rts_map : 1;
@ -202,8 +189,7 @@ typedef struct
uint32_t : 25;
} mxc_ioman_uart1_req_t;
typedef struct
{
typedef struct {
uint32_t io_map : 1;
uint32_t cts_map : 1;
uint32_t rts_map : 1;
@ -214,8 +200,7 @@ typedef struct
uint32_t : 25;
} mxc_ioman_uart1_ack_t;
typedef struct
{
typedef struct {
uint32_t io_map : 1;
uint32_t cts_map : 1;
uint32_t rts_map : 1;
@ -226,8 +211,7 @@ typedef struct
uint32_t : 25;
} mxc_ioman_uart2_req_t;
typedef struct
{
typedef struct {
uint32_t io_map : 1;
uint32_t cts_map : 1;
uint32_t rts_map : 1;
@ -238,8 +222,7 @@ typedef struct
uint32_t : 25;
} mxc_ioman_uart2_ack_t;
typedef struct
{
typedef struct {
uint32_t io_map : 1;
uint32_t cts_map : 1;
uint32_t rts_map : 1;
@ -250,8 +233,7 @@ typedef struct
uint32_t : 25;
} mxc_ioman_uart3_req_t;
typedef struct
{
typedef struct {
uint32_t io_map : 1;
uint32_t cts_map : 1;
uint32_t rts_map : 1;
@ -262,66 +244,57 @@ typedef struct
uint32_t : 25;
} mxc_ioman_uart3_ack_t;
typedef struct
{
typedef struct {
uint32_t : 4;
uint32_t mapping_req : 1;
uint32_t : 27;
} mxc_ioman_i2cm0_req_t;
typedef struct
{
typedef struct {
uint32_t : 4;
uint32_t mapping_ack : 1;
uint32_t : 27;
} mxc_ioman_i2cm0_ack_t;
typedef struct
{
typedef struct {
uint32_t : 4;
uint32_t mapping_req : 1;
uint32_t : 27;
} mxc_ioman_i2cm1_req_t;
typedef struct
{
typedef struct {
uint32_t : 4;
uint32_t mapping_ack : 1;
uint32_t : 27;
} mxc_ioman_i2cm1_ack_t;
typedef struct
{
typedef struct {
uint32_t : 4;
uint32_t mapping_req : 1;
uint32_t : 27;
} mxc_ioman_i2cm2_req_t;
typedef struct
{
typedef struct {
uint32_t : 4;
uint32_t mapping_ack : 1;
uint32_t : 27;
} mxc_ioman_i2cm2_ack_t;
typedef struct
{
typedef struct {
uint32_t io_sel : 2;
uint32_t : 2;
uint32_t mapping_req : 1;
uint32_t : 27;
} mxc_ioman_i2cs_req_t;
typedef struct
{
typedef struct {
uint32_t io_sel : 2;
uint32_t : 2;
uint32_t mapping_ack : 1;
uint32_t : 27;
} mxc_ioman_i2cs_ack_t;
typedef struct
{
typedef struct {
uint32_t : 4;
uint32_t core_io_req : 1;
uint32_t : 3;
@ -337,8 +310,7 @@ typedef struct
uint32_t : 7;
} mxc_ioman_spim0_req_t;
typedef struct
{
typedef struct {
uint32_t : 4;
uint32_t core_io_ack : 1;
uint32_t : 3;
@ -354,8 +326,7 @@ typedef struct
uint32_t : 7;
} mxc_ioman_spim0_ack_t;
typedef struct
{
typedef struct {
uint32_t : 4;
uint32_t core_io_req : 1;
uint32_t : 3;
@ -369,8 +340,7 @@ typedef struct
uint32_t : 7;
} mxc_ioman_spim1_req_t;
typedef struct
{
typedef struct {
uint32_t : 4;
uint32_t core_io_ack : 1;
uint32_t : 3;
@ -384,8 +354,7 @@ typedef struct
uint32_t : 7;
} mxc_ioman_spim1_ack_t;
typedef struct
{
typedef struct {
uint32_t mapping_req : 1;
uint32_t : 3;
uint32_t core_io_req : 1;
@ -403,8 +372,7 @@ typedef struct
uint32_t : 7;
} mxc_ioman_spim2_req_t;
typedef struct
{
typedef struct {
uint32_t mapping_ack : 1;
uint32_t : 3;
uint32_t core_io_ack : 1;
@ -422,8 +390,7 @@ typedef struct
uint32_t : 7;
} mxc_ioman_spim2_ack_t;
typedef struct
{
typedef struct {
uint32_t : 4;
uint32_t core_io_req : 1;
uint32_t : 3;
@ -433,8 +400,7 @@ typedef struct
uint32_t : 19;
} mxc_ioman_spib_req_t;
typedef struct
{
typedef struct {
uint32_t : 4;
uint32_t core_io_ack : 1;
uint32_t : 3;
@ -444,16 +410,14 @@ typedef struct
uint32_t : 19;
} mxc_ioman_spib_ack_t;
typedef struct
{
typedef struct {
uint32_t : 4;
uint32_t mapping_req : 1;
uint32_t epu_io_req : 1;
uint32_t : 26;
} mxc_ioman_owm_req_t;
typedef struct
{
typedef struct {
uint32_t : 4;
uint32_t mapping_ack : 1;
uint32_t epu_io_ack : 1;

20
targets/TARGET_Maxim/TARGET_MAX32620/device/pmu_regs.h
View File

@ -57,20 +57,20 @@ extern "C" {
typedef struct {
__IO uint32_t start_opcode[32];
__IO uint32_t enable;
__IO uint32_t rsvd0;
__IO uint32_t rsvd0;
__IO uint32_t ll_stopped;
__IO uint32_t manual;
__IO uint32_t bus_error;
__IO uint32_t rsvd1;
__IO uint32_t to_stat;
__IO uint32_t rsvd2[4];
__IO uint32_t to_sel[3];
__IO uint32_t manual;
__IO uint32_t bus_error;
__IO uint32_t rsvd1;
__IO uint32_t to_stat;
__IO uint32_t rsvd2[4];
__IO uint32_t to_sel[3];
__IO uint32_t ps_sel[2];
__IO uint32_t interrupt;
__IO uint32_t interrupt;
__IO uint32_t int_enable;
__IO uint32_t rsvd3[6];
__IO uint32_t rsvd3[6];
__IO uint32_t burst_size[5];
__IO uint32_t rsvd4[3];
__IO uint32_t rsvd4[3];
__IO uint32_t padding[192]; /* Offset to next channel */
} mxc_pmu_bits_t;

8
targets/TARGET_Maxim/TARGET_MAX32620/device/system_max32620.c
View File

@ -58,7 +58,7 @@ uint32_t SystemCoreClock = RO_FREQ;
void SystemCoreClockUpdate(void)
{
switch ((MXC_CLKMAN->clk_ctrl & MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) >> MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS) {
case MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2:
default:
SystemCoreClock = RO_FREQ / 2;
@ -187,11 +187,11 @@ void SystemInit(void)
// Clear all unused wakeup sources
// Beware! Do not change any flag not mentioned here, as they will gate important power sequencer signals
MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP |
MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP);
MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP);
// RTC sources are inverted, so a 1 will disable them
MXC_PWRSEQ->msk_flags |= (MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 |
MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP);
MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP);
/* Enable RTOS Mode: Enable 32kHz clock synchronizer to SysTick external clock input */
MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE;
@ -206,7 +206,7 @@ void SystemInit(void)
SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
__DSB();
__ISB();
#endif
#endif
// Trim ring oscillator
Trim_ROAtomic();

7
targets/TARGET_Maxim/TARGET_MAX32620/gpio_api.c
View File

@ -85,11 +85,10 @@ void pin_dir(PinName name, PinDirection direction)
if (direction == PIN_INPUT) {
/* Set requested output mode */
MXC_GPIO->out_mode[port] = (MXC_GPIO->out_mode[port] & ~(0xF << (4 * pin))) | (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * pin));
/* Enable default input weak pull-up by setting corresponding output */
MXC_GPIO->out_val[port] |= 1 << pin;
}
else {
} else {
/* Set requested output mode */
MXC_GPIO->out_mode[port] = (MXC_GPIO->out_mode[port] & ~(0xF << (4 * pin))) | (MXC_V_GPIO_OUT_MODE_NORMAL << (4 * pin));
}
@ -97,5 +96,5 @@ void pin_dir(PinName name, PinDirection direction)
void gpio_dir(gpio_t *obj, PinDirection direction)
{
pin_dir(obj->name, direction);
pin_dir(obj->name, direction);
}

2
targets/TARGET_Maxim/TARGET_MAX32620/gpio_irq_api.c
View File

@ -233,7 +233,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint3
void gpio_irq_free(gpio_irq_t *obj)
{
/* disable interrupt */
/* disable interrupt */
MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
MXC_GPIO->int_mode[obj->port] &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
objs[obj->port][obj->pin] = NULL;

5
targets/TARGET_Maxim/TARGET_MAX32620/gpio_object.h
View File

@ -30,7 +30,7 @@
* ownership rights.
*******************************************************************************
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
@ -60,7 +60,8 @@ static inline int gpio_read(gpio_t *obj)
void pin_dir(PinName name, PinDirection direction);
static inline int gpio_is_connected(const gpio_t *obj) {
static inline int gpio_is_connected(const gpio_t *obj)
{
return obj->name != (PinName)NC;
}

84
targets/TARGET_Maxim/TARGET_MAX32620/i2c_api.c
View File

@ -60,42 +60,42 @@ typedef enum {
static const uint32_t clk_div_table[2][8] = {
/* MXC_E_I2CM_SPEED_100KHZ */
{
/* 0: 12MHz */ ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(17 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
/* 1: 24MHz */ ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(38 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
/* 2: */ 0, /* not supported */
/* 3: 48MHz */ ((24 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(80 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(288 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
/* 4: */ 0, /* not supported */
/* 5: */ 0, /* not supported */
/* 6: */ 0, /* not supported */
/* 7: 96MHz */ ((48 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(164 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(576 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
},
/* MXC_E_I2CM_SPEED_400KHZ */
{
/* 0: 12MHz */ ((2 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(1 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(18 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
/* 1: 24MHz */ ((3 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(5 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(36 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
/* 2: */ 0, /* not supported */
/* 3: 48MHz */ ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(15 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
/* 4: */ 0, /* not supported */
/* 5: */ 0, /* not supported */
/* 6: */ 0, /* not supported */
/* 7: 96MHz */ ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(33 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
},
/* 0: 12MHz */ ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(17 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
/* 1: 24MHz */ ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(38 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
/* 2: */ 0, /* not supported */
/* 3: 48MHz */ ((24 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(80 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(288 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
/* 4: */ 0, /* not supported */
/* 5: */ 0, /* not supported */
/* 6: */ 0, /* not supported */
/* 7: 96MHz */ ((48 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(164 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(576 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
},
/* MXC_E_I2CM_SPEED_400KHZ */
{
/* 0: 12MHz */ ((2 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(1 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(18 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
/* 1: 24MHz */ ((3 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(5 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(36 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
/* 2: */ 0, /* not supported */
/* 3: 48MHz */ ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(15 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
/* 4: */ 0, /* not supported */
/* 5: */ 0, /* not supported */
/* 6: */ 0, /* not supported */
/* 7: 96MHz */ ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
(33 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
(144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
},
};
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
@ -109,7 +109,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
obj->i2c = i2c;
obj->fifos = (mxc_i2cm_fifo_regs_t*)MXC_I2CM_GET_BASE_FIFO(MXC_I2CM_GET_IDX(i2c));
obj->start_pending = 0;
obj->stop_pending = 0;
obj->stop_pending = 0;
// configure the pins
pinmap_pinout(sda, PinMap_I2C_SDA);
@ -135,10 +135,10 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
void i2c_frequency(i2c_t *obj, int hz)
{
// compute clock array index
// (96Mhz/12M) -1 = 7
// (48Mhz/12M) -1 = 3
// (24Mhz/12M) -1 = 1
// (12Mhz/12M) -1 = 0
// (96Mhz/12M) -1 = 7
// (48Mhz/12M) -1 = 3
// (24Mhz/12M) -1 = 1
// (12Mhz/12M) -1 = 0
int clki = (SystemCoreClock / 12000000) - 1;
// get clock divider settings from lookup table
@ -318,7 +318,7 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
}
if (stop) {
obj->stop_pending = 0;
obj->stop_pending = 0;
if ((err = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
retval = (retval ? retval : err);
}

2
targets/TARGET_Maxim/TARGET_MAX32620/pinmap.c
View File

@ -30,7 +30,7 @@
* ownership rights.
*******************************************************************************
*/
#include "mbed_assert.h"
#include "pinmap.h"
#include "objects.h"

4
targets/TARGET_Maxim/TARGET_MAX32620/port_api.c
View File

@ -30,7 +30,7 @@
* ownership rights.
*******************************************************************************
*/
#include "port_api.h"
#include "pinmap.h"
#include "gpio_api.h"
@ -50,7 +50,7 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
obj->reg_in = &MXC_GPIO->in_val[port];
/* Ensure that the GPIO clock is enabled */
MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_S_CLKMAN_CLK_SCALE_DIV_1;
MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_S_CLKMAN_CLK_SCALE_DIV_1;
uint32_t i;
// The function is set per pin: reuse gpio logic

6
targets/TARGET_Maxim/TARGET_MAX32620/pwmout_api.c
View File

@ -79,7 +79,7 @@ void pwmout_init(pwmout_t* obj, PinName pin)
obj->pwm = (mxc_pt_regs_t*)pwm.peripheral;
// Initialize object period and pulse width
obj->period = -1;
obj->period = -1;
obj->pulse_width = -1;
// Disable the output
@ -114,7 +114,7 @@ static void pwmout_update(pwmout_t* obj)
{
// Calculate and set the divider ratio
int div = (obj->period * (SystemCoreClock/1000000))/32;
if (div < 2){
if (div < 2) {
div = 2;
}
MXC_SET_FIELD(&obj->pwm->rate_length, MXC_F_PT_RATE_LENGTH_RATE_CONTROL, div);
@ -142,7 +142,7 @@ void pwmout_write(pwmout_t* obj, float percent)
float pwmout_read(pwmout_t* obj)
{
// Check for when pulsewidth or period equals 0
if ((obj->pulse_width == 0) || (obj->period == 0)){
if ((obj->pulse_width == 0) || (obj->period == 0)) {
return 0;
}

6
targets/TARGET_Maxim/TARGET_MAX32620/rtc_api.c
View File

@ -83,7 +83,7 @@ static uint64_t rtc_read64(void);
//******************************************************************************
static void overflow_handler(void)
{
MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
overflow_cnt++;
// Wait for pending transactions
@ -271,7 +271,7 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
}
MXC_RTCTMR->comp[0] = comp_value;
MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0; // enable the interrupt
// Enable wakeup from RTC
@ -290,7 +290,7 @@ inline void lp_ticker_disable_interrupt(void)
//******************************************************************************
inline void lp_ticker_clear_interrupt(void)
{
MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
// Wait for pending transactions
while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);

12
targets/TARGET_Maxim/TARGET_MAX32620/serial_api.c
View File

@ -92,7 +92,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
// To support the most common baud rates, 9600 and 115200, we need to
// scale down the uart input clock.
if (!(MXC_CLKMAN->sys_clk_ctrl_8_uart & MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE)) {
switch (SystemCoreClock) {
case RO_FREQ:
MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_4;
@ -134,7 +134,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
// Enable UART
obj->uart->ctrl |= MXC_F_UART_CTRL_UART_EN;
}
@ -311,7 +311,7 @@ void serial_putc(serial_t *obj, int c)
{
// Wait for TXFIFO to not be full
while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
>> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)
>> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)
>= MXC_UART_FIFO_DEPTH );
// Must clear before every write to the buffer to know that the fifo
@ -330,8 +330,8 @@ int serial_readable(serial_t *obj)
int serial_writable(serial_t *obj)
{
return ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
>> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)
< MXC_UART_FIFO_DEPTH );
>> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)
< MXC_UART_FIFO_DEPTH );
}
//******************************************************************************
@ -348,7 +348,7 @@ void serial_break_set(serial_t *obj)
{
// Make sure that nothing is being sent
while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
>> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) > 0);
>> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) > 0);
while (!(obj->uart->intfl & MXC_F_UART_INTFL_TX_DONE));
// Configure the GPIO to output 0

8
targets/TARGET_Maxim/TARGET_MAX32620/sleep.c
View File

@ -86,8 +86,7 @@ static void usb_sleep(void)
MXC_USB->dev_cn = 0;
MXC_USB->cn = 0;
restore_usb = 1; // USB should be restored upon wakeup
}
else {
} else {
restore_usb = 0;
}
}
@ -124,7 +123,7 @@ void deepsleep(void)
// Wait for all STDIO characters to be sent. The UART clock will stop.
while ((stdio_uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) ||
!(stdio_uart->intfl & MXC_F_UART_INTFL_TX_DONE));
!(stdio_uart->intfl & MXC_F_UART_INTFL_TX_DONE));
__disable_irq();
@ -187,8 +186,7 @@ void deepsleep(void)
__SEV();
__WFE();
__WFI();
}
else {
} else {
// Note: ARM deep-sleep requires a specific sequence to clear event latches,
// otherwise the CPU will not enter sleep.
__SEV();

22
targets/TARGET_Maxim/TARGET_MAX32620/spi_api.c
View File

@ -69,7 +69,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
// Give the application the option to manually control Slave Select
if ((SPIName)spi_ssel != (SPIName)NC) {
spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
// Slave select is currently limited to slave select zero. If others are
// Slave select is currently limited to slave select zero. If others are
// to be supported a function to map PinName to a value suitable for use
// in mstr_cfg.slave_sel will be required.
obj->spi.ssel = 0;
@ -352,7 +352,7 @@ static uint32_t spi_master_transfer_handler(spi_t *obj)
// Set the transaction configuration in the header
header = ((write | (read << 1)) << MXC_F_SPI_FIFO_DIR_POS) | (req->width << MXC_F_SPI_FIFO_WIDTH_POS);
if (remain >= SPI_MAX_BYTE_LEN) {
// Send a 32 byte header
@ -367,7 +367,7 @@ static uint32_t spi_master_transfer_handler(spi_t *obj)
// Send in increments of 32 byte pages
header |= MXC_S_SPI_FIFO_UNIT_PAGES;
pages = remain / SPI_MAX_PAGE_LEN;
if (pages >= 32) {
// 0 maps to 32 in the header
bytes = 32 * SPI_MAX_PAGE_LEN;
@ -380,7 +380,7 @@ static uint32_t spi_master_transfer_handler(spi_t *obj)
if ((remain - bytes) == 0) {
header |= MXC_F_SPI_FIFO_DASS;
}
}
}
fifo->trans_16[0] = header;
@ -414,7 +414,7 @@ static uint32_t spi_master_transfer_handler(spi_t *obj)
}
// Only memcpy even numbers
length = ((length / 2) * 2);
length = ((length / 2) * 2);
memcpy((void*)fifo->trans_32, &(req->tx_data[req->write_num]), length);
@ -450,8 +450,8 @@ static uint32_t spi_master_transfer_handler(spi_t *obj)
}
// Check to see if we've finished reading and writing
if (((read && (req->read_num == req->len)) || !read) &&
((req->write_num == req->len) || !write)) {
if (((read && (req->read_num == req->len)) || !read) &&
((req->write_num == req->len) || !write)) {
// Disable interrupts
spim->inten = 0;
@ -469,7 +469,7 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx,
// Save object reference for callback
state[obj->spi.index] = &obj->spi;
// Initialize request info
obj->spi.tx_data = tx;
obj->spi.rx_data = rx;
@ -491,7 +491,7 @@ uint32_t spi_irq_handler_asynch(spi_t *obj)
{
mxc_spi_regs_t *spim = obj->spi.spi;
uint32_t flags;
// Clear the interrupt flags
spim->inten = 0;
flags = spim->intfl;
@ -503,7 +503,7 @@ uint32_t spi_irq_handler_asynch(spi_t *obj)
return 0;
}
}
state[obj->spi.index] = NULL;
return SPI_EVENT_COMPLETE;
@ -516,7 +516,7 @@ uint8_t spi_active(spi_t *obj)
// Check to see if there are any ongoing transactions
if ((state[obj->spi.index] == NULL) &&
!(spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED)) {
!(spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED)) {
return 0;
}

21
targets/TARGET_Maxim/TARGET_MAX32620/us_ticker.c
View File

@ -72,7 +72,8 @@ static volatile uint64_t event_cnt; // Holds the value of the next event
#define MAX_TICK_VAL ((uint64_t)0xFFFFFFFF * ticks_per_us)
//******************************************************************************
static inline void inc_current_cnt(uint32_t inc) {
static inline void inc_current_cnt(uint32_t inc)
{
// Overflow the ticker when the us ticker overflows
current_cnt += inc;
@ -82,14 +83,15 @@ static inline void inc_current_cnt(uint32_t inc) {
}
//******************************************************************************
static inline int event_passed(uint64_t current, uint64_t event) {
static inline int event_passed(uint64_t current, uint64_t event)
{
// Determine if the event has already happened.
// If the event is behind the current ticker, within a window,
// then the event has already happened.
if (((current < tick_win) && ((event < current) ||
(event > (MAX_TICK_VAL - (tick_win - current))))) ||
((event < current) && (event > (current - tick_win)))) {
if (((current < tick_win) && ((event < current) ||
(event > (MAX_TICK_VAL - (tick_win - current))))) ||
((event < current) && (event > (current - tick_win)))) {
return 1;
}
@ -97,7 +99,8 @@ static inline int event_passed(uint64_t current, uint64_t event) {
}
//******************************************************************************
static inline uint64_t event_diff(uint64_t current, uint64_t event) {
static inline uint64_t event_diff(uint64_t current, uint64_t event)
{
// Check to see if the ticker will overflow before the event
if(current <= event) {
@ -129,7 +132,7 @@ static void tmr_handler(void)
US_TIMER->term_cnt32 = diff;
// Since the timer keeps counting after the terminal value is reached, it is possible that the new
// terminal value is in the past.
// terminal value is in the past.
if (US_TIMER->term_cnt32 < US_TIMER->count32) {
// the timestamp has expired
US_TIMER->term_cnt32 = 0xFFFFFFFF; // reset to max value to prevent further interrupts
@ -239,7 +242,7 @@ void us_ticker_set_interrupt(timestamp_t timestamp)
inc_current_cnt(US_TIMER->count32);
US_TIMER->count32 = 0;
// add the number of cycles that the timer is disabled here for
// add the number of cycles that the timer is disabled here for
inc_current_cnt(200);
event_cnt = (uint64_t)timestamp * ticks_per_us;
@ -251,7 +254,7 @@ void us_ticker_set_interrupt(timestamp_t timestamp)
// the event occurs before the next overflow
US_TIMER->term_cnt32 = diff;
} else {
// the event occurs after the next overflow
// the event occurs after the next overflow
US_TIMER->term_cnt32 = 0xFFFFFFFF; // set to max
}
} else {