Update 802.15.4 Atmel RF driver

Sync with master version v3.3.0

components/802.15.4_RF/atmel-rf-driver/atmel-rf-driver/NanostackRfPhyAtmel.h

@@ -70,9 +70,16 @@
 #if !defined(TEST_PIN_SPARE_2)
 #define TEST_PIN_SPARE_2    D8
 #endif
+#if !defined(SE2435L_CSD)
+#define SE2435L_CSD    D2
+#endif
+#if !defined(SE2435L_ANT_SEL)
+#define SE2435L_ANT_SEL    D8
+#endif
 
 class RFBits;
 class TestPins;
+class Se2435Pins;
 
 class NanostackRfPhyAtmel : public NanostackRfPhy {
 public:
@@ -86,10 +93,13 @@ public:
     virtual void set_mac_address(uint8_t *mac);
 
 private:
+#if !defined(DISABLE_AT24MAC)
     AT24Mac _mac;
+#endif
     uint8_t _mac_addr[8];
     RFBits *_rf;
     TestPins *_test_pins;
+    Se2435Pins *_se2435_pa_pins;
     bool _mac_set;
 
     const PinName _spi_mosi;

components/802.15.4_RF/atmel-rf-driver/source/AT86RF215Reg.h

@@ -26,6 +26,7 @@ extern "C" {
 #define RF24_IRQS                   0x01
 #define BBC0_IRQS                   0x02
 #define BBC1_IRQS                   0x03
+#define RF_AUXS                     0x01
 #define RF_CFG                      0x06
 #define RF_IQIFC1                   0x0B
 #define RF_PN                       0x0D
@@ -47,6 +48,8 @@ extern "C" {
 #define RF_EDV                      0x10
 #define RF_TXCUTC                   0x12
 #define RF_TXDFE                    0x13
+#define RF_PAC                      0x14
+#define RF_PADFE                    0x16
 #define BBC_IRQM                    0x00
 #define BBC_PC                      0x01
 #define BBC_RXFLL                   0x04
@@ -55,6 +58,9 @@ extern "C" {
 #define BBC_TXFLH                   0x07
 #define BBC_FBLL                    0x08
 #define BBC_FBLH                    0x09
+#define BBC_OFDMPHRTX               0x0C
+#define BBC_OFDMC                   0x0E
+#define BBC_OFDMSW                  0x0F
 #define BBC_OQPSKC0                 0x10
 #define BBC_OQPSKC1                 0x11
 #define BBC_OQPSKC2                 0x12
@@ -82,6 +88,20 @@ extern "C" {
 #define BBC1_FBRXS                  0x3000
 #define BBC1_FBTXS                  0x3800
 
+// RF_AUXS
+#define EXTLNABYP                   (1 << 7)
+#define AGCMAP                      0x60
+#define AGCMAP_2                    (2 << 5)
+#define AVEN                        (1 << 3)
+
+// RF_PAC
+#define TXPWR                       0x1F
+#define TXPWR_11                    (11 << 0)
+
+// RF_PADFE
+#define PADFE                       0xC0
+#define RF_FEMODE3                  (3 << 6)
+
 // RF_AGCC
 #define AGCI                        (1 << 6)
 #define AVGS                        0x30
@@ -90,7 +110,7 @@ extern "C" {
 // RF_AGCS
 #define TGT                         0xE0
 #define TGT_1                       (1 << 5)
-
+#define TGT_3                       (3 << 5)
 
 // RF_RXBWC
 #define BW                          0x0F
@@ -131,6 +151,7 @@ extern "C" {
 // RF_TXDFE, RF_RXDFE
 #define RCUT                        0xE0
 #define RCUT_4                      (4 << 5)
+#define RCUT_3                      (3 << 5)
 #define RCUT_2                      (2 << 5)
 #define RCUT_1                      (1 << 5)
 #define RCUT_0                      (0 << 5)
@@ -144,6 +165,41 @@ extern "C" {
 #define SR_2                        (2 << 0)
 #define SR_1                        (1 << 0)
 
+// BBC_OFDMPHRTX
+#define MCS                         0x07
+#define MCS_0                       (0 << 0)
+#define MCS_1                       (1 << 0)
+#define MCS_2                       (2 << 0)
+#define MCS_3                       (3 << 0)
+#define MCS_4                       (4 << 0)
+#define MCS_5                       (5 << 0)
+#define MCS_6                       (6 << 0)
+
+// BBC_OFDMC
+#define SSRX                        0xC0
+#define SSRX_0                      (0 << 6)
+#define SSRX_1                      (1 << 6)
+#define SSRX_2                      (2 << 6)
+#define SSRX_3                      (3 << 6)
+#define SSTX                        0x30
+#define SSTX_0                      (0 << 4)
+#define SSTX_1                      (1 << 4)
+#define SSTX_2                      (2 << 4)
+#define SSTX_3                      (3 << 4)
+#define LFO                         (1 << 3)
+#define POI                         (1 << 2)
+#define OPT                         0x03
+#define OPT_1                       (0 << 0)
+#define OPT_2                       (1 << 0)
+#define OPT_3                       (2 << 0)
+#define OPT_4                       (3 << 0)
+
+// BBC_OFDMSW
+#define OFDM_PDT                    0xE0
+#define OFDM_PDT_5                  (5 << 5)
+#define OFDM_PDT_4                  (4 << 5)
+#define OFDM_PDT_3                  (3 << 5)
+
 // BBC_FSKC0
 #define BT                          0xC0
 #define BT_20                       (3 << 6)

components/802.15.4_RF/atmel-rf-driver/source/AT86RFReg.h

@@ -48,6 +48,7 @@ extern "C" {
 #define PART_AT86RF212              0x07
 #define PART_AT86RF233              0x0B
 #define PART_AT86RF215              0x34
+#define PART_AT86RF215M             0x36
 #define VERSION_AT86RF212           0x01
 #define VERSION_AT86RF212B          0x03
 

components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAT86RF215.cpp

@@ -23,6 +23,7 @@
 #include "platform/mbed_wait_api.h"
 #include "nanostack/platform/arm_hal_phy.h"
 #include "NanostackRfPhyAtmel.h"
+#include "AT86RFReg.h"
 #include "AT86RF215Reg.h"
 #include "mbed_trace.h"
 #include "common_functions.h"
@@ -99,6 +100,7 @@ static int rf_set_channel(uint16_t channel, rf_modules_e module);
 static int rf_set_ch0_frequency(uint32_t frequency, rf_modules_e module);
 static int rf_set_channel_spacing(uint32_t channel_spacing, rf_modules_e module);
 static int rf_set_fsk_symbol_rate_configuration(uint32_t symbol_rate, rf_modules_e module);
+static int rf_configure_by_ofdm_bandwidth_option(uint8_t option, uint32_t data_rate, rf_modules_e module);
 static void rf_calculate_symbol_rate(uint32_t baudrate, phy_modulation_e modulation);
 static void rf_conf_set_cca_threshold(uint8_t percent);
 // Defined register read/write functions
@@ -164,6 +166,7 @@ using namespace rtos;
 #include "rfbits.h"
 static RFBits *rf;
 static TestPins *test_pins;
+static Se2435Pins *se2435_pa_pins = NULL;
 
 #define MAC_FRAME_TYPE_MASK     0x07
 #define MAC_TYPE_ACK            (2)
@@ -300,6 +303,9 @@ static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_pt
         case PHY_EXTENSION_SET_CCA_THRESHOLD:
             rf_conf_set_cca_threshold(*data_ptr);
             break;
+        case PHY_EXTENSION_SET_CHANNEL_CCA_THRESHOLD:
+            cca_threshold = (int8_t) *data_ptr; // *NOPAD*
+            break;
         case PHY_EXTENSION_SET_802_15_4_MODE:
             mac_mode = (phy_802_15_4_mode_t) *data_ptr; // *NOPAD*
             if (mac_mode == IEEE_802_15_4_2011) {
@@ -378,7 +384,8 @@ static void rf_init(void)
 static void rf_init_registers(rf_modules_e module)
 {
     // O-QPSK configuration using IEEE Std 802.15.4-2011
-    // FSK configuration using IEEE Std 802.15.4g-2012
+    // FSK/OFDM configuration using IEEE Std 802.15.4g-2012
+    // OFDM configuration is experimental only
     if (mac_mode == IEEE_802_15_4_2011) {
         device_driver.link_type = PHY_LINK_15_4_2_4GHZ_TYPE;
         // 16-bit FCS
@@ -405,41 +412,72 @@ static void rf_init_registers(rf_modules_e module)
         rf_write_bbc_register_field(BBC_AFFTM, module, TYPE_2, TYPE_2);
     } else if (mac_mode == IEEE_802_15_4G_2012) {
         device_driver.link_type = PHY_LINK_15_4_SUBGHZ_TYPE;
-        // Enable FSK
-        rf_write_bbc_register_field(BBC_PC, module, PT, BB_MRFSK);
         // Disable auto ack
         rf_write_bbc_register_field(BBC_AMCS, module, AACK, 0);
         // Disable address filter unit 0
         rf_write_bbc_register_field(BBC_AFC0, module, AFEN0, 0);
-        // Set bandwidth time product
+        // Enable FSK
-        rf_write_bbc_register_field(BBC_FSKC0, module, BT, BT_20);
+        if (phy_current_config.modulation == M_2FSK) {
-        // Disable interleaving
+            rf_write_bbc_register_field(BBC_PC, module, PT, BB_MRFSK);
-        rf_write_bbc_register_field(BBC_FSKC2, module, FECIE, 0);
+            // Set bandwidth time product
-        // Disable receiver override
+            rf_write_bbc_register_field(BBC_FSKC0, module, BT, BT_20);
-        rf_write_bbc_register_field(BBC_FSKC2, module, RXO, RXO_DIS);
+            // Disable interleaving
-        // Set modulation index
+            rf_write_bbc_register_field(BBC_FSKC2, module, FECIE, 0);
-        if (phy_current_config.modulation_index == MODULATION_INDEX_0_5) {
+            // Disable receiver override
-            rf_write_bbc_register_field(BBC_FSKC0, module, MIDX, MIDX_05);
+            rf_write_bbc_register_field(BBC_FSKC2, module, RXO, RXO_DIS);
-            rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_0);
+            // Set modulation index
-        } else {
+            if (phy_current_config.modulation_index == MODULATION_INDEX_0_5) {
-            rf_write_bbc_register_field(BBC_FSKC0, module, MIDX, MIDX_10);
+                rf_write_bbc_register_field(BBC_FSKC0, module, MIDX, MIDX_05);
-            rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_4);
+                rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_0);
+            } else {
+                rf_write_bbc_register_field(BBC_FSKC0, module, MIDX, MIDX_10);
+                rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_4);
+            }
+            // Set Gain control settings
+            rf_write_rf_register_field(RF_AGCC, module, AVGS, AVGS_8_SAMPLES);
+            rf_write_rf_register_field(RF_AGCS, module, TGT, TGT_1);
+            // Set symbol rate and related configurations
+            rf_set_fsk_symbol_rate_configuration(phy_current_config.datarate, module);
+            // Set preamble length
+            uint8_t preamble_len = 24;
+            if (phy_current_config.datarate < 150000) {
+                preamble_len = 8;
+            } else if (phy_current_config.datarate < 300000) {
+                preamble_len = 12;
+            }
+            rf_write_bbc_register(BBC_FSKPLL, module, preamble_len);
+            // Set preamble detector threshold
+            rf_write_bbc_register_field(BBC_FSKC3, module, PDT, PDT_6);
+        } else if (phy_current_config.modulation == M_OFDM) {
+            rf_write_bbc_register_field(BBC_PC, module, PT, BB_MROFDM);
+            // Set TX scrambler seed
+            rf_write_bbc_register_field(BBC_OFDMC, module, SSTX, SSTX_0);
+            // Set RX scrambler seed
+            rf_write_bbc_register_field(BBC_OFDMC, module, SSRX, SSRX_0);
+            // Set phyOFDMInterleaving
+            rf_write_bbc_register_field(BBC_OFDMC, module, POI, 0);
+            // Set low frequency offset bit
+            rf_write_bbc_register_field(BBC_OFDMC, module, LFO, 0);
+            // Configure using bandwidth option
+            rf_configure_by_ofdm_bandwidth_option(4, 300000, module);
+            // Set Gain control settings
+            rf_write_rf_register_field(RF_AGCC, module, AVGS, AVGS_8_SAMPLES);
+            rf_write_rf_register_field(RF_AGCC, module, AGCI, 0);
+            rf_write_rf_register_field(RF_AGCS, module, TGT, TGT_3);
         }
-        // Set Gain control settings
-        rf_write_rf_register_field(RF_AGCC, module, AVGS, AVGS_8_SAMPLES);
-        rf_write_rf_register_field(RF_AGCS, module, TGT, TGT_1);
-        // Set symbol rate and related configurations
-        rf_set_fsk_symbol_rate_configuration(phy_current_config.datarate, module);
-        // Set preamble length
-        uint8_t preamble_len = 24;
-        if (phy_current_config.datarate < 150000) {
-            preamble_len = 8;
-        } else if (phy_current_config.datarate < 300000) {
-            preamble_len = 12;
-        }
-        rf_write_bbc_register(BBC_FSKPLL, module, preamble_len);
-        rf_write_bbc_register_field(BBC_FSKC3, module, PDT, PDT_6);
     }
+    if (se2435_pa_pins) {
+        // Wakeup SE2435L
+        se2435_pa_pins->CSD = 1;
+        // Antenna port selection: (0 - port 1, 1 - port 2)
+        se2435_pa_pins->ANT_SEL = 0;
+        // Enable external front end with configuration 3
+        rf_write_rf_register_field(RF_PADFE, module, PADFE, RF_FEMODE3);
+        // Output power at 900MHz: 0 dBm with FSK/QPSK, less than -5 dBm with OFDM
+        rf_write_rf_register_field(RF_PAC, module, TXPWR, TXPWR_11);
+    }
+    // Enable analog voltage regulator
+    rf_write_rf_register_field(RF_AUXS, module, AVEN, AVEN);
     // Disable filtering FCS
     rf_write_bbc_register_field(BBC_PC, module, FCSFE, 0);
     // Set channel spacing
@@ -488,9 +526,10 @@ static int8_t rf_start_csma_ca(uint8_t *data_ptr, uint16_t data_length, uint8_t
         tx_sequence = *(data_ptr + 2);
     }
     rf_write_tx_buffer(data_ptr, data_length, rf_module);
-    if (phy_current_config.modulation == M_OQPSK) {
+    // Add CRC bytes
+    if (mac_mode == IEEE_802_15_4_2011) {
         data_length += 2;
-    } else if (phy_current_config.modulation == M_2FSK) {
+    } else {
         data_length += 4;
     }
     rf_write_tx_packet_length(data_length, rf_module);
@@ -614,9 +653,10 @@ static void rf_handle_rx_done(void)
                 rf_handle_ack(rx_buffer[2], rx_buffer[0] & MAC_DATA_PENDING);
             } else {
                 int8_t rssi = (int8_t) rf_read_rf_register(RF_EDV, rf_module);
-                if (phy_current_config.modulation == M_OQPSK) {
+                // Cut CRC bytes
+                if (mac_mode == IEEE_802_15_4_2011) {
                     cur_rx_packet_len -= 2;
-                } else if (phy_current_config.modulation == M_2FSK) {
+                } else {
                     cur_rx_packet_len -= 4;
                 }
                 device_driver.phy_rx_cb(rx_buffer, cur_rx_packet_len, 0xf0, rssi, rf_radio_driver_id);
@@ -1055,6 +1095,75 @@ static int rf_set_fsk_symbol_rate_configuration(uint32_t symbol_rate, rf_modules
     return 0;
 }
 
+static int rf_configure_by_ofdm_bandwidth_option(uint8_t option, uint32_t data_rate, rf_modules_e module)
+{
+    if (!option || option > 4) {
+        return -1;
+    }
+    uint32_t datarate_tmp = 100000 >> (option - 1);
+
+    // Set modulation and coding scheme
+    if (data_rate == datarate_tmp) {
+        rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_0);
+    } else if (data_rate == datarate_tmp * 2) {
+        rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_1);
+    } else if (data_rate == datarate_tmp * 4) {
+        rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_2);
+    } else if (data_rate == datarate_tmp * 8) {
+        rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_3);
+    } else if (data_rate == datarate_tmp * 12) {
+        rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_4);
+    } else if (data_rate == datarate_tmp * 16) {
+        rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_5);
+    } else if (data_rate == datarate_tmp * 24) {
+        rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_6);
+    } else {
+        return -1;
+    }
+    if (option == 1) {
+        rf_write_bbc_register_field(BBC_OFDMC, module, OPT, OPT_1);
+        rf_write_rf_register_field(RF_TXDFE, module, SR, SR_3);
+        rf_write_rf_register_field(RF_RXDFE, module, SR, SR_3);
+        rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_4);
+        rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_4);
+        rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC800KHZ);
+        rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW1250KHZ_IF2000KHZ);
+        rf_write_rf_register_field(RF_RXBWC, module, IFS, IFS);
+        rf_write_bbc_register_field(BBC_OFDMSW, module, OFDM_PDT, OFDM_PDT_5);
+    } else if (option == 2) {
+        rf_write_bbc_register_field(BBC_OFDMC, module, OPT, OPT_2);
+        rf_write_rf_register_field(RF_TXDFE, module, SR, SR_3);
+        rf_write_rf_register_field(RF_RXDFE, module, SR, SR_3);
+        rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_3);
+        rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_2);
+        rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC500KHZ);
+        rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW800KHZ_IF1000KHZ);
+        rf_write_rf_register_field(RF_RXBWC, module, IFS, IFS);
+        rf_write_bbc_register_field(BBC_OFDMSW, module, OFDM_PDT, OFDM_PDT_5);
+    } else if (option == 3) {
+        rf_write_bbc_register_field(BBC_OFDMC, module, OPT, OPT_3);
+        rf_write_rf_register_field(RF_TXDFE, module, SR, SR_6);
+        rf_write_rf_register_field(RF_RXDFE, module, SR, SR_6);
+        rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_3);
+        rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_2);
+        rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC250KHZ);
+        rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW400KHZ_IF500KHZ);
+        rf_write_rf_register_field(RF_RXBWC, module, IFS, 0);
+        rf_write_bbc_register_field(BBC_OFDMSW, module, OFDM_PDT, OFDM_PDT_4);
+    } else if (option == 4) {
+        rf_write_bbc_register_field(BBC_OFDMC, module, OPT, OPT_4);
+        rf_write_rf_register_field(RF_TXDFE, module, SR, SR_6);
+        rf_write_rf_register_field(RF_RXDFE, module, SR, SR_6);
+        rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_2);
+        rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_1);
+        rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC160KHZ);
+        rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW250KHZ_IF250KHZ);
+        rf_write_rf_register_field(RF_RXBWC, module, IFS, 1);
+        rf_write_bbc_register_field(BBC_OFDMSW, module, OFDM_PDT, OFDM_PDT_3);
+    }
+    return 0;
+}
+
 static void rf_conf_set_cca_threshold(uint8_t percent)
 {
     uint8_t step = (MAX_CCA_THRESHOLD - MIN_CCA_THRESHOLD);
@@ -1094,10 +1203,28 @@ int RFBits::init_215_driver(RFBits *_rf, TestPins *_test_pins, const uint8_t mac
     test_pins = _test_pins;
     irq_thread_215.start(mbed::callback(this, &RFBits::rf_irq_task));
     rf->spi.frequency(25000000);
+    /* Atmel AT86RF215 Device Family datasheet:
+     * Errata #9: RF215M device has a wrong part number
+     * Description:
+     * The RF215M device part number is 0x34 instead of 0x36 (register RF_PN.PN).
+     */
+#if !defined(HAVE_AT86RF215M)
     *rf_part_num = rf_read_common_register(RF_PN);
+#else
+    *rf_part_num = PART_AT86RF215M;
+    // AT86RF215M is Sub-GHz only transceiver. Change default settings.
+    rf_module = RF_09;
+    mac_mode = IEEE_802_15_4G_2012;
+#endif
     rf_version_num = rf_read_common_register(RF_VN);
     tr_info("RF version number: %x", rf_version_num);
     return rf_device_register(mac);
 }
 
+int RFBits::init_se2435_pa(Se2435Pins *_se2435_pa_pins)
+{
+    se2435_pa_pins = _se2435_pa_pins;
+    return 0;
+}
+
 #endif // MBED_CONF_NANOSTACK_CONFIGURATION && DEVICE_SPI && DEVICE_INTERRUPTIN && defined(MBED_CONF_RTOS_PRESENT)

components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp

@@ -275,8 +275,15 @@ TestPins::TestPins(PinName test_pin_1, PinName test_pin_2, PinName test_pin_3, P
 {
 }
 
+Se2435Pins::Se2435Pins(PinName csd_pin, PinName ant_sel_pin)
+    :   CSD(csd_pin),
+        ANT_SEL(ant_sel_pin)
+{
+}
+
 static RFBits *rf;
 static TestPins *test_pins;
+static Se2435Pins *se2435_pa_pins;
 static uint8_t rf_part_num = 0;
 /*TODO: RSSI Base value setting*/
 static int8_t rf_rssi_base_val = -91;
@@ -2168,14 +2175,21 @@ static uint8_t rf_scale_lqi(int8_t rssi)
 NanostackRfPhyAtmel::NanostackRfPhyAtmel(PinName spi_mosi, PinName spi_miso,
                                          PinName spi_sclk, PinName spi_cs,  PinName spi_rst, PinName spi_slp, PinName spi_irq,
                                          PinName i2c_sda, PinName i2c_scl)
-    : _mac(i2c_sda, i2c_scl), _mac_addr(), _rf(NULL), _test_pins(NULL), _mac_set(false),
+    :
-      _spi_mosi(spi_mosi), _spi_miso(spi_miso), _spi_sclk(spi_sclk),
+#if !defined(DISABLE_AT24MAC)
-      _spi_cs(spi_cs), _spi_rst(spi_rst), _spi_slp(spi_slp), _spi_irq(spi_irq)
+    _mac(i2c_sda, i2c_scl),
+#endif
+    _mac_addr(), _rf(NULL), _test_pins(NULL), _se2435_pa_pins(NULL), _mac_set(false),
+    _spi_mosi(spi_mosi), _spi_miso(spi_miso), _spi_sclk(spi_sclk),
+    _spi_cs(spi_cs), _spi_rst(spi_rst), _spi_slp(spi_slp), _spi_irq(spi_irq)
 {
     _rf = new RFBits(_spi_mosi, _spi_miso, _spi_sclk, _spi_cs, _spi_rst, _spi_slp, _spi_irq);
 #ifdef TEST_GPIOS_ENABLED
     _test_pins = new TestPins(TEST_PIN_TX, TEST_PIN_RX, TEST_PIN_CSMA, TEST_PIN_SPARE_1, TEST_PIN_SPARE_2);
 #endif
+#ifdef SE2435L_PA
+    _se2435_pa_pins = new Se2435Pins(SE2435L_CSD, SE2435L_ANT_SEL);
+#endif
 }
 
 NanostackRfPhyAtmel::~NanostackRfPhyAtmel()
@@ -2200,19 +2214,29 @@ int8_t NanostackRfPhyAtmel::rf_register()
     // Read the mac address if it hasn't been set by a user
     rf = _rf;
     test_pins = _test_pins;
+    se2435_pa_pins = _se2435_pa_pins;
     if (!_mac_set) {
+// Unless AT24MAC is available, using randomly generated MAC address
+#if !defined(DISABLE_AT24MAC)
         int ret = _mac.read_eui64((void *)_mac_addr);
         if (ret < 0) {
             rf = NULL;
             rf_if_unlock();
             return -1;
         }
+#else
+        randLIB_seed_random();
+        randLIB_get_n_bytes_random(_mac_addr, 8);
+        _mac_addr[0] |= 2; //Set Local Bit
+        _mac_addr[0] &= ~1; //Clear multicast bit
+#endif
     }
     /*Reset RF module*/
     rf_if_reset_radio();
     rf_part_num = rf_if_read_part_num();
     int8_t radio_id = -1;
     if (rf_part_num != PART_AT86RF231 && rf_part_num != PART_AT86RF233 && rf_part_num != PART_AT86RF212) {
+        rf->init_se2435_pa(_se2435_pa_pins);
         // Register RF type 215. Jumps to AT86RF215 driver.
         radio_id = rf->init_215_driver(_rf, _test_pins, _mac_addr, &rf_part_num);
     } else {

components/802.15.4_RF/atmel-rf-driver/source/rfbits.h

@@ -51,6 +51,7 @@ public:
     Timeout cca_timer;
     Timer tx_timer;
     int init_215_driver(RFBits *_rf, TestPins *_test_pins, const uint8_t mac[8], uint8_t *rf_part_num);
+    int init_se2435_pa(Se2435Pins *_se2435_pa_pins);
 #ifdef MBED_CONF_RTOS_PRESENT
     Thread irq_thread;
     Thread irq_thread_215;
@@ -70,4 +71,11 @@ public:
     DigitalOut TEST5;
 };
 
+class Se2435Pins {
+public:
+    Se2435Pins(PinName csd_pin, PinName ant_sel_pin);
+    DigitalOut CSD;
+    DigitalOut ANT_SEL;
+};
+
 #endif /* RFBITS_H_ */