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K82F, KL82Z: Update the QSPI SDK driver to the latest version 

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
pull/8637/head
Mahesh Mahadevan 2018-10-17 12:22:38 -05:00 committed by Cruz Monrreal II
parent 41b069860c
commit 04949045ea
4 changed files with 318 additions and 72 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_qspi.c
View File

@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@ -12,10 +15,11 @@
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@ -30,6 +34,12 @@
#include "fsl_qspi.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.qspi"
#endif
/*******************************************************************************
* Definitations
******************************************************************************/
@ -40,17 +50,11 @@ enum _qspi_transfer_state
kQSPI_TxError /*!< Transfer error occured. */
};
#define QSPI_AHB_BUFFER_REG(base, index) (*((uint32_t *)&(base->BUF0CR) + index))
#define QSPI_AHB_BUFFER_REG(base, index) (((volatile uint32_t *)&((base)->BUF0CR))[(index)])
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get the instance number for QSPI.
*
* @param base QSPI base pointer.
*/
uint32_t QSPI_GetInstance(QuadSPI_Type *base);
/*******************************************************************************
* Variables
@ -70,7 +74,7 @@ uint32_t QSPI_GetInstance(QuadSPI_Type *base)
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < FSL_FEATURE_SOC_QuadSPI_COUNT; instance++)
for (instance = 0; instance < ARRAY_SIZE(s_qspiBases); instance++)
{
if (s_qspiBases[instance] == base)
{
@ -78,7 +82,7 @@ uint32_t QSPI_GetInstance(QuadSPI_Type *base)
}
}
assert(instance < FSL_FEATURE_SOC_QuadSPI_COUNT);
assert(instance < ARRAY_SIZE(s_qspiBases));
return instance;
}
@ -102,12 +106,21 @@ void QSPI_Init(QuadSPI_Type *base, qspi_config_t *config, uint32_t srcClock_Hz)
/* Configure QSPI */
QSPI_Enable(base, false);
#if !defined (FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL) || (!FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL)
/* Set qspi clock source */
base->SOCCR = config->clockSource;
/* Set the divider of QSPI clock */
base->MCR &= ~QuadSPI_MCR_SCLKCFG_MASK;
base->MCR |= QuadSPI_MCR_SCLKCFG(srcClock_Hz / config->baudRate - 1U);
if (srcClock_Hz % config->baudRate) {
/* In case we cannot get the exact baudrate, get the closest lower value */
base->MCR |= QuadSPI_MCR_SCLKCFG(srcClock_Hz / config->baudRate);
} else {
base->MCR |= QuadSPI_MCR_SCLKCFG(srcClock_Hz / config->baudRate - 1U);
}
#endif /* FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL */
/* Set AHB buffer size and buffer master */
for (i = 0; i < FSL_FEATURE_QSPI_AHB_BUFFER_COUNT; i++)
@ -127,8 +140,11 @@ void QSPI_Init(QuadSPI_Type *base, qspi_config_t *config, uint32_t srcClock_Hz)
/* Set watermark */
base->RBCT &= ~QuadSPI_RBCT_WMRK_MASK;
base->RBCT |= QuadSPI_RBCT_WMRK(config->rxWatermark - 1);
#if !defined (FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
base->TBCT &= ~QuadSPI_TBCT_WMRK_MASK;
base->TBCT |= QuadSPI_TBCT_WMRK(config->txWatermark - 1);
#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
/* Enable QSPI module */
if (config->enableQspi)
@ -178,9 +194,11 @@ void QSPI_SetFlashConfig(QuadSPI_Type *base, qspi_flash_config_t *config)
base->SFB2AD = address;
#endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */
#if !defined (FSL_FEATURE_QSPI_HAS_NO_SFACR) || (!FSL_FEATURE_QSPI_HAS_NO_SFACR)
/* Set Word Addressable feature */
val = QuadSPI_SFACR_WA(config->enableWordAddress) | QuadSPI_SFACR_CAS(config->cloumnspace);
base->SFACR = val;
#endif /* FSL_FEATURE_QSPI_HAS_NO_SFACR */
/* Config look up table */
base->LUTKEY = 0x5AF05AF0U;
@ -192,9 +210,13 @@ void QSPI_SetFlashConfig(QuadSPI_Type *base, qspi_flash_config_t *config)
base->LUTKEY = 0x5AF05AF0U;
base->LCKCR = 0x1U;
#if !defined (FSL_FEATURE_QSPI_HAS_NO_TDH) || (!FSL_FEATURE_QSPI_HAS_NO_TDH)
/* Config flash timing */
val = QuadSPI_FLSHCR_TCSS(config->CSHoldTime) | QuadSPI_FLSHCR_TDH(config->dataHoldTime) |
QuadSPI_FLSHCR_TCSH(config->CSSetupTime);
#else
val = QuadSPI_FLSHCR_TCSS(config->CSHoldTime) | QuadSPI_FLSHCR_TCSH(config->CSSetupTime);
#endif /* FSL_FEATURE_QSPI_HAS_NO_TDH */
base->FLSHCR = val;
/* Set flash endianness */
@ -207,7 +229,7 @@ void QSPI_SetFlashConfig(QuadSPI_Type *base, qspi_flash_config_t *config)
void QSPI_SoftwareReset(QuadSPI_Type *base)
{
volatile uint32_t i = 0;
uint32_t i = 0;
/* Reset AHB domain and buffer domian */
base->MCR |= (QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK);

114
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_qspi.h
View File

@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@ -12,10 +15,11 @@
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@ -44,10 +48,43 @@
/*! @name Driver version */
/*@{*/
/*! @brief I2C driver version 2.0.1. */
#define FSL_QSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*! @brief QSPI driver version 2.0.2. */
#define FSL_QSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*@}*/
/*! @brief Macro functions for LUT table */
#define QSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(QuadSPI_LUT_INSTR0(cmd0) | QuadSPI_LUT_PAD0(pad0) | QuadSPI_LUT_OPRND0(op0) | QuadSPI_LUT_INSTR1(cmd1) | \
QuadSPI_LUT_PAD1(pad1) | QuadSPI_LUT_OPRND1(op1))
/*! @brief Macro for QSPI LUT command */
#define QSPI_CMD (0x1U)
#define QSPI_ADDR (0x2U)
#define QSPI_DUMMY (0x3U)
#define QSPI_MODE (0x4U)
#define QSPI_MODE2 (0x5U)
#define QSPI_MODE4 (0x6U)
#define QSPI_READ (0x7U)
#define QSPI_WRITE (0x8U)
#define QSPI_JMP_ON_CS (0x9U)
#define QSPI_ADDR_DDR (0xAU)
#define QSPI_MODE_DDR (0xBU)
#define QSPI_MODE2_DDR (0xCU)
#define QSPI_MODE4_DDR (0xDU)
#define QSPI_READ_DDR (0xEU)
#define QSPI_WRITE_DDR (0xFU)
#define QSPI_DATA_LEARN (0x10U)
#define QSPI_CMD_DDR (0x11U)
#define QSPI_CADDR (0x12U)
#define QSPI_CADDR_DDR (0x13U)
#define QSPI_STOP (0x0U)
/*! @brief Macro for QSPI PAD */
#define QSPI_PAD_1 (0x0U)
#define QSPI_PAD_2 (0x1U)
#define QSPI_PAD_4 (0x2U)
#define QSPI_PAD_8 (0x3U)
/*! @brief Status structure of QSPI.*/
enum _status_t
{
@ -91,15 +128,19 @@ typedef enum _qspi_endianness
/*! @brief QSPI error flags */
enum _qspi_error_flags
{
kQSPI_DataLearningFail = QuadSPI_FR_DLPFF_MASK, /*!< Data learning pattern failure flag */
kQSPI_DataLearningFail = (int)QuadSPI_FR_DLPFF_MASK, /*!< Data learning pattern failure flag */
kQSPI_TxBufferFill = QuadSPI_FR_TBFF_MASK, /*!< Tx buffer fill flag */
kQSPI_TxBufferUnderrun = QuadSPI_FR_TBUF_MASK, /*!< Tx buffer underrun flag */
kQSPI_IllegalInstruction = QuadSPI_FR_ILLINE_MASK, /*!< Illegal instruction error flag */
kQSPI_RxBufferOverflow = QuadSPI_FR_RBOF_MASK, /*!< Rx buffer overflow flag */
kQSPI_RxBufferDrain = QuadSPI_FR_RBDF_MASK, /*!< Rx buffer drain flag */
kQSPI_AHBSequenceError = QuadSPI_FR_ABSEF_MASK, /*!< AHB sequence error flag */
#if !defined(FSL_FEATURE_QSPI_HAS_NO_AITEF) || (!FSL_FEATURE_QSPI_HAS_NO_AITEF)
kQSPI_AHBIllegalTransaction = QuadSPI_FR_AITEF_MASK, /*!< AHB illegal transaction error flag */
#endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */
#if !defined(FSL_FEATURE_QSPI_HAS_NO_AIBSEF) || (!FSL_FEATURE_QSPI_HAS_NO_AIBSEF)
kQSPI_AHBIllegalBurstSize = QuadSPI_FR_AIBSEF_MASK, /*!< AHB illegal burst error flag */
#endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */
kQSPI_AHBBufferOverflow = QuadSPI_FR_ABOF_MASK, /*!< AHB buffer overflow flag */
#if defined(FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) && (FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR)
kQSPI_IPCommandUsageError = QuadSPI_FR_IUEF_MASK, /*!< IP command usage error flag */
@ -108,16 +149,18 @@ enum _qspi_error_flags
kQSPI_IPCommandTriggerDuringIPAccess = QuadSPI_FR_IPIEF_MASK, /*!< IP command trigger cannot be executed */
kQSPI_IPCommandTriggerDuringAHBGrant = QuadSPI_FR_IPGEF_MASK, /*!< IP command trigger during AHB grant error */
kQSPI_IPCommandTransactionFinished = QuadSPI_FR_TFF_MASK, /*!< IP command transaction finished flag */
kQSPI_FlagAll = 0x8C83F8D1U /*!< All error flag */
kQSPI_FlagAll = (int)0x8C83F8D1U /*!< All error flag */
};
/*! @brief QSPI state bit */
enum _qspi_flags
{
kQSPI_DataLearningSamplePoint = QuadSPI_SR_DLPSMP_MASK, /*!< Data learning sample point */
kQSPI_DataLearningSamplePoint = (int)QuadSPI_SR_DLPSMP_MASK, /*!< Data learning sample point */
kQSPI_TxBufferFull = QuadSPI_SR_TXFULL_MASK, /*!< Tx buffer full flag */
#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
kQSPI_TxDMA = QuadSPI_SR_TXDMA_MASK, /*!< Tx DMA is requested or running */
kQSPI_TxWatermark = QuadSPI_SR_TXWA_MASK, /*!< Tx buffer watermark available */
#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
kQSPI_TxBufferEnoughData = QuadSPI_SR_TXEDA_MASK, /*!< Tx buffer enough data available */
kQSPI_RxDMA = QuadSPI_SR_RXDMA_MASK, /*!< Rx DMA is requesting or running */
kQSPI_RxBufferFull = QuadSPI_SR_RXFULL_MASK, /*!< Rx buffer full */
@ -135,14 +178,14 @@ enum _qspi_flags
kQSPI_AHBAccess = QuadSPI_SR_AHB_ACC_MASK, /*!< AHB access */
kQSPI_IPAccess = QuadSPI_SR_IP_ACC_MASK, /*!< IP access */
kQSPI_Busy = QuadSPI_SR_BUSY_MASK, /*!< Module busy */
kQSPI_StateAll = 0xEF897FE7U /*!< All flags */
kQSPI_StateAll = (int)0xEF897FE7U /*!< All flags */
};
/*! @brief QSPI interrupt enable */
enum _qspi_interrupt_enable
{
kQSPI_DataLearningFailInterruptEnable =
QuadSPI_RSER_DLPFIE_MASK, /*!< Data learning pattern failure interrupt enable */
(int)QuadSPI_RSER_DLPFIE_MASK, /*!< Data learning pattern failure interrupt enable */
kQSPI_TxBufferFillInterruptEnable = QuadSPI_RSER_TBFIE_MASK, /*!< Tx buffer fill interrupt enable */
kQSPI_TxBufferUnderrunInterruptEnable = QuadSPI_RSER_TBUIE_MASK, /*!< Tx buffer underrun interrupt enable */
kQSPI_IllegalInstructionInterruptEnable =
@ -150,10 +193,14 @@ enum _qspi_interrupt_enable
kQSPI_RxBufferOverflowInterruptEnable = QuadSPI_RSER_RBOIE_MASK, /*!< Rx buffer overflow interrupt enable */
kQSPI_RxBufferDrainInterruptEnable = QuadSPI_RSER_RBDIE_MASK, /*!< Rx buffer drain interrupt enable */
kQSPI_AHBSequenceErrorInterruptEnable = QuadSPI_RSER_ABSEIE_MASK, /*!< AHB sequence error interrupt enable */
#if !defined(FSL_FEATURE_QSPI_HAS_NO_AITEF) || (!FSL_FEATURE_QSPI_HAS_NO_AITEF)
kQSPI_AHBIllegalTransactionInterruptEnable =
QuadSPI_RSER_AITIE_MASK, /*!< AHB illegal transaction error interrupt enable */
#endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */
#if !defined(FSL_FEATURE_QSPI_HAS_NO_AIBSEF) || (!FSL_FEATURE_QSPI_HAS_NO_AIBSEF)
kQSPI_AHBIllegalBurstSizeInterruptEnable =
QuadSPI_RSER_AIBSIE_MASK, /*!< AHB illegal burst error interrupt enable */
#endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */
kQSPI_AHBBufferOverflowInterruptEnable = QuadSPI_RSER_ABOIE_MASK, /*!< AHB buffer overflow interrupt enable */
#if defined(FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) && (FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR)
kQSPI_IPCommandUsageErrorInterruptEnable = QuadSPI_RSER_IUEIE_MASK, /*!< IP command usage error interrupt enable */
@ -166,15 +213,21 @@ enum _qspi_interrupt_enable
QuadSPI_RSER_IPGEIE_MASK, /*!< IP command trigger during AHB grant error */
kQSPI_IPCommandTransactionFinishedInterruptEnable =
QuadSPI_RSER_TFIE_MASK, /*!< IP command transaction finished interrupt enable */
kQSPI_AllInterruptEnable = 0x8C83F8D1U /*!< All error interrupt enable */
kQSPI_AllInterruptEnable = (int)0x8C83F8D1U /*!< All error interrupt enable */
};
/*! @brief QSPI DMA request flag */
enum _qspi_dma_enable
{
#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
kQSPI_TxBufferFillDMAEnable = QuadSPI_RSER_TBFDE_MASK, /*!< Tx buffer fill DMA */
#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
kQSPI_RxBufferDrainDMAEnable = QuadSPI_RSER_RBDDE_MASK, /*!< Rx buffer drain DMA */
#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
kQSPI_AllDDMAEnable = QuadSPI_RSER_TBFDE_MASK | QuadSPI_RSER_RBDDE_MASK /*!< All DMA source */
#else
kQSPI_AllDDMAEnable = QuadSPI_RSER_RBDDE_MASK /* All DMA source */
#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
};
/*! @brief Phrase shift number for DQS mode. */
@ -229,7 +282,9 @@ typedef struct _qspi_flash_config
uint32_t flashB2Size; /*!< Flash B2 size */
#endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */
uint32_t lookuptable[FSL_FEATURE_QSPI_LUT_DEPTH]; /*!< Flash command in LUT */
#if !defined(FSL_FEATURE_QSPI_HAS_NO_TDH) || (!FSL_FEATURE_QSPI_HAS_NO_TDH)
uint32_t dataHoldTime; /*!< Data line hold time. */
#endif /* FSL_FEATURE_QSPI_HAS_NO_TDH */
uint32_t CSHoldTime; /*!< CS line hold time */
uint32_t CSSetupTime; /*!< CS line setup time*/
uint32_t cloumnspace; /*!< Column space size */
@ -257,6 +312,13 @@ extern "C" {
* @{
*/
/*!
* @brief Get the instance number for QSPI.
*
* @param base QSPI base pointer.
*/
uint32_t QSPI_GetInstance(QuadSPI_Type *base);
/*!
* @brief Initializes the QSPI module and internal state.
*
@ -462,9 +524,9 @@ static inline void QSPI_SetIPCommandAddress(QuadSPI_Type *base, uint32_t addr)
* @param base Pointer to QuadSPI Type.
* @param size IP command size.
*/
static inline void QSPI_SetIPCommandSize(QuadSPI_Type *base, uint32_t size)
static inline void QSPI_SetIPCommandSize(QuadSPI_Type *base, uint16_t size)
{
base->IPCR = ((base->IPCR & (~QuadSPI_IPCR_IDATSZ_MASK)) | QuadSPI_IPCR_IDATSZ(size));
base->IPCR_ACCESSBIT.IDATZ = size;
}
/*! @brief Executes IP commands located in LUT table.
@ -546,6 +608,24 @@ static inline void QSPI_ClearCommandSequence(QuadSPI_Type *base, qspi_command_se
base->SPTRCLR = seq;
}
/*!
* @brief Enable or disable DDR mode.
*
* @param base QSPI base pointer
* @param eanble True means enable DDR mode, false means disable DDR mode.
*/
static inline void QSPI_EnableDDRMode(QuadSPI_Type *base, bool enable)
{
if (enable)
{
base->MCR |= QuadSPI_MCR_DDR_EN_MASK;
}
else
{
base->MCR &= ~QuadSPI_MCR_DDR_EN_MASK;
}
}
/*!@ brief Set the RX buffer readout area.
*
* This function can set the RX buffer readout, from AHB bus or IP Bus.
@ -576,7 +656,10 @@ static inline void QSPI_WriteData(QuadSPI_Type *base, uint32_t data)
/*!
* @brief Receives a buffer of data bytes using a blocking method.
* @note This function blocks via polling until all bytes have been sent.
* @note This function blocks via polling until all bytes have been sent. Users shall notice that
* this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers.
* For flash contents read, please use AHB bus read, this is much more efficiency.
*
* @param base QSPI base pointer
* @param buffer The data bytes to send
* @param size The number of data bytes to receive
@ -616,7 +699,10 @@ static inline void QSPI_TransferSendBlocking(QuadSPI_Type *base, qspi_transfer_t
* @brief Reads data from the QSPI receive buffer in polling way.
*
* This function reads continuous data from the QSPI receive buffer/FIFO. This function is a blocking
* function and can return only when finished. This function uses polling methods.
* function and can return only when finished. This function uses polling methods. Users shall notice that
* this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers.
* For flash contents read, please use AHB bus read, this is much more efficiency.
*
* @param base Pointer to QuadSPI Type.
* @param xfer QSPI transfer structure.
*/

79
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_qspi.c
View File

@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@ -12,10 +15,11 @@
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@ -30,6 +34,12 @@
#include "fsl_qspi.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.qspi"
#endif
/*******************************************************************************
* Definitations
******************************************************************************/
@ -40,25 +50,21 @@ enum _qspi_transfer_state
kQSPI_TxError /*!< Transfer error occured. */
};
#define QSPI_AHB_BUFFER_REG(base, index) (*((uint32_t *)&(base->BUF0CR) + index))
#define QSPI_AHB_BUFFER_REG(base, index) (((volatile uint32_t *)&((base)->BUF0CR))[(index)])
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get the instance number for QSPI.
*
* @param base QSPI base pointer.
*/
uint32_t QSPI_GetInstance(QuadSPI_Type *base);
/*******************************************************************************
* Variables
******************************************************************************/
/* Base pointer array */
static QuadSPI_Type *const s_qspiBases[] = QuadSPI_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Clock name array */
static const clock_ip_name_t s_qspiClock[] = QSPI_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Code
@ -68,7 +74,7 @@ uint32_t QSPI_GetInstance(QuadSPI_Type *base)
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < FSL_FEATURE_SOC_QuadSPI_COUNT; instance++)
for (instance = 0; instance < ARRAY_SIZE(s_qspiBases); instance++)
{
if (s_qspiBases[instance] == base)
{
@ -76,7 +82,7 @@ uint32_t QSPI_GetInstance(QuadSPI_Type *base)
}
}
assert(instance < FSL_FEATURE_SOC_QuadSPI_COUNT);
assert(instance < ARRAY_SIZE(s_qspiBases));
return instance;
}
@ -86,8 +92,10 @@ void QSPI_Init(QuadSPI_Type *base, qspi_config_t *config, uint32_t srcClock_Hz)
uint32_t i = 0;
uint32_t val = 0;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable QSPI clock */
CLOCK_EnableClock(s_qspiClock[QSPI_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Do software reset to QSPI module */
QSPI_SoftwareReset(base);
@ -98,12 +106,21 @@ void QSPI_Init(QuadSPI_Type *base, qspi_config_t *config, uint32_t srcClock_Hz)
/* Configure QSPI */
QSPI_Enable(base, false);
#if !defined (FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL) || (!FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL)
/* Set qspi clock source */
base->SOCCR = config->clockSource;
/* Set the divider of QSPI clock */
base->MCR &= ~QuadSPI_MCR_SCLKCFG_MASK;
base->MCR |= QuadSPI_MCR_SCLKCFG(srcClock_Hz / config->baudRate - 1U);
if (srcClock_Hz % config->baudRate) {
/* In case we cannot get the exact baudrate, get the closest lower value */
base->MCR |= QuadSPI_MCR_SCLKCFG(srcClock_Hz / config->baudRate);
} else {
base->MCR |= QuadSPI_MCR_SCLKCFG(srcClock_Hz / config->baudRate - 1U);
}
#endif /* FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL */
/* Set AHB buffer size and buffer master */
for (i = 0; i < FSL_FEATURE_QSPI_AHB_BUFFER_COUNT; i++)
@ -123,8 +140,11 @@ void QSPI_Init(QuadSPI_Type *base, qspi_config_t *config, uint32_t srcClock_Hz)
/* Set watermark */
base->RBCT &= ~QuadSPI_RBCT_WMRK_MASK;
base->RBCT |= QuadSPI_RBCT_WMRK(config->rxWatermark - 1);
#if !defined (FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
base->TBCT &= ~QuadSPI_TBCT_WMRK_MASK;
base->TBCT |= QuadSPI_TBCT_WMRK(config->txWatermark - 1);
#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
/* Enable QSPI module */
if (config->enableQspi)
@ -149,7 +169,9 @@ void QSPI_GetDefaultQspiConfig(qspi_config_t *config)
void QSPI_Deinit(QuadSPI_Type *base)
{
QSPI_Enable(base, false);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
CLOCK_DisableClock(s_qspiClock[QSPI_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
void QSPI_SetFlashConfig(QuadSPI_Type *base, qspi_flash_config_t *config)
@ -165,14 +187,18 @@ void QSPI_SetFlashConfig(QuadSPI_Type *base, qspi_flash_config_t *config)
base->SFA1AD = address;
address += config->flashA2Size;
base->SFA2AD = address;
#if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
address += config->flashB1Size;
base->SFB1AD = address;
address += config->flashB2Size;
base->SFB2AD = address;
#endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */
#if !defined (FSL_FEATURE_QSPI_HAS_NO_SFACR) || (!FSL_FEATURE_QSPI_HAS_NO_SFACR)
/* Set Word Addressable feature */
val = QuadSPI_SFACR_WA(config->enableWordAddress) | QuadSPI_SFACR_CAS(config->cloumnspace);
base->SFACR = val;
#endif /* FSL_FEATURE_QSPI_HAS_NO_SFACR */
/* Config look up table */
base->LUTKEY = 0x5AF05AF0U;
@ -184,9 +210,13 @@ void QSPI_SetFlashConfig(QuadSPI_Type *base, qspi_flash_config_t *config)
base->LUTKEY = 0x5AF05AF0U;
base->LCKCR = 0x1U;
#if !defined (FSL_FEATURE_QSPI_HAS_NO_TDH) || (!FSL_FEATURE_QSPI_HAS_NO_TDH)
/* Config flash timing */
val = QuadSPI_FLSHCR_TCSS(config->CSHoldTime) | QuadSPI_FLSHCR_TDH(config->dataHoldTime) |
QuadSPI_FLSHCR_TCSH(config->CSSetupTime);
#else
val = QuadSPI_FLSHCR_TCSS(config->CSHoldTime) | QuadSPI_FLSHCR_TCSH(config->CSSetupTime);
#endif /* FSL_FEATURE_QSPI_HAS_NO_TDH */
base->FLSHCR = val;
/* Set flash endianness */
@ -199,7 +229,7 @@ void QSPI_SetFlashConfig(QuadSPI_Type *base, qspi_flash_config_t *config)
void QSPI_SoftwareReset(QuadSPI_Type *base)
{
volatile uint32_t i = 0;
uint32_t i = 0;
/* Reset AHB domain and buffer domian */
base->MCR |= (QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK);
@ -314,15 +344,27 @@ void QSPI_ReadBlocking(QuadSPI_Type *base, uint32_t *buffer, size_t size)
{
uint32_t i = 0;
uint32_t j = 0;
uint32_t level = 0;
uint32_t temp = 0;
uint32_t level = (base->RBCT & QuadSPI_RBCT_WMRK_MASK) + 1U;
while (i < size / 4)
{
/* Check if there is data */
do
if ((size / 4 - i) < level)
{
level = (base->RBSR & QuadSPI_RBSR_RDBFL_MASK) >> QuadSPI_RBSR_RDBFL_SHIFT;
} while (!level);
do
{
temp = (base->RBSR & QuadSPI_RBSR_RDBFL_MASK) >> QuadSPI_RBSR_RDBFL_SHIFT;
} while (!temp);
}
else
{
while ((QSPI_GetStatusFlags(base) & kQSPI_RxWatermark) == 0U)
{
}
}
level = (level < (size / 4 - i)) ? level : (size / 4 - i);
/* Data from RBDR */
if (base->RBCT & QuadSPI_RBCT_RXBRD_MASK)
@ -341,5 +383,8 @@ void QSPI_ReadBlocking(QuadSPI_Type *base, uint32_t *buffer, size_t size)
}
}
i += level;
/* Clear the Buffer */
QSPI_ClearErrorFlag(base, kQSPI_RxBufferDrain);
}
}

149
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_qspi.h
View File

@ -1,9 +1,12 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@ -12,10 +15,11 @@
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@ -38,17 +42,49 @@
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief I2C driver version 2.0.1. */
#define FSL_QSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*! @brief QSPI driver version 2.0.2. */
#define FSL_QSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*@}*/
/*! @brief Macro functions for LUT table */
#define QSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(QuadSPI_LUT_INSTR0(cmd0) | QuadSPI_LUT_PAD0(pad0) | QuadSPI_LUT_OPRND0(op0) | QuadSPI_LUT_INSTR1(cmd1) | \
QuadSPI_LUT_PAD1(pad1) | QuadSPI_LUT_OPRND1(op1))
/*! @brief Macro for QSPI LUT command */
#define QSPI_CMD (0x1U)
#define QSPI_ADDR (0x2U)
#define QSPI_DUMMY (0x3U)
#define QSPI_MODE (0x4U)
#define QSPI_MODE2 (0x5U)
#define QSPI_MODE4 (0x6U)
#define QSPI_READ (0x7U)
#define QSPI_WRITE (0x8U)
#define QSPI_JMP_ON_CS (0x9U)
#define QSPI_ADDR_DDR (0xAU)
#define QSPI_MODE_DDR (0xBU)
#define QSPI_MODE2_DDR (0xCU)
#define QSPI_MODE4_DDR (0xDU)
#define QSPI_READ_DDR (0xEU)
#define QSPI_WRITE_DDR (0xFU)
#define QSPI_DATA_LEARN (0x10U)
#define QSPI_CMD_DDR (0x11U)
#define QSPI_CADDR (0x12U)
#define QSPI_CADDR_DDR (0x13U)
#define QSPI_STOP (0x0U)
/*! @brief Macro for QSPI PAD */
#define QSPI_PAD_1 (0x0U)
#define QSPI_PAD_2 (0x1U)
#define QSPI_PAD_4 (0x2U)
#define QSPI_PAD_8 (0x3U)
/*! @brief Status structure of QSPI.*/
enum _status_t
{
@ -92,31 +128,39 @@ typedef enum _qspi_endianness
/*! @brief QSPI error flags */
enum _qspi_error_flags
{
kQSPI_DataLearningFail = QuadSPI_FR_DLPFF_MASK, /*!< Data learning pattern failure flag */
kQSPI_TxBufferFill = QuadSPI_FR_TBFF_MASK, /*!< Tx buffer fill flag */
kQSPI_TxBufferUnderrun = QuadSPI_FR_TBUF_MASK, /*!< Tx buffer underrun flag */
kQSPI_IllegalInstruction = QuadSPI_FR_ILLINE_MASK, /*!< Illegal instruction error flag */
kQSPI_RxBufferOverflow = QuadSPI_FR_RBOF_MASK, /*!< Rx buffer overflow flag */
kQSPI_RxBufferDrain = QuadSPI_FR_RBDF_MASK, /*!< Rx buffer drain flag */
kQSPI_AHBSequenceError = QuadSPI_FR_ABSEF_MASK, /*!< AHB sequence error flag */
kQSPI_AHBIllegalTransaction = QuadSPI_FR_AITEF_MASK, /*!< AHB illegal transaction error flag */
kQSPI_AHBIllegalBurstSize = QuadSPI_FR_AIBSEF_MASK, /*!< AHB illegal burst error flag */
kQSPI_AHBBufferOverflow = QuadSPI_FR_ABOF_MASK, /*!< AHB buffer overflow flag */
kQSPI_DataLearningFail = (int)QuadSPI_FR_DLPFF_MASK, /*!< Data learning pattern failure flag */
kQSPI_TxBufferFill = QuadSPI_FR_TBFF_MASK, /*!< Tx buffer fill flag */
kQSPI_TxBufferUnderrun = QuadSPI_FR_TBUF_MASK, /*!< Tx buffer underrun flag */
kQSPI_IllegalInstruction = QuadSPI_FR_ILLINE_MASK, /*!< Illegal instruction error flag */
kQSPI_RxBufferOverflow = QuadSPI_FR_RBOF_MASK, /*!< Rx buffer overflow flag */
kQSPI_RxBufferDrain = QuadSPI_FR_RBDF_MASK, /*!< Rx buffer drain flag */
kQSPI_AHBSequenceError = QuadSPI_FR_ABSEF_MASK, /*!< AHB sequence error flag */
#if !defined(FSL_FEATURE_QSPI_HAS_NO_AITEF) || (!FSL_FEATURE_QSPI_HAS_NO_AITEF)
kQSPI_AHBIllegalTransaction = QuadSPI_FR_AITEF_MASK, /*!< AHB illegal transaction error flag */
#endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */
#if !defined(FSL_FEATURE_QSPI_HAS_NO_AIBSEF) || (!FSL_FEATURE_QSPI_HAS_NO_AIBSEF)
kQSPI_AHBIllegalBurstSize = QuadSPI_FR_AIBSEF_MASK, /*!< AHB illegal burst error flag */
#endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */
kQSPI_AHBBufferOverflow = QuadSPI_FR_ABOF_MASK, /*!< AHB buffer overflow flag */
#if defined(FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) && (FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR)
kQSPI_IPCommandUsageError = QuadSPI_FR_IUEF_MASK, /*!< IP command usage error flag */
#endif /* FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR */
kQSPI_IPCommandTriggerDuringAHBAccess = QuadSPI_FR_IPAEF_MASK, /*!< IP command trigger during AHB access error */
kQSPI_IPCommandTriggerDuringIPAccess = QuadSPI_FR_IPIEF_MASK, /*!< IP command trigger cannot be executed */
kQSPI_IPCommandTriggerDuringAHBGrant = QuadSPI_FR_IPGEF_MASK, /*!< IP command trigger during AHB grant error */
kQSPI_IPCommandTransactionFinished = QuadSPI_FR_TFF_MASK, /*!< IP command transaction finished flag */
kQSPI_FlagAll = 0x8C83F8D1U /*!< All error flag */
kQSPI_FlagAll = (int)0x8C83F8D1U /*!< All error flag */
};
/*! @brief QSPI state bit */
enum _qspi_flags
{
kQSPI_DataLearningSamplePoint = QuadSPI_SR_DLPSMP_MASK, /*!< Data learning sample point */
kQSPI_DataLearningSamplePoint = (int)QuadSPI_SR_DLPSMP_MASK, /*!< Data learning sample point */
kQSPI_TxBufferFull = QuadSPI_SR_TXFULL_MASK, /*!< Tx buffer full flag */
#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
kQSPI_TxDMA = QuadSPI_SR_TXDMA_MASK, /*!< Tx DMA is requested or running */
kQSPI_TxWatermark = QuadSPI_SR_TXWA_MASK, /*!< Tx buffer watermark available */
#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
kQSPI_TxBufferEnoughData = QuadSPI_SR_TXEDA_MASK, /*!< Tx buffer enough data available */
kQSPI_RxDMA = QuadSPI_SR_RXDMA_MASK, /*!< Rx DMA is requesting or running */
kQSPI_RxBufferFull = QuadSPI_SR_RXFULL_MASK, /*!< Rx buffer full */
@ -134,14 +178,14 @@ enum _qspi_flags
kQSPI_AHBAccess = QuadSPI_SR_AHB_ACC_MASK, /*!< AHB access */
kQSPI_IPAccess = QuadSPI_SR_IP_ACC_MASK, /*!< IP access */
kQSPI_Busy = QuadSPI_SR_BUSY_MASK, /*!< Module busy */
kQSPI_StateAll = 0xEF897FE7U /*!< All flags */
kQSPI_StateAll = (int)0xEF897FE7U /*!< All flags */
};
/*! @brief QSPI interrupt enable */
enum _qspi_interrupt_enable
{
kQSPI_DataLearningFailInterruptEnable =
QuadSPI_RSER_DLPFIE_MASK, /*!< Data learning pattern failure interrupt enable */
(int)QuadSPI_RSER_DLPFIE_MASK, /*!< Data learning pattern failure interrupt enable */
kQSPI_TxBufferFillInterruptEnable = QuadSPI_RSER_TBFIE_MASK, /*!< Tx buffer fill interrupt enable */
kQSPI_TxBufferUnderrunInterruptEnable = QuadSPI_RSER_TBUIE_MASK, /*!< Tx buffer underrun interrupt enable */
kQSPI_IllegalInstructionInterruptEnable =
@ -149,12 +193,18 @@ enum _qspi_interrupt_enable
kQSPI_RxBufferOverflowInterruptEnable = QuadSPI_RSER_RBOIE_MASK, /*!< Rx buffer overflow interrupt enable */
kQSPI_RxBufferDrainInterruptEnable = QuadSPI_RSER_RBDIE_MASK, /*!< Rx buffer drain interrupt enable */
kQSPI_AHBSequenceErrorInterruptEnable = QuadSPI_RSER_ABSEIE_MASK, /*!< AHB sequence error interrupt enable */
#if !defined(FSL_FEATURE_QSPI_HAS_NO_AITEF) || (!FSL_FEATURE_QSPI_HAS_NO_AITEF)
kQSPI_AHBIllegalTransactionInterruptEnable =
QuadSPI_RSER_AITIE_MASK, /*!< AHB illegal transaction error interrupt enable */
#endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */
#if !defined(FSL_FEATURE_QSPI_HAS_NO_AIBSEF) || (!FSL_FEATURE_QSPI_HAS_NO_AIBSEF)
kQSPI_AHBIllegalBurstSizeInterruptEnable =
QuadSPI_RSER_AIBSIE_MASK, /*!< AHB illegal burst error interrupt enable */
kQSPI_AHBBufferOverflowInterruptEnable = QuadSPI_RSER_ABOIE_MASK, /*!< AHB buffer overflow interrupt enable */
QuadSPI_RSER_AIBSIE_MASK, /*!< AHB illegal burst error interrupt enable */
#endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */
kQSPI_AHBBufferOverflowInterruptEnable = QuadSPI_RSER_ABOIE_MASK, /*!< AHB buffer overflow interrupt enable */
#if defined(FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) && (FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR)
kQSPI_IPCommandUsageErrorInterruptEnable = QuadSPI_RSER_IUEIE_MASK, /*!< IP command usage error interrupt enable */
#endif /* FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR */
kQSPI_IPCommandTriggerDuringAHBAccessInterruptEnable =
QuadSPI_RSER_IPAEIE_MASK, /*!< IP command trigger during AHB access error */
kQSPI_IPCommandTriggerDuringIPAccessInterruptEnable =
@ -163,15 +213,21 @@ enum _qspi_interrupt_enable
QuadSPI_RSER_IPGEIE_MASK, /*!< IP command trigger during AHB grant error */
kQSPI_IPCommandTransactionFinishedInterruptEnable =
QuadSPI_RSER_TFIE_MASK, /*!< IP command transaction finished interrupt enable */
kQSPI_AllInterruptEnable = 0x8C83F8D1U /*!< All error interrupt enable */
kQSPI_AllInterruptEnable = (int)0x8C83F8D1U /*!< All error interrupt enable */
};
/*! @brief QSPI DMA request flag */
enum _qspi_dma_enable
{
#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
kQSPI_TxBufferFillDMAEnable = QuadSPI_RSER_TBFDE_MASK, /*!< Tx buffer fill DMA */
#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
kQSPI_RxBufferDrainDMAEnable = QuadSPI_RSER_RBDDE_MASK, /*!< Rx buffer drain DMA */
#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
kQSPI_AllDDMAEnable = QuadSPI_RSER_TBFDE_MASK | QuadSPI_RSER_RBDDE_MASK /*!< All DMA source */
#else
kQSPI_AllDDMAEnable = QuadSPI_RSER_RBDDE_MASK /* All DMA source */
#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
};
/*! @brief Phrase shift number for DQS mode. */
@ -219,12 +275,16 @@ typedef struct QspiConfig
/*! @brief External flash configuration items*/
typedef struct _qspi_flash_config
{
uint32_t flashA1Size; /*!< Flash A1 size */
uint32_t flashA2Size; /*!< Flash A2 size */
uint32_t flashA1Size; /*!< Flash A1 size */
uint32_t flashA2Size; /*!< Flash A2 size */
#if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
uint32_t flashB1Size; /*!< Flash B1 size */
uint32_t flashB2Size; /*!< Flash B2 size */
#endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */
uint32_t lookuptable[FSL_FEATURE_QSPI_LUT_DEPTH]; /*!< Flash command in LUT */
#if !defined(FSL_FEATURE_QSPI_HAS_NO_TDH) || (!FSL_FEATURE_QSPI_HAS_NO_TDH)
uint32_t dataHoldTime; /*!< Data line hold time. */
#endif /* FSL_FEATURE_QSPI_HAS_NO_TDH */
uint32_t CSHoldTime; /*!< CS line hold time */
uint32_t CSSetupTime; /*!< CS line setup time*/
uint32_t cloumnspace; /*!< Column space size */
@ -252,6 +312,13 @@ extern "C" {
* @{
*/
/*!
* @brief Get the instance number for QSPI.
*
* @param base QSPI base pointer.
*/
uint32_t QSPI_GetInstance(QuadSPI_Type *base);
/*!
* @brief Initializes the QSPI module and internal state.
*
@ -457,9 +524,9 @@ static inline void QSPI_SetIPCommandAddress(QuadSPI_Type *base, uint32_t addr)
* @param base Pointer to QuadSPI Type.
* @param size IP command size.
*/
static inline void QSPI_SetIPCommandSize(QuadSPI_Type *base, uint32_t size)
static inline void QSPI_SetIPCommandSize(QuadSPI_Type *base, uint16_t size)
{
base->IPCR = ((base->IPCR & (~QuadSPI_IPCR_IDATSZ_MASK)) | QuadSPI_IPCR_IDATSZ(size));
base->IPCR_ACCESSBIT.IDATZ = size;
}
/*! @brief Executes IP commands located in LUT table.
@ -476,6 +543,7 @@ void QSPI_ExecuteIPCommand(QuadSPI_Type *base, uint32_t index);
*/
void QSPI_ExecuteAHBCommand(QuadSPI_Type *base, uint32_t index);
#if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
/*! @brief Enables/disables the QSPI IP command parallel mode.
*
* @param base Pointer to QuadSPI Type.
@ -509,6 +577,7 @@ static inline void QSPI_EnableAHBParallelMode(QuadSPI_Type *base, bool enable)
base->BFGENCR &= ~QuadSPI_BFGENCR_PAR_EN_MASK;
}
}
#endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */
/*! @brief Updates the LUT table.
*
@ -539,6 +608,24 @@ static inline void QSPI_ClearCommandSequence(QuadSPI_Type *base, qspi_command_se
base->SPTRCLR = seq;
}
/*!
* @brief Enable or disable DDR mode.
*
* @param base QSPI base pointer
* @param eanble True means enable DDR mode, false means disable DDR mode.
*/
static inline void QSPI_EnableDDRMode(QuadSPI_Type *base, bool enable)
{
if (enable)
{
base->MCR |= QuadSPI_MCR_DDR_EN_MASK;
}
else
{
base->MCR &= ~QuadSPI_MCR_DDR_EN_MASK;
}
}
/*!@ brief Set the RX buffer readout area.
*
* This function can set the RX buffer readout, from AHB bus or IP Bus.
@ -569,7 +656,10 @@ static inline void QSPI_WriteData(QuadSPI_Type *base, uint32_t data)
/*!
* @brief Receives a buffer of data bytes using a blocking method.
* @note This function blocks via polling until all bytes have been sent.
* @note This function blocks via polling until all bytes have been sent. Users shall notice that
* this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers.
* For flash contents read, please use AHB bus read, this is much more efficiency.
*
* @param base QSPI base pointer
* @param buffer The data bytes to send
* @param size The number of data bytes to receive
@ -609,7 +699,10 @@ static inline void QSPI_TransferSendBlocking(QuadSPI_Type *base, qspi_transfer_t
* @brief Reads data from the QSPI receive buffer in polling way.
*
* This function reads continuous data from the QSPI receive buffer/FIFO. This function is a blocking
* function and can return only when finished. This function uses polling methods.
* function and can return only when finished. This function uses polling methods. Users shall notice that
* this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers.
* For flash contents read, please use AHB bus read, this is much more efficiency.
*
* @param base Pointer to QuadSPI Type.
* @param xfer QSPI transfer structure.
*/