diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/PeripheralNames.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/PeripheralNames.h new file mode 100644 index 0000000000..6490643372 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/PeripheralNames.h @@ -0,0 +1,113 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OSC32KCLK = 0, +} RTCName; + +typedef enum { + LPUART_0 = 0, + LPUART_1 = 1, + LPUART_2 = 2, + LPUART_3 = 3, + LPUART_4 = 4, +} UARTName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART LPUART_0 + +/* LPTMR interrupt is defined differently in K82F */ +#define LPTMR0_IRQn LPTMR0_LPTMR1_IRQn + +typedef enum { + I2C_0 = 0, + I2C_1 = 1, + I2C_2 = 2, + I2C_3 = 3, +} I2CName; + +#define TPM_SHIFT 8 +typedef enum { + PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 + PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 + PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 + PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 + PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 + PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 + PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 + PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 + PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 + PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 + PWM_11 = (2 << TPM_SHIFT) | (0), // FTM2 CH0 + PWM_12 = (2 << TPM_SHIFT) | (1), // FTM2 CH1 + PWM_13 = (3 << TPM_SHIFT) | (0), // FTM3 CH0 + PWM_14 = (3 << TPM_SHIFT) | (1), // FTM3 CH1 + PWM_15 = (3 << TPM_SHIFT) | (2), // FTM3 CH2 + PWM_16 = (3 << TPM_SHIFT) | (3), // FTM3 CH3 + PWM_17 = (3 << TPM_SHIFT) | (4), // FTM3 CH4 + PWM_18 = (3 << TPM_SHIFT) | (5), // FTM3 CH5 + PWM_19 = (3 << TPM_SHIFT) | (6), // FTM3 CH6 + PWM_20 = (3 << TPM_SHIFT) | (7), // FTM3 CH7 +} PWMName; + +#define ADC_INSTANCE_SHIFT 8 +#define ADC_B_CHANNEL_SHIFT 5 +typedef enum { + ADC0_SE4a = (0 << ADC_INSTANCE_SHIFT) | 4, + ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, + ADC0_SE5a = (0 << ADC_INSTANCE_SHIFT) | 5, + ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, + ADC0_SE6a = (0 << ADC_INSTANCE_SHIFT) | 6, + ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, + ADC0_SE7a = (0 << ADC_INSTANCE_SHIFT) | 7, + ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, + ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8, + ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9, + ADC0_SE10 = (0 << ADC_INSTANCE_SHIFT) | 10, + ADC0_SE11 = (0 << ADC_INSTANCE_SHIFT) | 11, + ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12, + ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13, + ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14, + ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15, + ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22, + ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23, +} ADCName; + +typedef enum { + DAC_0 = 0 +} DACName; + + +typedef enum { + SPI_0 = 0, + SPI_1 = 1, + SPI_2 = 2, +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/PeripheralPins.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/PeripheralPins.c new file mode 100644 index 0000000000..8eab4d62df --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/PeripheralPins.c @@ -0,0 +1,267 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************RTC***************/ +const PinMap PinMap_RTC[] = { + {NC, OSC32KCLK, 0}, +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {PTE16, ADC0_SE4a, 0}, + {PTE17, ADC0_SE5a, 0}, + {PTE18, ADC0_SE6a, 0}, + {PTE19, ADC0_SE7a, 0}, + {PTB0, ADC0_SE8, 0}, + {PTB1, ADC0_SE9, 0}, + {PTA7, ADC0_SE10, 0}, + {PTA8, ADC0_SE11, 0}, + {PTB2, ADC0_SE12, 0}, + {PTB3, ADC0_SE13, 0}, + {PTC0, ADC0_SE14, 0}, + {PTC1, ADC0_SE15, 0}, + {PTC2, ADC0_SE4b, 0}, + {PTD1, ADC0_SE5b, 0}, + {PTD5, ADC0_SE6b, 0}, + {PTD6, ADC0_SE7b, 0}, + {NC , NC , 0} +}; + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {DAC0_OUT, DAC_0, 0}, + {NC , NC , 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {PTE0, I2C_1, 6}, + {PTE10, I2C_3, 2}, + {PTE18, I2C_0, 4}, + {PTA21, I2C_0, 2}, + {PTA1, I2C_3, 4}, + {PTA7, I2C_2, 2}, + {PTA10, I2C_2, 2}, + {PTB1, I2C_0, 2}, + {PTB3, I2C_0, 2}, + {PTB11, I2C_2, 4}, + {PTC11, I2C_1, 2}, + {PTD3, I2C_0, 7}, + {PTD9, I2C_0, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PTE1, I2C_1, 6}, + {PTE11, I2C_3, 2}, + {PTE19, I2C_0, 4}, + {PTA20, I2C_0, 2}, + {PTA2, I2C_3, 4}, + {PTA6, I2C_2, 2}, + {PTA11, I2C_2, 2}, + {PTB0, I2C_0, 2}, + {PTB2, I2C_0, 2}, + {PTB10, I2C_2, 4}, + {PTC10, I2C_1, 2}, + {PTD2, I2C_0, 7}, + {PTD8, I2C_0, 2}, + {NC , NC , 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {PTE0, LPUART_1, 3}, + {PTE4, LPUART_3, 3}, + {PTE12, LPUART_2, 3}, + {PTE16, LPUART_2, 3}, + {PTA20, LPUART_4, 3}, + {PTA2, LPUART_0, 2}, + {PTA14, LPUART_0, 3}, + {PTB11, LPUART_3, 3}, + {PTB17, LPUART_0, 3}, + {PTC4, LPUART_1, 3}, + {PTC15, LPUART_4, 3}, + {PTC17, LPUART_3, 3}, + {PTD3, LPUART_2, 3}, + {PTD7, LPUART_0, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PTE1, LPUART_1, 3}, + {PTE5, LPUART_3, 3}, + {PTE13, LPUART_2, 3}, + {PTE17, LPUART_2, 3}, + {PTA21, LPUART_4, 3}, + {PTA1, LPUART_0, 2}, + {PTA15, LPUART_0, 3}, + {PTB10, LPUART_3, 3}, + {PTB16, LPUART_0, 3}, + {PTC3, LPUART_1, 3}, + {PTC14, LPUART_4, 3}, + {PTC16, LPUART_3, 3}, + {PTD2, LPUART_2, 3}, + {PTD6, LPUART_0, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PTE2, LPUART_1, 3}, + {PTE6, LPUART_3, 3}, + {PTE18, LPUART_2, 3}, + {PTA0, LPUART_0, 2}, + {PTA16, LPUART_0, 3}, + {PTB3, LPUART_0, 3}, + {PTB9, LPUART_3, 3}, + {PTC2, LPUART_1, 3}, + {PTC13, LPUART_4, 3}, + {PTC19, LPUART_3, 3}, + {PTD1, LPUART_2, 3}, + {PTD5, LPUART_0, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {PTE3, LPUART_1, 3}, + {PTE7, LPUART_3, 3}, + {PTE19, LPUART_2, 3}, + {PTA3, LPUART_0, 2}, + {PTA17, LPUART_0, 3}, + {PTB2, LPUART_0, 3}, + {PTB8, LPUART_3, 3}, + {PTC1, LPUART_1, 3}, + {PTC12, LPUART_4, 3}, + {PTC18, LPUART_3, 3}, + {PTD0, LPUART_2, 3}, + {PTD4, LPUART_0, 3}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {PTE1, SPI_1, 2}, + {PTE2, SPI_1, 7}, + {PTE7, SPI_2, 2}, + {PTE17, SPI_0, 2}, + {PTA15, SPI_0, 2}, + {PTB11, SPI_1, 2}, + {PTB21, SPI_2, 2}, + {PTC5, SPI_0, 2}, + {PTD1, SPI_0, 2}, + {PTD5, SPI_1, 7}, + {PTD12, SPI_2, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {PTE2, SPI_1, 2}, + {PTE3, SPI_1, 7}, + {PTE8, SPI_2, 3}, + {PTE18, SPI_0, 2}, + {PTA16, SPI_0, 2}, + {PTB16, SPI_1, 2}, + {PTB16, SPI_1, 2}, + {PTB22, SPI_2, 2}, + {PTC6, SPI_0, 2}, + {PTD2, SPI_0, 2}, + {PTD6, SPI_1, 7}, + {PTD13, SPI_2, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PTE1, SPI_1, 7}, + {PTE4, SPI_1, 2}, + {PTE10, SPI_2, 3}, + {PTE19, SPI_0, 2}, + {PTA17, SPI_0, 2}, + {PTB17, SPI_1, 2}, + {PTB23, SPI_2, 2}, + {PTC7, SPI_0, 2}, + {PTD3, SPI_0, 2}, + {PTD7, SPI_1, 7}, + {PTD14, SPI_2, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PTE5, SPI_1, 2}, + {PTE11, SPI_2, 3}, + {PTE16, SPI_0, 2}, + {PTA14, SPI_0, 2}, + {PTB10, SPI_1, 2}, + {PTB20, SPI_2, 2}, + {PTC4, SPI_0, 2}, + {PTD0, SPI_0, 2}, + {PTD4, SPI_1, 7}, + {PTD11, SPI_2, 2}, + {NC , NC , 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + /* FTM 0 */ + {PTA0, PWM_6, 3}, + {PTA1, PWM_7, 3}, + {PTA2, PWM_8, 3}, + {PTA3, PWM_1, 3}, + {PTA4, PWM_2, 3}, + {PTA5, PWM_3, 3}, + {PTA6, PWM_4, 3}, + {PTA7, PWM_5, 3}, + {PTC1, PWM_1, 4}, + {PTC2, PWM_2, 4}, + {PTC3, PWM_3, 4}, + {PTC4, PWM_4, 4}, + {PTC5, PWM_3, 7}, + {PTD4, PWM_5, 4}, + {PTD5, PWM_6, 4}, + {PTD6, PWM_7, 4}, + {PTD7, PWM_8, 4}, + /* FTM 1 */ + {PTA8, PWM_9, 3}, + {PTA9, PWM_10, 3}, + {PTA12, PWM_9, 3}, + {PTA13, PWM_10, 3}, + {PTB0, PWM_9, 3}, + {PTB1, PWM_10, 3}, + /* FTM 2 */ + {PTA10, PWM_11, 3}, + {PTA11, PWM_12, 3}, + {PTB18, PWM_11, 3}, + {PTB19, PWM_12, 3}, + /* FTM 3 */ + {PTE5, PWM_13, 6}, + {PTE6, PWM_14, 6}, + {PTE7, PWM_15, 6}, + {PTE8, PWM_16, 6}, + {PTE9, PWM_17, 6}, + {PTE10, PWM_18, 6}, + {PTE11, PWM_19, 6}, + {PTE12, PWM_20, 6}, + {PTC8, PWM_17, 3}, + {PTC9, PWM_18, 3}, + {PTC10, PWM_19, 3}, + {PTC11, PWM_20, 3}, + {PTD0, PWM_13, 4}, + {PTD1, PWM_14, 4}, + {PTD2, PWM_15, 4}, + {PTD3, PWM_16, 4}, + + {NC , NC , 0} +}; diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/PinNames.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/PinNames.h new file mode 100644 index 0000000000..a10b156206 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/PinNames.h @@ -0,0 +1,180 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define GPIO_PORT_SHIFT 12 + +typedef enum { + PTA0 = (0 << GPIO_PORT_SHIFT | 0), + PTA1 = (0 << GPIO_PORT_SHIFT | 1), + PTA2 = (0 << GPIO_PORT_SHIFT | 2), + PTA3 = (0 << GPIO_PORT_SHIFT | 3), + PTA4 = (0 << GPIO_PORT_SHIFT | 4), + PTA5 = (0 << GPIO_PORT_SHIFT | 5), + PTA6 = (0 << GPIO_PORT_SHIFT | 6), + PTA7 = (0 << GPIO_PORT_SHIFT | 7), + PTA8 = (0 << GPIO_PORT_SHIFT | 8), + PTA9 = (0 << GPIO_PORT_SHIFT | 9), + PTA10 = (0 << GPIO_PORT_SHIFT | 10), + PTA11 = (0 << GPIO_PORT_SHIFT | 11), + PTA12 = (0 << GPIO_PORT_SHIFT | 12), + PTA13 = (0 << GPIO_PORT_SHIFT | 13), + PTA14 = (0 << GPIO_PORT_SHIFT | 14), + PTA15 = (0 << GPIO_PORT_SHIFT | 15), + PTA16 = (0 << GPIO_PORT_SHIFT | 16), + PTA17 = (0 << GPIO_PORT_SHIFT | 17), + PTA18 = (0 << GPIO_PORT_SHIFT | 18), + PTA19 = (0 << GPIO_PORT_SHIFT | 19), + PTA20 = (0 << GPIO_PORT_SHIFT | 20), + PTA21 = (0 << GPIO_PORT_SHIFT | 21), + PTB0 = (1 << GPIO_PORT_SHIFT | 0), + PTB1 = (1 << GPIO_PORT_SHIFT | 1), + PTB2 = (1 << GPIO_PORT_SHIFT | 2), + PTB3 = (1 << GPIO_PORT_SHIFT | 3), + PTB8 = (1 << GPIO_PORT_SHIFT | 8), + PTB9 = (1 << GPIO_PORT_SHIFT | 9), + PTB10 = (1 << GPIO_PORT_SHIFT | 10), + PTB11 = (1 << GPIO_PORT_SHIFT | 11), + PTB16 = (1 << GPIO_PORT_SHIFT | 16), + PTB17 = (1 << GPIO_PORT_SHIFT | 17), + PTB18 = (1 << GPIO_PORT_SHIFT | 18), + PTB19 = (1 << GPIO_PORT_SHIFT | 19), + PTB20 = (1 << GPIO_PORT_SHIFT | 20), + PTB21 = (1 << GPIO_PORT_SHIFT | 21), + PTB22 = (1 << GPIO_PORT_SHIFT | 22), + PTB23 = (1 << GPIO_PORT_SHIFT | 23), + PTC0 = (2 << GPIO_PORT_SHIFT | 0), + PTC1 = (2 << GPIO_PORT_SHIFT | 1), + PTC2 = (2 << GPIO_PORT_SHIFT | 2), + PTC3 = (2 << GPIO_PORT_SHIFT | 3), + PTC4 = (2 << GPIO_PORT_SHIFT | 4), + PTC5 = (2 << GPIO_PORT_SHIFT | 5), + PTC6 = (2 << GPIO_PORT_SHIFT | 6), + PTC7 = (2 << GPIO_PORT_SHIFT | 7), + PTC8 = (2 << GPIO_PORT_SHIFT | 8), + PTC9 = (2 << GPIO_PORT_SHIFT | 9), + PTC10 = (2 << GPIO_PORT_SHIFT | 10), + PTC11 = (2 << GPIO_PORT_SHIFT | 11), + PTC12 = (2 << GPIO_PORT_SHIFT | 12), + PTC13 = (2 << GPIO_PORT_SHIFT | 13), + PTC14 = (2 << GPIO_PORT_SHIFT | 14), + PTC15 = (2 << GPIO_PORT_SHIFT | 15), + PTC16 = (2 << GPIO_PORT_SHIFT | 16), + PTC17 = (2 << GPIO_PORT_SHIFT | 17), + PTC18 = (2 << GPIO_PORT_SHIFT | 18), + PTC19 = (2 << GPIO_PORT_SHIFT | 19), + PTD0 = (3 << GPIO_PORT_SHIFT | 0), + PTD1 = (3 << GPIO_PORT_SHIFT | 1), + PTD2 = (3 << GPIO_PORT_SHIFT | 2), + PTD3 = (3 << GPIO_PORT_SHIFT | 3), + PTD4 = (3 << GPIO_PORT_SHIFT | 4), + PTD5 = (3 << GPIO_PORT_SHIFT | 5), + PTD6 = (3 << GPIO_PORT_SHIFT | 6), + PTD7 = (3 << GPIO_PORT_SHIFT | 7), + PTD8 = (3 << GPIO_PORT_SHIFT | 8), + PTD9 = (3 << GPIO_PORT_SHIFT | 9), + PTD11 = (3 << GPIO_PORT_SHIFT | 11), + PTD12 = (3 << GPIO_PORT_SHIFT | 12), + PTD13 = (3 << GPIO_PORT_SHIFT | 13), + PTD14 = (3 << GPIO_PORT_SHIFT | 14), + PTE0 = (4 << GPIO_PORT_SHIFT | 0), + PTE1 = (4 << GPIO_PORT_SHIFT | 1), + PTE2 = (4 << GPIO_PORT_SHIFT | 2), + PTE3 = (4 << GPIO_PORT_SHIFT | 3), + PTE4 = (4 << GPIO_PORT_SHIFT | 4), + PTE5 = (4 << GPIO_PORT_SHIFT | 5), + PTE6 = (4 << GPIO_PORT_SHIFT | 6), + PTE7 = (4 << GPIO_PORT_SHIFT | 7), + PTE8 = (4 << GPIO_PORT_SHIFT | 8), + PTE9 = (4 << GPIO_PORT_SHIFT | 9), + PTE10 = (4 << GPIO_PORT_SHIFT | 10), + PTE11 = (4 << GPIO_PORT_SHIFT | 11), + PTE12 = (4 << GPIO_PORT_SHIFT | 12), + PTE13 = (4 << GPIO_PORT_SHIFT | 13), + PTE16 = (4 << GPIO_PORT_SHIFT | 16), + PTE17 = (4 << GPIO_PORT_SHIFT | 17), + PTE18 = (4 << GPIO_PORT_SHIFT | 18), + PTE19 = (4 << GPIO_PORT_SHIFT | 19), + + LED_RED = PTD4, + LED_RGB = PTA14, + + // mbed original LED naming + LED1 = LED_RED, + LED2 = LED_RED, + LED3 = LED_RED, + LED4 = LED_RED, + + //Push buttons + SW0 = PTD0, + + // Console Pins + USBTX = PTA2, + USBRX = PTA1, + + // GSM modem Pins + GSM_UART_TX = PTC15, + GSM_UART_RX = PTC14, + GSM_UART_CMD_TX = PTC4, + GSM_UART_CMD_RX = PTC3, + GSM_POWER = PTD7, + GSM_STATUS = PTE6, + GSM_PWRKEY = PTE8, + GSM_RI = PTE9, + GSM_DCD = PTE10, + + I2C_SCL = PTB10, + I2C_SDA = PTB11, + + SDHC_D0 = PTE1, + SDHC_D1 = PTE0, + SDHC_D2 = PTE5, + SDHC_D3 = PTE4, + SDHC_DCLK = PTE2, + SDHC_CMD = PTE3, + SHDC_DETECT = PTE7, + + DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */ + + // Not connected + NC = (int) 0xFFFFFFFF +} PinName; + + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 2, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/device.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/device.h new file mode 100644 index 0000000000..29a4e7a0b1 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/device.h @@ -0,0 +1,39 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + + + + + + + + + + + +#define DEVICE_ID_LENGTH 24 + + + + + +#include "objects.h" + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/fsl_clock_config.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/fsl_clock_config.c new file mode 100644 index 0000000000..ae5657490a --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/fsl_clock_config.c @@ -0,0 +1,506 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * How to setup clock using clock driver functions: + * + * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock + * and flash clock are in allowed range during clock mode switch. + * + * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. + * + * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and + * internal reference clock(MCGIRCLK). Follow the steps to setup: + * + * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. + * + * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured + * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig + * explicitly to setup MCGIRCLK. + * + * 3). Don't need to configure FLL explicitly, because if target mode is FLL + * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, + * if the target mode is not FLL mode, the FLL is disabled. + * + * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been + * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could + * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. + * + * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. + */ + +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!ClocksProfile +product: Clocks v1.0 +processor: MK82FN256xxx15 +package_id: MK82FN256VLL15 +mcu_data: ksdk2_0 +processor_version: 1.0.1 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +#include "fsl_smc.h" +#include "fsl_rtc.h" +#include "fsl_clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */ +#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */ +#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */ +#define RTC_OSC_CAP_LOAD_0PF 0x0U /*!< RTC oscillator capacity load: 0pF */ +#define RTC_RTC32KCLK_PERIPHERALS_ENABLED 1U /*!< RTC32KCLK to other peripherals: enabled */ +#define SIM_FLEXIO_CLK_SEL_CORE_SYSTEM_CLK 0U /*!< FLEXIO clock select: Core/system clock */ +#define SIM_FLEXIO_CLK_SEL_MCGIRCLK_CLK 3U /*!< FLEXIO clock select: MCGIRCLK clock */ +#define SIM_LPUART_CLK_SEL_MCGIRCLK_CLK 3U /*!< LPUART clock select: MCGIRCLK clock */ +#define SIM_LPUART_CLK_SEL_PLLFLLSEL_CLK 1U /*!< LPUART clock select: PLLFLLSEL output clock */ +#define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ +#define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /*!< PLLFLL select: MCGFLLCLK clock */ +#define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : CLOCK_CONFIG_SetRtcClock + * Description : This function is used to configuring RTC clock including + * enabling RTC oscillator. + * Param capLoad : RTC oscillator capacity load + * Param enableOutPeriph : Enable (1U)/Disable (0U) clock to peripherals + * + *END**************************************************************************/ +static void CLOCK_CONFIG_SetRtcClock(uint32_t capLoad, uint8_t enableOutPeriph) +{ + /* RTC clock gate enable */ + CLOCK_EnableClock(kCLOCK_Rtc0); + if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the Rtc oscillator is not already enabled */ + /* Set the specified capacitor configuration for the RTC oscillator */ + RTC_SetOscCapLoad(RTC, capLoad); + /* Enable the RTC 32KHz oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; + } + /* Output to other peripherals */ + if (enableOutPeriph) { + RTC->CR &= ~RTC_CR_CLKO_MASK; + } + else { + RTC->CR |= RTC_CR_CLKO_MASK; + } + /* Set the XTAL32/RTC_CLKIN frequency based on board setting. */ + CLOCK_SetXtal32Freq(BOARD_XTAL32K_CLK_HZ); + /* Set RTC_TSR if there is fault value in RTC */ + if (RTC->SR & RTC_SR_TIF_MASK) { + RTC -> TSR = RTC -> TSR; + } + /* RTC clock gate disable */ + CLOCK_DisableClock(kCLOCK_Rtc0); +} + +/*FUNCTION********************************************************************** + * + * Function Name : CLOCK_CONFIG_SetFllExtRefDiv + * Description : Configure FLL external reference divider (FRDIV). + * Param frdiv : The value to set FRDIV. + * + *END**************************************************************************/ +static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv) +{ + MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv)); +} + +/******************************************************************************* + ********************* Configuration BOARD_BootClockHSRUN ********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockHSRUN +outputs: +- {id: Bus_clock.outFreq, value: 75 MHz} +- {id: Core_clock.outFreq, value: 150 MHz} +- {id: ERCLK32K.outFreq, value: 32.768 kHz} +- {id: FLEXIOCLK.outFreq, value: 150 MHz} +- {id: Flash_clock.outFreq, value: 25 MHz} +- {id: FlexBus_clock.outFreq, value: 75 MHz} +- {id: IRC48MCLK.outFreq, value: 48 MHz} +- {id: LPO_clock.outFreq, value: 1 kHz} +- {id: LPUARTCLK.outFreq, value: 75 MHz} +- {id: MCGFFCLK.outFreq, value: 1.5 MHz} +- {id: MCGIRCLK.outFreq, value: 2 MHz} +- {id: MCGPLLCLK.outFreq, value: 150 MHz} +- {id: MCGPLLCLK2X.outFreq, value: 300 MHz} +- {id: PLLFLLCLK.outFreq, value: 150 MHz} +- {id: System_clock.outFreq, value: 150 MHz} +settings: +- {id: MCGMode, value: PEE} +- {id: powerMode, value: HSRUN} +- {id: FLEXIOClkConfig, value: 'yes'} +- {id: LPUARTClkConfig, value: 'yes'} +- {id: MCG.FLL_mul.scale, value: '2929', locked: true} +- {id: MCG.FRDIV.scale, value: '32', locked: true} +- {id: MCG.IRCS.sel, value: MCG.FCRDIV} +- {id: MCG.IREFS.sel, value: MCG.FRDIV} +- {id: MCG.OSCSEL.sel, value: SIM.IRC48MCLK} +- {id: MCG.OSCSEL_PLL.sel, value: SIM.IRC48MCLK} +- {id: MCG.PLLS.sel, value: MCG.PLL_DIV2} +- {id: MCG.PRDIV.scale, value: '4', locked: true} +- {id: MCG.VDIV.scale, value: '25', locked: true} +- {id: MCG_C1_IRCLKEN_CFG, value: Enabled} +- {id: MCG_C2_RANGE0_CFG, value: Very_high} +- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high} +- {id: MCG_C5_PLLCLKEN0_CFG, value: Enabled} +- {id: RTC_CR_OSCE_CFG, value: Enabled} +- {id: SIM.LPUARTSRCSEL.sel, value: SIM.PLLFLLDIV} +- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK} +- {id: SIM.OUTDIV2.scale, value: '2'} +- {id: SIM.OUTDIV4.scale, value: '6'} +- {id: SIM.PLLFLLDIV.scale, value: '2', locked: true} +- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK} +- {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK} +- {id: SIM.USBDIV.scale, value: '1', locked: true} +- {id: SIM.USBFRAC.scale, value: '1', locked: true} +sources: +- {id: IRC48M.IRC48M.outFreq, value: 48 MHz} +- {id: RTC.RTC32kHz.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockHSRUN configuration + ******************************************************************************/ +const mcg_config_t mcgConfig_BOARD_BootClockHSRUN = + { + .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ + .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */ + .fcrdiv = 0x1U, /* Fast IRC divider: divided by 2 */ + .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */ + .drs = kMCG_DrsHigh, /* High frequency range */ + .dmx32 = kMCG_Dmx32Fine, /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */ + .oscsel = kMCG_OscselIrc, /* Selects 48 MHz IRC Oscillator */ + .pll0Config = + { + .enableMode = kMCG_PllEnableIndependent,/* MCGPLLCLK enabled independent of MCG clock mode, MCGPLLCLK disabled in STOP mode */ + .prdiv = 0x3U, /* PLL Reference divider: divided by 4 */ + .vdiv = 0x9U, /* VCO divider: multiplied by 25 */ + }, + }; +const sim_clock_config_t simConfig_BOARD_BootClockHSRUN = + { + .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */ + .pllFllDiv = 1, /* PLLFLLSEL clock divider divisor: divided by 2 */ + .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */ + .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ + .clkdiv1 = 0x1150000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /6 */ + }; +const osc_config_t oscConfig_BOARD_BootClockHSRUN = + { + .freq = 0U, /* Oscillator frequency: 0Hz */ + .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ + .workMode = kOSC_ModeExt, /* Use external clock */ + .oscerConfig = + { + .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */ + .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */ + } + }; + +/******************************************************************************* + * Code for BOARD_BootClockHSRUN configuration + ******************************************************************************/ +void BOARD_BootClockHSRUN(void) +{ + /* Set HSRUN power mode */ + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); + SMC_SetPowerModeHsrun(SMC); + while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun) + { + } + /* Set the system clock dividers in SIM to safe value. */ + CLOCK_SetSimSafeDivs(); + /* Configure RTC clock including enabling RTC oscillator. */ + CLOCK_CONFIG_SetRtcClock(RTC_OSC_CAP_LOAD_0PF, RTC_RTC32KCLK_PERIPHERALS_ENABLED); + /* Configure the Internal Reference clock (MCGIRCLK). */ + CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode, + mcgConfig_BOARD_BootClockHSRUN.ircs, + mcgConfig_BOARD_BootClockHSRUN.fcrdiv); + /* Configure FLL external reference divider (FRDIV). */ + CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockHSRUN.frdiv); + /* Set MCG to PEE mode. */ + CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockHSRUN.oscsel, + kMCG_PllClkSelPll0, + &mcgConfig_BOARD_BootClockHSRUN.pll0Config); + /* Set the clock configuration in SIM module. */ + CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN); + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK; + /* Set LPUART clock source. */ + CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_PLLFLLSEL_CLK); + /* Set FLEXIO clock source. */ + CLOCK_SetFlexio0Clock(SIM_FLEXIO_CLK_SEL_CORE_SYSTEM_CLK); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockRUN +outputs: +- {id: Bus_clock.outFreq, value: 60 MHz} +- {id: Core_clock.outFreq, value: 120 MHz} +- {id: ERCLK32K.outFreq, value: 32.768 kHz} +- {id: FLEXIOCLK.outFreq, value: 120 MHz} +- {id: Flash_clock.outFreq, value: 20 MHz} +- {id: FlexBus_clock.outFreq, value: 60 MHz} +- {id: IRC48MCLK.outFreq, value: 48 MHz} +- {id: LPO_clock.outFreq, value: 1 kHz} +- {id: LPUARTCLK.outFreq, value: 60 MHz} +- {id: MCGFFCLK.outFreq, value: 1.5 MHz} +- {id: MCGIRCLK.outFreq, value: 2 MHz} +- {id: MCGPLLCLK.outFreq, value: 120 MHz} +- {id: MCGPLLCLK2X.outFreq, value: 240 MHz} +- {id: PLLFLLCLK.outFreq, value: 120 MHz} +- {id: System_clock.outFreq, value: 120 MHz} +settings: +- {id: MCGMode, value: PEE} +- {id: FLEXIOClkConfig, value: 'yes'} +- {id: LPUARTClkConfig, value: 'yes'} +- {id: MCG.FLL_mul.scale, value: '2929', locked: true} +- {id: MCG.FRDIV.scale, value: '32', locked: true} +- {id: MCG.IRCS.sel, value: MCG.FCRDIV} +- {id: MCG.IREFS.sel, value: MCG.FRDIV} +- {id: MCG.OSCSEL.sel, value: SIM.IRC48MCLK} +- {id: MCG.OSCSEL_PLL.sel, value: SIM.IRC48MCLK} +- {id: MCG.PLLS.sel, value: MCG.PLL_DIV2} +- {id: MCG.PRDIV.scale, value: '4', locked: true} +- {id: MCG.VDIV.scale, value: '20', locked: true} +- {id: MCG_C1_IRCLKEN_CFG, value: Enabled} +- {id: MCG_C2_RANGE0_CFG, value: Very_high} +- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high} +- {id: MCG_C5_PLLCLKEN0_CFG, value: Enabled} +- {id: RTC_CR_OSCE_CFG, value: Enabled} +- {id: SIM.LPUARTSRCSEL.sel, value: SIM.PLLFLLDIV} +- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK} +- {id: SIM.OUTDIV2.scale, value: '2'} +- {id: SIM.OUTDIV4.scale, value: '6'} +- {id: SIM.PLLFLLDIV.scale, value: '2', locked: true} +- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK} +- {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK} +- {id: SIM.USBDIV.scale, value: '1', locked: true} +- {id: SIM.USBFRAC.scale, value: '1', locked: true} +sources: +- {id: IRC48M.IRC48M.outFreq, value: 48 MHz} +- {id: RTC.RTC32kHz.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const mcg_config_t mcgConfig_BOARD_BootClockRUN = + { + .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ + .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */ + .fcrdiv = 0x1U, /* Fast IRC divider: divided by 2 */ + .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */ + .drs = kMCG_DrsHigh, /* High frequency range */ + .dmx32 = kMCG_Dmx32Fine, /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */ + .oscsel = kMCG_OscselIrc, /* Selects 48 MHz IRC Oscillator */ + .pll0Config = + { + .enableMode = kMCG_PllEnableIndependent,/* MCGPLLCLK enabled independent of MCG clock mode, MCGPLLCLK disabled in STOP mode */ + .prdiv = 0x3U, /* PLL Reference divider: divided by 4 */ + .vdiv = 0x4U, /* VCO divider: multiplied by 20 */ + }, + }; +const sim_clock_config_t simConfig_BOARD_BootClockRUN = + { + .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */ + .pllFllDiv = 1, /* PLLFLLSEL clock divider divisor: divided by 2 */ + .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */ + .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ + .clkdiv1 = 0x1150000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /6 */ + }; +const osc_config_t oscConfig_BOARD_BootClockRUN = + { + .freq = 0U, /* Oscillator frequency: 0Hz */ + .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ + .workMode = kOSC_ModeExt, /* Use external clock */ + .oscerConfig = + { + .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */ + .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */ + } + }; + +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Set the system clock dividers in SIM to safe value. */ + CLOCK_SetSimSafeDivs(); + /* Configure RTC clock including enabling RTC oscillator. */ + CLOCK_CONFIG_SetRtcClock(RTC_OSC_CAP_LOAD_0PF, RTC_RTC32KCLK_PERIPHERALS_ENABLED); + /* Configure the Internal Reference clock (MCGIRCLK). */ + CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, + mcgConfig_BOARD_BootClockRUN.ircs, + mcgConfig_BOARD_BootClockRUN.fcrdiv); + /* Configure FLL external reference divider (FRDIV). */ + CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv); + /* Set MCG to PEE mode. */ + CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, + kMCG_PllClkSelPll0, + &mcgConfig_BOARD_BootClockRUN.pll0Config); + /* Set the clock configuration in SIM module. */ + CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN); + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; + /* Set LPUART clock source. */ + CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_PLLFLLSEL_CLK); + /* Set FLEXIO clock source. */ + CLOCK_SetFlexio0Clock(SIM_FLEXIO_CLK_SEL_CORE_SYSTEM_CLK); +} + +/******************************************************************************* + ********************* Configuration BOARD_BootClockVLPR *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockVLPR +outputs: +- {id: Bus_clock.outFreq, value: 4 MHz} +- {id: Core_clock.outFreq, value: 4 MHz} +- {id: ERCLK32K.outFreq, value: 32.768 kHz} +- {id: FLEXIOCLK.outFreq, value: 4 MHz} +- {id: Flash_clock.outFreq, value: 800 kHz} +- {id: FlexBus_clock.outFreq, value: 4 MHz} +- {id: LPO_clock.outFreq, value: 1 kHz} +- {id: LPUARTCLK.outFreq, value: 4 MHz} +- {id: MCGIRCLK.outFreq, value: 4 MHz} +- {id: System_clock.outFreq, value: 4 MHz} +settings: +- {id: MCGMode, value: BLPI} +- {id: powerMode, value: VLPR} +- {id: FLEXIOClkConfig, value: 'yes'} +- {id: LPUARTClkConfig, value: 'yes'} +- {id: MCG.CLKS.sel, value: MCG.IRCS} +- {id: MCG.FCRDIV.scale, value: '1'} +- {id: MCG.IRCS.sel, value: MCG.FCRDIV} +- {id: MCG_C1_IRCLKEN_CFG, value: Enabled} +- {id: RTC_CR_OSCE_CFG, value: Enabled} +- {id: SIM.FLEXIOSRCSEL.sel, value: MCG.MCGIRCLK} +- {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK} +- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK} +- {id: SIM.OUTDIV3.scale, value: '1'} +- {id: SIM.OUTDIV4.scale, value: '5'} +sources: +- {id: RTC.RTC32kHz.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockVLPR configuration + ******************************************************************************/ +const mcg_config_t mcgConfig_BOARD_BootClockVLPR = + { + .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ + .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */ + .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */ + .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */ + .drs = kMCG_DrsLow, /* Low frequency range */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */ + .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */ + .pll0Config = + { + .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */ + .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */ + .vdiv = 0x0U, /* VCO divider: multiplied by 16 */ + }, + }; +const sim_clock_config_t simConfig_BOARD_BootClockVLPR = + { + .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */ + .pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */ + .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */ + .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ + .clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */ + }; +const osc_config_t oscConfig_BOARD_BootClockVLPR = + { + .freq = 0U, /* Oscillator frequency: 0Hz */ + .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ + .workMode = kOSC_ModeExt, /* Use external clock */ + .oscerConfig = + { + .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */ + .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */ + } + }; + +/******************************************************************************* + * Code for BOARD_BootClockVLPR configuration + ******************************************************************************/ +void BOARD_BootClockVLPR(void) +{ + /* Set the system clock dividers in SIM to safe value. */ + CLOCK_SetSimSafeDivs(); + /* Configure RTC clock including enabling RTC oscillator. */ + CLOCK_CONFIG_SetRtcClock(RTC_OSC_CAP_LOAD_0PF, RTC_RTC32KCLK_PERIPHERALS_ENABLED); + /* Set MCG to BLPI mode. */ + CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, + mcgConfig_BOARD_BootClockVLPR.ircs, + mcgConfig_BOARD_BootClockVLPR.irclkEnableMode); + /* Set the clock configuration in SIM module. */ + CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR); + /* Set VLPR power mode. */ + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); +#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) + SMC_SetPowerModeVlpr(SMC, false); +#else + SMC_SetPowerModeVlpr(SMC); +#endif + while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr) + { + } + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK; + /* Set LPUART clock source. */ + CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK); + /* Set FLEXIO clock source. */ + CLOCK_SetFlexio0Clock(SIM_FLEXIO_CLK_SEL_MCGIRCLK_CLK); +} + diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/fsl_clock_config.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/fsl_clock_config.h new file mode 100644 index 0000000000..df0bede6e3 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/fsl_clock_config.h @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board RTC xtal frequency in Hz */ + +/******************************************************************************* + ********************* Configuration BOARD_BootClockHSRUN ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockHSRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */ + +/*! @brief MCG set for BOARD_BootClockHSRUN configuration. + */ +extern const mcg_config_t mcgConfig_BOARD_BootClockHSRUN; +/*! @brief SIM module set for BOARD_BootClockHSRUN configuration. + */ +extern const sim_clock_config_t simConfig_BOARD_BootClockHSRUN; +/*! @brief OSC set for BOARD_BootClockHSRUN configuration. + */ +extern const osc_config_t oscConfig_BOARD_BootClockHSRUN; + +/******************************************************************************* + * API for BOARD_BootClockHSRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockHSRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 120000000U /*!< Core clock frequency: 120000000Hz */ + +/*! @brief MCG set for BOARD_BootClockRUN configuration. + */ +extern const mcg_config_t mcgConfig_BOARD_BootClockRUN; +/*! @brief SIM module set for BOARD_BootClockRUN configuration. + */ +extern const sim_clock_config_t simConfig_BOARD_BootClockRUN; +/*! @brief OSC set for BOARD_BootClockRUN configuration. + */ +extern const osc_config_t oscConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************* Configuration BOARD_BootClockVLPR *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockVLPR configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 2000000U /*!< Core clock frequency: 2000000Hz */ + +/*! @brief MCG set for BOARD_BootClockVLPR configuration. + */ +extern const mcg_config_t mcgConfig_BOARD_BootClockVLPR; +/*! @brief SIM module set for BOARD_BootClockVLPR configuration. + */ +extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR; +/*! @brief OSC set for BOARD_BootClockVLPR configuration. + */ +extern const osc_config_t oscConfig_BOARD_BootClockVLPR; + +/******************************************************************************* + * API for BOARD_BootClockVLPR configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockVLPR(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/mbed_overrides.c new file mode 100644 index 0000000000..4ac8d7e88b --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/mbed_overrides.c @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "fsl_smc.h" +#include "fsl_rcm.h" +#include "fsl_pmc.h" +#include "fsl_clock_config.h" + +//!< this contains the wakeup source +rcm_reset_source_t kinetisResetSource; + +// called before main +void mbed_sdk_init() { + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); + + // check the power mode source + kinetisResetSource = (rcm_reset_source_t) (RCM_GetPreviousResetSources(RCM)); + // if waking up from VLLS, do some cleanup + if (kinetisResetSource & kRCM_SourceWakeup) { + PMC_ClearPeriphIOIsolationFlag(PMC); + NVIC_ClearPendingIRQ(LLWU_IRQn); + } + + BOARD_BootClockRUN(); + +} + +// Change the NMI pin to an input. This allows NMI pin to +// be used as a low power mode wakeup. The application will +// need to change the pin back to NMI_b or wakeup only occurs once! +void NMI_Handler(void) +{ + gpio_t gpio; + gpio_init_in(&gpio, PTA4); +} + +// Enable the RTC oscillator if available on the board +void rtc_setup_oscillator(RTC_Type *base) +{ + /* Enable the RTC oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/serial_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/serial_api.c index 0b6268752e..c7fc6bfdcd 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/serial_api.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/serial_api.c @@ -47,8 +47,30 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) obj->index = pinmap_merge(uart_tx, uart_rx); MBED_ASSERT((int)obj->index != NC); - /* Set the LPUART clock source */ - CLOCK_SetLpuartClock(2U); + // since the LPuart initialization depends very much on the source clock and its + // frequency, we do a check here and retrieve the frequency accordingly + // The CLOCK_SetLpuartSrc() is already done during clock init. + uint32_t lpuart_src_freq; + switch (SIM->SOPT2 & SIM_SOPT2_LPUARTSRC_MASK) { + case SIM_SOPT2_LPUARTSRC(3U): { + lpuart_src_freq = CLOCK_GetInternalRefClkFreq(); + break; + } + case SIM_SOPT2_LPUARTSRC(2U): { + lpuart_src_freq = CLOCK_GetOsc0ErClkFreq(); + break; + } + case SIM_SOPT2_LPUARTSRC(1U): { + lpuart_src_freq = CLOCK_GetPllFllSelClkFreq(); + break; + } + default: { + /* Set the LPUART clock source */ + CLOCK_SetLpuartClock(1U); + lpuart_src_freq = CLOCK_GetFreq(uart_clocks[obj->index]); + break; + } + } lpuart_config_t config; LPUART_GetDefaultConfig(&config); @@ -56,7 +78,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) config.enableTx = false; config.enableRx = false; - LPUART_Init(uart_addrs[obj->index], &config, CLOCK_GetFreq(uart_clocks[obj->index])); + LPUART_Init(uart_addrs[obj->index], &config, lpuart_src_freq); pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(rx, PinMap_UART_RX); diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/trng_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/trng_api.c new file mode 100644 index 0000000000..16c3448415 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/trng_api.c @@ -0,0 +1,52 @@ +/* + * Hardware entropy collector for the K66F, using Freescale's RNGA + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* + * Reference: "K66 Sub-Family Reference Manual, Rev. 2", chapter 38 + */ + +#include +#include "cmsis.h" +#include "fsl_trng.h" +#include "trng_api.h" + +void trng_init(trng_t *obj) +{ + (void)obj; + trng_config_t trngConfig; + TRNG_GetDefaultConfig(&trngConfig); + TRNG_Init(TRNG0, &trngConfig); +} + +void trng_free(trng_t *obj) +{ + (void)obj; + TRNG_Deinit(TRNG0); +} + +int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) +{ + (void)obj; + + if(TRNG_GetRandomData(TRNG0, output, length) != kStatus_Success) return -1; + *output_length = length; + + return 0; +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PeripheralNames.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PeripheralNames.h new file mode 100644 index 0000000000..373051da51 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PeripheralNames.h @@ -0,0 +1,102 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OSC32KCLK = 0, +} RTCName; + +/* LPUART */ +typedef enum { + LPUART_0 = 0, + LPUART_1 = 1, + LPUART_2 = 2, +} UARTName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART LPUART_0 + +typedef enum { + I2C_0 = 0, + I2C_1 = 1, +} I2CName; + +#define TPM_SHIFT 8 +typedef enum { + PWM_1 = (0 << TPM_SHIFT) | (0), // TPM0 CH0 + PWM_2 = (0 << TPM_SHIFT) | (1), // TPM0 CH1 + PWM_3 = (0 << TPM_SHIFT) | (2), // TPM0 CH2 + PWM_4 = (0 << TPM_SHIFT) | (3), // TPM0 CH3 + PWM_5 = (0 << TPM_SHIFT) | (4), // TPM0 CH4 + PWM_6 = (0 << TPM_SHIFT) | (5), // TPM0 CH5 + PWM_7 = (1 << TPM_SHIFT) | (0), // TPM1 CH0 + PWM_8 = (1 << TPM_SHIFT) | (1), // TPM1 CH1 + PWM_9 = (2 << TPM_SHIFT) | (0), // TPM2 CH0 + PWM_10 = (2 << TPM_SHIFT) | (1), // TPM2 CH1 +} PWMName; + +#define ADC_INSTANCE_SHIFT 8 +#define ADC_B_CHANNEL_SHIFT 5 +typedef enum { + ADC0_SE0 = (0 << ADC_INSTANCE_SHIFT) | 0, + ADC0_SE1 = (0 << ADC_INSTANCE_SHIFT) | 1, + ADC0_SE2 = (0 << ADC_INSTANCE_SHIFT) | 2, + ADC0_SE3 = (0 << ADC_INSTANCE_SHIFT) | 3, + ADC0_SE4a = (0 << ADC_INSTANCE_SHIFT) | 4, + ADC0_SE5a = (0 << ADC_INSTANCE_SHIFT) | 5, + ADC0_SE6a = (0 << ADC_INSTANCE_SHIFT) | 6, + ADC0_SE7a = (0 << ADC_INSTANCE_SHIFT) | 7, + ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, + ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, + ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, + ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, + ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8, + ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9, + ADC0_SE11 = (0 << ADC_INSTANCE_SHIFT) | 11, + ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12, + ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13, + ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14, + ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15, + ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16, + ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17, + ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18, + ADC0_SE21 = (0 << ADC_INSTANCE_SHIFT) | 21, + ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22, + ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23, +} ADCName; + +typedef enum { + SPI_0 = 0, + SPI_1 = 1, +} SPIName; + +typedef enum { + DAC_0 = 0 +} DACName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PeripheralPins.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PeripheralPins.c new file mode 100644 index 0000000000..3cbfd04c6b --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PeripheralPins.c @@ -0,0 +1,159 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************RTC***************/ +const PinMap PinMap_RTC[] = { + {NC, OSC32KCLK, 0}, +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {PTB0, ADC0_SE8, 0}, + {PTB1, ADC0_SE9, 0}, + {PTB2, ADC0_SE12, 0}, + {PTB3, ADC0_SE13, 0}, + {PTC0, ADC0_SE14, 0}, + {PTC1, ADC0_SE15, 0}, + {PTC2, ADC0_SE4b, 0}, + {PTD1, ADC0_SE5b, 0}, + {PTD5, ADC0_SE6b, 0}, + {PTD6, ADC0_SE7b, 0}, + {NC , NC , 0} +}; + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {DAC0_OUT, DAC_0, 0}, + {NC , NC , 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {PTB1, I2C_0, 2}, + {PTB3, I2C_0, 2}, + {PTC11, I2C_1, 2}, + {PTD3, I2C_0, 7}, + {PTD9, I2C_0, 2}, + {PTE0, I2C_1, 6}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PTB0, I2C_0, 2}, + {PTB2, I2C_0, 2}, + {PTC10, I2C_1, 2}, + {PTD2, I2C_0, 7}, + {PTD8, I2C_0, 2}, + {PTE1, I2C_1, 6}, + {NC , NC , 0} +}; + +/************LPUART***************/ +const PinMap PinMap_UART_TX[] = { + {PTA2, LPUART_0, 2}, + {PTA14, LPUART_0, 3}, + {PTB17, LPUART_0, 3}, + {PTC4, LPUART_1, 3}, + {PTD3, LPUART_2, 3}, + {PTD7, LPUART_0, 3}, + {PTE0, LPUART_1, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PTA1, LPUART_0, 2}, + {PTA15, LPUART_0, 3}, + {PTB16, LPUART_0, 3}, + {PTC3, LPUART_1, 3}, + {PTD2, LPUART_2, 3}, + {PTD6, LPUART_0, 3}, + {PTE1, LPUART_1, 3}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {PTE1, SPI_1, 2}, + {PTE2, SPI_1, 7}, + {PTA15, SPI_1, 2}, + {PTB11, SPI_1, 2}, + {PTC5, SPI_0, 2}, + {PTD1, SPI_0, 2}, + {PTD5, SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {PTE2, SPI_1, 2}, + {PTE3, SPI_1, 7}, + {PTA16, SPI_1, 2}, + {PTB16, SPI_1, 2}, + {PTC6, SPI_0, 2}, + {PTD2, SPI_0, 2}, + {PTD6, SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PTE1, SPI_1, 7}, + {PTE4, SPI_1, 2}, + {PTA17, SPI_1, 2}, + {PTB17, SPI_1, 2}, + {PTC7, SPI_0, 2}, + {PTD3, SPI_0, 2}, + {PTD7, SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PTE5, SPI_1, 2}, + {PTA14, SPI_1, 2}, + {PTB10, SPI_1, 2}, + {PTC4, SPI_0, 2}, + {PTD0, SPI_0, 2}, + {PTD4, SPI_1, 7}, + {NC , NC , 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {PTA0, PWM_6, 3}, // PTA0 , TPM0 CH5 + {PTA3, PWM_1, 3}, // PTA3 , TPM0 CH0 + {PTA4, PWM_2 , 3}, // PTA4 , TPM0 CH1 + {PTA5, PWM_3 , 3}, // PTA5 , TPM0 CH2 + {PTA10, PWM_9, 3}, // PTA10, TPM2 CH0 + {PTA11, PWM_10, 3}, // PTA11, TPM2 CH1 + {PTA12, PWM_7 , 3}, // PTA12, TPM1 CH0 + {PTA13, PWM_8 , 3}, // PTA13, TPM1 CH1 + + {PTB0, PWM_7, 3}, // PTB0 , TPM1 CH0 + {PTB1, PWM_8, 3}, // PTB1 , TPM1 CH1 + {PTB18, PWM_9, 3}, // PTB18, TPM2 CH0 + {PTB19, PWM_10, 3}, // PTB18, TPM2 CH1 + + {PTC1, PWM_1, 4}, // PTC1 , TPM0 CH0 + {PTC2, PWM_2, 4}, // PTC2 , TPM0 CH1 + {PTC3, PWM_3, 4}, // PTC3 , TPM0 CH2 + {PTC4, PWM_4, 4}, // PTC4 , TPM0 CH3 + {PTC5, PWM_3, 7}, // PTC4 , TPM0 CH2 + + {PTD4, PWM_5 , 4}, // PTD4 , TPM0 CH4 + {PTD5, PWM_6 , 4}, // PTD5 , TPM0 CH5 + + {NC , NC , 0} +}; diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PinNames.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PinNames.h new file mode 100644 index 0000000000..62a8495bef --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PinNames.h @@ -0,0 +1,147 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define GPIO_PORT_SHIFT 12 + +typedef enum { + PTA0 = (0 << GPIO_PORT_SHIFT | 0), + PTA1 = (0 << GPIO_PORT_SHIFT | 1), + PTA2 = (0 << GPIO_PORT_SHIFT | 2), + PTA3 = (0 << GPIO_PORT_SHIFT | 3), + PTA4 = (0 << GPIO_PORT_SHIFT | 4), + PTA5 = (0 << GPIO_PORT_SHIFT | 5), + PTA10 = (0 << GPIO_PORT_SHIFT | 10), + PTA11 = (0 << GPIO_PORT_SHIFT | 11), + PTA12 = (0 << GPIO_PORT_SHIFT | 12), + PTA13 = (0 << GPIO_PORT_SHIFT | 13), + PTA14 = (0 << GPIO_PORT_SHIFT | 14), + PTA15 = (0 << GPIO_PORT_SHIFT | 15), + PTA16 = (0 << GPIO_PORT_SHIFT | 16), + PTA17 = (0 << GPIO_PORT_SHIFT | 17), + PTA18 = (0 << GPIO_PORT_SHIFT | 18), + PTA19 = (0 << GPIO_PORT_SHIFT | 19), + + PTB0 = (1 << GPIO_PORT_SHIFT | 0), + PTB1 = (1 << GPIO_PORT_SHIFT | 1), + PTB2 = (1 << GPIO_PORT_SHIFT | 2), + PTB3 = (1 << GPIO_PORT_SHIFT | 3), + PTB9 = (1 << GPIO_PORT_SHIFT | 9), + PTB10 = (1 << GPIO_PORT_SHIFT | 10), + PTB11 = (1 << GPIO_PORT_SHIFT | 11), + PTB16 = (1 << GPIO_PORT_SHIFT | 16), + PTB17 = (1 << GPIO_PORT_SHIFT | 17), + PTB18 = (1 << GPIO_PORT_SHIFT | 18), + PTB19 = (1 << GPIO_PORT_SHIFT | 19), + PTB20 = (1 << GPIO_PORT_SHIFT | 20), + PTB21 = (1 << GPIO_PORT_SHIFT | 21), + PTB22 = (1 << GPIO_PORT_SHIFT | 22), + PTB23 = (1 << GPIO_PORT_SHIFT | 23), + PTC0 = (2 << GPIO_PORT_SHIFT | 0), + PTC1 = (2 << GPIO_PORT_SHIFT | 1), + PTC2 = (2 << GPIO_PORT_SHIFT | 2), + PTC3 = (2 << GPIO_PORT_SHIFT | 3), + PTC4 = (2 << GPIO_PORT_SHIFT | 4), + PTC5 = (2 << GPIO_PORT_SHIFT | 5), + PTC6 = (2 << GPIO_PORT_SHIFT | 6), + PTC7 = (2 << GPIO_PORT_SHIFT | 7), + PTC8 = (2 << GPIO_PORT_SHIFT | 8), + PTC9 = (2 << GPIO_PORT_SHIFT | 9), + PTC10 = (2 << GPIO_PORT_SHIFT | 10), + PTC11 = (2 << GPIO_PORT_SHIFT | 11), + PTC12 = (2 << GPIO_PORT_SHIFT | 12), + PTC13 = (2 << GPIO_PORT_SHIFT | 13), + PTC14 = (2 << GPIO_PORT_SHIFT | 14), + PTC15 = (2 << GPIO_PORT_SHIFT | 15), + PTC17 = (2 << GPIO_PORT_SHIFT | 17), + + PTD0 = (3 << GPIO_PORT_SHIFT | 0), + PTD1 = (3 << GPIO_PORT_SHIFT | 1), + PTD2 = (3 << GPIO_PORT_SHIFT | 2), + PTD3 = (3 << GPIO_PORT_SHIFT | 3), + PTD4 = (3 << GPIO_PORT_SHIFT | 4), + PTD5 = (3 << GPIO_PORT_SHIFT | 5), + PTD6 = (3 << GPIO_PORT_SHIFT | 6), + PTD7 = (3 << GPIO_PORT_SHIFT | 7), + PTD8 = (3 << GPIO_PORT_SHIFT | 8), + PTD9 = (3 << GPIO_PORT_SHIFT | 9), + + PTE0 = (4 << GPIO_PORT_SHIFT | 0), + PTE1 = (4 << GPIO_PORT_SHIFT | 1), + PTE2 = (4 << GPIO_PORT_SHIFT | 2), + PTE3 = (4 << GPIO_PORT_SHIFT | 3), + PTE4 = (4 << GPIO_PORT_SHIFT | 4), + PTE5 = (4 << GPIO_PORT_SHIFT | 5), + PTE6 = (4 << GPIO_PORT_SHIFT | 6), + PTE7 = (4 << GPIO_PORT_SHIFT | 7), + PTE8 = (4 << GPIO_PORT_SHIFT | 9), + PTE9 = (4 << GPIO_PORT_SHIFT | 9), + PTE10 = (4 << GPIO_PORT_SHIFT | 10), + PTE11 = (4 << GPIO_PORT_SHIFT | 11), + + LED_RED = PTE1, + + // mbed original LED naming + LED1 = LED_RED, + LED2 = LED_RED, + LED3 = LED_RED, + LED4 = LED_RED, + + //Push buttons + SW0 = PTE2, + + USBRX = PTA1, + USBTX = PTA2, + + UART_RTS = PTC1, + UART_CTS = PTC2, + UART_RX = PTC3, + UART_TX = PTC4, + + I2C_SCL = PTC10, + I2C_SDA = PTC11, + + DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */ + + // Not connected + NC = (int) 0xFFFFFFFF +} PinName; + + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 2, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/device.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/device.h new file mode 100644 index 0000000000..29a4e7a0b1 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/device.h @@ -0,0 +1,39 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + + + + + + + + + + + +#define DEVICE_ID_LENGTH 24 + + + + + +#include "objects.h" + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/fsl_clock_config.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/fsl_clock_config.c new file mode 100755 index 0000000000..d89cf89c38 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/fsl_clock_config.c @@ -0,0 +1,180 @@ +/* + * How to setup clock using clock driver functions: + * + * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock + * and flash clock are in allowed range during clock mode switch. + * + * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. + * + * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and + * internal reference clock(MCGIRCLK). Follow the steps to setup: + * + * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. + * + * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured + * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig + * explicitly to setup MCGIRCLK. + * + * 3). Don't need to configure FLL explicitly, because if target mode is FLL + * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, + * if the target mode is not FLL mode, the FLL is disabled. + * + * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been + * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could + * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. + * + * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v3.0 +processor: MKL82Z128xxx7 +package_id: MKL82Z128VLL7 +mcu_data: ksdk2_0 +processor_version: 2.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "fsl_clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define MCG_IRCLK_DISABLE 0U /*!< MCGIRCLK disabled */ +#define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */ +#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */ +#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */ +#define SIM_LPUART_CLK_SEL_PLLFLLSEL_CLK 1U /*!< LPUART clock select: PLLFLLSEL output clock */ +#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */ +#define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : CLOCK_CONFIG_SetFllExtRefDiv + * Description : Configure FLL external reference divider (FRDIV). + * Param frdiv : The value to set FRDIV. + * + *END**************************************************************************/ +static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv) +{ + MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv)); +} + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: Bus_clock.outFreq, value: 16 MHz} +- {id: Core_clock.outFreq, value: 48 MHz} +- {id: Fast_bus_clock.outFreq, value: 48 MHz} +- {id: Flash_clock.outFreq, value: 16 MHz} +- {id: IRC48MCLK.outFreq, value: 48 MHz} +- {id: LPO_clock.outFreq, value: 1 kHz} +- {id: LPUARTCLK.outFreq, value: 48 MHz} +- {id: MCGPLLCLK.outFreq, value: 96 MHz} +- {id: MCGPLLCLK2X.outFreq, value: 192 MHz} +- {id: PLLFLLCLK.outFreq, value: 96 MHz} +- {id: System_clock.outFreq, value: 48 MHz} +settings: +- {id: MCGMode, value: PEE} +- {id: LPUARTClkConfig, value: 'yes'} +- {id: MCG.IREFS.sel, value: MCG.FRDIV} +- {id: MCG.OSCSEL.sel, value: SIM.IRC48MCLK} +- {id: MCG.OSCSEL_PLL.sel, value: SIM.IRC48MCLK} +- {id: MCG.PLLS.sel, value: MCG.PLL_DIV2} +- {id: MCG.PRDIV.scale, value: '4'} +- {id: RTC_CR_OSCE_CFG, value: Enabled} +- {id: SIM.FLEXIOSRCSEL.sel, value: SIM.PLLFLLDIV} +- {id: SIM.LPUARTSRCSEL.sel, value: SIM.PLLFLLDIV} +- {id: SIM.OUTDIV1.scale, value: '2'} +- {id: SIM.OUTDIV2.scale, value: '6'} +- {id: SIM.OUTDIV4.scale, value: '6'} +- {id: SIM.OUTDIV5.scale, value: '2'} +- {id: SIM.PLLFLLDIV.scale, value: '2'} +- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK} +sources: +- {id: IRC48M.IRC48M.outFreq, value: 48 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const mcg_config_t mcgConfig_BOARD_BootClockRUN = + { + .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */ + .irclkEnableMode = MCG_IRCLK_DISABLE, /* MCGIRCLK disabled */ + .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */ + .fcrdiv = 0x1U, /* Fast IRC divider: divided by 2 */ + .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */ + .drs = kMCG_DrsLow, /* Low frequency range */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */ + .oscsel = kMCG_OscselIrc, /* Selects 48 MHz IRC Oscillator */ + .pll0Config = + { + .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */ + .prdiv = 0x3U, /* PLL Reference divider: divided by 4 */ + .vdiv = 0x0U, /* VCO divider: multiplied by 16 */ + }, + }; +const sim_clock_config_t simConfig_BOARD_BootClockRUN = + { + .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */ + .pllFllDiv = 1, /* PLLFLLSEL clock divider divisor: divided by 2 */ + .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */ + .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */ + .clkdiv1 = 0x15051000U, /* SIM_CLKDIV1 - OUTDIV1: /2, OUTDIV2: /6, OUTDIV4: /6, OUTDIV5: /2 */ + }; +const osc_config_t oscConfig_BOARD_BootClockRUN = + { + .freq = 0U, /* Oscillator frequency: 0Hz */ + .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ + .workMode = kOSC_ModeExt, /* Use external clock */ + .oscerConfig = + { + .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */ + .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */ + } + }; + +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Set the system clock dividers in SIM to safe value. */ + CLOCK_SetSimSafeDivs(); + /* Configure FLL external reference divider (FRDIV). */ + CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv); + /* Set MCG to PEE mode. */ + CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, + kMCG_PllClkSelPll0, + &mcgConfig_BOARD_BootClockRUN.pll0Config); + /* Set the clock configuration in SIM module. */ + CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN); + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; + /* Set LPUART clock source. */ + CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_PLLFLLSEL_CLK); +} + diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/fsl_clock_config.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/fsl_clock_config.h new file mode 100755 index 0000000000..85363ad469 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/fsl_clock_config.h @@ -0,0 +1,64 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */ + +/*! @brief MCG set for BOARD_BootClockRUN configuration. + */ +extern const mcg_config_t mcgConfig_BOARD_BootClockRUN; +/*! @brief SIM module set for BOARD_BootClockRUN configuration. + */ +extern const sim_clock_config_t simConfig_BOARD_BootClockRUN; +/*! @brief OSC set for BOARD_BootClockRUN configuration. + */ +extern const osc_config_t oscConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/mbed_overrides.c new file mode 100644 index 0000000000..d2f3061e6c --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/mbed_overrides.c @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "fsl_smc.h" +#include "fsl_rcm.h" +#include "fsl_pmc.h" +#include "fsl_clock_config.h" + +//!< this contains the wakeup source +rcm_reset_source_t kinetisResetSource; + +// called before main +void mbed_sdk_init() { + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); + + // check the power mode source + kinetisResetSource = (rcm_reset_source_t) (RCM_GetPreviousResetSources(RCM)); + // if waking up from VLLS, do some cleanup + if (kinetisResetSource & kRCM_SourceWakeup) { + PMC_ClearPeriphIOIsolationFlag(PMC); + NVIC_ClearPendingIRQ(LLWU_IRQn); + } + + BOARD_BootClockRUN(); +} + +// Change the NMI pin to an input. This allows NMI pin to +// be used as a low power mode wakeup. The application will +// need to change the pin back to NMI_b or wakeup only occurs once! +void NMI_Handler(void) +{ + gpio_t gpio; + gpio_init_in(&gpio, PTA4); +} + +#ifdef DEVICE_RTC +// Enable the RTC oscillator if available on the board +void rtc_setup_oscillator(RTC_Type *base) +{ + /* Enable the RTC oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; +} +#endif \ No newline at end of file diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/serial_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/serial_api.c index ca2cea38f8..40abd9d4e1 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/serial_api.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/serial_api.c @@ -47,8 +47,30 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) obj->index = pinmap_merge(uart_tx, uart_rx); MBED_ASSERT((int)obj->index != NC); + // since the LPuart initialization depends very much on the source clock and its + // frequency, we do a check here and retrieve the frequency accordingly + // The CLOCK_SetLpuartSrc() is already done during clock init. + uint32_t lpuart_src_freq; + switch (SIM->SOPT2 & SIM_SOPT2_LPUARTSRC_MASK) { + case SIM_SOPT2_LPUARTSRC(3U): { + lpuart_src_freq = CLOCK_GetInternalRefClkFreq(); + break; + } + case SIM_SOPT2_LPUARTSRC(2U): { + lpuart_src_freq = CLOCK_GetOsc0ErClkFreq(); + break; + } + case SIM_SOPT2_LPUARTSRC(1U): { + lpuart_src_freq = CLOCK_GetPllFllSelClkFreq(); + break; + } + default: { /* Set the LPUART clock source */ - CLOCK_SetLpuartClock(2U); + CLOCK_SetLpuartClock(1U); + lpuart_src_freq = CLOCK_GetFreq(uart_clocks[obj->index]); + break; + } + } lpuart_config_t config; LPUART_GetDefaultConfig(&config); @@ -56,7 +78,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) config.enableTx = false; config.enableRx = false; - LPUART_Init(uart_addrs[obj->index], &config, CLOCK_GetFreq(uart_clocks[obj->index])); + LPUART_Init(uart_addrs[obj->index], &config, lpuart_src_freq); pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(rx, PinMap_UART_RX); diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/trng_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/trng_api.c new file mode 100644 index 0000000000..16c3448415 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/trng_api.c @@ -0,0 +1,52 @@ +/* + * Hardware entropy collector for the K66F, using Freescale's RNGA + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* + * Reference: "K66 Sub-Family Reference Manual, Rev. 2", chapter 38 + */ + +#include +#include "cmsis.h" +#include "fsl_trng.h" +#include "trng_api.h" + +void trng_init(trng_t *obj) +{ + (void)obj; + trng_config_t trngConfig; + TRNG_GetDefaultConfig(&trngConfig); + TRNG_Init(TRNG0, &trngConfig); +} + +void trng_free(trng_t *obj) +{ + (void)obj; + TRNG_Deinit(TRNG0); +} + +int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) +{ + (void)obj; + + if(TRNG_GetRandomData(TRNG0, output, length) != kStatus_Success) return -1; + *output_length = length; + + return 0; +} diff --git a/targets/targets.json b/targets/targets.json index 4916e55eaf..03267d8d4b 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -520,10 +520,16 @@ "is_disk_virtual": true, "inherits": ["Target"], "detect_code": ["0218"], - "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], + "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"], "release_versions": ["2", "5"], "device_name": "MKL82Z128xxx7" }, + "USENSE": { + "inherits": ["KL82Z"], + "device_has_add": ["LOWPOWERTIMER"], + "extra_labels_remove": ["FRDM"], + "supported_form_factors": [] + }, "KW24D": { "supported_form_factors": ["ARDUINO"], "core": "Cortex-M4", @@ -629,10 +635,15 @@ "macros": ["CPU_MK82FN256VDC15", "FSL_RTOS_MBED"], "inherits": ["Target"], "detect_code": ["0217"], - "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], + "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"], "release_versions": ["2", "5"], "device_name": "MK82FN256xxx15" }, + "UBRIDGE": { + "inherits": ["K82F"], + "extra_labels_remove": ["FRDM"], + "supported_form_factors": [] + }, "NUCLEO_F030R8": { "supported_form_factors": ["ARDUINO", "MORPHO"], "core": "Cortex-M0",