diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_GENERIC_H745I/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_GENERIC_H745I/PeripheralPins.c
deleted file mode 100644
index d60c91c698..0000000000
--- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_GENERIC_H745I/PeripheralPins.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/* mbed Microcontroller Library
- * SPDX-License-Identifier: BSD-3-Clause
- ******************************************************************************
- *
- * Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-#include "PeripheralPins.h"
-#include "mbed_toolchain.h"
-
-
-
-//*** ADC ***
-
-MBED_WEAK const PinMap PinMap_ADC[] = {
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
- {NC, NC, 0}
-};
-
-//*** DAC ***
-
-MBED_WEAK const PinMap PinMap_DAC[] = {
- {NC, NC, 0}
-};
-
-//*** I2C ***
-
-MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
- {NC, NC, 0}
-};
-
-//*** PWM ***
-
-MBED_WEAK const PinMap PinMap_PWM[] = {
- {NC, NC, 0}
-};
-
-//*** SERIAL ***
-
-MBED_WEAK const PinMap PinMap_UART_TX[] = {
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_UART_RX[] = {
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_UART_RTS[] = {
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_UART_CTS[] = {
- {NC, NC, 0}
-};
-
-//*** SPI ***
-
-MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
- {NC, NC, 0}
-};
-
-//*** CAN ***
-
-MBED_WEAK const PinMap PinMap_CAN_RD[] = {
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_CAN_TD[] = {
- {NC, NC, 0}
-};
-
-//*** QUADSPI ***
-
-MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = {
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = {
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = {
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = {
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
- {NC, NC, 0}
-};
-
-//*** USBDEVICE ***
-
-MBED_WEAK const PinMap PinMap_USB_FS[] = {
- {NC, NC, 0}
-};
-
-//*** USBDEVICE ***
-
-MBED_WEAK const PinMap PinMap_USB_HS[] = {
- {NC, NC, 0}
-};
diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_GENERIC_H745I/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_GENERIC_H745I/PinNames.h
deleted file mode 100644
index f20203027a..0000000000
--- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/TARGET_GENERIC_H745I/PinNames.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* mbed Microcontroller Library
- * SPDX-License-Identifier: BSD-3-Clause
- ******************************************************************************
- *
- * Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-#include "PinNamesTypes.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- ALT0 = 0x100,
- ALT1 = 0x200,
- ALT2 = 0x300,
- ALT3 = 0x400,
- ALT4 = 0x500
-} ALTx;
-
-typedef enum {
-
- // ADC internal channels
- ADC_TEMP = 0xF0,
- ADC_VREF = 0xF1,
- ADC_VBAT = 0xF2,
-
- // Arduino connector namings
-
- // STDIO for console print
-#ifdef MBED_CONF_TARGET_STDIO_UART_TX
- STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
-#else
- STDIO_UART_TX = 0, // Virtual Com Port
-#endif
-#ifdef MBED_CONF_TARGET_STDIO_UART_RX
- STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
-#else
- STDIO_UART_RX = 0, // Virtual Com Port
-#endif
-
- // Generic signals namings
- LED1 = 0, // platform/source/mbed_board.c
-
- // Standardized button names
- // BUTTON1 = USER_BUTTON,
-
-
- USBTX = STDIO_UART_TX, // hal/mbed_pinmap_default.cpp
- USBRX = STDIO_UART_RX, // hal/mbed_pinmap_default.cpp
-
- // I2C_SCL = D15,
- // I2C_SDA = D14,
- // SPI_MOSI = D11,
- // SPI_MISO = D12,
- // SPI_SCK = D13,
- // SPI_CS = D10,
- // PWM_OUT = D9,
-
- // Not connected
- NC = (int)0xFFFFFFFF
-} PinName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/system_stm32h7xx.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/system_stm32h7xx.c
deleted file mode 100644
index 3af62b6959..0000000000
--- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H745xI/system_stm32h7xx.c
+++ /dev/null
@@ -1,371 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32h7xx_dualcore_boot_cm4_cm7.c
- * @author MCD Application Team
- * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
- * This provides system initialization template function is case of
- * an application using a dual core STM32H7 device where
- * Cortex-M7 and Cortex-M4 boot are enabled at the FLASH option bytes
- *
- * This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32h7xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variables SystemD1Clock and SystemD2Clock
- * and must be called whenever the core clock is changed
- * during program execution.
- *
- *
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32h7xx_system
- * @{
- */
-
-/** @addtogroup STM32H7xx_System_Private_Includes
- * @{
- */
-
-#include "stm32h7xx.h"
-#include
-#include "nvic_addr.h" // MBED PATCH for Bootloader
-
-#if !defined (HSE_VALUE)
-#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined (CSI_VALUE)
-#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* CSI_VALUE */
-
-#if !defined (HSI_VALUE)
-#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_Defines
- * @{
- */
-
-/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
-/******************************************************************************/
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_Variables
- * @{
- */
-/* This variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
- Note: If you use this function to configure the system clock; then there
- is no need to call the 2 first functions listed above, since SystemCoreClock
- variable is updated automatically.
-*/
-#if defined(CORE_CM7)
-#define SystemCoreClock SystemD1Clock
-#elif defined(CORE_CM4)
-#define SystemCoreClock SystemD2Clock
-#else
-#error "Wrong core selection"
-#endif
-uint32_t SystemD1Clock = 64000000;
-uint32_t SystemD2Clock = 64000000;
-const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_Functions
- * @{
- */
-
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the FPU setting and vector table location
- * configuration.
- * @param None
- * @retval None
- */
-void SystemInit(void)
-{
- /* FPU settings ------------------------------------------------------------*/
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << (10 * 2)) | (3UL << (11 * 2))); /* set CP10 and CP11 Full Access */
-#endif
-
- /*SEVONPEND enabled so that an interrupt coming from the CPU(n) interrupt signal is
- detectable by the CPU after a WFI/WFE instruction.*/
- SCB->SCR |= SCB_SCR_SEVONPEND_Pos;
-
-#ifdef CORE_CM7
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= RCC_CR_HSION;
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
-
- /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
- RCC->CR &= 0xEAF6ED7FU;
-
- /* Reset D1CFGR register */
- RCC->D1CFGR = 0x00000000;
-
- /* Reset D2CFGR register */
- RCC->D2CFGR = 0x00000000;
-
- /* Reset D3CFGR register */
- RCC->D3CFGR = 0x00000000;
-
- /* Reset PLLCKSELR register */
- RCC->PLLCKSELR = 0x00000000;
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x00000000;
- /* Reset PLL1DIVR register */
- RCC->PLL1DIVR = 0x00000000;
- /* Reset PLL1FRACR register */
- RCC->PLL1FRACR = 0x00000000;
-
- /* Reset PLL2DIVR register */
- RCC->PLL2DIVR = 0x00000000;
-
- /* Reset PLL2FRACR register */
-
- RCC->PLL2FRACR = 0x00000000;
- /* Reset PLL3DIVR register */
- RCC->PLL3DIVR = 0x00000000;
-
- /* Reset PLL3FRACR register */
- RCC->PLL3FRACR = 0x00000000;
-
- /* Reset HSEBYP bit */
- RCC->CR &= 0xFFFBFFFFU;
-
- /* Disable all interrupts */
- RCC->CIER = 0x00000000;
-
- /* Enable CortexM7 HSEM EXTI line (line 78)*/
- EXTI_D2->EMR3 |= 0x4000UL;
-
-
- if ((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) {
- /* if stm32h7 revY*/
- /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
- *((__IO uint32_t *)0x51008108) = 0x000000001U;
- }
-
-#endif /* CORE_CM7*/
-
-#ifdef CORE_CM4
-
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ // MBED PATCH for Bootloader
-#endif
-
-#else
-#ifdef CORE_CM7
-
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM */
-#else
- SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ // MBED PATCH for Bootloader
-#endif
-
-#else
-#error Please #define CORE_CM4 or CORE_CM7
-#endif
-#endif
-
-}
-
-/**
- * @brief Update SystemD1Clock and SystemD2Clock variables according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock , it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is CSI, SystemD1Clock will contain the CSI_VALUE(*)
- * - If SYSCLK source is HSI, SystemD1Clock will contain the HSI_VALUE(**)
- * - If SYSCLK source is HSE, SystemD1Clock will contain the HSE_VALUE(***)
- * - If SYSCLK source is PLL, SystemD1Clock will contain the CSI_VALUE(*),
- * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
- *
- * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
- * 4 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
- * 64 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
- * 25 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate(void)
-{
- uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
- float_t fracn1, pllvco;
-
- /* Get SYSCLK source -------------------------------------------------------*/
-
- switch (RCC->CFGR & RCC_CFGR_SWS) {
- case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
- SystemD1Clock = (uint32_t)(HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
-
- break;
-
- case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
- SystemD1Clock = CSI_VALUE;
- break;
-
- case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
- SystemD1Clock = HSE_VALUE;
- break;
-
- case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
- SYSCLK = PLL_VCO / PLLR
- */
- pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
- pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ;
- pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
- fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
-
- if (pllm != 0U) {
- switch (pllsource) {
- case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
-
- hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3)) ;
- pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
-
- break;
-
- case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
- pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
- break;
-
- case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
- pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
- break;
-
- default:
- pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
- break;
- }
- pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ;
- SystemD1Clock = (uint32_t)(float_t)(pllvco / (float_t)pllp);
- } else {
- SystemD1Clock = 0U;
- }
- break;
-
- default:
- SystemD1Clock = CSI_VALUE;
- break;
- }
-
- /* Compute SystemClock frequency --------------------------------------------------*/
- tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos];
-
- /* SystemD1Clock frequency : CM7 CPU frequency */
- SystemD1Clock >>= tmp;
-
- /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
- SystemD2Clock = (SystemD1Clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
-
-}
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/targets.json b/targets/targets.json
index 50f3df2677..3e9c54cf82 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -2811,7 +2811,7 @@
"device_name": "STM32H743ZI",
"bootloader_supported": true
},
- "MCU_STM32H745I": {
+ "MCU_STM32H745xI": {
"inherits": [
"MCU_STM32"
],
@@ -2850,9 +2850,12 @@
"bootloader_supported": true,
"public": false
},
- "MCU_STM32H745I_CM4": {
+ "MCU_STM32H745xI_CM4": {
"inherits": [
- "MCU_STM32H745I"
+ "MCU_STM32H745xI"
+ ],
+ "extra_labels_add": [
+ "STM32H745xI_CM4"
],
"core": "Cortex-M4F",
"mbed_rom_start": "0x08100000",
@@ -2864,17 +2867,12 @@
],
"public": false
},
- "GENERIC_H745I_CM4": {
+ "MCU_STM32H745xI_CM7": {
"inherits": [
- "MCU_STM32H745I_CM4"
+ "MCU_STM32H745xI"
],
"extra_labels_add": [
- "GENERIC_H745I"
- ]
- },
- "MCU_STM32H745I_CM7": {
- "inherits": [
- "MCU_STM32H745I"
+ "STM32H745xI_CM7"
],
"core": "Cortex-M7FD",
"mbed_rom_start": "0x08000000",
@@ -2886,14 +2884,6 @@
],
"public": false
},
- "GENERIC_H745I_CM7": {
- "inherits": [
- "MCU_STM32H745I_CM7"
- ],
- "extra_labels_add": [
- "GENERIC_H745I"
- ]
- },
"MCU_STM32H747xI": {
"inherits": [
"MCU_STM32"