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[STM32F4xx] update of STM32CubeF4 to version 1.5 - part 4 

Update of all files in target specific folders to new STM32CubeF4
version
pull/1076/head
ohagendorf 2015-04-26 01:52:07 +02:00
parent 5b2d25f201
commit 03ff51f74a
43 changed files with 4842 additions and 528 deletions
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6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/TOOLCHAIN_GCC_ARM/startup_stm32f401xc.s
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file startup_stm32f401xc.s * @file startup_stm32f401xc.s
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief STM32F401xCxx Devices vector table for Atollic TrueSTUDIO toolchain. * @brief STM32F401xCxx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs: * This module performs:
* - Set the initial SP * - Set the initial SP
@ -16,7 +16,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:

65
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f401xe.h → libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f401xc.h
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@ -1,10 +1,10 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f401xe.h * @file stm32f401xc.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS STM32F401xExx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F401xCxx Device Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
* - Data structures and the address mapping for all peripherals * - Data structures and the address mapping for all peripherals
@ -14,7 +14,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -45,12 +45,12 @@
* @{ * @{
*/ */
/** @addtogroup stm32f401xe /** @addtogroup stm32f401xc
* @{ * @{
*/ */
#ifndef __STM32F401xE_H #ifndef __STM32F401xC_H
#define __STM32F401xE_H #define __STM32F401xC_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -290,8 +290,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef; } GPIO_TypeDef;
@ -536,7 +535,7 @@ typedef struct
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef; } WWDG_TypeDef;
/** /**
* @brief __USB_OTG_Core_register * @brief __USB_OTG_Core_register
*/ */
@ -675,7 +674,7 @@ USB_OTG_HostChannelTypeDef;
#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */ #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */ #define FLASH_END ((uint32_t)0x0803FFFF) /*!< FLASH end address */
/* Legacy defines */ /* Legacy defines */
#define SRAM_BASE SRAM1_BASE #define SRAM_BASE SRAM1_BASE
@ -1423,6 +1422,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/ /******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@ -1445,6 +1447,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/ /****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@ -1467,6 +1472,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/ /****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@ -1489,6 +1497,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/ /****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@ -1511,6 +1522,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/ /******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@ -1533,6 +1547,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
@ -1954,7 +1971,7 @@ USB_OTG_HostChannelTypeDef;
#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000) #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000) #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
/****************** Bit definition for GPIO_LCKR register ********************/ /****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
@ -2125,7 +2142,7 @@ USB_OTG_HostChannelTypeDef;
#define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */ #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
#define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */ #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */
#define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */ #define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */ #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */ #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
@ -4511,14 +4528,14 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == I2C3)) ((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/ /******************************** I2S Instances *******************************/
#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3)) ((INSTANCE) == SPI3))
/*************************** I2S Extended Instances ***************************/ /*************************** I2S Extended Instances ***************************/
#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \ #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \ ((INSTANCE) == SPI3) || \
((INSTANCE) == I2S2ext) || \ ((INSTANCE) == I2S2ext) || \
((INSTANCE) == I2S3ext)) ((INSTANCE) == I2S3ext))
/****************************** RTC Instances *********************************/ /****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
@ -4728,6 +4745,14 @@ USB_OTG_HostChannelTypeDef;
/****************************** WWDG Instances ********************************/ /****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/****************************** SDIO Instances ********************************/
#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
/****************************** USB Exported Constants ************************/
#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
/** /**
* @} * @}
@ -4745,7 +4770,7 @@ USB_OTG_HostChannelTypeDef;
} }
#endif /* __cplusplus */ #endif /* __cplusplus */
#endif /* __STM32F401xE_H */ #endif /* __STM32F401xC_H */

31
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f4xx.h
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx.h * @file stm32f4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -63,13 +63,20 @@
/** @addtogroup Library_configuration_section /** @addtogroup Library_configuration_section
* @{ * @{
*/ */
/**
* @brief STM32 Family
*/
#if !defined (STM32F4)
#define STM32F4
#endif /* STM32F4 */
/* Uncomment the line below according to the target STM32 device used in your /* Uncomment the line below according to the target STM32 device used in your
application application
*/ */
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ #if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@ -80,9 +87,11 @@
STM32F439NI, STM32F429IG and STM32F429II Devices */ STM32F439NI, STM32F429IG and STM32F429II Devices */
/* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
STM32F439NI, STM32F439IG and STM32F439II Devices */ STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ #define STM32F401xC /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
#define STM32F401xE /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
/* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */ /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
/* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
and STM32F446ZE Devices */
#endif #endif
/* Tip: To avoid modifying this file each time you need to switch between these /* Tip: To avoid modifying this file each time you need to switch between these
@ -94,14 +103,14 @@
In this case, these drivers will not be included and the application code will In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers be based on direct access to peripherals registers
*/ */
#define USE_HAL_DRIVER #define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V2.1.0 * @brief CMSIS Device version number V2.3.0
*/ */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ #define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
@ -139,6 +148,8 @@
#include "stm32f401xe.h" #include "stm32f401xe.h"
#elif defined(STM32F411xE) #elif defined(STM32F411xE)
#include "stm32f411xe.h" #include "stm32f411xe.h"
#elif defined(STM32F446xx)
#include "stm32f446xx.h"
#else #else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif #endif

406
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f4xx_hal_conf.h Normal file
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@ -0,0 +1,406 @@
/**
******************************************************************************
* @file stm32f4xx_hal_conf.h
* @author MCD Application Team
* @version V1.2.1
* @date 13-March-2015
* @brief HAL configuration file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CONF_H
#define __STM32F4xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_CAN_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
#define HAL_CRYP_MODULE_ENABLED
#define HAL_DAC_MODULE_ENABLED
#define HAL_DCMI_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
/* #define HAL_DMA2D_MODULE_ENABLED */
#define HAL_ETH_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_NAND_MODULE_ENABLED
#define HAL_NOR_MODULE_ENABLED
#define HAL_PCCARD_MODULE_ENABLED
#define HAL_SRAM_MODULE_ENABLED
/* #define HAL_SDRAM_MODULE_ENABLED */
#define HAL_HASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_LTDC_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
/* #define HAL_SAI_MODULE_ENABLED */
#define HAL_SD_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_PCD_MODULE_ENABLED
#define HAL_HCD_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define INSTRUCTION_CACHE_ENABLE 1
#define DATA_CACHE_ENABLE 1
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1 */
/* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2
#define MAC_ADDR1 0
#define MAC_ADDR2 0
#define MAC_ADDR3 0
#define MAC_ADDR4 0
#define MAC_ADDR5 0
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* DP83848 PHY Address*/
#define DP83848_PHY_ADDRESS 0x01
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
#define PHY_READ_TO ((uint32_t)0x0000FFFF)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f4xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f4xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f4xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f4xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f4xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f4xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32f4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32f4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32f4xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32f4xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f4xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f4xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f4xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_SDRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sdram.h"
#endif /* HAL_SDRAM_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32f4xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f4xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32f4xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32f4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32f4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32f4xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f4xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

7
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/system_stm32f4xx.h
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@ -2,13 +2,13 @@
****************************************************************************** ******************************************************************************
* @file system_stm32f4xx.h * @file system_stm32f4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -103,7 +103,6 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Cloc
extern void SystemInit(void); extern void SystemInit(void);
extern void SystemCoreClockUpdate(void); extern void SystemCoreClockUpdate(void);
extern void SetSysClock(void); extern void SetSysClock(void);
/** /**
* @} * @}
*/ */

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.s
View File

@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file startup_stm32f429xx.s * @file startup_stm32f429xx.s
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief STM32F429xx Devices vector table for Atollic TrueSTUDIO toolchain. * @brief STM32F429xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs: * This module performs:
* - Set the initial SP * - Set the initial SP
@ -16,7 +16,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:

274
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f429xx.h
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32f429xx.h * @file stm32f429xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS STM32F429xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F429xx Device Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -14,7 +14,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -598,8 +598,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef; } GPIO_TypeDef;
@ -1940,72 +1939,128 @@ USB_OTG_HostChannelTypeDef;
#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */ #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
/******************* Bit definition for CAN_FM1R register *******************/ /******************* Bit definition for CAN_FM1R register *******************/
#define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */ #define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
#define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */ #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
#define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */ #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
#define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */ #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
#define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */ #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
#define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */ #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
#define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */ #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
#define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */ #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
#define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */ #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
#define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */ #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
#define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */ #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
#define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */ #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
#define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */ #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
#define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */ #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
#define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */ #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
/******************* Bit definition for CAN_FS1R register *******************/ /******************* Bit definition for CAN_FS1R register *******************/
#define CAN_FS1R_FSC ((uint32_t)0x3FFF) /*!<Filter Scale Configuration */ #define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
#define CAN_FS1R_FSC0 ((uint32_t)0x0001) /*!<Filter Scale Configuration bit 0 */ #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
#define CAN_FS1R_FSC1 ((uint32_t)0x0002) /*!<Filter Scale Configuration bit 1 */ #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
#define CAN_FS1R_FSC2 ((uint32_t)0x0004) /*!<Filter Scale Configuration bit 2 */ #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
#define CAN_FS1R_FSC3 ((uint32_t)0x0008) /*!<Filter Scale Configuration bit 3 */ #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
#define CAN_FS1R_FSC4 ((uint32_t)0x0010) /*!<Filter Scale Configuration bit 4 */ #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
#define CAN_FS1R_FSC5 ((uint32_t)0x0020) /*!<Filter Scale Configuration bit 5 */ #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
#define CAN_FS1R_FSC6 ((uint32_t)0x0040) /*!<Filter Scale Configuration bit 6 */ #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
#define CAN_FS1R_FSC7 ((uint32_t)0x0080) /*!<Filter Scale Configuration bit 7 */ #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
#define CAN_FS1R_FSC8 ((uint32_t)0x0100) /*!<Filter Scale Configuration bit 8 */ #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
#define CAN_FS1R_FSC9 ((uint32_t)0x0200) /*!<Filter Scale Configuration bit 9 */ #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
#define CAN_FS1R_FSC10 ((uint32_t)0x0400) /*!<Filter Scale Configuration bit 10 */ #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
#define CAN_FS1R_FSC11 ((uint32_t)0x0800) /*!<Filter Scale Configuration bit 11 */ #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
#define CAN_FS1R_FSC12 ((uint32_t)0x1000) /*!<Filter Scale Configuration bit 12 */ #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
#define CAN_FS1R_FSC13 ((uint32_t)0x2000) /*!<Filter Scale Configuration bit 13 */ #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
/****************** Bit definition for CAN_FFA1R register *******************/ /****************** Bit definition for CAN_FFA1R register *******************/
#define CAN_FFA1R_FFA ((uint32_t)0x3FFF) /*!<Filter FIFO Assignment */ #define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
#define CAN_FFA1R_FFA0 ((uint32_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */ #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
#define CAN_FFA1R_FFA1 ((uint32_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */ #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
#define CAN_FFA1R_FFA2 ((uint32_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */ #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
#define CAN_FFA1R_FFA3 ((uint32_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */ #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
#define CAN_FFA1R_FFA4 ((uint32_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */ #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
#define CAN_FFA1R_FFA5 ((uint32_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */ #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
#define CAN_FFA1R_FFA6 ((uint32_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */ #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
#define CAN_FFA1R_FFA7 ((uint32_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */ #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
#define CAN_FFA1R_FFA8 ((uint32_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */ #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
#define CAN_FFA1R_FFA9 ((uint32_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */ #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
#define CAN_FFA1R_FFA10 ((uint32_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */ #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
#define CAN_FFA1R_FFA11 ((uint32_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */ #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
#define CAN_FFA1R_FFA12 ((uint32_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */ #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
#define CAN_FFA1R_FFA13 ((uint32_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */ #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
/******************* Bit definition for CAN_FA1R register *******************/ /******************* Bit definition for CAN_FA1R register *******************/
#define CAN_FA1R_FACT ((uint32_t)0x3FFF) /*!<Filter Active */ #define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
#define CAN_FA1R_FACT0 ((uint32_t)0x0001) /*!<Filter 0 Active */ #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
#define CAN_FA1R_FACT1 ((uint32_t)0x0002) /*!<Filter 1 Active */ #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
#define CAN_FA1R_FACT2 ((uint32_t)0x0004) /*!<Filter 2 Active */ #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
#define CAN_FA1R_FACT3 ((uint32_t)0x0008) /*!<Filter 3 Active */ #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
#define CAN_FA1R_FACT4 ((uint32_t)0x0010) /*!<Filter 4 Active */ #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
#define CAN_FA1R_FACT5 ((uint32_t)0x0020) /*!<Filter 5 Active */ #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
#define CAN_FA1R_FACT6 ((uint32_t)0x0040) /*!<Filter 6 Active */ #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
#define CAN_FA1R_FACT7 ((uint32_t)0x0080) /*!<Filter 7 Active */ #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
#define CAN_FA1R_FACT8 ((uint32_t)0x0100) /*!<Filter 8 Active */ #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
#define CAN_FA1R_FACT9 ((uint32_t)0x0200) /*!<Filter 9 Active */ #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
#define CAN_FA1R_FACT10 ((uint32_t)0x0400) /*!<Filter 10 Active */ #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
#define CAN_FA1R_FACT11 ((uint32_t)0x0800) /*!<Filter 11 Active */ #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
#define CAN_FA1R_FACT12 ((uint32_t)0x1000) /*!<Filter 12 Active */ #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
#define CAN_FA1R_FACT13 ((uint32_t)0x2000) /*!<Filter 13 Active */ #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
/******************* Bit definition for CAN_F0R1 register *******************/ /******************* Bit definition for CAN_F0R1 register *******************/
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
@ -3463,6 +3518,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/ /******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@ -3485,6 +3543,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/ /****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@ -3507,6 +3568,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/ /****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@ -3529,6 +3593,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/ /****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@ -3551,6 +3618,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/ /******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@ -3573,6 +3643,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
@ -3984,6 +4057,12 @@ USB_OTG_HostChannelTypeDef;
#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ #define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ #define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ #define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ #define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ #define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@ -4023,6 +4102,12 @@ USB_OTG_HostChannelTypeDef;
#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ #define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ #define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ #define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ #define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/ #define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
@ -4062,6 +4147,12 @@ USB_OTG_HostChannelTypeDef;
#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ #define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ #define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ #define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ #define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ #define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@ -4101,6 +4192,12 @@ USB_OTG_HostChannelTypeDef;
#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ #define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ #define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ #define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ #define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ #define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@ -4665,7 +4762,7 @@ USB_OTG_HostChannelTypeDef;
#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */ #define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */ #define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */ #define FMC_SDCMR_MODE_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */ #define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
@ -5572,7 +5669,7 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000) #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000) #define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000) #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000) #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/ /******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001) #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
@ -5879,7 +5976,11 @@ USB_OTG_HostChannelTypeDef;
#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00) #define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
#define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000) #define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
#define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000) #define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)
#define RCC_DCKCFGR_SAI1ASRC_0 ((uint32_t)0x00100000)
#define RCC_DCKCFGR_SAI1ASRC_1 ((uint32_t)0x00200000)
#define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000) #define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
#define RCC_DCKCFGR_SAI1BSRC_0 ((uint32_t)0x00400000)
#define RCC_DCKCFGR_SAI1BSRC_1 ((uint32_t)0x00800000)
#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000) #define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
@ -6320,16 +6421,17 @@ USB_OTG_HostChannelTypeDef;
#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */ #define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */ #define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
#define SAI_xCR1_MCKDIV ((uint32_t)0x00780000) /*!<MCKDIV[3:0] (Master ClocK Divider) */ #define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000) /*!<Bit 0 */ #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000) /*!<Bit 1 */ #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000) /*!<Bit 2 */ #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000) /*!<Bit 3 */ #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
/******************* Bit definition for SAI_xCR2 register *******************/ /******************* Bit definition for SAI_xCR2 register *******************/
#define SAI_xCR2_FTH ((uint32_t)0x00000003) /*!<FTH[1:0](Fifo THreshold) */ #define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */
#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */ #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */ #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */ #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */ #define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
@ -8590,14 +8692,14 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == I2C3)) ((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/ /******************************** I2S Instances *******************************/
#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3)) ((INSTANCE) == SPI3))
/*************************** I2S Extended Instances ***************************/ /*************************** I2S Extended Instances ***************************/
#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \ #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \ ((INSTANCE) == SPI3) || \
((INSTANCE) == I2S2ext) || \ ((INSTANCE) == I2S2ext) || \
((INSTANCE) == I2S3ext)) ((INSTANCE) == I2S3ext))
/****************************** LTDC Instances ********************************/ /****************************** LTDC Instances ********************************/
#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
@ -8885,6 +8987,20 @@ USB_OTG_HostChannelTypeDef;
/****************************** WWDG Instances ********************************/ /****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/****************************** SDIO Instances ********************************/
#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
/****************************** USB Exported Constants ************************/
#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12
#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
/******************************************************************************/ /******************************************************************************/
/* For a painless codes migration between the STM32F4xx device product */ /* For a painless codes migration between the STM32F4xx device product */
/* lines, the aliases defined below are put in place to overcome the */ /* lines, the aliases defined below are put in place to overcome the */

30
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f4xx.h
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx.h * @file stm32f4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -63,27 +63,35 @@
/** @addtogroup Library_configuration_section /** @addtogroup Library_configuration_section
* @{ * @{
*/ */
/**
* @brief STM32 Family
*/
#if !defined (STM32F4)
#define STM32F4
#endif /* STM32F4 */
/* Uncomment the line below according to the target STM32 device used in your /* Uncomment the line below according to the target STM32 device used in your
application application
*/ */
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ #if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
/* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
/* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
/* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
#define STM32F429xx /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, #define STM32F429xx /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
STM32F439NI, STM32F429IG and STM32F429II Devices */ STM32F439NI, STM32F429IG and STM32F429II Devices */
/* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
STM32F439NI, STM32F439IG and STM32F439II Devices */ STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
/* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */ /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
/* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
and STM32F446ZE Devices */
#endif #endif
/* Tip: To avoid modifying this file each time you need to switch between these /* Tip: To avoid modifying this file each time you need to switch between these
@ -95,14 +103,14 @@
In this case, these drivers will not be included and the application code will In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers be based on direct access to peripherals registers
*/ */
#define USE_HAL_DRIVER #define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V2.1.0 * @brief CMSIS Device version number V2.3.0
*/ */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ #define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
@ -140,6 +148,8 @@
#include "stm32f401xe.h" #include "stm32f401xe.h"
#elif defined(STM32F411xE) #elif defined(STM32F411xE)
#include "stm32f411xe.h" #include "stm32f411xe.h"
#elif defined(STM32F446xx)
#include "stm32f446xx.h"
#else #else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif #endif

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@ -0,0 +1,406 @@
/**
******************************************************************************
* @file stm32f4xx_hal_conf.h
* @author MCD Application Team
* @version V1.2.1
* @date 13-March-2015
* @brief HAL configuration file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CONF_H
#define __STM32F4xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_CAN_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
/* #define HAL_CRYP_MODULE_ENABLED */
#define HAL_DAC_MODULE_ENABLED
#define HAL_DCMI_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_DMA2D_MODULE_ENABLED
#define HAL_ETH_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_NAND_MODULE_ENABLED
#define HAL_NOR_MODULE_ENABLED
#define HAL_PCCARD_MODULE_ENABLED
#define HAL_SRAM_MODULE_ENABLED
#define HAL_SDRAM_MODULE_ENABLED
#define HAL_HASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_LTDC_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_SAI_MODULE_ENABLED
#define HAL_SD_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_PCD_MODULE_ENABLED
#define HAL_HCD_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define INSTRUCTION_CACHE_ENABLE 1
#define DATA_CACHE_ENABLE 1
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1 */
/* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2
#define MAC_ADDR1 0
#define MAC_ADDR2 0
#define MAC_ADDR3 0
#define MAC_ADDR4 0
#define MAC_ADDR5 0
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* DP83848 PHY Address*/
#define DP83848_PHY_ADDRESS 0x01
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
#define PHY_READ_TO ((uint32_t)0x0000FFFF)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f4xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f4xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f4xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f4xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f4xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f4xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32f4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32f4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32f4xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32f4xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f4xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f4xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f4xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_SDRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sdram.h"
#endif /* HAL_SDRAM_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32f4xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f4xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32f4xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32f4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32f4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32f4xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f4xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

7
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.h
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@ -2,13 +2,13 @@
****************************************************************************** ******************************************************************************
* @file system_stm32f4xx.h * @file system_stm32f4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -103,7 +103,6 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Cloc
extern void SystemInit(void); extern void SystemInit(void);
extern void SystemCoreClockUpdate(void); extern void SystemCoreClockUpdate(void);
extern void SetSysClock(void); extern void SetSysClock(void);
/** /**
* @} * @}
*/ */

53
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f411xe.h
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@ -2,19 +2,19 @@
****************************************************************************** ******************************************************************************
* @file stm32f411xe.h * @file stm32f411xe.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
* - Data structures and the address mapping for all peripherals * - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition * - Peripheral's registers declarations and bits definition
* - Macros to access peripheral’s registers hardware * - Macros to access peripheral’s registers hardware
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -45,12 +45,12 @@
* @{ * @{
*/ */
/** @addtogroup stm32f411xe /** @addtogroup stm32f401xe
* @{ * @{
*/ */
#ifndef __STM32F411xE_H #ifndef __STM32F401xE_H
#define __STM32F411xE_H #define __STM32F401xE_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -291,8 +291,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef; } GPIO_TypeDef;
@ -1427,6 +1426,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/ /******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@ -1449,6 +1451,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/ /****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@ -1471,6 +1476,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/ /****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@ -1493,6 +1501,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/ /****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@ -1515,6 +1526,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/ /******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@ -1537,6 +1551,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
@ -4531,17 +4548,17 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == I2C3)) ((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/ /******************************** I2S Instances *******************************/
#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2) || \ ((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \ ((INSTANCE) == SPI3) || \
((INSTANCE) == SPI4) || \ ((INSTANCE) == SPI4) || \
((INSTANCE) == SPI5)) ((INSTANCE) == SPI5))
/*************************** I2S Extended Instances ***************************/ /*************************** I2S Extended Instances ***************************/
#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \ #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \ ((INSTANCE) == SPI3) || \
((INSTANCE) == I2S2ext) || \ ((INSTANCE) == I2S2ext) || \
((INSTANCE) == I2S3ext)) ((INSTANCE) == I2S3ext))
/****************************** RTC Instances *********************************/ /****************************** RTC Instances *********************************/
@ -4754,6 +4771,14 @@ USB_OTG_HostChannelTypeDef;
/****************************** WWDG Instances ********************************/ /****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/****************************** SDIO Instances ********************************/
#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
/****************************** USB Exported Constants ************************/
#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
/** /**
* @} * @}

27
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx.h
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx.h * @file stm32f4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -63,13 +63,20 @@
/** @addtogroup Library_configuration_section /** @addtogroup Library_configuration_section
* @{ * @{
*/ */
/**
* @brief STM32 Family
*/
#if !defined (STM32F4)
#define STM32F4
#endif /* STM32F4 */
/* Uncomment the line below according to the target STM32 device used in your /* Uncomment the line below according to the target STM32 device used in your
application application
*/ */
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ #if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@ -82,7 +89,9 @@
STM32F439NI, STM32F439IG and STM32F439II Devices */ STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
#define STM32F411xE /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */ #define STM32F411xE /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
/* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
and STM32F446ZE Devices */
#endif #endif
/* Tip: To avoid modifying this file each time you need to switch between these /* Tip: To avoid modifying this file each time you need to switch between these
@ -94,14 +103,14 @@
In this case, these drivers will not be included and the application code will In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers be based on direct access to peripherals registers
*/ */
#define USE_HAL_DRIVER #define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V2.1.0 * @brief CMSIS Device version number V2.3.0
*/ */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ #define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
@ -139,6 +148,8 @@
#include "stm32f401xe.h" #include "stm32f401xe.h"
#elif defined(STM32F411xE) #elif defined(STM32F411xE)
#include "stm32f411xe.h" #include "stm32f411xe.h"
#elif defined(STM32F446xx)
#include "stm32f446xx.h"
#else #else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif #endif

405
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx_hal_conf.h Normal file
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@ -0,0 +1,405 @@
/**
******************************************************************************
* @file stm32f4xx_hal_conf.h
* @author MCD Application Team
* @version V1.1.0
* @date 26-December-2014
* @brief HAL configuration file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CONF_H
#define __STM32F4xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_CAN_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
#define HAL_CRYP_MODULE_ENABLED
#define HAL_DAC_MODULE_ENABLED
#define HAL_DCMI_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
/* #define HAL_DMA2D_MODULE_ENABLED */
#define HAL_ETH_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_NAND_MODULE_ENABLED
#define HAL_NOR_MODULE_ENABLED
#define HAL_PCCARD_MODULE_ENABLED
#define HAL_SRAM_MODULE_ENABLED
/* #define HAL_SDRAM_MODULE_ENABLED */
#define HAL_HASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_LTDC_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
/* #define HAL_SAI_MODULE_ENABLED */
#define HAL_SD_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_PCD_MODULE_ENABLED
#define HAL_HCD_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define INSTRUCTION_CACHE_ENABLE 1
#define DATA_CACHE_ENABLE 1
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1 */
/* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2
#define MAC_ADDR1 0
#define MAC_ADDR2 0
#define MAC_ADDR3 0
#define MAC_ADDR4 0
#define MAC_ADDR5 0
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* DP83848 PHY Address*/
#define DP83848_PHY_ADDRESS 0x01
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
#define PHY_READ_TO ((uint32_t)0x0000FFFF)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f4xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f4xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f4xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f4xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f4xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f4xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32f4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32f4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32f4xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32f4xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f4xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f4xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f4xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_SDRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sdram.h"
#endif /* HAL_SDRAM_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32f4xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f4xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32f4xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32f4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32f4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32f4xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f4xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

7
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.h
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@ -2,13 +2,13 @@
****************************************************************************** ******************************************************************************
* @file system_stm32f4xx.h * @file system_stm32f4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -103,7 +103,6 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Cloc
extern void SystemInit(void); extern void SystemInit(void);
extern void SystemCoreClockUpdate(void); extern void SystemCoreClockUpdate(void);
extern void SetSysClock(void); extern void SetSysClock(void);
/** /**
* @} * @}
*/ */

261
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f405xx.h
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32f405xx.h * @file stm32f405xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS STM32F405xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F405xx Device Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -14,7 +14,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -454,8 +454,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef; } GPIO_TypeDef;
@ -1688,72 +1687,128 @@ USB_OTG_HostChannelTypeDef;
#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */ #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
/******************* Bit definition for CAN_FM1R register *******************/ /******************* Bit definition for CAN_FM1R register *******************/
#define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */ #define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
#define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */ #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
#define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */ #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
#define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */ #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
#define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */ #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
#define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */ #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
#define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */ #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
#define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */ #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
#define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */ #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
#define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */ #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
#define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */ #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
#define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */ #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
#define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */ #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
#define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */ #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
#define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */ #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
/******************* Bit definition for CAN_FS1R register *******************/ /******************* Bit definition for CAN_FS1R register *******************/
#define CAN_FS1R_FSC ((uint32_t)0x3FFF) /*!<Filter Scale Configuration */ #define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
#define CAN_FS1R_FSC0 ((uint32_t)0x0001) /*!<Filter Scale Configuration bit 0 */ #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
#define CAN_FS1R_FSC1 ((uint32_t)0x0002) /*!<Filter Scale Configuration bit 1 */ #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
#define CAN_FS1R_FSC2 ((uint32_t)0x0004) /*!<Filter Scale Configuration bit 2 */ #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
#define CAN_FS1R_FSC3 ((uint32_t)0x0008) /*!<Filter Scale Configuration bit 3 */ #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
#define CAN_FS1R_FSC4 ((uint32_t)0x0010) /*!<Filter Scale Configuration bit 4 */ #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
#define CAN_FS1R_FSC5 ((uint32_t)0x0020) /*!<Filter Scale Configuration bit 5 */ #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
#define CAN_FS1R_FSC6 ((uint32_t)0x0040) /*!<Filter Scale Configuration bit 6 */ #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
#define CAN_FS1R_FSC7 ((uint32_t)0x0080) /*!<Filter Scale Configuration bit 7 */ #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
#define CAN_FS1R_FSC8 ((uint32_t)0x0100) /*!<Filter Scale Configuration bit 8 */ #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
#define CAN_FS1R_FSC9 ((uint32_t)0x0200) /*!<Filter Scale Configuration bit 9 */ #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
#define CAN_FS1R_FSC10 ((uint32_t)0x0400) /*!<Filter Scale Configuration bit 10 */ #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
#define CAN_FS1R_FSC11 ((uint32_t)0x0800) /*!<Filter Scale Configuration bit 11 */ #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
#define CAN_FS1R_FSC12 ((uint32_t)0x1000) /*!<Filter Scale Configuration bit 12 */ #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
#define CAN_FS1R_FSC13 ((uint32_t)0x2000) /*!<Filter Scale Configuration bit 13 */ #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
/****************** Bit definition for CAN_FFA1R register *******************/ /****************** Bit definition for CAN_FFA1R register *******************/
#define CAN_FFA1R_FFA ((uint32_t)0x3FFF) /*!<Filter FIFO Assignment */ #define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
#define CAN_FFA1R_FFA0 ((uint32_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */ #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
#define CAN_FFA1R_FFA1 ((uint32_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */ #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
#define CAN_FFA1R_FFA2 ((uint32_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */ #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
#define CAN_FFA1R_FFA3 ((uint32_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */ #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
#define CAN_FFA1R_FFA4 ((uint32_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */ #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
#define CAN_FFA1R_FFA5 ((uint32_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */ #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
#define CAN_FFA1R_FFA6 ((uint32_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */ #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
#define CAN_FFA1R_FFA7 ((uint32_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */ #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
#define CAN_FFA1R_FFA8 ((uint32_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */ #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
#define CAN_FFA1R_FFA9 ((uint32_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */ #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
#define CAN_FFA1R_FFA10 ((uint32_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */ #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
#define CAN_FFA1R_FFA11 ((uint32_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */ #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
#define CAN_FFA1R_FFA12 ((uint32_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */ #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
#define CAN_FFA1R_FFA13 ((uint32_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */ #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
/******************* Bit definition for CAN_FA1R register *******************/ /******************* Bit definition for CAN_FA1R register *******************/
#define CAN_FA1R_FACT ((uint32_t)0x3FFF) /*!<Filter Active */ #define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
#define CAN_FA1R_FACT0 ((uint32_t)0x0001) /*!<Filter 0 Active */ #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
#define CAN_FA1R_FACT1 ((uint32_t)0x0002) /*!<Filter 1 Active */ #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
#define CAN_FA1R_FACT2 ((uint32_t)0x0004) /*!<Filter 2 Active */ #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
#define CAN_FA1R_FACT3 ((uint32_t)0x0008) /*!<Filter 3 Active */ #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
#define CAN_FA1R_FACT4 ((uint32_t)0x0010) /*!<Filter 4 Active */ #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
#define CAN_FA1R_FACT5 ((uint32_t)0x0020) /*!<Filter 5 Active */ #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
#define CAN_FA1R_FACT6 ((uint32_t)0x0040) /*!<Filter 6 Active */ #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
#define CAN_FA1R_FACT7 ((uint32_t)0x0080) /*!<Filter 7 Active */ #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
#define CAN_FA1R_FACT8 ((uint32_t)0x0100) /*!<Filter 8 Active */ #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
#define CAN_FA1R_FACT9 ((uint32_t)0x0200) /*!<Filter 9 Active */ #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
#define CAN_FA1R_FACT10 ((uint32_t)0x0400) /*!<Filter 10 Active */ #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
#define CAN_FA1R_FACT11 ((uint32_t)0x0800) /*!<Filter 11 Active */ #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
#define CAN_FA1R_FACT12 ((uint32_t)0x1000) /*!<Filter 12 Active */ #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
#define CAN_FA1R_FACT13 ((uint32_t)0x2000) /*!<Filter 13 Active */ #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
/******************* Bit definition for CAN_F0R1 register *******************/ /******************* Bit definition for CAN_F0R1 register *******************/
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
@ -3008,6 +3063,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/ /******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@ -3030,6 +3088,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/ /****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@ -3052,6 +3113,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/ /****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@ -3074,6 +3138,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/ /****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@ -3096,6 +3163,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/ /******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@ -3118,6 +3188,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
@ -3497,6 +3570,12 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FSMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FSMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FSMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@ -3532,6 +3611,12 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FSMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FSMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FSMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/ #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
@ -3567,6 +3652,12 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FSMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FSMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FSMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@ -3602,6 +3693,12 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FSMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FSMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FSMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@ -4510,11 +4607,9 @@ USB_OTG_HostChannelTypeDef;
#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */ #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */ #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */ #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */ #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ #define PWR_CR_VOS ((uint32_t)0x00004000) /*!< VOS bit (Regulator voltage scaling output selection) */
#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
/* Legacy define */ /* Legacy define */
#define PWR_CR_PMODE PWR_CR_VOS #define PWR_CR_PMODE PWR_CR_VOS
@ -4727,7 +4822,7 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000) #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000) #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000) #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000) #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/ /******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040) #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
@ -7034,14 +7129,14 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == I2C3)) ((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/ /******************************** I2S Instances *******************************/
#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3)) ((INSTANCE) == SPI3))
/*************************** I2S Extended Instances ***************************/ /*************************** I2S Extended Instances ***************************/
#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \ #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \ ((INSTANCE) == SPI3) || \
((INSTANCE) == I2S2ext) || \ ((INSTANCE) == I2S2ext) || \
((INSTANCE) == I2S3ext)) ((INSTANCE) == I2S3ext))
/******************************* RNG Instances ********************************/ /******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
@ -7312,6 +7407,20 @@ USB_OTG_HostChannelTypeDef;
/****************************** WWDG Instances ********************************/ /****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/****************************** SDIO Instances ********************************/
#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
/****************************** USB Exported Constants ************************/
#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12
#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
/******************************************************************************/ /******************************************************************************/
/* For a painless codes migration between the STM32F4xx device product */ /* For a painless codes migration between the STM32F4xx device product */
/* lines, the aliases defined below are put in place to overcome the */ /* lines, the aliases defined below are put in place to overcome the */

30
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f4xx.h
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx.h * @file stm32f4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -63,15 +63,21 @@
/** @addtogroup Library_configuration_section /** @addtogroup Library_configuration_section
* @{ * @{
*/ */
/**
* @brief STM32 Family
*/
#if !defined (STM32F4)
#define STM32F4
#endif /* STM32F4 */
/* Uncomment the line below according to the target STM32 device used in your /* Uncomment the line below according to the target STM32 device used in your
application application
*/ */
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ #if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
#define STM32F405xx /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ #define STM32F405xx /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
/* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
@ -83,7 +89,9 @@
STM32F439NI, STM32F439IG and STM32F439II Devices */ STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
/* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */ /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
/* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
and STM32F446ZE Devices */
#endif #endif
/* Tip: To avoid modifying this file each time you need to switch between these /* Tip: To avoid modifying this file each time you need to switch between these
@ -95,14 +103,14 @@
In this case, these drivers will not be included and the application code will In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers be based on direct access to peripherals registers
*/ */
#define USE_HAL_DRIVER #define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V2.1.0 * @brief CMSIS Device version number V2.3.0
*/ */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ #define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
@ -140,6 +148,8 @@
#include "stm32f401xe.h" #include "stm32f401xe.h"
#elif defined(STM32F411xE) #elif defined(STM32F411xE)
#include "stm32f411xe.h" #include "stm32f411xe.h"
#elif defined(STM32F446xx)
#include "stm32f446xx.h"
#else #else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif #endif

407
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_conf.h Normal file
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@ -0,0 +1,407 @@
/**
******************************************************************************
* @file stm32f4xx_hal_conf.h
* @author MCD Application Team
* @version V1.2.1
* @date 13-March-2015
* @brief HAL configuration file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CONF_H
#define __STM32F4xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_CAN_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
#define HAL_CRYP_MODULE_ENABLED
#define HAL_DAC_MODULE_ENABLED
#define HAL_DCMI_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
/* #define HAL_DMA2D_MODULE_ENABLED */
#define HAL_ETH_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_NAND_MODULE_ENABLED
#define HAL_NOR_MODULE_ENABLED
#define HAL_PCCARD_MODULE_ENABLED
#define HAL_SRAM_MODULE_ENABLED
/* #define HAL_SDRAM_MODULE_ENABLED */
#define HAL_HASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_LTDC_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
/* #define HAL_SAI_MODULE_ENABLED */
#define HAL_SD_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_PCD_MODULE_ENABLED
#define HAL_HCD_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 0 /* The prefetch will be enabled in SystemClock_Config(), depending on the used
STM32F405/415/07/417 device: RevA (prefetch must be off) or RevZ (prefetch can be on/off) */
#define INSTRUCTION_CACHE_ENABLE 1
#define DATA_CACHE_ENABLE 1
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1 */
/* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2
#define MAC_ADDR1 0
#define MAC_ADDR2 0
#define MAC_ADDR3 0
#define MAC_ADDR4 0
#define MAC_ADDR5 0
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* DP83848 PHY Address*/
#define DP83848_PHY_ADDRESS 0x01
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
#define PHY_READ_TO ((uint32_t)0x0000FFFF)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f4xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f4xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f4xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f4xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f4xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f4xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32f4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32f4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32f4xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32f4xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f4xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f4xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f4xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_SDRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sdram.h"
#endif /* HAL_SDRAM_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32f4xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f4xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32f4xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32f4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32f4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32f4xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f4xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

7
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/system_stm32f4xx.h
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@ -2,13 +2,13 @@
****************************************************************************** ******************************************************************************
* @file system_stm32f4xx.h * @file system_stm32f4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -103,7 +103,6 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Cloc
extern void SystemInit(void); extern void SystemInit(void);
extern void SystemCoreClockUpdate(void); extern void SystemCoreClockUpdate(void);
extern void SetSysClock(void); extern void SetSysClock(void);
/** /**
* @} * @}
*/ */

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.s
View File

@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file startup_stm32f411xe.s * @file startup_stm32f411xe.s
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief STM32F411xExx Devices vector table for Atollic TrueSTUDIO toolchain. * @brief STM32F411xExx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs: * This module performs:
* - Set the initial SP * - Set the initial SP
@ -16,7 +16,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:

53
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f411xe.h
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@ -2,19 +2,19 @@
****************************************************************************** ******************************************************************************
* @file stm32f411xe.h * @file stm32f411xe.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
* - Data structures and the address mapping for all peripherals * - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition * - Peripheral's registers declarations and bits definition
* - Macros to access peripheral’s registers hardware * - Macros to access peripheral’s registers hardware
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -45,12 +45,12 @@
* @{ * @{
*/ */
/** @addtogroup stm32f411xe /** @addtogroup stm32f401xe
* @{ * @{
*/ */
#ifndef __STM32F411xE_H #ifndef __STM32F401xE_H
#define __STM32F411xE_H #define __STM32F401xE_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -291,8 +291,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef; } GPIO_TypeDef;
@ -1427,6 +1426,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/ /******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@ -1449,6 +1451,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/ /****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@ -1471,6 +1476,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/ /****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@ -1493,6 +1501,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/ /****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@ -1515,6 +1526,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/ /******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@ -1537,6 +1551,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
@ -4531,17 +4548,17 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == I2C3)) ((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/ /******************************** I2S Instances *******************************/
#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2) || \ ((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \ ((INSTANCE) == SPI3) || \
((INSTANCE) == SPI4) || \ ((INSTANCE) == SPI4) || \
((INSTANCE) == SPI5)) ((INSTANCE) == SPI5))
/*************************** I2S Extended Instances ***************************/ /*************************** I2S Extended Instances ***************************/
#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \ #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \ ((INSTANCE) == SPI3) || \
((INSTANCE) == I2S2ext) || \ ((INSTANCE) == I2S2ext) || \
((INSTANCE) == I2S3ext)) ((INSTANCE) == I2S3ext))
/****************************** RTC Instances *********************************/ /****************************** RTC Instances *********************************/
@ -4754,6 +4771,14 @@ USB_OTG_HostChannelTypeDef;
/****************************** WWDG Instances ********************************/ /****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/****************************** SDIO Instances ********************************/
#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
/****************************** USB Exported Constants ************************/
#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
/** /**
* @} * @}

27
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f4xx.h
View File

@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx.h * @file stm32f4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -63,13 +63,20 @@
/** @addtogroup Library_configuration_section /** @addtogroup Library_configuration_section
* @{ * @{
*/ */
/**
* @brief STM32 Family
*/
#if !defined (STM32F4)
#define STM32F4
#endif /* STM32F4 */
/* Uncomment the line below according to the target STM32 device used in your /* Uncomment the line below according to the target STM32 device used in your
application application
*/ */
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ #if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@ -82,7 +89,9 @@
STM32F439NI, STM32F439IG and STM32F439II Devices */ STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
#define STM32F411xE /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */ #define STM32F411xE /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
/* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
and STM32F446ZE Devices */
#endif #endif
/* Tip: To avoid modifying this file each time you need to switch between these /* Tip: To avoid modifying this file each time you need to switch between these
@ -94,14 +103,14 @@
In this case, these drivers will not be included and the application code will In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers be based on direct access to peripherals registers
*/ */
#define USE_HAL_DRIVER #define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V2.1.0 * @brief CMSIS Device version number V2.3.0
*/ */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ #define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
@ -139,6 +148,8 @@
#include "stm32f401xe.h" #include "stm32f401xe.h"
#elif defined(STM32F411xE) #elif defined(STM32F411xE)
#include "stm32f411xe.h" #include "stm32f411xe.h"
#elif defined(STM32F446xx)
#include "stm32f446xx.h"
#else #else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif #endif

405
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f4xx_hal_conf.h Normal file
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@ -0,0 +1,405 @@
/**
******************************************************************************
* @file stm32f4xx_hal_conf.h
* @author MCD Application Team
* @version V1.1.0
* @date 26-December-2014
* @brief HAL configuration file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CONF_H
#define __STM32F4xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_CAN_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
#define HAL_CRYP_MODULE_ENABLED
#define HAL_DAC_MODULE_ENABLED
#define HAL_DCMI_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
/* #define HAL_DMA2D_MODULE_ENABLED */
#define HAL_ETH_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_NAND_MODULE_ENABLED
#define HAL_NOR_MODULE_ENABLED
#define HAL_PCCARD_MODULE_ENABLED
#define HAL_SRAM_MODULE_ENABLED
/* #define HAL_SDRAM_MODULE_ENABLED */
#define HAL_HASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_LTDC_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
/* #define HAL_SAI_MODULE_ENABLED */
#define HAL_SD_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_PCD_MODULE_ENABLED
#define HAL_HCD_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define INSTRUCTION_CACHE_ENABLE 1
#define DATA_CACHE_ENABLE 1
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1 */
/* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2
#define MAC_ADDR1 0
#define MAC_ADDR2 0
#define MAC_ADDR3 0
#define MAC_ADDR4 0
#define MAC_ADDR5 0
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* DP83848 PHY Address*/
#define DP83848_PHY_ADDRESS 0x01
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
#define PHY_READ_TO ((uint32_t)0x0000FFFF)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f4xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f4xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f4xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f4xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f4xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f4xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32f4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32f4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32f4xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32f4xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f4xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f4xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f4xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_SDRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sdram.h"
#endif /* HAL_SDRAM_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32f4xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f4xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32f4xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32f4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32f4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32f4xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f4xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

7
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.h
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@ -2,13 +2,13 @@
****************************************************************************** ******************************************************************************
* @file system_stm32f4xx.h * @file system_stm32f4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -103,7 +103,6 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Cloc
extern void SystemInit(void); extern void SystemInit(void);
extern void SystemCoreClockUpdate(void); extern void SystemCoreClockUpdate(void);
extern void SetSysClock(void); extern void SetSysClock(void);
/** /**
* @} * @}
*/ */

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/TOOLCHAIN_GCC_ARM/startup_stm32f401xe.s
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file startup_stm32f401xe.s * @file startup_stm32f401xe.s
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief STM32F401xExx Devices vector table for Atollic TrueSTUDIO toolchain. * @brief STM32F401xExx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs: * This module performs:
* - Set the initial SP * - Set the initial SP
@ -16,7 +16,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:

45
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f401xe.h
View File

@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32f401xe.h * @file stm32f401xe.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS STM32F401xExx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F401xExx Device Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -14,7 +14,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -290,8 +290,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef; } GPIO_TypeDef;
@ -1423,6 +1422,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/ /******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@ -1445,6 +1447,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/ /****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@ -1467,6 +1472,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/ /****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@ -1489,6 +1497,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/ /****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@ -1511,6 +1522,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/ /******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@ -1533,6 +1547,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
@ -4511,14 +4528,14 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == I2C3)) ((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/ /******************************** I2S Instances *******************************/
#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3)) ((INSTANCE) == SPI3))
/*************************** I2S Extended Instances ***************************/ /*************************** I2S Extended Instances ***************************/
#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \ #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \ ((INSTANCE) == SPI3) || \
((INSTANCE) == I2S2ext) || \ ((INSTANCE) == I2S2ext) || \
((INSTANCE) == I2S3ext)) ((INSTANCE) == I2S3ext))
/****************************** RTC Instances *********************************/ /****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
@ -4728,6 +4745,14 @@ USB_OTG_HostChannelTypeDef;
/****************************** WWDG Instances ********************************/ /****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/****************************** SDIO Instances ********************************/
#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
/****************************** USB Exported Constants ************************/
#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
/** /**
* @} * @}

29
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f4xx.h
View File

@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx.h * @file stm32f4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -63,13 +63,20 @@
/** @addtogroup Library_configuration_section /** @addtogroup Library_configuration_section
* @{ * @{
*/ */
/**
* @brief STM32 Family
*/
#if !defined (STM32F4)
#define STM32F4
#endif /* STM32F4 */
/* Uncomment the line below according to the target STM32 device used in your /* Uncomment the line below according to the target STM32 device used in your
application application
*/ */
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ #if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@ -81,8 +88,10 @@
/* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
STM32F439NI, STM32F439IG and STM32F439II Devices */ STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
#define STM32F401xE /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ #define STM32F401xE /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
/* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */ /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
/* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
and STM32F446ZE Devices */
#endif #endif
/* Tip: To avoid modifying this file each time you need to switch between these /* Tip: To avoid modifying this file each time you need to switch between these
@ -94,14 +103,14 @@
In this case, these drivers will not be included and the application code will In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers be based on direct access to peripherals registers
*/ */
#define USE_HAL_DRIVER #define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V2.1.0 * @brief CMSIS Device version number V2.3.0
*/ */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ #define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
@ -139,6 +148,8 @@
#include "stm32f401xe.h" #include "stm32f401xe.h"
#elif defined(STM32F411xE) #elif defined(STM32F411xE)
#include "stm32f411xe.h" #include "stm32f411xe.h"
#elif defined(STM32F446xx)
#include "stm32f446xx.h"
#else #else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif #endif

405
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h Normal file
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@ -0,0 +1,405 @@
/**
******************************************************************************
* @file stm32f4xx_hal_conf.h
* @author MCD Application Team
* @version V1.2.0
* @date 26-December-2014
* @brief HAL configuration file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CONF_H
#define __STM32F4xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_CAN_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
#define HAL_CRYP_MODULE_ENABLED
#define HAL_DAC_MODULE_ENABLED
#define HAL_DCMI_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
/* #define HAL_DMA2D_MODULE_ENABLED */
#define HAL_ETH_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_NAND_MODULE_ENABLED
#define HAL_NOR_MODULE_ENABLED
#define HAL_PCCARD_MODULE_ENABLED
#define HAL_SRAM_MODULE_ENABLED
/* #define HAL_SDRAM_MODULE_ENABLED */
#define HAL_HASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_LTDC_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
/* #define HAL_SAI_MODULE_ENABLED */
#define HAL_SD_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_PCD_MODULE_ENABLED
#define HAL_HCD_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define INSTRUCTION_CACHE_ENABLE 1
#define DATA_CACHE_ENABLE 1
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1 */
/* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2
#define MAC_ADDR1 0
#define MAC_ADDR2 0
#define MAC_ADDR3 0
#define MAC_ADDR4 0
#define MAC_ADDR5 0
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* DP83848 PHY Address*/
#define DP83848_PHY_ADDRESS 0x01
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
#define PHY_READ_TO ((uint32_t)0x0000FFFF)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f4xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f4xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f4xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f4xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f4xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f4xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32f4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32f4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32f4xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32f4xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f4xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f4xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f4xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_SDRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sdram.h"
#endif /* HAL_SDRAM_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32f4xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f4xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32f4xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32f4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32f4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32f4xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f4xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/system_stm32f4xx.h
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@ -2,13 +2,13 @@
****************************************************************************** ******************************************************************************
* @file system_stm32f4xx.h * @file system_stm32f4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.s
View File

@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file startup_stm32f411xe.s * @file startup_stm32f411xe.s
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief STM32F411xExx Devices vector table for Atollic TrueSTUDIO toolchain. * @brief STM32F411xExx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs: * This module performs:
* - Set the initial SP * - Set the initial SP
@ -16,7 +16,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:

53
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f411xe.h
View File

@ -2,19 +2,19 @@
****************************************************************************** ******************************************************************************
* @file stm32f411xe.h * @file stm32f411xe.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
* - Data structures and the address mapping for all peripherals * - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition * - Peripheral's registers declarations and bits definition
* - Macros to access peripheral’s registers hardware * - Macros to access peripheral’s registers hardware
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -45,12 +45,12 @@
* @{ * @{
*/ */
/** @addtogroup stm32f411xe /** @addtogroup stm32f401xe
* @{ * @{
*/ */
#ifndef __STM32F411xE_H #ifndef __STM32F401xE_H
#define __STM32F411xE_H #define __STM32F401xE_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -291,8 +291,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef; } GPIO_TypeDef;
@ -1427,6 +1426,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/ /******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@ -1449,6 +1451,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/ /****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@ -1471,6 +1476,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/ /****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@ -1493,6 +1501,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/ /****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@ -1515,6 +1526,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/ /******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@ -1537,6 +1551,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
@ -4531,17 +4548,17 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == I2C3)) ((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/ /******************************** I2S Instances *******************************/
#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2) || \ ((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \ ((INSTANCE) == SPI3) || \
((INSTANCE) == SPI4) || \ ((INSTANCE) == SPI4) || \
((INSTANCE) == SPI5)) ((INSTANCE) == SPI5))
/*************************** I2S Extended Instances ***************************/ /*************************** I2S Extended Instances ***************************/
#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \ #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \ ((INSTANCE) == SPI3) || \
((INSTANCE) == I2S2ext) || \ ((INSTANCE) == I2S2ext) || \
((INSTANCE) == I2S3ext)) ((INSTANCE) == I2S3ext))
/****************************** RTC Instances *********************************/ /****************************** RTC Instances *********************************/
@ -4754,6 +4771,14 @@ USB_OTG_HostChannelTypeDef;
/****************************** WWDG Instances ********************************/ /****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/****************************** SDIO Instances ********************************/
#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
/****************************** USB Exported Constants ************************/
#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
/** /**
* @} * @}

27
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f4xx.h
View File

@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx.h * @file stm32f4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -63,13 +63,20 @@
/** @addtogroup Library_configuration_section /** @addtogroup Library_configuration_section
* @{ * @{
*/ */
/**
* @brief STM32 Family
*/
#if !defined (STM32F4)
#define STM32F4
#endif /* STM32F4 */
/* Uncomment the line below according to the target STM32 device used in your /* Uncomment the line below according to the target STM32 device used in your
application application
*/ */
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ #if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@ -82,7 +89,9 @@
STM32F439NI, STM32F439IG and STM32F439II Devices */ STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
#define STM32F411xE /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */ #define STM32F411xE /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
/* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
and STM32F446ZE Devices */
#endif #endif
/* Tip: To avoid modifying this file each time you need to switch between these /* Tip: To avoid modifying this file each time you need to switch between these
@ -94,14 +103,14 @@
In this case, these drivers will not be included and the application code will In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers be based on direct access to peripherals registers
*/ */
#define USE_HAL_DRIVER #define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V2.1.0 * @brief CMSIS Device version number V2.3.0
*/ */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ #define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
@ -139,6 +148,8 @@
#include "stm32f401xe.h" #include "stm32f401xe.h"
#elif defined(STM32F411xE) #elif defined(STM32F411xE)
#include "stm32f411xe.h" #include "stm32f411xe.h"
#elif defined(STM32F446xx)
#include "stm32f446xx.h"
#else #else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif #endif

405
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f4xx_hal_conf.h Normal file
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@ -0,0 +1,405 @@
/**
******************************************************************************
* @file stm32f4xx_hal_conf.h
* @author MCD Application Team
* @version V1.1.0
* @date 26-December-2014
* @brief HAL configuration file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CONF_H
#define __STM32F4xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_CAN_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
#define HAL_CRYP_MODULE_ENABLED
#define HAL_DAC_MODULE_ENABLED
#define HAL_DCMI_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
/* #define HAL_DMA2D_MODULE_ENABLED */
#define HAL_ETH_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_NAND_MODULE_ENABLED
#define HAL_NOR_MODULE_ENABLED
#define HAL_PCCARD_MODULE_ENABLED
#define HAL_SRAM_MODULE_ENABLED
/* #define HAL_SDRAM_MODULE_ENABLED */
#define HAL_HASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_LTDC_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
/* #define HAL_SAI_MODULE_ENABLED */
#define HAL_SD_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_PCD_MODULE_ENABLED
#define HAL_HCD_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define INSTRUCTION_CACHE_ENABLE 1
#define DATA_CACHE_ENABLE 1
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1 */
/* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2
#define MAC_ADDR1 0
#define MAC_ADDR2 0
#define MAC_ADDR3 0
#define MAC_ADDR4 0
#define MAC_ADDR5 0
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* DP83848 PHY Address*/
#define DP83848_PHY_ADDRESS 0x01
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
#define PHY_READ_TO ((uint32_t)0x0000FFFF)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f4xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f4xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f4xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f4xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f4xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f4xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32f4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32f4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32f4xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32f4xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f4xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f4xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f4xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_SDRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sdram.h"
#endif /* HAL_SDRAM_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32f4xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f4xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32f4xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32f4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32f4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32f4xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f4xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

7
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.h
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@ -2,13 +2,13 @@
****************************************************************************** ******************************************************************************
* @file system_stm32f4xx.h * @file system_stm32f4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -103,7 +103,6 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Cloc
extern void SystemInit(void); extern void SystemInit(void);
extern void SystemCoreClockUpdate(void); extern void SystemCoreClockUpdate(void);
extern void SetSysClock(void); extern void SetSysClock(void);
/** /**
* @} * @}
*/ */

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/TOOLCHAIN_GCC_ARM/startup_stm32f407xx.s
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file startup_stm32f407xx.s * @file startup_stm32f407xx.s
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief STM32F407xx Devices vector table for Atollic TrueSTUDIO toolchain. * @brief STM32F407xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs: * This module performs:
* - Set the initial SP * - Set the initial SP
@ -16,7 +16,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:

263
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f407xx.h
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32f407xx.h * @file stm32f407xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -14,7 +14,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -549,8 +549,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef; } GPIO_TypeDef;
@ -1790,72 +1789,128 @@ USB_OTG_HostChannelTypeDef;
#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */ #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
/******************* Bit definition for CAN_FM1R register *******************/ /******************* Bit definition for CAN_FM1R register *******************/
#define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */ #define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
#define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */ #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
#define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */ #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
#define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */ #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
#define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */ #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
#define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */ #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
#define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */ #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
#define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */ #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
#define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */ #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
#define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */ #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
#define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */ #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
#define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */ #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
#define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */ #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
#define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */ #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
#define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */ #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
/******************* Bit definition for CAN_FS1R register *******************/ /******************* Bit definition for CAN_FS1R register *******************/
#define CAN_FS1R_FSC ((uint32_t)0x3FFF) /*!<Filter Scale Configuration */ #define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
#define CAN_FS1R_FSC0 ((uint32_t)0x0001) /*!<Filter Scale Configuration bit 0 */ #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
#define CAN_FS1R_FSC1 ((uint32_t)0x0002) /*!<Filter Scale Configuration bit 1 */ #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
#define CAN_FS1R_FSC2 ((uint32_t)0x0004) /*!<Filter Scale Configuration bit 2 */ #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
#define CAN_FS1R_FSC3 ((uint32_t)0x0008) /*!<Filter Scale Configuration bit 3 */ #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
#define CAN_FS1R_FSC4 ((uint32_t)0x0010) /*!<Filter Scale Configuration bit 4 */ #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
#define CAN_FS1R_FSC5 ((uint32_t)0x0020) /*!<Filter Scale Configuration bit 5 */ #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
#define CAN_FS1R_FSC6 ((uint32_t)0x0040) /*!<Filter Scale Configuration bit 6 */ #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
#define CAN_FS1R_FSC7 ((uint32_t)0x0080) /*!<Filter Scale Configuration bit 7 */ #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
#define CAN_FS1R_FSC8 ((uint32_t)0x0100) /*!<Filter Scale Configuration bit 8 */ #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
#define CAN_FS1R_FSC9 ((uint32_t)0x0200) /*!<Filter Scale Configuration bit 9 */ #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
#define CAN_FS1R_FSC10 ((uint32_t)0x0400) /*!<Filter Scale Configuration bit 10 */ #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
#define CAN_FS1R_FSC11 ((uint32_t)0x0800) /*!<Filter Scale Configuration bit 11 */ #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
#define CAN_FS1R_FSC12 ((uint32_t)0x1000) /*!<Filter Scale Configuration bit 12 */ #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
#define CAN_FS1R_FSC13 ((uint32_t)0x2000) /*!<Filter Scale Configuration bit 13 */ #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
/****************** Bit definition for CAN_FFA1R register *******************/ /****************** Bit definition for CAN_FFA1R register *******************/
#define CAN_FFA1R_FFA ((uint32_t)0x3FFF) /*!<Filter FIFO Assignment */ #define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
#define CAN_FFA1R_FFA0 ((uint32_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */ #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
#define CAN_FFA1R_FFA1 ((uint32_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */ #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
#define CAN_FFA1R_FFA2 ((uint32_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */ #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
#define CAN_FFA1R_FFA3 ((uint32_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */ #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
#define CAN_FFA1R_FFA4 ((uint32_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */ #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
#define CAN_FFA1R_FFA5 ((uint32_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */ #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
#define CAN_FFA1R_FFA6 ((uint32_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */ #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
#define CAN_FFA1R_FFA7 ((uint32_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */ #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
#define CAN_FFA1R_FFA8 ((uint32_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */ #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
#define CAN_FFA1R_FFA9 ((uint32_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */ #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
#define CAN_FFA1R_FFA10 ((uint32_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */ #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
#define CAN_FFA1R_FFA11 ((uint32_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */ #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
#define CAN_FFA1R_FFA12 ((uint32_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */ #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
#define CAN_FFA1R_FFA13 ((uint32_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */ #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
/******************* Bit definition for CAN_FA1R register *******************/ /******************* Bit definition for CAN_FA1R register *******************/
#define CAN_FA1R_FACT ((uint32_t)0x3FFF) /*!<Filter Active */ #define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
#define CAN_FA1R_FACT0 ((uint32_t)0x0001) /*!<Filter 0 Active */ #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
#define CAN_FA1R_FACT1 ((uint32_t)0x0002) /*!<Filter 1 Active */ #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
#define CAN_FA1R_FACT2 ((uint32_t)0x0004) /*!<Filter 2 Active */ #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
#define CAN_FA1R_FACT3 ((uint32_t)0x0008) /*!<Filter 3 Active */ #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
#define CAN_FA1R_FACT4 ((uint32_t)0x0010) /*!<Filter 4 Active */ #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
#define CAN_FA1R_FACT5 ((uint32_t)0x0020) /*!<Filter 5 Active */ #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
#define CAN_FA1R_FACT6 ((uint32_t)0x0040) /*!<Filter 6 Active */ #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
#define CAN_FA1R_FACT7 ((uint32_t)0x0080) /*!<Filter 7 Active */ #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
#define CAN_FA1R_FACT8 ((uint32_t)0x0100) /*!<Filter 8 Active */ #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
#define CAN_FA1R_FACT9 ((uint32_t)0x0200) /*!<Filter 9 Active */ #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
#define CAN_FA1R_FACT10 ((uint32_t)0x0400) /*!<Filter 10 Active */ #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
#define CAN_FA1R_FACT11 ((uint32_t)0x0800) /*!<Filter 11 Active */ #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
#define CAN_FA1R_FACT12 ((uint32_t)0x1000) /*!<Filter 12 Active */ #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
#define CAN_FA1R_FACT13 ((uint32_t)0x2000) /*!<Filter 13 Active */ #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
/******************* Bit definition for CAN_F0R1 register *******************/ /******************* Bit definition for CAN_F0R1 register *******************/
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
@ -3164,6 +3219,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/ /******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@ -3186,6 +3244,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/ /****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@ -3208,6 +3269,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/ /****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@ -3230,6 +3294,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/ /****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@ -3252,6 +3319,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/ /******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@ -3274,6 +3344,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
@ -3653,6 +3726,12 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FSMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FSMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FSMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@ -3688,6 +3767,12 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FSMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FSMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FSMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/ #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
@ -3723,6 +3808,12 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FSMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FSMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FSMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@ -3758,6 +3849,12 @@ USB_OTG_HostChannelTypeDef;
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FSMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FSMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FSMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FSMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@ -4666,11 +4763,9 @@ USB_OTG_HostChannelTypeDef;
#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */ #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */ #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */ #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */ #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ #define PWR_CR_VOS ((uint32_t)0x00004000) /*!< VOS bit (Regulator voltage scaling output selection) */
#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
/* Legacy define */ /* Legacy define */
#define PWR_CR_PMODE PWR_CR_VOS #define PWR_CR_PMODE PWR_CR_VOS
@ -4884,7 +4979,7 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000) #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000) #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000) #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000) #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/ /******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001) #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
@ -7638,14 +7733,14 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == I2C3)) ((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/ /******************************** I2S Instances *******************************/
#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3)) ((INSTANCE) == SPI3))
/*************************** I2S Extended Instances ***************************/ /*************************** I2S Extended Instances ***************************/
#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \ #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \ ((INSTANCE) == SPI3) || \
((INSTANCE) == I2S2ext) || \ ((INSTANCE) == I2S2ext) || \
((INSTANCE) == I2S3ext)) ((INSTANCE) == I2S3ext))
/******************************* RNG Instances ********************************/ /******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
@ -7916,6 +8011,20 @@ USB_OTG_HostChannelTypeDef;
/****************************** WWDG Instances ********************************/ /****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/****************************** SDIO Instances ********************************/
#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
/****************************** USB Exported Constants ************************/
#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12
#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
/******************************************************************************/ /******************************************************************************/
/* For a painless codes migration between the STM32F4xx device product */ /* For a painless codes migration between the STM32F4xx device product */
/* lines, the aliases defined below are put in place to overcome the */ /* lines, the aliases defined below are put in place to overcome the */

40
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f4xx.h
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx.h * @file stm32f4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0RC2 * @version V2.3.0
* @date 14-May-2014 * @date 02-March-2015
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -63,17 +63,23 @@
/** @addtogroup Library_configuration_section /** @addtogroup Library_configuration_section
* @{ * @{
*/ */
/**
* @brief STM32 Family
*/
#if !defined (STM32F4)
#define STM32F4
#endif /* STM32F4 */
/* Uncomment the line below according to the target STM32 device used in your /* Uncomment the line below according to the target STM32 device used in your
application application
*/ */
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ #if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
#define STM32F407xx /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ #define STM32F407xx /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
/* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
/* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
/* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
@ -83,7 +89,9 @@
STM32F439NI, STM32F439IG and STM32F439II Devices */ STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
/* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */ /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
/* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
and STM32F446ZE Devices */
#endif #endif
/* Tip: To avoid modifying this file each time you need to switch between these /* Tip: To avoid modifying this file each time you need to switch between these
@ -95,20 +103,20 @@
In this case, these drivers will not be included and the application code will In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers be based on direct access to peripherals registers
*/ */
#define USE_HAL_DRIVER #define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V2.1.0RC2 * @brief CMSIS Device version number V2.3.0
*/ */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x02) /*!< [7:0] release candidate */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ #define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\ |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\ |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\
|(__CMSIS_DEVICE_HAL_VERSION_RC)) |(__STM32F4xx_CMSIS_DEVICE_VERSION))
/** /**
* @} * @}
@ -140,6 +148,8 @@
#include "stm32f401xe.h" #include "stm32f401xe.h"
#elif defined(STM32F411xE) #elif defined(STM32F411xE)
#include "stm32f411xe.h" #include "stm32f411xe.h"
#elif defined(STM32F446xx)
#include "stm32f446xx.h"
#else #else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif #endif

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libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f4xx_hal_conf.h Normal file
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@ -0,0 +1,407 @@
/**
******************************************************************************
* @file stm32f4xx_hal_conf.h
* @author MCD Application Team
* @version V1.2.1
* @date 13-March-2015
* @brief HAL configuration file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CONF_H
#define __STM32F4xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_CAN_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
#define HAL_CRYP_MODULE_ENABLED
#define HAL_DAC_MODULE_ENABLED
#define HAL_DCMI_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
/* #define HAL_DMA2D_MODULE_ENABLED */
#define HAL_ETH_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_NAND_MODULE_ENABLED
#define HAL_NOR_MODULE_ENABLED
#define HAL_PCCARD_MODULE_ENABLED
#define HAL_SRAM_MODULE_ENABLED
/* #define HAL_SDRAM_MODULE_ENABLED */
#define HAL_HASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_LTDC_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
/* #define HAL_SAI_MODULE_ENABLED */
#define HAL_SD_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_PCD_MODULE_ENABLED
#define HAL_HCD_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 0 /* The prefetch will be enabled in SystemClock_Config(), depending on the used
STM32F405/415/07/417 device: RevA (prefetch must be off) or RevZ (prefetch can be on/off) */
#define INSTRUCTION_CACHE_ENABLE 1
#define DATA_CACHE_ENABLE 1
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1 */
/* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2
#define MAC_ADDR1 0
#define MAC_ADDR2 0
#define MAC_ADDR3 0
#define MAC_ADDR4 0
#define MAC_ADDR5 0
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* DP83848 PHY Address*/
#define DP83848_PHY_ADDRESS 0x01
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
#define PHY_READ_TO ((uint32_t)0x0000FFFF)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f4xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f4xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f4xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f4xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f4xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f4xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32f4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32f4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32f4xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32f4xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f4xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f4xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f4xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_SDRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sdram.h"
#endif /* HAL_SDRAM_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32f4xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f4xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32f4xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32f4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32f4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32f4xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f4xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

7
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/system_stm32f4xx.h
View File

@ -2,13 +2,13 @@
****************************************************************************** ******************************************************************************
* @file system_stm32f4xx.h * @file system_stm32f4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0RC2 * @version V2.3.0
* @date 14-May-2014 * @date 02-March-2015
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -103,7 +103,6 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Cloc
extern void SystemInit(void); extern void SystemInit(void);
extern void SystemCoreClockUpdate(void); extern void SystemCoreClockUpdate(void);
extern void SetSysClock(void); extern void SetSysClock(void);
/** /**
* @} * @}
*/ */

8
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/startup_stm32f439xx.s
View File

@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file startup_stm32f439xx.s * @file startup_stm32f439xx.s
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief STM32F439xx Devices vector table for Atollic TrueSTUDIO toolchain. * @brief STM32F439xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs: * This module performs:
* - Set the initial SP * - Set the initial SP
@ -16,7 +16,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -567,4 +567,4 @@ Infinite_Loop:

274
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f439xx.h
View File

@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32f439xx.h * @file stm32f439xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS STM32F439xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F439xx Device Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
@ -14,7 +14,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -599,8 +599,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef; } GPIO_TypeDef;
@ -2015,72 +2014,128 @@ USB_OTG_HostChannelTypeDef;
#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */ #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
/******************* Bit definition for CAN_FM1R register *******************/ /******************* Bit definition for CAN_FM1R register *******************/
#define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */ #define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
#define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */ #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
#define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */ #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
#define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */ #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
#define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */ #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
#define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */ #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
#define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */ #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
#define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */ #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
#define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */ #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
#define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */ #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
#define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */ #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
#define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */ #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
#define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */ #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
#define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */ #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
#define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */ #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
/******************* Bit definition for CAN_FS1R register *******************/ /******************* Bit definition for CAN_FS1R register *******************/
#define CAN_FS1R_FSC ((uint32_t)0x3FFF) /*!<Filter Scale Configuration */ #define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
#define CAN_FS1R_FSC0 ((uint32_t)0x0001) /*!<Filter Scale Configuration bit 0 */ #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
#define CAN_FS1R_FSC1 ((uint32_t)0x0002) /*!<Filter Scale Configuration bit 1 */ #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
#define CAN_FS1R_FSC2 ((uint32_t)0x0004) /*!<Filter Scale Configuration bit 2 */ #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
#define CAN_FS1R_FSC3 ((uint32_t)0x0008) /*!<Filter Scale Configuration bit 3 */ #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
#define CAN_FS1R_FSC4 ((uint32_t)0x0010) /*!<Filter Scale Configuration bit 4 */ #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
#define CAN_FS1R_FSC5 ((uint32_t)0x0020) /*!<Filter Scale Configuration bit 5 */ #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
#define CAN_FS1R_FSC6 ((uint32_t)0x0040) /*!<Filter Scale Configuration bit 6 */ #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
#define CAN_FS1R_FSC7 ((uint32_t)0x0080) /*!<Filter Scale Configuration bit 7 */ #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
#define CAN_FS1R_FSC8 ((uint32_t)0x0100) /*!<Filter Scale Configuration bit 8 */ #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
#define CAN_FS1R_FSC9 ((uint32_t)0x0200) /*!<Filter Scale Configuration bit 9 */ #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
#define CAN_FS1R_FSC10 ((uint32_t)0x0400) /*!<Filter Scale Configuration bit 10 */ #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
#define CAN_FS1R_FSC11 ((uint32_t)0x0800) /*!<Filter Scale Configuration bit 11 */ #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
#define CAN_FS1R_FSC12 ((uint32_t)0x1000) /*!<Filter Scale Configuration bit 12 */ #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
#define CAN_FS1R_FSC13 ((uint32_t)0x2000) /*!<Filter Scale Configuration bit 13 */ #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
/****************** Bit definition for CAN_FFA1R register *******************/ /****************** Bit definition for CAN_FFA1R register *******************/
#define CAN_FFA1R_FFA ((uint32_t)0x3FFF) /*!<Filter FIFO Assignment */ #define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
#define CAN_FFA1R_FFA0 ((uint32_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */ #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
#define CAN_FFA1R_FFA1 ((uint32_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */ #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
#define CAN_FFA1R_FFA2 ((uint32_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */ #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
#define CAN_FFA1R_FFA3 ((uint32_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */ #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
#define CAN_FFA1R_FFA4 ((uint32_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */ #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
#define CAN_FFA1R_FFA5 ((uint32_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */ #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
#define CAN_FFA1R_FFA6 ((uint32_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */ #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
#define CAN_FFA1R_FFA7 ((uint32_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */ #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
#define CAN_FFA1R_FFA8 ((uint32_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */ #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
#define CAN_FFA1R_FFA9 ((uint32_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */ #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
#define CAN_FFA1R_FFA10 ((uint32_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */ #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
#define CAN_FFA1R_FFA11 ((uint32_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */ #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
#define CAN_FFA1R_FFA12 ((uint32_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */ #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
#define CAN_FFA1R_FFA13 ((uint32_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */ #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
/******************* Bit definition for CAN_FA1R register *******************/ /******************* Bit definition for CAN_FA1R register *******************/
#define CAN_FA1R_FACT ((uint32_t)0x3FFF) /*!<Filter Active */ #define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
#define CAN_FA1R_FACT0 ((uint32_t)0x0001) /*!<Filter 0 Active */ #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
#define CAN_FA1R_FACT1 ((uint32_t)0x0002) /*!<Filter 1 Active */ #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
#define CAN_FA1R_FACT2 ((uint32_t)0x0004) /*!<Filter 2 Active */ #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
#define CAN_FA1R_FACT3 ((uint32_t)0x0008) /*!<Filter 3 Active */ #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
#define CAN_FA1R_FACT4 ((uint32_t)0x0010) /*!<Filter 4 Active */ #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
#define CAN_FA1R_FACT5 ((uint32_t)0x0020) /*!<Filter 5 Active */ #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
#define CAN_FA1R_FACT6 ((uint32_t)0x0040) /*!<Filter 6 Active */ #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
#define CAN_FA1R_FACT7 ((uint32_t)0x0080) /*!<Filter 7 Active */ #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
#define CAN_FA1R_FACT8 ((uint32_t)0x0100) /*!<Filter 8 Active */ #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
#define CAN_FA1R_FACT9 ((uint32_t)0x0200) /*!<Filter 9 Active */ #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
#define CAN_FA1R_FACT10 ((uint32_t)0x0400) /*!<Filter 10 Active */ #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
#define CAN_FA1R_FACT11 ((uint32_t)0x0800) /*!<Filter 11 Active */ #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
#define CAN_FA1R_FACT12 ((uint32_t)0x1000) /*!<Filter 12 Active */ #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
#define CAN_FA1R_FACT13 ((uint32_t)0x2000) /*!<Filter 13 Active */ #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
/******************* Bit definition for CAN_F0R1 register *******************/ /******************* Bit definition for CAN_F0R1 register *******************/
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
@ -3592,6 +3647,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
/******************* Bit definition for EXTI_EMR register *******************/ /******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@ -3614,6 +3672,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
/****************** Bit definition for EXTI_RTSR register *******************/ /****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@ -3636,6 +3697,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR register *******************/ /****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@ -3658,6 +3722,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER register ******************/ /****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@ -3680,6 +3747,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR register ********************/ /******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@ -3702,6 +3772,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
@ -4113,6 +4186,12 @@ USB_OTG_HostChannelTypeDef;
#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ #define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ #define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ #define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ #define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ #define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@ -4152,6 +4231,12 @@ USB_OTG_HostChannelTypeDef;
#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ #define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ #define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ #define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ #define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/ #define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
@ -4191,6 +4276,12 @@ USB_OTG_HostChannelTypeDef;
#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ #define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ #define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ #define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ #define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ #define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@ -4230,6 +4321,12 @@ USB_OTG_HostChannelTypeDef;
#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ #define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ #define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ #define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ #define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ #define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
@ -4794,7 +4891,7 @@ USB_OTG_HostChannelTypeDef;
#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */ #define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */ #define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */ #define FMC_SDCMR_MODE_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */ #define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
@ -5744,7 +5841,7 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000) #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000) #define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000) #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000) #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/ /******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001) #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
@ -6059,7 +6156,11 @@ USB_OTG_HostChannelTypeDef;
#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00) #define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
#define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000) #define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
#define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000) #define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)
#define RCC_DCKCFGR_SAI1ASRC_0 ((uint32_t)0x00100000)
#define RCC_DCKCFGR_SAI1ASRC_1 ((uint32_t)0x00200000)
#define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000) #define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
#define RCC_DCKCFGR_SAI1BSRC_0 ((uint32_t)0x00400000)
#define RCC_DCKCFGR_SAI1BSRC_1 ((uint32_t)0x00800000)
#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000) #define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
@ -6500,16 +6601,17 @@ USB_OTG_HostChannelTypeDef;
#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */ #define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */ #define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
#define SAI_xCR1_MCKDIV ((uint32_t)0x00780000) /*!<MCKDIV[3:0] (Master ClocK Divider) */ #define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000) /*!<Bit 0 */ #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000) /*!<Bit 1 */ #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000) /*!<Bit 2 */ #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000) /*!<Bit 3 */ #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
/******************* Bit definition for SAI_xCR2 register *******************/ /******************* Bit definition for SAI_xCR2 register *******************/
#define SAI_xCR2_FTH ((uint32_t)0x00000003) /*!<FTH[1:0](Fifo THreshold) */ #define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */
#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */ #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */ #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */ #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */ #define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
@ -8770,14 +8872,14 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == I2C3)) ((INSTANCE) == I2C3))
/******************************** I2S Instances *******************************/ /******************************** I2S Instances *******************************/
#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3)) ((INSTANCE) == SPI3))
/*************************** I2S Extended Instances ***************************/ /*************************** I2S Extended Instances ***************************/
#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \ #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \ ((INSTANCE) == SPI3) || \
((INSTANCE) == I2S2ext) || \ ((INSTANCE) == I2S2ext) || \
((INSTANCE) == I2S3ext)) ((INSTANCE) == I2S3ext))
/****************************** LTDC Instances ********************************/ /****************************** LTDC Instances ********************************/
#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
@ -9065,6 +9167,20 @@ USB_OTG_HostChannelTypeDef;
/****************************** WWDG Instances ********************************/ /****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/****************************** SDIO Instances ********************************/
#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
/****************************** USB Exported Constants ************************/
#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12
#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
#define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
/******************************************************************************/ /******************************************************************************/
/* For a painless codes migration between the STM32F4xx device product */ /* For a painless codes migration between the STM32F4xx device product */
/* lines, the aliases defined below are put in place to overcome the */ /* lines, the aliases defined below are put in place to overcome the */

30
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f4xx.h
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@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx.h * @file stm32f4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -63,14 +63,20 @@
/** @addtogroup Library_configuration_section /** @addtogroup Library_configuration_section
* @{ * @{
*/ */
/**
* @brief STM32 Family
*/
#if !defined (STM32F4)
#define STM32F4
#endif /* STM32F4 */
/* Uncomment the line below according to the target STM32 device used in your /* Uncomment the line below according to the target STM32 device used in your
application application
*/ */
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ #if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@ -79,11 +85,13 @@
/* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
/* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
STM32F439NI, STM32F429IG and STM32F429II Devices */ STM32F439NI, STM32F429IG and STM32F429II Devices */
#define STM32F439xx /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, #define STM32F439xx /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
STM32F439NI, STM32F439IG and STM32F439II Devices */ STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
/* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */ /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
/* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
and STM32F446ZE Devices */
#endif #endif
/* Tip: To avoid modifying this file each time you need to switch between these /* Tip: To avoid modifying this file each time you need to switch between these
@ -95,14 +103,14 @@
In this case, these drivers will not be included and the application code will In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers be based on direct access to peripherals registers
*/ */
#define USE_HAL_DRIVER #define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V2.1.0 * @brief CMSIS Device version number V2.3.0
*/ */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ #define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
@ -140,6 +148,8 @@
#include "stm32f401xe.h" #include "stm32f401xe.h"
#elif defined(STM32F411xE) #elif defined(STM32F411xE)
#include "stm32f411xe.h" #include "stm32f411xe.h"
#elif defined(STM32F446xx)
#include "stm32f446xx.h"
#else #else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif #endif

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libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f4xx_hal_conf.h Normal file
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@ -0,0 +1,406 @@
/**
******************************************************************************
* @file stm32f4xx_hal_conf.h
* @author MCD Application Team
* @version V1.2.1
* @date 13-March-2015
* @brief HAL configuration file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CONF_H
#define __STM32F4xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_CAN_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
#define HAL_CRYP_MODULE_ENABLED
#define HAL_DAC_MODULE_ENABLED
#define HAL_DCMI_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_DMA2D_MODULE_ENABLED
#define HAL_ETH_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_NAND_MODULE_ENABLED
#define HAL_NOR_MODULE_ENABLED
#define HAL_PCCARD_MODULE_ENABLED
#define HAL_SRAM_MODULE_ENABLED
#define HAL_SDRAM_MODULE_ENABLED
#define HAL_HASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_LTDC_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_SAI_MODULE_ENABLED
#define HAL_SD_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_PCD_MODULE_ENABLED
#define HAL_HCD_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define INSTRUCTION_CACHE_ENABLE 1
#define DATA_CACHE_ENABLE 1
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1 */
/* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2
#define MAC_ADDR1 0
#define MAC_ADDR2 0
#define MAC_ADDR3 0
#define MAC_ADDR4 0
#define MAC_ADDR5 0
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* DP83848 PHY Address*/
#define DP83848_PHY_ADDRESS 0x01
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
#define PHY_READ_TO ((uint32_t)0x0000FFFF)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f4xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f4xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f4xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f4xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f4xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f4xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32f4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32f4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32f4xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32f4xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f4xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f4xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f4xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_SDRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sdram.h"
#endif /* HAL_SDRAM_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32f4xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f4xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32f4xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32f4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32f4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32f4xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f4xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

7
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.h
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@ -2,13 +2,13 @@
****************************************************************************** ******************************************************************************
* @file system_stm32f4xx.h * @file system_stm32f4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.1.0 * @version V2.3.0
* @date 19-June-2014 * @date 02-March-2015
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
@ -103,7 +103,6 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Cloc
extern void SystemInit(void); extern void SystemInit(void);
extern void SystemCoreClockUpdate(void); extern void SystemCoreClockUpdate(void);
extern void SetSysClock(void); extern void SetSysClock(void);
/** /**
* @} * @}
*/ */