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Target K64F addition. 

Squashed commit of the following:

commit db3c9f7682083abeb291e01df31e67e4c50845b3
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Wed Apr 2 09:52:00 2014 +0200

    K64F - KSDK - Warnings fixes

commit a639a5cdff889c13509c954b0a34ebac861c1361
Merge: 67a2c2a f3de345
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Tue Apr 1 12:48:35 2014 +0200

    Merge branch latest 'master' into dev_target_k64f

    Conflicts:
    	libraries/rtos/rtx/RTX_Conf_CM.c
    	workspace_tools/build_api.py

commit 67a2c2aeb976f264db52ea10d18fea9de0d7685f
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Sun Mar 30 13:19:51 2014 +0200

    K64F - PinName for buttons (SW2, SW3)

commit 957573e2cd42d5c73ed99477abb98c8b883695b2
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Tue Mar 25 11:46:57 2014 +0100

    K64F - pins addition to mbed HAL, uart - 4 instances, fix i2c instance which was not stored

commit 2347a6d03984e297190910a250f2771032ae6327
Author: sg- <sam.w.grove@gmail.com>
Date:   Mon Mar 24 15:20:51 2014 -0500

    Added wait to i2c stop

commit b7b4a9c72e8724087a44078c41a2cb33e4c8d5e3
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Mon Mar 24 19:28:16 2014 +0100

    K64F - I2c - ack flag retreive correction (logic inverted in ksdk hal)

commit 46c875251263029e32463c3b48473b10496088d9
Author: sg- <sam.w.grove@gmail.com>
Date:   Mon Mar 24 13:16:18 2014 -0500

    Added I2C Pinnames

commit b71c7a0dfba7025662f9a9d176494ce4dc86273e
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Tue Mar 18 17:02:34 2014 +0100

    K64F Arduino pinNames update

commit d41b0ee493263d1d80fcb72b3f0d4d788359c7c9
Merge: 9c0a982 e2574eb
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Tue Mar 18 14:57:57 2014 +0100

    Merge remote-tracking branch 'upstream/master' into dev_target_k64f.
    K64F gpio changed according to the latest mbed master.

    Conflicts:
    	libraries/rtos/rtx/RTX_CM_lib.h
    	workspace_tools/export/uvision4.py

commit 9c0a9822ab14263fff5e3b6459b7c2b4a77ce30c
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Mon Mar 17 21:08:17 2014 +0100

    K64F - sleep support

commit 5edcf3603d2e7b00eedbb377203a054b7a01e51d
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Sun Mar 16 18:19:55 2014 +0100

    K64F - pullup/down corrections, LED1 - R, LED2 - G, LED3 - B

commit a2b3b53a1474d32779654765cd1ce2ba2c6b2186
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Thu Mar 13 20:55:39 2014 +0100

    K64F - SPI - delays are set, pin definition for tests

commit 1f3b3abe16f4afaaf1b75cb4bf3e3a9d5b6e50a7
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Tue Mar 11 21:26:00 2014 +0100

    K64F - DAC update - tested with test a8

    	- internal reference set to VDDA
    	- PinName DAC0_OUT

commit 26d8cf47f8c0786b290ae659beb022901029b313
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Tue Mar 11 08:31:44 2014 +0100

    KSDK - drivers layer removal, mbed HAL using only KSDK HAL

    	- ADC corrections with channels, and clock configuration

commit 67ebe14f5c88725033ea0fb135d94b6bf9a00fdb
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Mon Mar 10 12:46:08 2014 +0100

    K20 copy files removed, targets.py - vertical alignment for K64F definition

commit be5c562d513c808e5bd425195a4fb1c71f47a57e
Merge: 696a713 fe0aca9
Author: Emilio Monti <emilmont@gmail.com>
Date:   Mon Mar 10 11:14:55 2014 +0000

    Merge branch 'rtos_support' into dev_target_k64f

commit 696a713751194b4762f1cdf6c17c0786decd7808
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Mon Mar 10 12:05:30 2014 +0100

    [FIX] K64F - adc, sgtl driver updates

commit fe0aca9940bbdd5ee70a1a7341a0a2ad2abf912b
Author: Emilio Monti <emilmont@gmail.com>
Date:   Mon Mar 10 11:04:16 2014 +0000

    Add RTOS support for K64F

commit 5c3edcbca6dbcce628c7cde51ac94a6fc6278ba5
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Sun Mar 9 20:43:38 2014 +0100

    K64F - uvision templates update

    	- uvision 5.10 supports K64F

commit 33f18d11d0eadb9243f1be0ae96c5f82e2913d48
Merge: 26f7587 74e9b2e
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Sat Mar 8 10:34:25 2014 +0100

    Update branch from mbed master

    	- merge branch 'master' into dev_target_k64f

    Conflicts:
    	libraries/USBDevice/USBDevice/USBEndpoints.h
    	libraries/USBDevice/USBDevice/USBHAL_KL25Z.cpp
    	workspace_tools/export/uvision4.py
    	workspace_tools/targets.py

commit 26f75872b19a1db2a3abb34c6e773bac56acb32f
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Thu Mar 6 22:15:53 2014 +0100

    K64F - USBDevice - MPU disable in init

commit e54d6bbaa68827bd63058fbf2428e289d15ac1f7
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Wed Feb 26 21:06:58 2014 +0100

    K64F - clock setup 4 (usb clock enable)

commit c4165732b9520cb31ae3d649d50c353d09dc9932
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Wed Feb 26 20:01:47 2014 +0100

    K64F - USBDevice addition

commit 9fcdbb8562b1415561b04e902fcdbb4724add5af
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Mon Feb 24 19:11:48 2014 +0100

    K64F SPI HAL - initial version

commit 8093df58fa7d17fcb5ad04872c958d5254ee1d8a
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Sat Feb 22 13:14:44 2014 +0100

    K64F - RTC and I2C implementation (using KPSDK HAL)

    	- instance correction in objects and peripherals names headers

commit 7ef3fbda605c2bd53a86f37d0676c0393b2e2949
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Fri Feb 14 09:45:27 2014 +0100

    mbed RTC HAL for K64F

commit e40332fd2db8bf36b3e6cabac5729e013da40c28
Merge: e059f65 6bfcd87
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Thu Feb 13 14:20:20 2014 +0100

    Merge branch 'master' into dev_target_k64f

    Conflicts:
    	workspace_tools/build_api.py
    	workspace_tools/export/uvision4.py
    	workspace_tools/targets.py
    	workspace_tools/toolchains/__init__.py

commit e059f65fd09694418f9fa4f38da90954ab9decfe
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Wed Feb 5 21:35:49 2014 +0100

    pwm mbed HAL

    	- using jusst ftm hal from KPSDK, not yet functional

commit b784278872b1d66ce2940f4988e0479971de8bc0
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Mon Feb 3 18:28:24 2014 +0100

    uvision exporters for K64F, uticker - lptmr

    	- lptmr - no hal neiter driver, quick implementation using registers and internal clock
    	- exporters for K64F - using K60 1MB target, because K64F is not available in 4.7 yet

commit 7a030693e025c2bd456563f3e6f4456033d3f644
Author: Bogdan Marinescu <bogdan.marinescu@arm.com>
Date:   Tue Jan 28 16:29:54 2014 +0200

    Attempt to keep target's include directory structure

commit a2445b383224125abf4ee23bd17f1e685010a4a5
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Mon Jan 27 07:25:16 2014 +0100

    Original KPSDK include directory structure for device

commit 9c07c58bb9cf5e9d8be4c3bec117ee87a5ea81c0
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Fri Jan 24 16:51:17 2014 +0000

    K64F ADC - initial commit

    	- ADC using KPSDK driver

commit 88e03ef8c5855a57887bb36cddfa5ab1491d400c
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Fri Jan 24 12:18:14 2014 +0000

    GPI IRQ

    	- nvic vectors number correction
    	- gpio irq HAL implementation

commit e83f1108ae9f779ce240d6cdfe23532bfa00a55e
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Fri Jan 24 10:06:44 2014 +0000

    PORT HAL implementation

    	- using gpio hal port

commit 75c21943200c8240d1edaf0a67f84b9f3b43db7f
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Thu Jan 23 16:02:36 2014 +0000

    Serial (only 8bit at the moment), using KPSDK HAL

commit 296e79def617f005918cd8e2aa574f2908a362ca
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Thu Jan 23 08:35:50 2014 +0000

    Folder structure correction for K64F - KPSDK

    	- scripts reverted, only new macro is available
    	- K64F specific headers are in HAL in device folder

commit f236b1ffcb9c8b443ad8483bca8b0e564a63f004
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Wed Jan 22 16:07:30 2014 +0100

    update KPSDK to RC1

    	- the update causes few more dependences which were reported. Will be removed later (usb, boards)
    	- pit timer - hal use , pit driver uses us period

commit f02c5353d4920e885f803ad235e5e82001e97b94
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Tue Jan 21 09:45:55 2014 +0100

    KPSDK In/out  declaration removal

commit 8c88e098b4dc4901753309f1e6db4adb8aca4384
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Tue Jan 21 09:12:41 2014 +0100

    gpio_t struct only needs pinName

    	- gpio_init creates init objects on stack

commit 6b96d4ea2c5a6a2cb13571d740ffb679a62f8f3d
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Mon Jan 20 19:59:03 2014 +0100

    us ticker - pit implementation (not functional yet)

    	- pit driver in KPSDK - added sdk prefix to needed functions

commit 098e60a3846abcd4c9c00bd199b01d4b1899807f
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Mon Jan 20 13:01:58 2014 +0100

    GPIO HAL - gpio_set implementation

commit 2bfebbfc75dcd08c20297ba42dc0cc82e5381a40
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Sun Jan 19 20:46:55 2014 +0100

    GPIO KPSDK changes

    	- gpio driver - sdk prefix, no lookuptable, input/output declaration, refactoring, set MUX to GPIO
    	- gpio api in mbed implementation, tested on blue led

commit d083733c485fbdd79ed9ce87100df9fee82294a7
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Sat Jan 18 17:14:09 2014 +0100

    Update folder structure for KPSDK

    	- drivers addition
    	- usb (needed by drivers - needs to be fixed)
    	- utilities
    	- hal folder
    	- drivers/flash removed (needs to be fixed)
    	- usb host removed (needs to be fixed)

commit 9abcf3d94a2cc849cd6e586c1bad650b6a340a0c
Author: 0xc0170 <c0170@rocketmail.com>
Date:   Thu Jan 16 11:06:16 2014 +0100

    Initial commit for K64F

    	- KPSDK addition
    	- CMSIS + HAL for K64F
    	- HAL is not yet implemented
    	- scripts - target contain macros, ignore folders, cmsis copy folders
pull/245/head
0xc0170 2014-04-02 14:39:01 +02:00
parent 213efa7175
commit 03b3a4e895
160 changed files with 171586 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
libraries/USBDevice/USBDevice/USBEndpoints.h
View File

@ -41,7 +41,7 @@ typedef enum {
#include "USBEndpoints_LPC17_LPC23.h"
#elif defined(TARGET_LPC11UXX) || defined(TARGET_LPC1347)
#include "USBEndpoints_LPC11U.h"
#elif defined(TARGET_KL25Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D5M)
#elif defined(TARGET_KL25Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D5M) | defined(TARGET_K64F)
#include "USBEndpoints_KL25Z.h"
#elif defined (TARGET_STM32F4XX)
#include "USBEndpoints_STM32F4.h"

11
libraries/USBDevice/USBDevice/USBHAL_KL25Z.cpp
View File

@ -16,7 +16,7 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#if defined(TARGET_KL25Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D5M)
#if defined(TARGET_KL25Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D5M) | defined(TARGET_K64F)
#include "USBHAL.h"
@ -86,6 +86,9 @@ USBHAL::USBHAL(void) {
// Disable IRQ
NVIC_DisableIRQ(USB0_IRQn);
#if defined(TARGET_K64F)
MPU->CESR=0;
#endif
// fill in callback array
epCallback[0] = &USBHAL::EP1_OUT_callback;
epCallback[1] = &USBHAL::EP1_IN_callback;
@ -136,9 +139,9 @@ USBHAL::USBHAL(void) {
while(USB0->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
// Set BDT Base Register
USB0->BDTPAGE1=(uint8_t)((uint32_t)bdt>>8);
USB0->BDTPAGE2=(uint8_t)((uint32_t)bdt>>16);
USB0->BDTPAGE3=(uint8_t)((uint32_t)bdt>>24);
USB0->BDTPAGE1 = (uint8_t)((uint32_t)bdt>>8);
USB0->BDTPAGE2 = (uint8_t)((uint32_t)bdt>>16);
USB0->BDTPAGE3 = (uint8_t)((uint32_t)bdt>>24);
// Clear interrupt flag
USB0->ISTAT = 0xff;

13416
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/MK64F12.h Normal file
View File

File diff suppressed because it is too large Load Diff

14
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_ARM_STD/MK64F.sct Normal file
View File

@ -0,0 +1,14 @@
LR_IROM1 0x00000000 0x100000 { ; load region size_region (1000k)
ER_IROM1 0x00000000 0x100000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0x194) = 0x198
; 0x40000 - 0x198 = 0x3FE68
RW_IRAM1 0x1FFF0198 0x3FE68 {
.ANY (+RW +ZI)
}
}

685
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_ARM_STD/startup_MK64F12.s Normal file
View File

@ -0,0 +1,685 @@
;/*****************************************************************************
; * @file: startup_MK70F12.s
; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
; * MK70F12
; * @version: 1.5
; * @date: 2012-10-19
; *
; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
;*
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; *****************************************************************************/
__initial_sp EQU 0x20030000 ; Top of RAM
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete
DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete
DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete
DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete
DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete
DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete
DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete
DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete
DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete
DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete
DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete
DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete
DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete
DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete
DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete
DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete
DCD DMA_Error_IRQHandler ; DMA Error Interrupt
DCD MCM_IRQHandler ; Normal Interrupt
DCD FTFE_IRQHandler ; FTFE Command complete interrupt
DCD Read_Collision_IRQHandler ; Read Collision Interrupt
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
DCD LLW_IRQHandler ; Low Leakage Wakeup
DCD Watchdog_IRQHandler ; WDOG Interrupt
DCD RNG_IRQHandler ; RNG Interrupt
DCD I2C0_IRQHandler ; I2C0 interrupt
DCD I2C1_IRQHandler ; I2C1 interrupt
DCD SPI0_IRQHandler ; SPI0 Interrupt
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
DCD UART0_LON_IRQHandler ; UART0 LON interrupt
DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt
DCD UART0_ERR_IRQHandler ; UART0 Error interrupt
DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt
DCD UART1_ERR_IRQHandler ; UART1 Error interrupt
DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt
DCD UART2_ERR_IRQHandler ; UART2 Error interrupt
DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt
DCD UART3_ERR_IRQHandler ; UART3 Error interrupt
DCD ADC0_IRQHandler ; ADC0 interrupt
DCD CMP0_IRQHandler ; CMP0 interrupt
DCD CMP1_IRQHandler ; CMP1 interrupt
DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
DCD CMT_IRQHandler ; CMT interrupt
DCD RTC_IRQHandler ; RTC interrupt
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
DCD PDB0_IRQHandler ; PDB0 Interrupt
DCD USB0_IRQHandler ; USB0 interrupt
DCD USBDCD_IRQHandler ; USBDCD Interrupt
DCD Reserved71_IRQHandler ; Reserved interrupt 71
DCD DAC0_IRQHandler ; DAC0 interrupt
DCD MCG_IRQHandler ; MCG Interrupt
DCD LPTimer_IRQHandler ; LPTimer interrupt
DCD PORTA_IRQHandler ; Port A interrupt
DCD PORTB_IRQHandler ; Port B interrupt
DCD PORTC_IRQHandler ; Port C interrupt
DCD PORTD_IRQHandler ; Port D interrupt
DCD PORTE_IRQHandler ; Port E interrupt
DCD SWI_IRQHandler ; Software interrupt
DCD SPI2_IRQHandler ; SPI2 Interrupt
DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt
DCD UART4_ERR_IRQHandler ; UART4 Error interrupt
DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt
DCD UART5_ERR_IRQHandler ; UART5 Error interrupt
DCD CMP2_IRQHandler ; CMP2 interrupt
DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt
DCD DAC1_IRQHandler ; DAC1 interrupt
DCD ADC1_IRQHandler ; ADC1 interrupt
DCD I2C2_IRQHandler ; I2C2 interrupt
DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
DCD SDHC_IRQHandler ; SDHC interrupt
DCD ENET_1588_Timer_IRQHandler ; Ethernet MAC IEEE 1588 Timer Interrupt
DCD ENET_Transmit_IRQHandler ; Ethernet MAC Transmit Interrupt
DCD ENET_Receive_IRQHandler ; Ethernet MAC Receive Interrupt
DCD ENET_Error_IRQHandler ; Ethernet MAC Error and miscelaneous Interrupt
DCD DefaultISR ; 102
DCD DefaultISR ; 103
DCD DefaultISR ; 104
DCD DefaultISR ; 105
DCD DefaultISR ; 106
DCD DefaultISR ; 107
DCD DefaultISR ; 108
DCD DefaultISR ; 109
DCD DefaultISR ; 110
DCD DefaultISR ; 111
DCD DefaultISR ; 112
DCD DefaultISR ; 113
DCD DefaultISR ; 114
DCD DefaultISR ; 115
DCD DefaultISR ; 116
DCD DefaultISR ; 117
DCD DefaultISR ; 118
DCD DefaultISR ; 119
DCD DefaultISR ; 120
DCD DefaultISR ; 121
DCD DefaultISR ; 122
DCD DefaultISR ; 123
DCD DefaultISR ; 124
DCD DefaultISR ; 125
DCD DefaultISR ; 126
DCD DefaultISR ; 127
DCD DefaultISR ; 128
DCD DefaultISR ; 129
DCD DefaultISR ; 130
DCD DefaultISR ; 131
DCD DefaultISR ; 132
DCD DefaultISR ; 133
DCD DefaultISR ; 134
DCD DefaultISR ; 135
DCD DefaultISR ; 136
DCD DefaultISR ; 137
DCD DefaultISR ; 138
DCD DefaultISR ; 139
DCD DefaultISR ; 140
DCD DefaultISR ; 141
DCD DefaultISR ; 142
DCD DefaultISR ; 143
DCD DefaultISR ; 144
DCD DefaultISR ; 145
DCD DefaultISR ; 146
DCD DefaultISR ; 147
DCD DefaultISR ; 148
DCD DefaultISR ; 149
DCD DefaultISR ; 150
DCD DefaultISR ; 151
DCD DefaultISR ; 152
DCD DefaultISR ; 153
DCD DefaultISR ; 154
DCD DefaultISR ; 155
DCD DefaultISR ; 156
DCD DefaultISR ; 157
DCD DefaultISR ; 158
DCD DefaultISR ; 159
DCD DefaultISR ; 160
DCD DefaultISR ; 161
DCD DefaultISR ; 162
DCD DefaultISR ; 163
DCD DefaultISR ; 164
DCD DefaultISR ; 165
DCD DefaultISR ; 166
DCD DefaultISR ; 167
DCD DefaultISR ; 168
DCD DefaultISR ; 169
DCD DefaultISR ; 170
DCD DefaultISR ; 171
DCD DefaultISR ; 172
DCD DefaultISR ; 173
DCD DefaultISR ; 174
DCD DefaultISR ; 175
DCD DefaultISR ; 176
DCD DefaultISR ; 177
DCD DefaultISR ; 178
DCD DefaultISR ; 179
DCD DefaultISR ; 180
DCD DefaultISR ; 181
DCD DefaultISR ; 182
DCD DefaultISR ; 183
DCD DefaultISR ; 184
DCD DefaultISR ; 185
DCD DefaultISR ; 186
DCD DefaultISR ; 187
DCD DefaultISR ; 188
DCD DefaultISR ; 189
DCD DefaultISR ; 190
DCD DefaultISR ; 191
DCD DefaultISR ; 192
DCD DefaultISR ; 193
DCD DefaultISR ; 194
DCD DefaultISR ; 195
DCD DefaultISR ; 196
DCD DefaultISR ; 197
DCD DefaultISR ; 198
DCD DefaultISR ; 199
DCD DefaultISR ; 200
DCD DefaultISR ; 201
DCD DefaultISR ; 202
DCD DefaultISR ; 203
DCD DefaultISR ; 204
DCD DefaultISR ; 205
DCD DefaultISR ; 206
DCD DefaultISR ; 207
DCD DefaultISR ; 208
DCD DefaultISR ; 209
DCD DefaultISR ; 210
DCD DefaultISR ; 211
DCD DefaultISR ; 212
DCD DefaultISR ; 213
DCD DefaultISR ; 214
DCD DefaultISR ; 215
DCD DefaultISR ; 216
DCD DefaultISR ; 217
DCD DefaultISR ; 218
DCD DefaultISR ; 219
DCD DefaultISR ; 220
DCD DefaultISR ; 221
DCD DefaultISR ; 222
DCD DefaultISR ; 223
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DCD DefaultISR ; 225
DCD DefaultISR ; 226
DCD DefaultISR ; 227
DCD DefaultISR ; 228
DCD DefaultISR ; 229
DCD DefaultISR ; 230
DCD DefaultISR ; 231
DCD DefaultISR ; 232
DCD DefaultISR ; 233
DCD DefaultISR ; 234
DCD DefaultISR ; 235
DCD DefaultISR ; 236
DCD DefaultISR ; 237
DCD DefaultISR ; 238
DCD DefaultISR ; 239
DCD DefaultISR ; 240
DCD DefaultISR ; 241
DCD DefaultISR ; 242
DCD DefaultISR ; 243
DCD DefaultISR ; 244
DCD DefaultISR ; 245
DCD DefaultISR ; 246
DCD DefaultISR ; 247
DCD DefaultISR ; 248
DCD DefaultISR ; 249
DCD DefaultISR ; 250
DCD DefaultISR ; 251
DCD DefaultISR ; 252
DCD DefaultISR ; 253
DCD DefaultISR ; 254
DCD DefaultISR ; 255
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
; <h> Flash Configuration
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
; <i> and security information that allows the MCU to restrict acces to the FTFL module.
; <h> Backdoor Comparison Key
; <o0> Backdoor Key 0 <0x0-0xFF:2>
; <o1> Backdoor Key 1 <0x0-0xFF:2>
; <o2> Backdoor Key 2 <0x0-0xFF:2>
; <o3> Backdoor Key 3 <0x0-0xFF:2>
; <o4> Backdoor Key 4 <0x0-0xFF:2>
; <o5> Backdoor Key 5 <0x0-0xFF:2>
; <o6> Backdoor Key 6 <0x0-0xFF:2>
; <o7> Backdoor Key 7 <0x0-0xFF:2>
BackDoorK0 EQU 0xFF
BackDoorK1 EQU 0xFF
BackDoorK2 EQU 0xFF
BackDoorK3 EQU 0xFF
BackDoorK4 EQU 0xFF
BackDoorK5 EQU 0xFF
BackDoorK6 EQU 0xFF
BackDoorK7 EQU 0xFF
; </h>
; <h> Program flash protection bytes (FPROT)
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
; <i> Each bit protects a 1/32 region of the program flash memory.
; <h> FPROT0
; <i> Program flash protection bytes
; <i> 1/32 - 8/32 region
; <o.0> FPROT0.0
; <o.1> FPROT0.1
; <o.2> FPROT0.2
; <o.3> FPROT0.3
; <o.4> FPROT0.4
; <o.5> FPROT0.5
; <o.6> FPROT0.6
; <o.7> FPROT0.7
nFPROT0 EQU 0x00
FPROT0 EQU nFPROT0:EOR:0xFF
; </h>
; <h> FPROT1
; <i> Program Flash Region Protect Register 1
; <i> 9/32 - 16/32 region
; <o.0> FPROT1.0
; <o.1> FPROT1.1
; <o.2> FPROT1.2
; <o.3> FPROT1.3
; <o.4> FPROT1.4
; <o.5> FPROT1.5
; <o.6> FPROT1.6
; <o.7> FPROT1.7
nFPROT1 EQU 0x00
FPROT1 EQU nFPROT1:EOR:0xFF
; </h>
; <h> FPROT2
; <i> Program Flash Region Protect Register 2
; <i> 17/32 - 24/32 region
; <o.0> FPROT2.0
; <o.1> FPROT2.1
; <o.2> FPROT2.2
; <o.3> FPROT2.3
; <o.4> FPROT2.4
; <o.5> FPROT2.5
; <o.6> FPROT2.6
; <o.7> FPROT2.7
nFPROT2 EQU 0x00
FPROT2 EQU nFPROT2:EOR:0xFF
; </h>
; <h> FPROT3
; <i> Program Flash Region Protect Register 3
; <i> 25/32 - 32/32 region
; <o.0> FPROT3.0
; <o.1> FPROT3.1
; <o.2> FPROT3.2
; <o.3> FPROT3.3
; <o.4> FPROT3.4
; <o.5> FPROT3.5
; <o.6> FPROT3.6
; <o.7> FPROT3.7
nFPROT3 EQU 0x00
FPROT3 EQU nFPROT3:EOR:0xFF
; </h>
; </h>
; <h> Data flash protection byte (FDPROT)
; <i> Each bit protects a 1/8 region of the data flash memory.
; <i> (Program flash only devices: Reserved)
; <o.0> FDPROT.0
; <o.1> FDPROT.1
; <o.2> FDPROT.2
; <o.3> FDPROT.3
; <o.4> FDPROT.4
; <o.5> FDPROT.5
; <o.6> FDPROT.6
; <o.7> FDPROT.7
nFDPROT EQU 0x00
FDPROT EQU nFDPROT:EOR:0xFF
; </h>
; <h> EEPROM protection byte (FEPROT)
; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
; <i> (Program flash only devices: Reserved)
; <o.0> FEPROT.0
; <o.1> FEPROT.1
; <o.2> FEPROT.2
; <o.3> FEPROT.3
; <o.4> FEPROT.4
; <o.5> FEPROT.5
; <o.6> FEPROT.6
; <o.7> FEPROT.7
nFEPROT EQU 0x00
FEPROT EQU nFEPROT:EOR:0xFF
; </h>
; <h> Flash nonvolatile option byte (FOPT)
; <i> Allows the user to customize the operation of the MCU at boot time.
; <o.0> LPBOOT
; <0=> Low-power boot
; <1=> normal boot
; <o.1> EZPORT_DIS
; <0=> EzPort operation is enabled
; <1=> EzPort operation is disabled
FOPT EQU 0xFF
; </h>
; <h> Flash security byte (FSEC)
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
; <o.0..1> SEC
; <2=> MCU security status is unsecure
; <3=> MCU security status is secure
; <i> Flash Security
; <i> This bits define the security state of the MCU.
; <o.2..3> FSLACC
; <2=> Freescale factory access denied
; <3=> Freescale factory access granted
; <i> Freescale Failure Analysis Access Code
; <i> This bits define the security state of the MCU.
; <o.4..5> MEEN
; <2=> Mass erase is disabled
; <3=> Mass erase is enabled
; <i> Mass Erase Enable Bits
; <i> Enables and disables mass erase capability of the FTFL module
; <o.6..7> KEYEN
; <2=> Backdoor key access enabled
; <3=> Backdoor key access disabled
; <i> Backdoor key Security Enable
; <i> These bits enable and disable backdoor key access to the FTFL module.
FSEC EQU 0xFE
; </h>
; </h>
IF :LNOT::DEF:RAM_TARGET
AREA |.ARM.__at_0x400|, CODE, READONLY
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
DCB FPROT0, FPROT1, FPROT2, FPROT3
DCB FSEC, FOPT, FEPROT, FDPROT
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DMA0_IRQHandler [WEAK]
EXPORT DMA1_IRQHandler [WEAK]
EXPORT DMA2_IRQHandler [WEAK]
EXPORT DMA3_IRQHandler [WEAK]
EXPORT DMA4_IRQHandler [WEAK]
EXPORT DMA5_IRQHandler [WEAK]
EXPORT DMA6_IRQHandler [WEAK]
EXPORT DMA7_IRQHandler [WEAK]
EXPORT DMA8_IRQHandler [WEAK]
EXPORT DMA9_IRQHandler [WEAK]
EXPORT DMA10_IRQHandler [WEAK]
EXPORT DMA11_IRQHandler [WEAK]
EXPORT DMA12_IRQHandler [WEAK]
EXPORT DMA13_IRQHandler [WEAK]
EXPORT DMA14_IRQHandler [WEAK]
EXPORT DMA15_IRQHandler [WEAK]
EXPORT DMA_Error_IRQHandler [WEAK]
EXPORT MCM_IRQHandler [WEAK]
EXPORT FTFE_IRQHandler [WEAK]
EXPORT Read_Collision_IRQHandler [WEAK]
EXPORT LVD_LVW_IRQHandler [WEAK]
EXPORT LLW_IRQHandler [WEAK]
EXPORT Watchdog_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT I2S0_Tx_IRQHandler [WEAK]
EXPORT I2S0_Rx_IRQHandler [WEAK]
EXPORT UART0_LON_IRQHandler [WEAK]
EXPORT UART0_RX_TX_IRQHandler [WEAK]
EXPORT UART0_ERR_IRQHandler [WEAK]
EXPORT UART1_RX_TX_IRQHandler [WEAK]
EXPORT UART1_ERR_IRQHandler [WEAK]
EXPORT UART2_RX_TX_IRQHandler [WEAK]
EXPORT UART2_ERR_IRQHandler [WEAK]
EXPORT UART3_RX_TX_IRQHandler [WEAK]
EXPORT UART3_ERR_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT CMP0_IRQHandler [WEAK]
EXPORT CMP1_IRQHandler [WEAK]
EXPORT FTM0_IRQHandler [WEAK]
EXPORT FTM1_IRQHandler [WEAK]
EXPORT FTM2_IRQHandler [WEAK]
EXPORT CMT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RTC_Seconds_IRQHandler [WEAK]
EXPORT PIT0_IRQHandler [WEAK]
EXPORT PIT1_IRQHandler [WEAK]
EXPORT PIT2_IRQHandler [WEAK]
EXPORT PIT3_IRQHandler [WEAK]
EXPORT PDB0_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USBDCD_IRQHandler [WEAK]
EXPORT Reserved71_IRQHandler [WEAK]
EXPORT DAC0_IRQHandler [WEAK]
EXPORT MCG_IRQHandler [WEAK]
EXPORT LPTimer_IRQHandler [WEAK]
EXPORT PORTA_IRQHandler [WEAK]
EXPORT PORTB_IRQHandler [WEAK]
EXPORT PORTC_IRQHandler [WEAK]
EXPORT PORTD_IRQHandler [WEAK]
EXPORT PORTE_IRQHandler [WEAK]
EXPORT SWI_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT UART4_RX_TX_IRQHandler [WEAK]
EXPORT UART4_ERR_IRQHandler [WEAK]
EXPORT UART5_RX_TX_IRQHandler [WEAK]
EXPORT UART5_ERR_IRQHandler [WEAK]
EXPORT CMP2_IRQHandler [WEAK]
EXPORT FTM3_IRQHandler [WEAK]
EXPORT DAC1_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK]
EXPORT CAN0_Bus_Off_IRQHandler [WEAK]
EXPORT CAN0_Error_IRQHandler [WEAK]
EXPORT CAN0_Tx_Warning_IRQHandler [WEAK]
EXPORT CAN0_Rx_Warning_IRQHandler [WEAK]
EXPORT CAN0_Wake_Up_IRQHandler [WEAK]
EXPORT SDHC_IRQHandler [WEAK]
EXPORT ENET_1588_Timer_IRQHandler [WEAK]
EXPORT ENET_Transmit_IRQHandler [WEAK]
EXPORT ENET_Receive_IRQHandler [WEAK]
EXPORT ENET_Error_IRQHandler [WEAK]
DMA0_IRQHandler ; DMA Channel 0 Transfer Complete
DMA1_IRQHandler ; DMA Channel 1 Transfer Complete
DMA2_IRQHandler ; DMA Channel 2 Transfer Complete
DMA3_IRQHandler ; DMA Channel 3 Transfer Complete
DMA4_IRQHandler ; DMA Channel 4 Transfer Complete
DMA5_IRQHandler ; DMA Channel 5 Transfer Complete
DMA6_IRQHandler ; DMA Channel 6 Transfer Complete
DMA7_IRQHandler ; DMA Channel 7 Transfer Complete
DMA8_IRQHandler ; DMA Channel 8 Transfer Complete
DMA9_IRQHandler ; DMA Channel 9 Transfer Complete
DMA10_IRQHandler ; DMA Channel 10 Transfer Complete
DMA11_IRQHandler ; DMA Channel 11 Transfer Complete
DMA12_IRQHandler ; DMA Channel 12 Transfer Complete
DMA13_IRQHandler ; DMA Channel 13 Transfer Complete
DMA14_IRQHandler ; DMA Channel 14 Transfer Complete
DMA15_IRQHandler ; DMA Channel 15 Transfer Complete
DMA_Error_IRQHandler ; DMA Error Interrupt
MCM_IRQHandler ; Normal Interrupt
FTFE_IRQHandler ; FTFE Command complete interrupt
Read_Collision_IRQHandler ; Read Collision Interrupt
LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
LLW_IRQHandler ; Low Leakage Wakeup
Watchdog_IRQHandler ; WDOG Interrupt
RNG_IRQHandler ; RNG Interrupt
I2C0_IRQHandler ; I2C0 interrupt
I2C1_IRQHandler ; I2C1 interrupt
SPI0_IRQHandler ; SPI0 Interrupt
SPI1_IRQHandler ; SPI1 Interrupt
I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
I2S0_Rx_IRQHandler ; I2S0 receive interrupt
UART0_LON_IRQHandler ; UART0 LON interrupt
UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt
UART0_ERR_IRQHandler ; UART0 Error interrupt
UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt
UART1_ERR_IRQHandler ; UART1 Error interrupt
UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt
UART2_ERR_IRQHandler ; UART2 Error interrupt
UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt
UART3_ERR_IRQHandler ; UART3 Error interrupt
ADC0_IRQHandler ; ADC0 interrupt
CMP0_IRQHandler ; CMP0 interrupt
CMP1_IRQHandler ; CMP1 interrupt
FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
CMT_IRQHandler ; CMT interrupt
RTC_IRQHandler ; RTC interrupt
RTC_Seconds_IRQHandler ; RTC seconds interrupt
PIT0_IRQHandler ; PIT timer channel 0 interrupt
PIT1_IRQHandler ; PIT timer channel 1 interrupt
PIT2_IRQHandler ; PIT timer channel 2 interrupt
PIT3_IRQHandler ; PIT timer channel 3 interrupt
PDB0_IRQHandler ; PDB0 Interrupt
USB0_IRQHandler ; USB0 interrupt
USBDCD_IRQHandler ; USBDCD Interrupt
Reserved71_IRQHandler ; Reserved interrupt 71
DAC0_IRQHandler ; DAC0 interrupt
MCG_IRQHandler ; MCG Interrupt
LPTimer_IRQHandler ; LPTimer interrupt
PORTA_IRQHandler ; Port A interrupt
PORTB_IRQHandler ; Port B interrupt
PORTC_IRQHandler ; Port C interrupt
PORTD_IRQHandler ; Port D interrupt
PORTE_IRQHandler ; Port E interrupt
SWI_IRQHandler ; Software interrupt
SPI2_IRQHandler ; SPI2 Interrupt
UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt
UART4_ERR_IRQHandler ; UART4 Error interrupt
UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt
UART5_ERR_IRQHandler ; UART5 Error interrupt
CMP2_IRQHandler ; CMP2 interrupt
FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt
DAC1_IRQHandler ; DAC1 interrupt
ADC1_IRQHandler ; ADC1 interrupt
I2C2_IRQHandler ; I2C2 interrupt
CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
CAN0_Error_IRQHandler ; CAN0 error interrupt
CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
SDHC_IRQHandler ; SDHC interrupt
ENET_1588_Timer_IRQHandler ; Ethernet MAC IEEE 1588 Timer Interrupt
ENET_Transmit_IRQHandler ; Ethernet MAC Transmit Interrupt
ENET_Receive_IRQHandler ; Ethernet MAC Receive Interrupt
ENET_Error_IRQHandler ; Ethernet MAC Error and miscelaneous Interrupt
DefaultISR
B .
ENDP
ALIGN
END

31
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_ARM_STD/sys.cpp Normal file
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/* mbed Microcontroller Library - stackheap
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* Setup a fixed single stack/heap memory model,
* between the top of the RW/ZI region and the stackpointer
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$RW_IRAM1$$ZI$$Limit[];
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
return r;
}
#ifdef __cplusplus
}
#endif

13
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/cmsis.h Normal file
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/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in LPC11U24 specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "MK64F12.h"
#include "cmsis_nvic.h"
#endif

30
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/cmsis_nvic.c Normal file
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/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
* Copyright (c) 2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x1FFF0000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
uint32_t i;
// Copy and switch to dynamic vectors if the first time called
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
uint32_t *old_vectors = vectors;
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
for (i=0; i<NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
}
vectors[IRQn + 16] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + 16];
}

26
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/cmsis_nvic.h Normal file
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/* mbed Microcontroller Library - cmsis_nvic
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 85) // CORE + MCU Peripherals
#define NVIC_USER_IRQ_OFFSET 16
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

422
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K64F/system_MK64F12.c Normal file
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/*
** ###################################################################
** Processor: MK64FN1M0VMD12
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K64P144M120SF5RM, Rev.1, July 2013
** Version: rev. 2.1, 2013-10-29
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2013 Freescale, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-08-12)
** Initial version.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** MCG - registers updated.
** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
** - rev. 2.1 (2013-10-29)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
**
** ###################################################################
*/
/*!
* @file MK64F12
* @version 2.1
* @date 2013-10-29
* @brief Device specific configuration file for MK64F12 (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "MK64F12.h"
#define DISABLE_WDOG 1
#ifndef CLOCK_SETUP
#define CLOCK_SETUP 4
#endif
/* Predefined clock setups
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
Default part configuration.
Reference clock source for MCG module is the slow internal clock source 32.768kHz
Core clock = 20.97MHz, BusClock = 20.97MHz
1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
Maximum achievable clock frequency configuration.
Reference clock source for MCG module is an external clock source 50MHz
Core clock = 120MHz, BusClock = 60MHz
2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power Internal (BLPI) mode
Core clock/Bus clock derived directly from an fast internal clock 4MHz with no multiplication
The clock settings is ready for Very Low Power Run mode.
Core clock = 4MHz, BusClock = 4MHz
3 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
Core clock/Bus clock derived directly from the RTC oscillator clock source 32.768kHz
The clock settings is ready for Very Low Power Run mode.
Core clock = 32.768kHz, BusClock = 32.768kHz
4 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
USB clock setup
USB clock divider is set for USB to receive 48MHz input clock.
Reference clock source for MCG module is an external clock source 50MHz
USB clock divider is set for USB to receive 48MHz input clock.
Core clock = 120MHz, BusClock = 60MHz
*/
/*----------------------------------------------------------------------------
Define clock source values
*----------------------------------------------------------------------------*/
#if (CLOCK_SETUP == 0)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 20485760u /* Default System clock value */
#elif (CLOCK_SETUP == 1)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
#elif (CLOCK_SETUP == 2)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
#elif (CLOCK_SETUP == 3)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
#elif (CLOCK_SETUP == 4)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
#endif /* (CLOCK_SETUP == 4) */
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit (void) {
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
#if (DISABLE_WDOG)
/* Disable the WDOG module */
/* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
/* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
/* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
WDOG_STCTRLH_WAITEN_MASK |
WDOG_STCTRLH_STOPEN_MASK |
WDOG_STCTRLH_ALLOWUPDATE_MASK |
WDOG_STCTRLH_CLKSRC_MASK |
0x0100U;
#endif /* (DISABLE_WDOG) */
/*
* Release hold with ACKISO: Only has an effect if recovering from VLLSx.
* if ACKISO is set you must clear ackiso before initializing the PLL
* if osc enabled in low power modes - enable it first before ack
*/
if (PMC->REGSC & PMC_REGSC_ACKISO_MASK)
{
PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
}
#if (CLOCK_SETUP == 0)
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV2(0x00) |
SIM_CLKDIV1_OUTDIV3(0x01) |
SIM_CLKDIV1_OUTDIV4(0x01); /* Update system prescalers */
/* SIM->SOPT2: PLLFLLSEL=0 */
SIM->SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */
/* SIM->SOPT1: OSC32KSEL=3 */
SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
/* Switch to FEI Mode */
/* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(0x00) |
MCG_C1_FRDIV(0x00) |
MCG_C1_IREFS_MASK |
MCG_C1_IRCLKEN_MASK;
/* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
MCG->C2 = MCG_C2_RANGE0(0x00);
/* MCG->C4: DMX32=0,DRST_DRS=0 */
MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
/* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC->CR = OSC_CR_ERCLKEN_MASK;
/* MCG->C7: OSCSEL=0 */
MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);
/* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
MCG->C5 = MCG_C5_PRDIV0(0x00);
/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
MCG->C6 = MCG_C6_VDIV0(0x00);
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
}
while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
}
#elif (CLOCK_SETUP == 1) || (CLOCK_SETUP == 4)
/* SIM->SCGC5: PORTA=1 */
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV2(0x01) |
SIM_CLKDIV1_OUTDIV3(0x02) |
SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */
/* SIM->SOPT2: PLLFLLSEL=1 */
SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */
/* SIM->SOPT1: OSC32KSEL=3 */
SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
/* PORTA->PCR[18]: ISF=0,MUX=0 */
PORTA->PCR[18] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* Switch to FBE Mode */
/* MCG->C2: LOCRE0=0,?=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
MCG->C2 = MCG_C2_RANGE0(0x02);
/* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC->CR = OSC_CR_ERCLKEN_MASK;
/* MCG->C7: OSCSEL=0 */
MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);
/* MCG->C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x07) | MCG_C1_IRCLKEN_MASK);
/* MCG->C4: DMX32=0,DRST_DRS=0 */
MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
/* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
MCG->C5 = MCG_C5_PRDIV0(0x13);
/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0x18 */
MCG->C6 = MCG_C6_VDIV0(0x18);
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
/* Switch to PBE Mode */
/* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
MCG->C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x18));
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
}
/* Switch to PEE Mode */
/* MCG->C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x05) | MCG_C1_IRCLKEN_MASK);
while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
}
#if (CLOCK_SETUP == 4)
/* Set USB input clock to 48MHz */
/* SIM->CLKDIV2: USBDIV=4,USBFRAC=1 */
SIM->CLKDIV2 = (uint32_t)((SIM->CLKDIV2 & (uint32_t)~(uint32_t)(
SIM_CLKDIV2_USBDIV(0x03)
)) | (uint32_t)(
SIM_CLKDIV2_USBDIV(0x04) |
SIM_CLKDIV2_USBFRAC_MASK
));
#endif
#elif (CLOCK_SETUP == 2)
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV2(0x00) |
SIM_CLKDIV1_OUTDIV3(0x00) |
SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */
/* SIM->SOPT2: PLLFLLSEL=0 */
SIM->SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */
/* SIM->SOPT1: OSC32KSEL=3 */
SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
/* MCG->SC: FCRDIV=0 */
MCG->SC &= (uint8_t)~(uint8_t)(MCG_SC_FCRDIV(0x07));
/* Switch to FBI Mode */
/* MCG->C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(0x01) |
MCG_C1_FRDIV(0x00) |
MCG_C1_IREFS_MASK |
MCG_C1_IRCLKEN_MASK;
/* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=1 */
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_IRCS_MASK);
/* MCG->C4: DMX32=0,DRST_DRS=0 */
MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
/* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC->CR = OSC_CR_ERCLKEN_MASK;
/* MCG->C7: OSCSEL=0 */
MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);
/* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
MCG->C5 = MCG_C5_PRDIV0(0x00);
/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
MCG->C6 = MCG_C6_VDIV0(0x00);
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
}
while((MCG->S & 0x0CU) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
}
/* Switch to BLPI Mode */
/* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=1,IRCS=1 */
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_LP_MASK | MCG_C2_IRCS_MASK);
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
}
while((MCG->S & MCG_S_IRCST_MASK) == 0x00U) { /* Check that the fast external reference clock is selected. */
}
#elif (CLOCK_SETUP == 3)
/* SIM->SCGC6: RTC=1 */
SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the OSCILLATOR is not already enabled */
/* RTC->CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
RTC->CR &= (uint32_t)~(uint32_t)(
RTC_CR_SC2P_MASK |
RTC_CR_SC4P_MASK |
RTC_CR_SC8P_MASK |
RTC_CR_SC16P_MASK
);
/* RTC->CR: OSCE=1 */
RTC->CR |= RTC_CR_OSCE_MASK;
/* RTC->CR: CLKO=0 */
RTC->CR &= (uint32_t)~(uint32_t)(RTC_CR_CLKO_MASK);
}
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV2(0x00) |
SIM_CLKDIV1_OUTDIV3(0x00) |
SIM_CLKDIV1_OUTDIV4(0x00); /* Update system prescalers */
/* SIM->SOPT1: OSC32KSEL=2 */
SIM->SOPT1 = (uint32_t)((SIM->SOPT1 & (uint32_t)~(uint32_t)(
SIM_SOPT1_OSC32KSEL(0x01)
)) | (uint32_t)(
SIM_SOPT1_OSC32KSEL(0x02)
)); /* System oscillator drives 32 kHz clock for various peripherals */
/* Switch to FBE Mode */
/* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
MCG->C2 = MCG_C2_RANGE0(0x00);
/* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC->CR = OSC_CR_ERCLKEN_MASK;
/* MCG->C7: OSCSEL=1 */
MCG->C7 |= MCG_C7_OSCSEL_MASK;
/* MCG->C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
/* MCG->C4: DMX32=0,DRST_DRS=0 */
MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
/* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
MCG->C5 = MCG_C5_PRDIV0(0x00);
/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
MCG->C6 = MCG_C6_VDIV0(0x00);
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
/* Switch to BLPE Mode */
/* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=1,IRCS=0 */
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_LP_MASK);
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
#endif
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate (void) {
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
uint8_t Divider;
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
/* Output of FLL or PLL is selected */
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
/* FLL is selected */
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
/* External reference clock is selected */
if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
} else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
} /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
} /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
/* Select correct multiplier to calculate the MCG output clock */
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
case 0x0u:
MCGOUTClock *= 640u;
break;
case 0x20u:
MCGOUTClock *= 1280u;
break;
case 0x40u:
MCGOUTClock *= 1920u;
break;
case 0x60u:
MCGOUTClock *= 2560u;
break;
case 0x80u:
MCGOUTClock *= 732u;
break;
case 0xA0u:
MCGOUTClock *= 1464u;
break;
case 0xC0u:
MCGOUTClock *= 2197u;
break;
case 0xE0u:
MCGOUTClock *= 2929u;
break;
default:
break;
}
} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
/* PLL is selected */
Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
MCGOUTClock *= Divider; /* Calculate the MCG output clock */
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
/* Internal reference clock is selected */
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
/* External reference clock is selected */
if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
} else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
} /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
/* Reserved value */
return;
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
}

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/*
** ###################################################################
** Processor: MK64FN1M0VMD12
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K64P144M120SF5RM, Rev.1, July 2013
** Version: rev. 2.1, 2013-10-29
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2013 Freescale, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-08-12)
** Initial version.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** MCG - registers updated.
** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
** - rev. 2.1 (2013-10-29)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
**
** ###################################################################
*/
/*!
* @file MK64F12
* @version 2.1
* @date 2013-10-29
* @brief Device specific configuration file for MK64F12 (header file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#ifndef SYSTEM_MK64F12_H_
#define SYSTEM_MK64F12_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit (void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* #if !defined(SYSTEM_MK64F12_H_) */

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
OSC32KCLK = 0,
} RTCName;
typedef enum {
UART_0 = 0,
UART_1 = 1,
UART_2 = 2,
UART_3 = 3,
UART_4 = 4,
} UARTName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_0
typedef enum {
I2C_0 = 0,
I2C_1 = 1,
I2C_2 = 2,
} I2CName;
#define TPM_SHIFT 8
typedef enum {
PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0
PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1
PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2
PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3
PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4
PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5
PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6
PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7
PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0
PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1
PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2
PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3
PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4
PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5
PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6
PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7
PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0
PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1
PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2
PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3
PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4
PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5
PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6
PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7
} PWMName;
#define ADC_INSTANCE_SHIFT 8
#define ADC_B_CHANNEL_SHIFT 5
typedef enum {
ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4,
ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5,
ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6,
ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7,
ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8,
ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9,
ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12,
ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13,
ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14,
ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15,
ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16,
ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17,
ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18,
ADC1_SE4b = (1 << ADC_INSTANCE_SHIFT) | 4,
ADC1_SE5b = (1 << ADC_INSTANCE_SHIFT) | 5,
ADC1_SE6b = (1 << ADC_INSTANCE_SHIFT) | 6,
ADC1_SE7b = (1 << ADC_INSTANCE_SHIFT) | 7,
ADC1_SE8 = (1 << ADC_INSTANCE_SHIFT) | 8,
ADC1_SE9 = (1 << ADC_INSTANCE_SHIFT) | 9,
ADC1_SE12 = (1 << ADC_INSTANCE_SHIFT) | 12,
ADC1_SE13 = (1 << ADC_INSTANCE_SHIFT) | 13,
ADC1_SE14 = (1 << ADC_INSTANCE_SHIFT) | 14,
ADC1_SE15 = (1 << ADC_INSTANCE_SHIFT) | 15,
ADC1_SE16 = (1 << ADC_INSTANCE_SHIFT) | 16,
ADC1_SE17 = (1 << ADC_INSTANCE_SHIFT) | 17,
ADC1_SE18 = (1 << ADC_INSTANCE_SHIFT) | 18,
} ADCName;
typedef enum {
DAC_0 = 0
} DACName;
typedef enum {
SPI_0 = 0,
SPI_1 = 1,
SPI_2 = 2,
} SPIName;
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define GPIO_PORT_SHIFT 12
typedef enum {
PTA0 = (0 << GPIO_PORT_SHIFT | 0),
PTA1 = (0 << GPIO_PORT_SHIFT | 1),
PTA2 = (0 << GPIO_PORT_SHIFT | 2),
PTA3 = (0 << GPIO_PORT_SHIFT | 3),
PTA4 = (0 << GPIO_PORT_SHIFT | 4),
PTA5 = (0 << GPIO_PORT_SHIFT | 5),
PTA6 = (0 << GPIO_PORT_SHIFT | 6),
PTA7 = (0 << GPIO_PORT_SHIFT | 7),
PTA8 = (0 << GPIO_PORT_SHIFT | 8),
PTA9 = (0 << GPIO_PORT_SHIFT | 9),
PTA10 = (0 << GPIO_PORT_SHIFT | 10),
PTA11 = (0 << GPIO_PORT_SHIFT | 11),
PTA12 = (0 << GPIO_PORT_SHIFT | 12),
PTA13 = (0 << GPIO_PORT_SHIFT | 13),
PTA14 = (0 << GPIO_PORT_SHIFT | 14),
PTA15 = (0 << GPIO_PORT_SHIFT | 15),
PTA16 = (0 << GPIO_PORT_SHIFT | 16),
PTA17 = (0 << GPIO_PORT_SHIFT | 17),
PTA18 = (0 << GPIO_PORT_SHIFT | 18),
PTA19 = (0 << GPIO_PORT_SHIFT | 19),
PTA20 = (0 << GPIO_PORT_SHIFT | 20),
PTA21 = (0 << GPIO_PORT_SHIFT | 21),
PTA22 = (0 << GPIO_PORT_SHIFT | 22),
PTA23 = (0 << GPIO_PORT_SHIFT | 23),
PTA24 = (0 << GPIO_PORT_SHIFT | 24),
PTA25 = (0 << GPIO_PORT_SHIFT | 25),
PTA26 = (0 << GPIO_PORT_SHIFT | 26),
PTA27 = (0 << GPIO_PORT_SHIFT | 27),
PTA28 = (0 << GPIO_PORT_SHIFT | 28),
PTA29 = (0 << GPIO_PORT_SHIFT | 29),
PTA30 = (0 << GPIO_PORT_SHIFT | 30),
PTA31 = (0 << GPIO_PORT_SHIFT | 31),
PTB0 = (1 << GPIO_PORT_SHIFT | 0),
PTB1 = (1 << GPIO_PORT_SHIFT | 1),
PTB2 = (1 << GPIO_PORT_SHIFT | 2),
PTB3 = (1 << GPIO_PORT_SHIFT | 3),
PTB4 = (1 << GPIO_PORT_SHIFT | 4),
PTB5 = (1 << GPIO_PORT_SHIFT | 5),
PTB6 = (1 << GPIO_PORT_SHIFT | 6),
PTB7 = (1 << GPIO_PORT_SHIFT | 7),
PTB8 = (1 << GPIO_PORT_SHIFT | 8),
PTB9 = (1 << GPIO_PORT_SHIFT | 9),
PTB10 = (1 << GPIO_PORT_SHIFT | 10),
PTB11 = (1 << GPIO_PORT_SHIFT | 11),
PTB12 = (1 << GPIO_PORT_SHIFT | 12),
PTB13 = (1 << GPIO_PORT_SHIFT | 13),
PTB14 = (1 << GPIO_PORT_SHIFT | 14),
PTB15 = (1 << GPIO_PORT_SHIFT | 15),
PTB16 = (1 << GPIO_PORT_SHIFT | 16),
PTB17 = (1 << GPIO_PORT_SHIFT | 17),
PTB18 = (1 << GPIO_PORT_SHIFT | 18),
PTB19 = (1 << GPIO_PORT_SHIFT | 19),
PTB20 = (1 << GPIO_PORT_SHIFT | 20),
PTB21 = (1 << GPIO_PORT_SHIFT | 21),
PTB22 = (1 << GPIO_PORT_SHIFT | 22),
PTB23 = (1 << GPIO_PORT_SHIFT | 23),
PTB24 = (1 << GPIO_PORT_SHIFT | 24),
PTB25 = (1 << GPIO_PORT_SHIFT | 25),
PTB26 = (1 << GPIO_PORT_SHIFT | 26),
PTB27 = (1 << GPIO_PORT_SHIFT | 27),
PTB28 = (1 << GPIO_PORT_SHIFT | 28),
PTB29 = (1 << GPIO_PORT_SHIFT | 29),
PTB30 = (1 << GPIO_PORT_SHIFT | 30),
PTB31 = (1 << GPIO_PORT_SHIFT | 31),
PTC0 = (2 << GPIO_PORT_SHIFT | 0),
PTC1 = (2 << GPIO_PORT_SHIFT | 1),
PTC2 = (2 << GPIO_PORT_SHIFT | 2),
PTC3 = (2 << GPIO_PORT_SHIFT | 3),
PTC4 = (2 << GPIO_PORT_SHIFT | 4),
PTC5 = (2 << GPIO_PORT_SHIFT | 5),
PTC6 = (2 << GPIO_PORT_SHIFT | 6),
PTC7 = (2 << GPIO_PORT_SHIFT | 7),
PTC8 = (2 << GPIO_PORT_SHIFT | 8),
PTC9 = (2 << GPIO_PORT_SHIFT | 9),
PTC10 = (2 << GPIO_PORT_SHIFT | 10),
PTC11 = (2 << GPIO_PORT_SHIFT | 11),
PTC12 = (2 << GPIO_PORT_SHIFT | 12),
PTC13 = (2 << GPIO_PORT_SHIFT | 13),
PTC14 = (2 << GPIO_PORT_SHIFT | 14),
PTC15 = (2 << GPIO_PORT_SHIFT | 15),
PTC16 = (2 << GPIO_PORT_SHIFT | 16),
PTC17 = (2 << GPIO_PORT_SHIFT | 17),
PTC18 = (2 << GPIO_PORT_SHIFT | 18),
PTC19 = (2 << GPIO_PORT_SHIFT | 19),
PTC20 = (2 << GPIO_PORT_SHIFT | 20),
PTC21 = (2 << GPIO_PORT_SHIFT | 21),
PTC22 = (2 << GPIO_PORT_SHIFT | 22),
PTC23 = (2 << GPIO_PORT_SHIFT | 23),
PTC24 = (2 << GPIO_PORT_SHIFT | 24),
PTC25 = (2 << GPIO_PORT_SHIFT | 25),
PTC26 = (2 << GPIO_PORT_SHIFT | 26),
PTC27 = (2 << GPIO_PORT_SHIFT | 27),
PTC28 = (2 << GPIO_PORT_SHIFT | 28),
PTC29 = (2 << GPIO_PORT_SHIFT | 29),
PTC30 = (2 << GPIO_PORT_SHIFT | 30),
PTC31 = (2 << GPIO_PORT_SHIFT | 31),
PTD0 = (3 << GPIO_PORT_SHIFT | 0),
PTD1 = (3 << GPIO_PORT_SHIFT | 1),
PTD2 = (3 << GPIO_PORT_SHIFT | 2),
PTD3 = (3 << GPIO_PORT_SHIFT | 3),
PTD4 = (3 << GPIO_PORT_SHIFT | 4),
PTD5 = (3 << GPIO_PORT_SHIFT | 5),
PTD6 = (3 << GPIO_PORT_SHIFT | 6),
PTD7 = (3 << GPIO_PORT_SHIFT | 7),
PTD8 = (3 << GPIO_PORT_SHIFT | 8),
PTD9 = (3 << GPIO_PORT_SHIFT | 9),
PTD10 = (3 << GPIO_PORT_SHIFT | 10),
PTD11 = (3 << GPIO_PORT_SHIFT | 11),
PTD12 = (3 << GPIO_PORT_SHIFT | 12),
PTD13 = (3 << GPIO_PORT_SHIFT | 13),
PTD14 = (3 << GPIO_PORT_SHIFT | 14),
PTD15 = (3 << GPIO_PORT_SHIFT | 15),
PTD16 = (3 << GPIO_PORT_SHIFT | 16),
PTD17 = (3 << GPIO_PORT_SHIFT | 17),
PTD18 = (3 << GPIO_PORT_SHIFT | 18),
PTD19 = (3 << GPIO_PORT_SHIFT | 19),
PTD20 = (3 << GPIO_PORT_SHIFT | 20),
PTD21 = (3 << GPIO_PORT_SHIFT | 21),
PTD22 = (3 << GPIO_PORT_SHIFT | 22),
PTD23 = (3 << GPIO_PORT_SHIFT | 23),
PTD24 = (3 << GPIO_PORT_SHIFT | 24),
PTD25 = (3 << GPIO_PORT_SHIFT | 25),
PTD26 = (3 << GPIO_PORT_SHIFT | 26),
PTD27 = (3 << GPIO_PORT_SHIFT | 27),
PTD28 = (3 << GPIO_PORT_SHIFT | 28),
PTD29 = (3 << GPIO_PORT_SHIFT | 29),
PTD30 = (3 << GPIO_PORT_SHIFT | 30),
PTD31 = (3 << GPIO_PORT_SHIFT | 31),
PTE0 = (4 << GPIO_PORT_SHIFT | 0),
PTE1 = (4 << GPIO_PORT_SHIFT | 1),
PTE2 = (4 << GPIO_PORT_SHIFT | 2),
PTE3 = (4 << GPIO_PORT_SHIFT | 3),
PTE4 = (4 << GPIO_PORT_SHIFT | 4),
PTE5 = (4 << GPIO_PORT_SHIFT | 5),
PTE6 = (4 << GPIO_PORT_SHIFT | 6),
PTE7 = (4 << GPIO_PORT_SHIFT | 7),
PTE8 = (4 << GPIO_PORT_SHIFT | 8),
PTE9 = (4 << GPIO_PORT_SHIFT | 9),
PTE10 = (4 << GPIO_PORT_SHIFT | 10),
PTE11 = (4 << GPIO_PORT_SHIFT | 11),
PTE12 = (4 << GPIO_PORT_SHIFT | 12),
PTE13 = (4 << GPIO_PORT_SHIFT | 13),
PTE14 = (4 << GPIO_PORT_SHIFT | 14),
PTE15 = (4 << GPIO_PORT_SHIFT | 15),
PTE16 = (4 << GPIO_PORT_SHIFT | 16),
PTE17 = (4 << GPIO_PORT_SHIFT | 17),
PTE18 = (4 << GPIO_PORT_SHIFT | 18),
PTE19 = (4 << GPIO_PORT_SHIFT | 19),
PTE20 = (4 << GPIO_PORT_SHIFT | 20),
PTE21 = (4 << GPIO_PORT_SHIFT | 21),
PTE22 = (4 << GPIO_PORT_SHIFT | 22),
PTE23 = (4 << GPIO_PORT_SHIFT | 23),
PTE24 = (4 << GPIO_PORT_SHIFT | 24),
PTE25 = (4 << GPIO_PORT_SHIFT | 25),
PTE26 = (4 << GPIO_PORT_SHIFT | 26),
PTE27 = (4 << GPIO_PORT_SHIFT | 27),
PTE28 = (4 << GPIO_PORT_SHIFT | 28),
PTE29 = (4 << GPIO_PORT_SHIFT | 29),
PTE30 = (4 << GPIO_PORT_SHIFT | 30),
PTE31 = (4 << GPIO_PORT_SHIFT | 31),
LED_RED = PTB22,
LED_GREEN = PTE26,
LED_BLUE = PTB21,
// mbed original LED naming
LED1 = LED_RED,
LED2 = LED_GREEN,
LED3 = LED_BLUE,
LED4 = LED_RED,
//Push buttons
SW2 = PTC6,
SW3 = PTA4,
// USB Pins
USBTX = PTB17,
USBRX = PTB16,
// Arduino Headers
D0 = PTC16,
D1 = PTC17,
D2 = PTB9,
D3 = PTA1,
D4 = PTB23,
D5 = PTA2,
D6 = PTC2,
D7 = PTC3,
D8 = PTA0,
D9 = PTC4,
D10 = PTD0,
D11 = PTD2,
D12 = PTD3,
D13 = PTD1,
D14 = PTE24,
D15 = PTE25,
I2C_SCL = D14,
I2C_SDA = D15,
A0 = PTB2,
A1 = PTB3,
A2 = PTB10,
A3 = PTB11,
A4 = PTC10,
A5 = PTC11,
DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 2,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortE = 4
} PortName;
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "analogin_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
#include "PeripheralNames.h"
#include "fsl_adc_hal.h"
#include "fsl_clock_manager.h"
#define MAX_FADC 6000000
static const PinMap PinMap_ADC[] = {
{PTC2, ADC0_SE4b, 0},
{PTC8, ADC1_SE4b, 0},
{PTC9, ADC0_SE5b, 0},
{PTD1, ADC0_SE5b, 0},
{PTC10, ADC0_SE6b, 0},
{PTD5, ADC0_SE6b, 0},
{PTC11, ADC0_SE7b, 0},
{PTD7, ADC0_SE7b, 0},
{PTB0 , ADC0_SE8 , 0},
{PTB1 , ADC0_SE9 , 0},
{PTB2 , ADC0_SE12, 0},
{PTB3 , ADC0_SE13, 0},
{PTC0 , ADC0_SE14, 0},
{PTB10, ADC1_SE14, 0},
{PTB11, ADC1_SE15, 0},
{PTC1 , ADC0_SE15, 0},
{PTE24, ADC0_SE17, 0},
{PTA17, ADC1_SE17, 0},
{PTE25, ADC0_SE18, 0},
{NC , NC , 0}
};
void analogin_init(analogin_t *obj, PinName pin) {
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
if (obj->adc == (ADCName)NC) {
error("ADC pin mapping failed");
}
uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT;
clock_manager_set_gate(kClockModuleADC, instance, true);
uint32_t bus_clock;
clock_manager_get_frequency(kBusClock, &bus_clock);
uint32_t clkdiv;
for (clkdiv = 0; clkdiv < 4; clkdiv++) {
if ((bus_clock >> clkdiv) <= MAX_FADC)
break;
}
if (clkdiv == 4) {//Set max div
clkdiv = 0x7;
}
adc_hal_set_clock_source_mode(instance, (adc_clock_source_mode_t)(clkdiv >> 2));
adc_hal_set_clock_divider_mode(instance, (adc_clock_divider_mode_t)(clkdiv & 0x3));
adc_hal_set_reference_voltage_mode(instance, kAdcVoltageVref);
adc_hal_set_resolution_mode(instance, kAdcSingleDiff16);
adc_hal_configure_continuous_conversion(instance, false);
adc_group_mux_mode_t mode = (obj->adc & (1 << ADC_B_CHANNEL_SHIFT)) ?
kAdcChannelMuxB : kAdcChannelMuxA;
adc_hal_disable(instance, mode);
adc_hal_set_group_mux(instance, mode);
adc_hal_enable(instance, mode, (adc_channel_mode_t)(obj->adc & 0xF), false);
}
uint16_t analogin_read_u16(analogin_t *obj) {
uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT;
adc_group_mux_mode_t mode = (obj->adc & (1 << ADC_B_CHANNEL_SHIFT)) ?
kAdcChannelMuxB : kAdcChannelMuxA;
adc_hal_enable(instance, mode, (adc_channel_mode_t)(obj->adc & 0xF), false);
while (!adc_hal_is_conversion_completed(instance, mode));
return adc_hal_get_conversion_value(instance, mode);
}
float analogin_read(analogin_t *obj) {
uint16_t value = analogin_read_u16(obj);
return (float)value * (1.0f / (float)0xFFFF);
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "analogout_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
#define RANGE_12BIT 0xFFF
const PinMap PinMap_DAC[] = {
{DAC0_OUT, DAC_0, 0},
{NC , NC , 0}
};
void analogout_init(dac_t *obj, PinName pin) {
obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
if (obj->dac == (DACName)NC) {
error("DAC pin mapping failed");
}
SIM->SCGC2 |= SIM_SCGC2_DAC0_MASK;
DAC0->DAT[obj->dac].DATH = 0;
DAC0->DAT[obj->dac].DATL = 0;
DAC0->C1 = DAC_C1_DACBFMD(2); // One-Time Scan Mode
DAC0->C0 = DAC_C0_DACEN_MASK // Enable
| DAC_C0_DACSWTRG_MASK // Software Trigger
| DAC_C0_DACRFS_MASK; // VDDA selected
analogout_write_u16(obj, 0);
}
void analogout_free(dac_t *obj) {}
static inline void dac_write(dac_t *obj, int value) {
DAC0->DAT[obj->dac].DATL = (uint8_t)( value & 0xFF);
DAC0->DAT[obj->dac].DATH = (uint8_t)((value >> 8) & 0xFF);
}
static inline int dac_read(dac_t *obj) {
return ((DAC0->DAT[obj->dac].DATH << 8) | DAC0->DAT[obj->dac].DATL);
}
void analogout_write(dac_t *obj, float value) {
if (value < 0.0f) {
dac_write(obj, 0);
} else if (value > 1.0f) {
dac_write(obj, RANGE_12BIT);
} else {
dac_write(obj, value * (float)RANGE_12BIT);
}
}
void analogout_write_u16(dac_t *obj, uint16_t value) {
dac_write(obj, value >> 4); // 12-bit
}
float analogout_read(dac_t *obj) {
uint32_t value = dac_read(obj);
return (float)value * (1.0f / (float)RANGE_12BIT);
}
uint16_t analogout_read_u16(dac_t *obj) {
uint32_t value = dac_read(obj); // 12-bit
return (value << 4) | ((value >> 8) & 0x003F);
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_PORTIN 1
#define DEVICE_PORTOUT 1
#define DEVICE_PORTINOUT 1
#define DEVICE_INTERRUPTIN 1
#define DEVICE_ANALOGIN 1
#define DEVICE_ANALOGOUT 1
#define DEVICE_SERIAL 1
#define DEVICE_I2C 1
#define DEVICE_I2CSLAVE 1
#define DEVICE_SPI 1
#define DEVICE_SPISLAVE 1
#define DEVICE_CAN 0
#define DEVICE_RTC 1
#define DEVICE_ETHERNET 0
#define DEVICE_PWMOUT 1
#define DEVICE_SEMIHOST 0
#define DEVICE_LOCALFILESYSTEM 0
#define DEVICE_ID_LENGTH 24
#define DEVICE_SLEEP 1
#define DEVICE_DEBUG_AWARENESS 0
#define DEVICE_STDIO_MESSAGES 0
#define DEVICE_ERROR_RED 1
#include "objects.h"
#endif

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_DAC_REGISTERS_H__
#define __HW_DAC_REGISTERS_H__
#include "regs.h"
/*
* MK64F12 DAC
*
* 12-Bit Digital-to-Analog Converter
*
* Registers defined in this header file:
* - HW_DAC_DATnL - DAC Data Low Register
* - HW_DAC_DATnH - DAC Data High Register
* - HW_DAC_SR - DAC Status Register
* - HW_DAC_C0 - DAC Control Register
* - HW_DAC_C1 - DAC Control Register 1
* - HW_DAC_C2 - DAC Control Register 2
*
* - hw_dac_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_DAC_BASE
#define HW_DAC_INSTANCE_COUNT (2U) //!< Number of instances of the DAC module.
#define HW_DAC0 (0U) //!< Instance number for DAC0.
#define HW_DAC1 (1U) //!< Instance number for DAC1.
#define REGS_DAC0_BASE (0x400CC000U) //!< Base address for DAC0.
#define REGS_DAC1_BASE (0x400CD000U) //!< Base address for DAC1.
//! @brief Table of base addresses for DAC instances.
static const uint32_t __g_regs_DAC_base_addresses[] = {
REGS_DAC0_BASE,
REGS_DAC1_BASE,
};
//! @brief Get the base address of DAC by instance number.
//! @param x DAC instance number, from 0 through 1.
#define REGS_DAC_BASE(x) (__g_regs_DAC_base_addresses[(x)])
//! @brief Get the instance number given a base address.
//! @param b Base address for an instance of DAC.
#define REGS_DAC_INSTANCE(b) ((b) == REGS_DAC0_BASE ? HW_DAC0 : (b) == REGS_DAC1_BASE ? HW_DAC1 : 0)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_DAC_DATnL - DAC Data Low Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_DAC_DATnL - DAC Data Low Register (RW)
*
* Reset value: 0x00U
*/
typedef union _hw_dac_datnl
{
uint8_t U;
struct _hw_dac_datnl_bitfields
{
uint8_t DATA0 : 8; //!< [7:0]
} B;
} hw_dac_datnl_t;
#endif
/*!
* @name Constants and macros for entire DAC_DATnL register
*/
//@{
#define HW_DAC_DATnL_COUNT (16U)
#define HW_DAC_DATnL_ADDR(x, n) (REGS_DAC_BASE(x) + 0x0U + (0x2U * n))
#ifndef __LANGUAGE_ASM__
#define HW_DAC_DATnL(x, n) (*(__IO hw_dac_datnl_t *) HW_DAC_DATnL_ADDR(x, n))
#define HW_DAC_DATnL_RD(x, n) (HW_DAC_DATnL(x, n).U)
#define HW_DAC_DATnL_WR(x, n, v) (HW_DAC_DATnL(x, n).U = (v))
#define HW_DAC_DATnL_SET(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) | (v)))
#define HW_DAC_DATnL_CLR(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) & ~(v)))
#define HW_DAC_DATnL_TOG(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual DAC_DATnL bitfields
*/
/*!
* @name Register DAC_DATnL, field DATA0[7:0] (RW)
*
* When the DAC buffer is not enabled, DATA[11:0] controls the output voltage
* based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the
* DAC buffer is enabled, DATA is mapped to the 16-word buffer.
*/
//@{
#define BP_DAC_DATnL_DATA0 (0U) //!< Bit position for DAC_DATnL_DATA0.
#define BM_DAC_DATnL_DATA0 (0xFFU) //!< Bit mask for DAC_DATnL_DATA0.
#define BS_DAC_DATnL_DATA0 (8U) //!< Bit field size in bits for DAC_DATnL_DATA0.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DAC_DATnL_DATA0 field.
#define BR_DAC_DATnL_DATA0(x, n) (HW_DAC_DATnL(x, n).U)
#endif
//! @brief Format value for bitfield DAC_DATnL_DATA0.
#define BF_DAC_DATnL_DATA0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_DATnL_DATA0), uint8_t) & BM_DAC_DATnL_DATA0)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DATA0 field to a new value.
#define BW_DAC_DATnL_DATA0(x, n, v) (HW_DAC_DATnL_WR(x, n, v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_DAC_DATnH - DAC Data High Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_DAC_DATnH - DAC Data High Register (RW)
*
* Reset value: 0x00U
*/
typedef union _hw_dac_datnh
{
uint8_t U;
struct _hw_dac_datnh_bitfields
{
uint8_t DATA1 : 4; //!< [3:0]
uint8_t RESERVED0 : 4; //!< [7:4]
} B;
} hw_dac_datnh_t;
#endif
/*!
* @name Constants and macros for entire DAC_DATnH register
*/
//@{
#define HW_DAC_DATnH_COUNT (16U)
#define HW_DAC_DATnH_ADDR(x, n) (REGS_DAC_BASE(x) + 0x1U + (0x2U * n))
#ifndef __LANGUAGE_ASM__
#define HW_DAC_DATnH(x, n) (*(__IO hw_dac_datnh_t *) HW_DAC_DATnH_ADDR(x, n))
#define HW_DAC_DATnH_RD(x, n) (HW_DAC_DATnH(x, n).U)
#define HW_DAC_DATnH_WR(x, n, v) (HW_DAC_DATnH(x, n).U = (v))
#define HW_DAC_DATnH_SET(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) | (v)))
#define HW_DAC_DATnH_CLR(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) & ~(v)))
#define HW_DAC_DATnH_TOG(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual DAC_DATnH bitfields
*/
/*!
* @name Register DAC_DATnH, field DATA1[3:0] (RW)
*
* When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
* based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
* DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
*/
//@{
#define BP_DAC_DATnH_DATA1 (0U) //!< Bit position for DAC_DATnH_DATA1.
#define BM_DAC_DATnH_DATA1 (0x0FU) //!< Bit mask for DAC_DATnH_DATA1.
#define BS_DAC_DATnH_DATA1 (4U) //!< Bit field size in bits for DAC_DATnH_DATA1.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DAC_DATnH_DATA1 field.
#define BR_DAC_DATnH_DATA1(x, n) (HW_DAC_DATnH(x, n).B.DATA1)
#endif
//! @brief Format value for bitfield DAC_DATnH_DATA1.
#define BF_DAC_DATnH_DATA1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_DATnH_DATA1), uint8_t) & BM_DAC_DATnH_DATA1)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DATA1 field to a new value.
#define BW_DAC_DATnH_DATA1(x, n, v) (HW_DAC_DATnH_WR(x, n, (HW_DAC_DATnH_RD(x, n) & ~BM_DAC_DATnH_DATA1) | BF_DAC_DATnH_DATA1(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_DAC_SR - DAC Status Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_DAC_SR - DAC Status Register (RW)
*
* Reset value: 0x02U
*
* If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
* request is done. Writing 0 to a field clears it whereas writing 1 has no
* effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
* The flags are set only when the data buffer status is changed. Do not use
* 32/16-bit accesses to this register.
*/
typedef union _hw_dac_sr
{
uint8_t U;
struct _hw_dac_sr_bitfields
{
uint8_t DACBFRPBF : 1; //!< [0] DAC Buffer Read Pointer Bottom
//! Position Flag
uint8_t DACBFRPTF : 1; //!< [1] DAC Buffer Read Pointer Top Position
//! Flag
uint8_t DACBFWMF : 1; //!< [2] DAC Buffer Watermark Flag
uint8_t RESERVED0 : 5; //!< [7:3]
} B;
} hw_dac_sr_t;
#endif
/*!
* @name Constants and macros for entire DAC_SR register
*/
//@{
#define HW_DAC_SR_ADDR(x) (REGS_DAC_BASE(x) + 0x20U)
#ifndef __LANGUAGE_ASM__
#define HW_DAC_SR(x) (*(__IO hw_dac_sr_t *) HW_DAC_SR_ADDR(x))
#define HW_DAC_SR_RD(x) (HW_DAC_SR(x).U)
#define HW_DAC_SR_WR(x, v) (HW_DAC_SR(x).U = (v))
#define HW_DAC_SR_SET(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) | (v)))
#define HW_DAC_SR_CLR(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) & ~(v)))
#define HW_DAC_SR_TOG(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual DAC_SR bitfields
*/
/*!
* @name Register DAC_SR, field DACBFRPBF[0] (RW)
*
* Values:
* - 0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
* - 1 - The DAC buffer read pointer is equal to C2[DACBFUP].
*/
//@{
#define BP_DAC_SR_DACBFRPBF (0U) //!< Bit position for DAC_SR_DACBFRPBF.
#define BM_DAC_SR_DACBFRPBF (0x01U) //!< Bit mask for DAC_SR_DACBFRPBF.
#define BS_DAC_SR_DACBFRPBF (1U) //!< Bit field size in bits for DAC_SR_DACBFRPBF.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DAC_SR_DACBFRPBF field.
#define BR_DAC_SR_DACBFRPBF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF))
#endif
//! @brief Format value for bitfield DAC_SR_DACBFRPBF.
#define BF_DAC_SR_DACBFRPBF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_SR_DACBFRPBF), uint8_t) & BM_DAC_SR_DACBFRPBF)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DACBFRPBF field to a new value.
#define BW_DAC_SR_DACBFRPBF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF) = (v))
#endif
//@}
/*!
* @name Register DAC_SR, field DACBFRPTF[1] (RW)
*
* Values:
* - 0 - The DAC buffer read pointer is not zero.
* - 1 - The DAC buffer read pointer is zero.
*/
//@{
#define BP_DAC_SR_DACBFRPTF (1U) //!< Bit position for DAC_SR_DACBFRPTF.
#define BM_DAC_SR_DACBFRPTF (0x02U) //!< Bit mask for DAC_SR_DACBFRPTF.
#define BS_DAC_SR_DACBFRPTF (1U) //!< Bit field size in bits for DAC_SR_DACBFRPTF.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DAC_SR_DACBFRPTF field.
#define BR_DAC_SR_DACBFRPTF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF))
#endif
//! @brief Format value for bitfield DAC_SR_DACBFRPTF.
#define BF_DAC_SR_DACBFRPTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_SR_DACBFRPTF), uint8_t) & BM_DAC_SR_DACBFRPTF)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DACBFRPTF field to a new value.
#define BW_DAC_SR_DACBFRPTF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF) = (v))
#endif
//@}
/*!
* @name Register DAC_SR, field DACBFWMF[2] (RW)
*
* Values:
* - 0 - The DAC buffer read pointer has not reached the watermark level.
* - 1 - The DAC buffer read pointer has reached the watermark level.
*/
//@{
#define BP_DAC_SR_DACBFWMF (2U) //!< Bit position for DAC_SR_DACBFWMF.
#define BM_DAC_SR_DACBFWMF (0x04U) //!< Bit mask for DAC_SR_DACBFWMF.
#define BS_DAC_SR_DACBFWMF (1U) //!< Bit field size in bits for DAC_SR_DACBFWMF.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DAC_SR_DACBFWMF field.
#define BR_DAC_SR_DACBFWMF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF))
#endif
//! @brief Format value for bitfield DAC_SR_DACBFWMF.
#define BF_DAC_SR_DACBFWMF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_SR_DACBFWMF), uint8_t) & BM_DAC_SR_DACBFWMF)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DACBFWMF field to a new value.
#define BW_DAC_SR_DACBFWMF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_DAC_C0 - DAC Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_DAC_C0 - DAC Control Register (RW)
*
* Reset value: 0x00U
*
* Do not use 32- or 16-bit accesses to this register.
*/
typedef union _hw_dac_c0
{
uint8_t U;
struct _hw_dac_c0_bitfields
{
uint8_t DACBBIEN : 1; //!< [0] DAC Buffer Read Pointer Bottom Flag
//! Interrupt Enable
uint8_t DACBTIEN : 1; //!< [1] DAC Buffer Read Pointer Top Flag
//! Interrupt Enable
uint8_t DACBWIEN : 1; //!< [2] DAC Buffer Watermark Interrupt Enable
uint8_t LPEN : 1; //!< [3] DAC Low Power Control
uint8_t DACSWTRG : 1; //!< [4] DAC Software Trigger
uint8_t DACTRGSEL : 1; //!< [5] DAC Trigger Select
uint8_t DACRFS : 1; //!< [6] DAC Reference Select
uint8_t DACEN : 1; //!< [7] DAC Enable
} B;
} hw_dac_c0_t;
#endif
/*!
* @name Constants and macros for entire DAC_C0 register
*/
//@{
#define HW_DAC_C0_ADDR(x) (REGS_DAC_BASE(x) + 0x21U)
#ifndef __LANGUAGE_ASM__
#define HW_DAC_C0(x) (*(__IO hw_dac_c0_t *) HW_DAC_C0_ADDR(x))
#define HW_DAC_C0_RD(x) (HW_DAC_C0(x).U)
#define HW_DAC_C0_WR(x, v) (HW_DAC_C0(x).U = (v))
#define HW_DAC_C0_SET(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) | (v)))
#define HW_DAC_C0_CLR(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) & ~(v)))
#define HW_DAC_C0_TOG(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual DAC_C0 bitfields
*/
/*!
* @name Register DAC_C0, field DACBBIEN[0] (RW)
*
* Values:
* - 0 - The DAC buffer read pointer bottom flag interrupt is disabled.
* - 1 - The DAC buffer read pointer bottom flag interrupt is enabled.
*/
//@{
#define BP_DAC_C0_DACBBIEN (0U) //!< Bit position for DAC_C0_DACBBIEN.
#define BM_DAC_C0_DACBBIEN (0x01U) //!< Bit mask for DAC_C0_DACBBIEN.
#define BS_DAC_C0_DACBBIEN (1U) //!< Bit field size in bits for DAC_C0_DACBBIEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DAC_C0_DACBBIEN field.
#define BR_DAC_C0_DACBBIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN))
#endif
//! @brief Format value for bitfield DAC_C0_DACBBIEN.
#define BF_DAC_C0_DACBBIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACBBIEN), uint8_t) & BM_DAC_C0_DACBBIEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DACBBIEN field to a new value.
#define BW_DAC_C0_DACBBIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN) = (v))
#endif
//@}
/*!
* @name Register DAC_C0, field DACBTIEN[1] (RW)
*
* Values:
* - 0 - The DAC buffer read pointer top flag interrupt is disabled.
* - 1 - The DAC buffer read pointer top flag interrupt is enabled.
*/
//@{
#define BP_DAC_C0_DACBTIEN (1U) //!< Bit position for DAC_C0_DACBTIEN.
#define BM_DAC_C0_DACBTIEN (0x02U) //!< Bit mask for DAC_C0_DACBTIEN.
#define BS_DAC_C0_DACBTIEN (1U) //!< Bit field size in bits for DAC_C0_DACBTIEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DAC_C0_DACBTIEN field.
#define BR_DAC_C0_DACBTIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN))
#endif
//! @brief Format value for bitfield DAC_C0_DACBTIEN.
#define BF_DAC_C0_DACBTIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACBTIEN), uint8_t) & BM_DAC_C0_DACBTIEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DACBTIEN field to a new value.
#define BW_DAC_C0_DACBTIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN) = (v))
#endif
//@}
/*!
* @name Register DAC_C0, field DACBWIEN[2] (RW)
*
* Values:
* - 0 - The DAC buffer watermark interrupt is disabled.
* - 1 - The DAC buffer watermark interrupt is enabled.
*/
//@{
#define BP_DAC_C0_DACBWIEN (2U) //!< Bit position for DAC_C0_DACBWIEN.
#define BM_DAC_C0_DACBWIEN (0x04U) //!< Bit mask for DAC_C0_DACBWIEN.
#define BS_DAC_C0_DACBWIEN (1U) //!< Bit field size in bits for DAC_C0_DACBWIEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DAC_C0_DACBWIEN field.
#define BR_DAC_C0_DACBWIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN))
#endif
//! @brief Format value for bitfield DAC_C0_DACBWIEN.
#define BF_DAC_C0_DACBWIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACBWIEN), uint8_t) & BM_DAC_C0_DACBWIEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DACBWIEN field to a new value.
#define BW_DAC_C0_DACBWIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN) = (v))
#endif
//@}
/*!
* @name Register DAC_C0, field LPEN[3] (RW)
*
* See the 12-bit DAC electrical characteristics of the device data sheet for
* details on the impact of the modes below.
*
* Values:
* - 0 - High-Power mode
* - 1 - Low-Power mode
*/
//@{
#define BP_DAC_C0_LPEN (3U) //!< Bit position for DAC_C0_LPEN.
#define BM_DAC_C0_LPEN (0x08U) //!< Bit mask for DAC_C0_LPEN.
#define BS_DAC_C0_LPEN (1U) //!< Bit field size in bits for DAC_C0_LPEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DAC_C0_LPEN field.
#define BR_DAC_C0_LPEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN))
#endif
//! @brief Format value for bitfield DAC_C0_LPEN.
#define BF_DAC_C0_LPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_LPEN), uint8_t) & BM_DAC_C0_LPEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the LPEN field to a new value.
#define BW_DAC_C0_LPEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN) = (v))
#endif
//@}
/*!
* @name Register DAC_C0, field DACSWTRG[4] (WORZ)
*
* Active high. This is a write-only field, which always reads 0. If DAC
* software trigger is selected and buffer is enabled, writing 1 to this field will
* advance the buffer read pointer once.
*
* Values:
* - 0 - The DAC soft trigger is not valid.
* - 1 - The DAC soft trigger is valid.
*/
//@{
#define BP_DAC_C0_DACSWTRG (4U) //!< Bit position for DAC_C0_DACSWTRG.
#define BM_DAC_C0_DACSWTRG (0x10U) //!< Bit mask for DAC_C0_DACSWTRG.
#define BS_DAC_C0_DACSWTRG (1U) //!< Bit field size in bits for DAC_C0_DACSWTRG.
//! @brief Format value for bitfield DAC_C0_DACSWTRG.
#define BF_DAC_C0_DACSWTRG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACSWTRG), uint8_t) & BM_DAC_C0_DACSWTRG)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DACSWTRG field to a new value.
#define BW_DAC_C0_DACSWTRG(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACSWTRG) = (v))
#endif
//@}
/*!
* @name Register DAC_C0, field DACTRGSEL[5] (RW)
*
* Values:
* - 0 - The DAC hardware trigger is selected.
* - 1 - The DAC software trigger is selected.
*/
//@{
#define BP_DAC_C0_DACTRGSEL (5U) //!< Bit position for DAC_C0_DACTRGSEL.
#define BM_DAC_C0_DACTRGSEL (0x20U) //!< Bit mask for DAC_C0_DACTRGSEL.
#define BS_DAC_C0_DACTRGSEL (1U) //!< Bit field size in bits for DAC_C0_DACTRGSEL.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DAC_C0_DACTRGSEL field.
#define BR_DAC_C0_DACTRGSEL(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL))
#endif
//! @brief Format value for bitfield DAC_C0_DACTRGSEL.
#define BF_DAC_C0_DACTRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACTRGSEL), uint8_t) & BM_DAC_C0_DACTRGSEL)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DACTRGSEL field to a new value.
#define BW_DAC_C0_DACTRGSEL(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL) = (v))
#endif
//@}
/*!
* @name Register DAC_C0, field DACRFS[6] (RW)
*
* Values:
* - 0 - The DAC selects DACREF_1 as the reference voltage.
* - 1 - The DAC selects DACREF_2 as the reference voltage.
*/
//@{
#define BP_DAC_C0_DACRFS (6U) //!< Bit position for DAC_C0_DACRFS.
#define BM_DAC_C0_DACRFS (0x40U) //!< Bit mask for DAC_C0_DACRFS.
#define BS_DAC_C0_DACRFS (1U) //!< Bit field size in bits for DAC_C0_DACRFS.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DAC_C0_DACRFS field.
#define BR_DAC_C0_DACRFS(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS))
#endif
//! @brief Format value for bitfield DAC_C0_DACRFS.
#define BF_DAC_C0_DACRFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACRFS), uint8_t) & BM_DAC_C0_DACRFS)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DACRFS field to a new value.
#define BW_DAC_C0_DACRFS(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS) = (v))
#endif
//@}
/*!
* @name Register DAC_C0, field DACEN[7] (RW)
*
* Starts the Programmable Reference Generator operation.
*
* Values:
* - 0 - The DAC system is disabled.
* - 1 - The DAC system is enabled.
*/
//@{
#define BP_DAC_C0_DACEN (7U) //!< Bit position for DAC_C0_DACEN.
#define BM_DAC_C0_DACEN (0x80U) //!< Bit mask for DAC_C0_DACEN.
#define BS_DAC_C0_DACEN (1U) //!< Bit field size in bits for DAC_C0_DACEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DAC_C0_DACEN field.
#define BR_DAC_C0_DACEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN))
#endif
//! @brief Format value for bitfield DAC_C0_DACEN.
#define BF_DAC_C0_DACEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACEN), uint8_t) & BM_DAC_C0_DACEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DACEN field to a new value.
#define BW_DAC_C0_DACEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_DAC_C1 - DAC Control Register 1
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_DAC_C1 - DAC Control Register 1 (RW)
*
* Reset value: 0x00U
*
* Do not use 32- or 16-bit accesses to this register.
*/
typedef union _hw_dac_c1
{
uint8_t U;
struct _hw_dac_c1_bitfields
{
uint8_t DACBFEN : 1; //!< [0] DAC Buffer Enable
uint8_t DACBFMD : 2; //!< [2:1] DAC Buffer Work Mode Select
uint8_t DACBFWM : 2; //!< [4:3] DAC Buffer Watermark Select
uint8_t RESERVED0 : 2; //!< [6:5]
uint8_t DMAEN : 1; //!< [7] DMA Enable Select
} B;
} hw_dac_c1_t;
#endif
/*!
* @name Constants and macros for entire DAC_C1 register
*/
//@{
#define HW_DAC_C1_ADDR(x) (REGS_DAC_BASE(x) + 0x22U)
#ifndef __LANGUAGE_ASM__
#define HW_DAC_C1(x) (*(__IO hw_dac_c1_t *) HW_DAC_C1_ADDR(x))
#define HW_DAC_C1_RD(x) (HW_DAC_C1(x).U)
#define HW_DAC_C1_WR(x, v) (HW_DAC_C1(x).U = (v))
#define HW_DAC_C1_SET(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) | (v)))
#define HW_DAC_C1_CLR(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) & ~(v)))
#define HW_DAC_C1_TOG(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual DAC_C1 bitfields
*/
/*!
* @name Register DAC_C1, field DACBFEN[0] (RW)
*
* Values:
* - 0 - Buffer read pointer is disabled. The converted data is always the first
* word of the buffer.
* - 1 - Buffer read pointer is enabled. The converted data is the word that the
* read pointer points to. It means converted data can be from any word of
* the buffer.
*/
//@{
#define BP_DAC_C1_DACBFEN (0U) //!< Bit position for DAC_C1_DACBFEN.
#define BM_DAC_C1_DACBFEN (0x01U) //!< Bit mask for DAC_C1_DACBFEN.
#define BS_DAC_C1_DACBFEN (1U) //!< Bit field size in bits for DAC_C1_DACBFEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DAC_C1_DACBFEN field.
#define BR_DAC_C1_DACBFEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN))
#endif
//! @brief Format value for bitfield DAC_C1_DACBFEN.
#define BF_DAC_C1_DACBFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DACBFEN), uint8_t) & BM_DAC_C1_DACBFEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DACBFEN field to a new value.
#define BW_DAC_C1_DACBFEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN) = (v))
#endif
//@}
/*!
* @name Register DAC_C1, field DACBFMD[2:1] (RW)
*
* Values:
* - 00 - Normal mode
* - 01 - Swing mode
* - 10 - One-Time Scan mode
* - 11 - Reserved
*/
//@{
#define BP_DAC_C1_DACBFMD (1U) //!< Bit position for DAC_C1_DACBFMD.
#define BM_DAC_C1_DACBFMD (0x06U) //!< Bit mask for DAC_C1_DACBFMD.
#define BS_DAC_C1_DACBFMD (2U) //!< Bit field size in bits for DAC_C1_DACBFMD.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DAC_C1_DACBFMD field.
#define BR_DAC_C1_DACBFMD(x) (HW_DAC_C1(x).B.DACBFMD)
#endif
//! @brief Format value for bitfield DAC_C1_DACBFMD.
#define BF_DAC_C1_DACBFMD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DACBFMD), uint8_t) & BM_DAC_C1_DACBFMD)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DACBFMD field to a new value.
#define BW_DAC_C1_DACBFMD(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFMD) | BF_DAC_C1_DACBFMD(v)))
#endif
//@}
/*!
* @name Register DAC_C1, field DACBFWM[4:3] (RW)
*
* Controls when SR[DACBFWMF] is set. When the DAC buffer read pointer reaches
* the word defined by this field, which is 1-4 words away from the upper limit
* (DACBUP), SR[DACBFWMF] will be set. This allows user configuration of the
* watermark interrupt.
*
* Values:
* - 00 - 1 word
* - 01 - 2 words
* - 10 - 3 words
* - 11 - 4 words
*/
//@{
#define BP_DAC_C1_DACBFWM (3U) //!< Bit position for DAC_C1_DACBFWM.
#define BM_DAC_C1_DACBFWM (0x18U) //!< Bit mask for DAC_C1_DACBFWM.
#define BS_DAC_C1_DACBFWM (2U) //!< Bit field size in bits for DAC_C1_DACBFWM.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DAC_C1_DACBFWM field.
#define BR_DAC_C1_DACBFWM(x) (HW_DAC_C1(x).B.DACBFWM)
#endif
//! @brief Format value for bitfield DAC_C1_DACBFWM.
#define BF_DAC_C1_DACBFWM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DACBFWM), uint8_t) & BM_DAC_C1_DACBFWM)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DACBFWM field to a new value.
#define BW_DAC_C1_DACBFWM(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFWM) | BF_DAC_C1_DACBFWM(v)))
#endif
//@}
/*!
* @name Register DAC_C1, field DMAEN[7] (RW)
*
* Values:
* - 0 - DMA is disabled.
* - 1 - DMA is enabled. When DMA is enabled, the DMA request will be generated
* by original interrupts. The interrupts will not be presented on this
* module at the same time.
*/
//@{
#define BP_DAC_C1_DMAEN (7U) //!< Bit position for DAC_C1_DMAEN.
#define BM_DAC_C1_DMAEN (0x80U) //!< Bit mask for DAC_C1_DMAEN.
#define BS_DAC_C1_DMAEN (1U) //!< Bit field size in bits for DAC_C1_DMAEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DAC_C1_DMAEN field.
#define BR_DAC_C1_DMAEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN))
#endif
//! @brief Format value for bitfield DAC_C1_DMAEN.
#define BF_DAC_C1_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DMAEN), uint8_t) & BM_DAC_C1_DMAEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DMAEN field to a new value.
#define BW_DAC_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_DAC_C2 - DAC Control Register 2
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_DAC_C2 - DAC Control Register 2 (RW)
*
* Reset value: 0x0FU
*/
typedef union _hw_dac_c2
{
uint8_t U;
struct _hw_dac_c2_bitfields
{
uint8_t DACBFUP : 4; //!< [3:0] DAC Buffer Upper Limit
uint8_t DACBFRP : 4; //!< [7:4] DAC Buffer Read Pointer
} B;
} hw_dac_c2_t;
#endif
/*!
* @name Constants and macros for entire DAC_C2 register
*/
//@{
#define HW_DAC_C2_ADDR(x) (REGS_DAC_BASE(x) + 0x23U)
#ifndef __LANGUAGE_ASM__
#define HW_DAC_C2(x) (*(__IO hw_dac_c2_t *) HW_DAC_C2_ADDR(x))
#define HW_DAC_C2_RD(x) (HW_DAC_C2(x).U)
#define HW_DAC_C2_WR(x, v) (HW_DAC_C2(x).U = (v))
#define HW_DAC_C2_SET(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) | (v)))
#define HW_DAC_C2_CLR(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) & ~(v)))
#define HW_DAC_C2_TOG(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual DAC_C2 bitfields
*/
/*!
* @name Register DAC_C2, field DACBFUP[3:0] (RW)
*
* Selects the upper limit of the DAC buffer. The buffer read pointer cannot
* exceed it.
*/
//@{
#define BP_DAC_C2_DACBFUP (0U) //!< Bit position for DAC_C2_DACBFUP.
#define BM_DAC_C2_DACBFUP (0x0FU) //!< Bit mask for DAC_C2_DACBFUP.
#define BS_DAC_C2_DACBFUP (4U) //!< Bit field size in bits for DAC_C2_DACBFUP.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DAC_C2_DACBFUP field.
#define BR_DAC_C2_DACBFUP(x) (HW_DAC_C2(x).B.DACBFUP)
#endif
//! @brief Format value for bitfield DAC_C2_DACBFUP.
#define BF_DAC_C2_DACBFUP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C2_DACBFUP), uint8_t) & BM_DAC_C2_DACBFUP)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DACBFUP field to a new value.
#define BW_DAC_C2_DACBFUP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFUP) | BF_DAC_C2_DACBFUP(v)))
#endif
//@}
/*!
* @name Register DAC_C2, field DACBFRP[7:4] (RW)
*
* Keeps the current value of the buffer read pointer.
*/
//@{
#define BP_DAC_C2_DACBFRP (4U) //!< Bit position for DAC_C2_DACBFRP.
#define BM_DAC_C2_DACBFRP (0xF0U) //!< Bit mask for DAC_C2_DACBFRP.
#define BS_DAC_C2_DACBFRP (4U) //!< Bit field size in bits for DAC_C2_DACBFRP.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DAC_C2_DACBFRP field.
#define BR_DAC_C2_DACBFRP(x) (HW_DAC_C2(x).B.DACBFRP)
#endif
//! @brief Format value for bitfield DAC_C2_DACBFRP.
#define BF_DAC_C2_DACBFRP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C2_DACBFRP), uint8_t) & BM_DAC_C2_DACBFRP)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DACBFRP field to a new value.
#define BW_DAC_C2_DACBFRP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFRP) | BF_DAC_C2_DACBFRP(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_dac_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All DAC module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_dac
{
struct {
__IO hw_dac_datnl_t DATnL; //!< [0x0] DAC Data Low Register
__IO hw_dac_datnh_t DATnH; //!< [0x1] DAC Data High Register
} DAT[16];
__IO hw_dac_sr_t SR; //!< [0x20] DAC Status Register
__IO hw_dac_c0_t C0; //!< [0x21] DAC Control Register
__IO hw_dac_c1_t C1; //!< [0x22] DAC Control Register 1
__IO hw_dac_c2_t C2; //!< [0x23] DAC Control Register 2
} hw_dac_t;
#pragma pack()
//! @brief Macro to access all DAC registers.
//! @param x DAC instance number.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_DAC(0)</code>.
#define HW_DAC(x) (*(hw_dac_t *) REGS_DAC_BASE(x))
#endif
#endif // __HW_DAC_REGISTERS_H__
// v22/130726/0.9
// EOF

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_DMAMUX_REGISTERS_H__
#define __HW_DMAMUX_REGISTERS_H__
#include "regs.h"
/*
* MK64F12 DMAMUX
*
* DMA channel multiplexor
*
* Registers defined in this header file:
* - HW_DMAMUX_CHCFGn - Channel Configuration register
*
* - hw_dmamux_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_DMAMUX_BASE
#define HW_DMAMUX_INSTANCE_COUNT (1U) //!< Number of instances of the DMAMUX module.
#define HW_DMAMUX0 (0U) //!< Instance number for DMAMUX.
#define REGS_DMAMUX0_BASE (0x40021000U) //!< Base address for DMAMUX.
//! @brief Table of base addresses for DMAMUX instances.
static const uint32_t __g_regs_DMAMUX_base_addresses[] = {
REGS_DMAMUX0_BASE,
};
//! @brief Get the base address of DMAMUX by instance number.
//! @param x DMAMUX instance number, from 0 through 0.
#define REGS_DMAMUX_BASE(x) (__g_regs_DMAMUX_base_addresses[(x)])
//! @brief Get the instance number given a base address.
//! @param b Base address for an instance of DMAMUX.
#define REGS_DMAMUX_INSTANCE(b) ((b) == REGS_DMAMUX0_BASE ? HW_DMAMUX0 : 0)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_DMAMUX_CHCFGn - Channel Configuration register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_DMAMUX_CHCFGn - Channel Configuration register (RW)
*
* Reset value: 0x00U
*
* Each of the DMA channels can be independently enabled/disabled and associated
* with one of the DMA slots (peripheral slots or always-on slots) in the
* system. Setting multiple CHCFG registers with the same source value will result in
* unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
* Before changing the trigger or source settings, a DMA channel must be disabled
* via CHCFGn[ENBL].
*/
typedef union _hw_dmamux_chcfgn
{
uint8_t U;
struct _hw_dmamux_chcfgn_bitfields
{
uint8_t SOURCE : 6; //!< [5:0] DMA Channel Source (Slot)
uint8_t TRIG : 1; //!< [6] DMA Channel Trigger Enable
uint8_t ENBL : 1; //!< [7] DMA Channel Enable
} B;
} hw_dmamux_chcfgn_t;
#endif
/*!
* @name Constants and macros for entire DMAMUX_CHCFGn register
*/
//@{
#define HW_DMAMUX_CHCFGn_COUNT (16U)
#define HW_DMAMUX_CHCFGn_ADDR(x, n) (REGS_DMAMUX_BASE(x) + 0x0U + (0x1U * n))
#ifndef __LANGUAGE_ASM__
#define HW_DMAMUX_CHCFGn(x, n) (*(__IO hw_dmamux_chcfgn_t *) HW_DMAMUX_CHCFGn_ADDR(x, n))
#define HW_DMAMUX_CHCFGn_RD(x, n) (HW_DMAMUX_CHCFGn(x, n).U)
#define HW_DMAMUX_CHCFGn_WR(x, n, v) (HW_DMAMUX_CHCFGn(x, n).U = (v))
#define HW_DMAMUX_CHCFGn_SET(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) | (v)))
#define HW_DMAMUX_CHCFGn_CLR(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) & ~(v)))
#define HW_DMAMUX_CHCFGn_TOG(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual DMAMUX_CHCFGn bitfields
*/
/*!
* @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW)
*
* Specifies which DMA source, if any, is routed to a particular DMA channel.
* See your device's chip configuration details for information about the
* peripherals and their slot numbers.
*/
//@{
#define BP_DMAMUX_CHCFGn_SOURCE (0U) //!< Bit position for DMAMUX_CHCFGn_SOURCE.
#define BM_DMAMUX_CHCFGn_SOURCE (0x3FU) //!< Bit mask for DMAMUX_CHCFGn_SOURCE.
#define BS_DMAMUX_CHCFGn_SOURCE (6U) //!< Bit field size in bits for DMAMUX_CHCFGn_SOURCE.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DMAMUX_CHCFGn_SOURCE field.
#define BR_DMAMUX_CHCFGn_SOURCE(x, n) (HW_DMAMUX_CHCFGn(x, n).B.SOURCE)
#endif
//! @brief Format value for bitfield DMAMUX_CHCFGn_SOURCE.
#define BF_DMAMUX_CHCFGn_SOURCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_SOURCE), uint8_t) & BM_DMAMUX_CHCFGn_SOURCE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SOURCE field to a new value.
#define BW_DMAMUX_CHCFGn_SOURCE(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, (HW_DMAMUX_CHCFGn_RD(x, n) & ~BM_DMAMUX_CHCFGn_SOURCE) | BF_DMAMUX_CHCFGn_SOURCE(v)))
#endif
//@}
/*!
* @name Register DMAMUX_CHCFGn, field TRIG[6] (RW)
*
* Enables the periodic trigger capability for the triggered DMA channel.
*
* Values:
* - 0 - Triggering is disabled. If triggering is disabled and ENBL is set, the
* DMA Channel will simply route the specified source to the DMA channel.
* (Normal mode)
* - 1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
* DMAMUX is in Periodic Trigger mode.
*/
//@{
#define BP_DMAMUX_CHCFGn_TRIG (6U) //!< Bit position for DMAMUX_CHCFGn_TRIG.
#define BM_DMAMUX_CHCFGn_TRIG (0x40U) //!< Bit mask for DMAMUX_CHCFGn_TRIG.
#define BS_DMAMUX_CHCFGn_TRIG (1U) //!< Bit field size in bits for DMAMUX_CHCFGn_TRIG.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DMAMUX_CHCFGn_TRIG field.
#define BR_DMAMUX_CHCFGn_TRIG(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG))
#endif
//! @brief Format value for bitfield DMAMUX_CHCFGn_TRIG.
#define BF_DMAMUX_CHCFGn_TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_TRIG), uint8_t) & BM_DMAMUX_CHCFGn_TRIG)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TRIG field to a new value.
#define BW_DMAMUX_CHCFGn_TRIG(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG) = (v))
#endif
//@}
/*!
* @name Register DMAMUX_CHCFGn, field ENBL[7] (RW)
*
* Enables the DMA channel.
*
* Values:
* - 0 - DMA channel is disabled. This mode is primarily used during
* configuration of the DMAMux. The DMA has separate channel enables/disables, which
* should be used to disable or reconfigure a DMA channel.
* - 1 - DMA channel is enabled
*/
//@{
#define BP_DMAMUX_CHCFGn_ENBL (7U) //!< Bit position for DMAMUX_CHCFGn_ENBL.
#define BM_DMAMUX_CHCFGn_ENBL (0x80U) //!< Bit mask for DMAMUX_CHCFGn_ENBL.
#define BS_DMAMUX_CHCFGn_ENBL (1U) //!< Bit field size in bits for DMAMUX_CHCFGn_ENBL.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DMAMUX_CHCFGn_ENBL field.
#define BR_DMAMUX_CHCFGn_ENBL(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL))
#endif
//! @brief Format value for bitfield DMAMUX_CHCFGn_ENBL.
#define BF_DMAMUX_CHCFGn_ENBL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_ENBL), uint8_t) & BM_DMAMUX_CHCFGn_ENBL)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ENBL field to a new value.
#define BW_DMAMUX_CHCFGn_ENBL(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_dmamux_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All DMAMUX module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_dmamux
{
__IO hw_dmamux_chcfgn_t CHCFGn[16]; //!< [0x0] Channel Configuration register
} hw_dmamux_t;
#pragma pack()
//! @brief Macro to access all DMAMUX registers.
//! @param x DMAMUX instance number.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_DMAMUX(0)</code>.
#define HW_DMAMUX(x) (*(hw_dmamux_t *) REGS_DMAMUX_BASE(x))
#endif
#endif // __HW_DMAMUX_REGISTERS_H__
// v22/130726/0.9
// EOF

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_EWM_REGISTERS_H__
#define __HW_EWM_REGISTERS_H__
#include "regs.h"
/*
* MK64F12 EWM
*
* External Watchdog Monitor
*
* Registers defined in this header file:
* - HW_EWM_CTRL - Control Register
* - HW_EWM_SERV - Service Register
* - HW_EWM_CMPL - Compare Low Register
* - HW_EWM_CMPH - Compare High Register
*
* - hw_ewm_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_EWM_BASE
#define HW_EWM_INSTANCE_COUNT (1U) //!< Number of instances of the EWM module.
#define REGS_EWM_BASE (0x40061000U) //!< Base address for EWM.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_EWM_CTRL - Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_EWM_CTRL - Control Register (RW)
*
* Reset value: 0x00U
*
* The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be
* written once after a CPU reset. Modifying these bits more than once, generates
* a bus transfer error.
*/
typedef union _hw_ewm_ctrl
{
uint8_t U;
struct _hw_ewm_ctrl_bitfields
{
uint8_t EWMEN : 1; //!< [0] EWM enable.
uint8_t ASSIN : 1; //!< [1] EWM_in's Assertion State Select.
uint8_t INEN : 1; //!< [2] Input Enable.
uint8_t INTEN : 1; //!< [3] Interrupt Enable.
uint8_t RESERVED0 : 4; //!< [7:4]
} B;
} hw_ewm_ctrl_t;
#endif
/*!
* @name Constants and macros for entire EWM_CTRL register
*/
//@{
#define HW_EWM_CTRL_ADDR (REGS_EWM_BASE + 0x0U)
#ifndef __LANGUAGE_ASM__
#define HW_EWM_CTRL (*(__IO hw_ewm_ctrl_t *) HW_EWM_CTRL_ADDR)
#define HW_EWM_CTRL_RD() (HW_EWM_CTRL.U)
#define HW_EWM_CTRL_WR(v) (HW_EWM_CTRL.U = (v))
#define HW_EWM_CTRL_SET(v) (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() | (v)))
#define HW_EWM_CTRL_CLR(v) (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() & ~(v)))
#define HW_EWM_CTRL_TOG(v) (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() ^ (v)))
#endif
//@}
/*
* Constants & macros for individual EWM_CTRL bitfields
*/
/*!
* @name Register EWM_CTRL, field EWMEN[0] (RW)
*
* This bit when set, enables the EWM module. This resets the EWM counter to
* zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and
* therefore it cannot be enabled until a reset occurs, due to the write-once
* nature of this bit.
*/
//@{
#define BP_EWM_CTRL_EWMEN (0U) //!< Bit position for EWM_CTRL_EWMEN.
#define BM_EWM_CTRL_EWMEN (0x01U) //!< Bit mask for EWM_CTRL_EWMEN.
#define BS_EWM_CTRL_EWMEN (1U) //!< Bit field size in bits for EWM_CTRL_EWMEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the EWM_CTRL_EWMEN field.
#define BR_EWM_CTRL_EWMEN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_EWMEN))
#endif
//! @brief Format value for bitfield EWM_CTRL_EWMEN.
#define BF_EWM_CTRL_EWMEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_EWMEN), uint8_t) & BM_EWM_CTRL_EWMEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the EWMEN field to a new value.
#define BW_EWM_CTRL_EWMEN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_EWMEN) = (v))
#endif
//@}
/*!
* @name Register EWM_CTRL, field ASSIN[1] (RW)
*
* Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit
* inverts the assert state to a logic one.
*/
//@{
#define BP_EWM_CTRL_ASSIN (1U) //!< Bit position for EWM_CTRL_ASSIN.
#define BM_EWM_CTRL_ASSIN (0x02U) //!< Bit mask for EWM_CTRL_ASSIN.
#define BS_EWM_CTRL_ASSIN (1U) //!< Bit field size in bits for EWM_CTRL_ASSIN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the EWM_CTRL_ASSIN field.
#define BR_EWM_CTRL_ASSIN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_ASSIN))
#endif
//! @brief Format value for bitfield EWM_CTRL_ASSIN.
#define BF_EWM_CTRL_ASSIN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_ASSIN), uint8_t) & BM_EWM_CTRL_ASSIN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ASSIN field to a new value.
#define BW_EWM_CTRL_ASSIN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_ASSIN) = (v))
#endif
//@}
/*!
* @name Register EWM_CTRL, field INEN[2] (RW)
*
* This bit when set, enables the EWM_in port.
*/
//@{
#define BP_EWM_CTRL_INEN (2U) //!< Bit position for EWM_CTRL_INEN.
#define BM_EWM_CTRL_INEN (0x04U) //!< Bit mask for EWM_CTRL_INEN.
#define BS_EWM_CTRL_INEN (1U) //!< Bit field size in bits for EWM_CTRL_INEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the EWM_CTRL_INEN field.
#define BR_EWM_CTRL_INEN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INEN))
#endif
//! @brief Format value for bitfield EWM_CTRL_INEN.
#define BF_EWM_CTRL_INEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_INEN), uint8_t) & BM_EWM_CTRL_INEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the INEN field to a new value.
#define BW_EWM_CTRL_INEN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INEN) = (v))
#endif
//@}
/*!
* @name Register EWM_CTRL, field INTEN[3] (RW)
*
* This bit when set and EWM_out is asserted, an interrupt request is generated.
* To de-assert interrupt request, user should clear this bit by writing 0.
*/
//@{
#define BP_EWM_CTRL_INTEN (3U) //!< Bit position for EWM_CTRL_INTEN.
#define BM_EWM_CTRL_INTEN (0x08U) //!< Bit mask for EWM_CTRL_INTEN.
#define BS_EWM_CTRL_INTEN (1U) //!< Bit field size in bits for EWM_CTRL_INTEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the EWM_CTRL_INTEN field.
#define BR_EWM_CTRL_INTEN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INTEN))
#endif
//! @brief Format value for bitfield EWM_CTRL_INTEN.
#define BF_EWM_CTRL_INTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_INTEN), uint8_t) & BM_EWM_CTRL_INTEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the INTEN field to a new value.
#define BW_EWM_CTRL_INTEN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INTEN) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_EWM_SERV - Service Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_EWM_SERV - Service Register (WORZ)
*
* Reset value: 0x00U
*
* The SERV register provides the interface from the CPU to the EWM module. It
* is write-only and reads of this register return zero.
*/
typedef union _hw_ewm_serv
{
uint8_t U;
struct _hw_ewm_serv_bitfields
{
uint8_t SERVICE : 8; //!< [7:0]
} B;
} hw_ewm_serv_t;
#endif
/*!
* @name Constants and macros for entire EWM_SERV register
*/
//@{
#define HW_EWM_SERV_ADDR (REGS_EWM_BASE + 0x1U)
#ifndef __LANGUAGE_ASM__
#define HW_EWM_SERV (*(__O hw_ewm_serv_t *) HW_EWM_SERV_ADDR)
#define HW_EWM_SERV_RD() (HW_EWM_SERV.U)
#define HW_EWM_SERV_WR(v) (HW_EWM_SERV.U = (v))
#endif
//@}
/*
* Constants & macros for individual EWM_SERV bitfields
*/
/*!
* @name Register EWM_SERV, field SERVICE[7:0] (WORZ)
*
* The EWM service mechanism requires the CPU to write two values to the SERV
* register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The
* EWM service is illegal if either of the following conditions is true. The
* first or second data byte is not written correctly. The second data byte is not
* written within a fixed number of peripheral bus cycles of the first data byte.
* This fixed number of cycles is called EWM_service_time.
*/
//@{
#define BP_EWM_SERV_SERVICE (0U) //!< Bit position for EWM_SERV_SERVICE.
#define BM_EWM_SERV_SERVICE (0xFFU) //!< Bit mask for EWM_SERV_SERVICE.
#define BS_EWM_SERV_SERVICE (8U) //!< Bit field size in bits for EWM_SERV_SERVICE.
//! @brief Format value for bitfield EWM_SERV_SERVICE.
#define BF_EWM_SERV_SERVICE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_SERV_SERVICE), uint8_t) & BM_EWM_SERV_SERVICE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SERVICE field to a new value.
#define BW_EWM_SERV_SERVICE(v) (HW_EWM_SERV_WR(v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_EWM_CMPL - Compare Low Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_EWM_CMPL - Compare Low Register (RW)
*
* Reset value: 0x00U
*
* The CMPL register is reset to zero after a CPU reset. This provides no
* minimum time for the CPU to service the EWM counter. This register can be written
* only once after a CPU reset. Writing this register more than once generates a
* bus transfer error.
*/
typedef union _hw_ewm_cmpl
{
uint8_t U;
struct _hw_ewm_cmpl_bitfields
{
uint8_t COMPAREL : 8; //!< [7:0]
} B;
} hw_ewm_cmpl_t;
#endif
/*!
* @name Constants and macros for entire EWM_CMPL register
*/
//@{
#define HW_EWM_CMPL_ADDR (REGS_EWM_BASE + 0x2U)
#ifndef __LANGUAGE_ASM__
#define HW_EWM_CMPL (*(__IO hw_ewm_cmpl_t *) HW_EWM_CMPL_ADDR)
#define HW_EWM_CMPL_RD() (HW_EWM_CMPL.U)
#define HW_EWM_CMPL_WR(v) (HW_EWM_CMPL.U = (v))
#define HW_EWM_CMPL_SET(v) (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() | (v)))
#define HW_EWM_CMPL_CLR(v) (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() & ~(v)))
#define HW_EWM_CMPL_TOG(v) (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() ^ (v)))
#endif
//@}
/*
* Constants & macros for individual EWM_CMPL bitfields
*/
/*!
* @name Register EWM_CMPL, field COMPAREL[7:0] (RW)
*
* To prevent runaway code from changing this field, software should write to
* this field after a CPU reset even if the (default) minimum service time is
* required.
*/
//@{
#define BP_EWM_CMPL_COMPAREL (0U) //!< Bit position for EWM_CMPL_COMPAREL.
#define BM_EWM_CMPL_COMPAREL (0xFFU) //!< Bit mask for EWM_CMPL_COMPAREL.
#define BS_EWM_CMPL_COMPAREL (8U) //!< Bit field size in bits for EWM_CMPL_COMPAREL.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the EWM_CMPL_COMPAREL field.
#define BR_EWM_CMPL_COMPAREL (HW_EWM_CMPL.U)
#endif
//! @brief Format value for bitfield EWM_CMPL_COMPAREL.
#define BF_EWM_CMPL_COMPAREL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CMPL_COMPAREL), uint8_t) & BM_EWM_CMPL_COMPAREL)
#ifndef __LANGUAGE_ASM__
//! @brief Set the COMPAREL field to a new value.
#define BW_EWM_CMPL_COMPAREL(v) (HW_EWM_CMPL_WR(v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_EWM_CMPH - Compare High Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_EWM_CMPH - Compare High Register (RW)
*
* Reset value: 0xFFU
*
* The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum
* of 256 clocks time, for the CPU to service the EWM counter. This register can
* be written only once after a CPU reset. Writing this register more than once
* generates a bus transfer error. The valid values for CMPH are up to 0xFE
* because the EWM counter never expires when CMPH = 0xFF. The expiration happens only
* if EWM counter is greater than CMPH.
*/
typedef union _hw_ewm_cmph
{
uint8_t U;
struct _hw_ewm_cmph_bitfields
{
uint8_t COMPAREH : 8; //!< [7:0]
} B;
} hw_ewm_cmph_t;
#endif
/*!
* @name Constants and macros for entire EWM_CMPH register
*/
//@{
#define HW_EWM_CMPH_ADDR (REGS_EWM_BASE + 0x3U)
#ifndef __LANGUAGE_ASM__
#define HW_EWM_CMPH (*(__IO hw_ewm_cmph_t *) HW_EWM_CMPH_ADDR)
#define HW_EWM_CMPH_RD() (HW_EWM_CMPH.U)
#define HW_EWM_CMPH_WR(v) (HW_EWM_CMPH.U = (v))
#define HW_EWM_CMPH_SET(v) (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() | (v)))
#define HW_EWM_CMPH_CLR(v) (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() & ~(v)))
#define HW_EWM_CMPH_TOG(v) (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() ^ (v)))
#endif
//@}
/*
* Constants & macros for individual EWM_CMPH bitfields
*/
/*!
* @name Register EWM_CMPH, field COMPAREH[7:0] (RW)
*
* To prevent runaway code from changing this field, software should write to
* this field after a CPU reset even if the (default) maximum service time is
* required.
*/
//@{
#define BP_EWM_CMPH_COMPAREH (0U) //!< Bit position for EWM_CMPH_COMPAREH.
#define BM_EWM_CMPH_COMPAREH (0xFFU) //!< Bit mask for EWM_CMPH_COMPAREH.
#define BS_EWM_CMPH_COMPAREH (8U) //!< Bit field size in bits for EWM_CMPH_COMPAREH.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the EWM_CMPH_COMPAREH field.
#define BR_EWM_CMPH_COMPAREH (HW_EWM_CMPH.U)
#endif
//! @brief Format value for bitfield EWM_CMPH_COMPAREH.
#define BF_EWM_CMPH_COMPAREH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CMPH_COMPAREH), uint8_t) & BM_EWM_CMPH_COMPAREH)
#ifndef __LANGUAGE_ASM__
//! @brief Set the COMPAREH field to a new value.
#define BW_EWM_CMPH_COMPAREH(v) (HW_EWM_CMPH_WR(v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_ewm_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All EWM module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_ewm
{
__IO hw_ewm_ctrl_t CTRL; //!< [0x0] Control Register
__O hw_ewm_serv_t SERV; //!< [0x1] Service Register
__IO hw_ewm_cmpl_t CMPL; //!< [0x2] Compare Low Register
__IO hw_ewm_cmph_t CMPH; //!< [0x3] Compare High Register
} hw_ewm_t;
#pragma pack()
//! @brief Macro to access all EWM registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_EWM</code>.
#define HW_EWM (*(hw_ewm_t *) REGS_EWM_BASE)
#endif
#endif // __HW_EWM_REGISTERS_H__
// v22/130726/0.9
// EOF

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_FB_REGISTERS_H__
#define __HW_FB_REGISTERS_H__
#include "regs.h"
/*
* MK64F12 FB
*
* FlexBus external bus interface
*
* Registers defined in this header file:
* - HW_FB_CSARn - Chip Select Address Register
* - HW_FB_CSMRn - Chip Select Mask Register
* - HW_FB_CSCRn - Chip Select Control Register
* - HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
*
* - hw_fb_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_FB_BASE
#define HW_FB_INSTANCE_COUNT (1U) //!< Number of instances of the FB module.
#define REGS_FB_BASE (0x4000C000U) //!< Base address for FB.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_FB_CSARn - Chip Select Address Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_FB_CSARn - Chip Select Address Register (RW)
*
* Reset value: 0x00000000U
*
* Specifies the associated chip-select's base address.
*/
typedef union _hw_fb_csarn
{
uint32_t U;
struct _hw_fb_csarn_bitfields
{
uint32_t RESERVED0 : 16; //!< [15:0]
uint32_t BA : 16; //!< [31:16] Base Address
} B;
} hw_fb_csarn_t;
#endif
/*!
* @name Constants and macros for entire FB_CSARn register
*/
//@{
#define HW_FB_CSARn_COUNT (6U)
#define HW_FB_CSARn_ADDR(n) (REGS_FB_BASE + 0x0U + (0xCU * n))
#ifndef __LANGUAGE_ASM__
#define HW_FB_CSARn(n) (*(__IO hw_fb_csarn_t *) HW_FB_CSARn_ADDR(n))
#define HW_FB_CSARn_RD(n) (HW_FB_CSARn(n).U)
#define HW_FB_CSARn_WR(n, v) (HW_FB_CSARn(n).U = (v))
#define HW_FB_CSARn_SET(n, v) (HW_FB_CSARn_WR(n, HW_FB_CSARn_RD(n) | (v)))
#define HW_FB_CSARn_CLR(n, v) (HW_FB_CSARn_WR(n, HW_FB_CSARn_RD(n) & ~(v)))
#define HW_FB_CSARn_TOG(n, v) (HW_FB_CSARn_WR(n, HW_FB_CSARn_RD(n) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual FB_CSARn bitfields
*/
/*!
* @name Register FB_CSARn, field BA[31:16] (RW)
*
* Defines the base address for memory dedicated to the associated chip-select.
* BA is compared to bits 31-16 on the internal address bus to determine if the
* associated chip-select's memory is being accessed. Because the FlexBus module
* is one of the slaves connected to the crossbar switch, it is only accessible
* within a certain memory range. See the chip memory map for the applicable
* FlexBus "expansion" address range for which the chip-selects can be active. Set the
* CSARn and CSMRn registers appropriately before accessing this region.
*/
//@{
#define BP_FB_CSARn_BA (16U) //!< Bit position for FB_CSARn_BA.
#define BM_FB_CSARn_BA (0xFFFF0000U) //!< Bit mask for FB_CSARn_BA.
#define BS_FB_CSARn_BA (16U) //!< Bit field size in bits for FB_CSARn_BA.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSARn_BA field.
#define BR_FB_CSARn_BA(n) (HW_FB_CSARn(n).B.BA)
#endif
//! @brief Format value for bitfield FB_CSARn_BA.
#define BF_FB_CSARn_BA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSARn_BA), uint32_t) & BM_FB_CSARn_BA)
#ifndef __LANGUAGE_ASM__
//! @brief Set the BA field to a new value.
#define BW_FB_CSARn_BA(n, v) (HW_FB_CSARn_WR(n, (HW_FB_CSARn_RD(n) & ~BM_FB_CSARn_BA) | BF_FB_CSARn_BA(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_FB_CSMRn - Chip Select Mask Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_FB_CSMRn - Chip Select Mask Register (RW)
*
* Reset value: 0x00000000U
*
* Specifies the address mask and allowable access types for the associated
* chip-select.
*/
typedef union _hw_fb_csmrn
{
uint32_t U;
struct _hw_fb_csmrn_bitfields
{
uint32_t V : 1; //!< [0] Valid
uint32_t RESERVED0 : 7; //!< [7:1]
uint32_t WP : 1; //!< [8] Write Protect
uint32_t RESERVED1 : 7; //!< [15:9]
uint32_t BAM : 16; //!< [31:16] Base Address Mask
} B;
} hw_fb_csmrn_t;
#endif
/*!
* @name Constants and macros for entire FB_CSMRn register
*/
//@{
#define HW_FB_CSMRn_COUNT (6U)
#define HW_FB_CSMRn_ADDR(n) (REGS_FB_BASE + 0x4U + (0xCU * n))
#ifndef __LANGUAGE_ASM__
#define HW_FB_CSMRn(n) (*(__IO hw_fb_csmrn_t *) HW_FB_CSMRn_ADDR(n))
#define HW_FB_CSMRn_RD(n) (HW_FB_CSMRn(n).U)
#define HW_FB_CSMRn_WR(n, v) (HW_FB_CSMRn(n).U = (v))
#define HW_FB_CSMRn_SET(n, v) (HW_FB_CSMRn_WR(n, HW_FB_CSMRn_RD(n) | (v)))
#define HW_FB_CSMRn_CLR(n, v) (HW_FB_CSMRn_WR(n, HW_FB_CSMRn_RD(n) & ~(v)))
#define HW_FB_CSMRn_TOG(n, v) (HW_FB_CSMRn_WR(n, HW_FB_CSMRn_RD(n) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual FB_CSMRn bitfields
*/
/*!
* @name Register FB_CSMRn, field V[0] (RW)
*
* Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid.
* Programmed chip-selects do not assert until the V bit is 1b (except for
* FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any
* access to the FlexBus memory region. CSMR0[V] must be set as part of the chip
* select initialization sequence to allow other chip selects to function as
* programmed.
*
* Values:
* - 0 - Chip-select is invalid.
* - 1 - Chip-select is valid.
*/
//@{
#define BP_FB_CSMRn_V (0U) //!< Bit position for FB_CSMRn_V.
#define BM_FB_CSMRn_V (0x00000001U) //!< Bit mask for FB_CSMRn_V.
#define BS_FB_CSMRn_V (1U) //!< Bit field size in bits for FB_CSMRn_V.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSMRn_V field.
#define BR_FB_CSMRn_V(n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_V))
#endif
//! @brief Format value for bitfield FB_CSMRn_V.
#define BF_FB_CSMRn_V(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSMRn_V), uint32_t) & BM_FB_CSMRn_V)
#ifndef __LANGUAGE_ASM__
//! @brief Set the V field to a new value.
#define BW_FB_CSMRn_V(n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_V) = (v))
#endif
//@}
/*!
* @name Register FB_CSMRn, field WP[8] (RW)
*
* Controls write accesses to the address range in the corresponding CSAR.
*
* Values:
* - 0 - Write accesses are allowed.
* - 1 - Write accesses are not allowed. Attempting to write to the range of
* addresses for which the WP bit is set results in a bus error termination of
* the internal cycle and no external cycle.
*/
//@{
#define BP_FB_CSMRn_WP (8U) //!< Bit position for FB_CSMRn_WP.
#define BM_FB_CSMRn_WP (0x00000100U) //!< Bit mask for FB_CSMRn_WP.
#define BS_FB_CSMRn_WP (1U) //!< Bit field size in bits for FB_CSMRn_WP.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSMRn_WP field.
#define BR_FB_CSMRn_WP(n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_WP))
#endif
//! @brief Format value for bitfield FB_CSMRn_WP.
#define BF_FB_CSMRn_WP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSMRn_WP), uint32_t) & BM_FB_CSMRn_WP)
#ifndef __LANGUAGE_ASM__
//! @brief Set the WP field to a new value.
#define BW_FB_CSMRn_WP(n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_WP) = (v))
#endif
//@}
/*!
* @name Register FB_CSMRn, field BAM[31:16] (RW)
*
* Defines the associated chip-select's block size by masking address bits.
*
* Values:
* - 0 - The corresponding address bit in CSAR is used in the chip-select decode.
* - 1 - The corresponding address bit in CSAR is a don't care in the
* chip-select decode.
*/
//@{
#define BP_FB_CSMRn_BAM (16U) //!< Bit position for FB_CSMRn_BAM.
#define BM_FB_CSMRn_BAM (0xFFFF0000U) //!< Bit mask for FB_CSMRn_BAM.
#define BS_FB_CSMRn_BAM (16U) //!< Bit field size in bits for FB_CSMRn_BAM.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSMRn_BAM field.
#define BR_FB_CSMRn_BAM(n) (HW_FB_CSMRn(n).B.BAM)
#endif
//! @brief Format value for bitfield FB_CSMRn_BAM.
#define BF_FB_CSMRn_BAM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSMRn_BAM), uint32_t) & BM_FB_CSMRn_BAM)
#ifndef __LANGUAGE_ASM__
//! @brief Set the BAM field to a new value.
#define BW_FB_CSMRn_BAM(n, v) (HW_FB_CSMRn_WR(n, (HW_FB_CSMRn_RD(n) & ~BM_FB_CSMRn_BAM) | BF_FB_CSMRn_BAM(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_FB_CSCRn - Chip Select Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_FB_CSCRn - Chip Select Control Register (RW)
*
* Reset value: 0x003FFC00U
*
* Controls the auto-acknowledge, address setup and hold times, port size, burst
* capability, and number of wait states for the associated chip select. To
* support the global chip-select (FB_CS0), the CSCR0 reset values differ from the
* other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3
* are chip-dependent Bits 3-0 are 0b See the chip configuration details for your
* particular chip for information on the exact CSCR0 reset value.
*/
typedef union _hw_fb_cscrn
{
uint32_t U;
struct _hw_fb_cscrn_bitfields
{
uint32_t RESERVED0 : 3; //!< [2:0]
uint32_t BSTW : 1; //!< [3] Burst-Write Enable
uint32_t BSTR : 1; //!< [4] Burst-Read Enable
uint32_t BEM : 1; //!< [5] Byte-Enable Mode
uint32_t PS : 2; //!< [7:6] Port Size
uint32_t AA : 1; //!< [8] Auto-Acknowledge Enable
uint32_t BLS : 1; //!< [9] Byte-Lane Shift
uint32_t WS : 6; //!< [15:10] Wait States
uint32_t WRAH : 2; //!< [17:16] Write Address Hold or Deselect
uint32_t RDAH : 2; //!< [19:18] Read Address Hold or Deselect
uint32_t ASET : 2; //!< [21:20] Address Setup
uint32_t EXTS : 1; //!< [22]
uint32_t SWSEN : 1; //!< [23] Secondary Wait State Enable
uint32_t RESERVED1 : 2; //!< [25:24]
uint32_t SWS : 6; //!< [31:26] Secondary Wait States
} B;
} hw_fb_cscrn_t;
#endif
/*!
* @name Constants and macros for entire FB_CSCRn register
*/
//@{
#define HW_FB_CSCRn_COUNT (6U)
#define HW_FB_CSCRn_ADDR(n) (REGS_FB_BASE + 0x8U + (0xCU * n))
#ifndef __LANGUAGE_ASM__
#define HW_FB_CSCRn(n) (*(__IO hw_fb_cscrn_t *) HW_FB_CSCRn_ADDR(n))
#define HW_FB_CSCRn_RD(n) (HW_FB_CSCRn(n).U)
#define HW_FB_CSCRn_WR(n, v) (HW_FB_CSCRn(n).U = (v))
#define HW_FB_CSCRn_SET(n, v) (HW_FB_CSCRn_WR(n, HW_FB_CSCRn_RD(n) | (v)))
#define HW_FB_CSCRn_CLR(n, v) (HW_FB_CSCRn_WR(n, HW_FB_CSCRn_RD(n) & ~(v)))
#define HW_FB_CSCRn_TOG(n, v) (HW_FB_CSCRn_WR(n, HW_FB_CSCRn_RD(n) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual FB_CSCRn bitfields
*/
/*!
* @name Register FB_CSCRn, field BSTW[3] (RW)
*
* Specifies whether burst writes are enabled for memory associated with each
* chip select.
*
* Values:
* - 0 - Disabled. Data exceeding the specified port size is broken into
* individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit
* port takes four byte writes.
* - 1 - Enabled. Enables burst write of data larger than the specified port
* size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit
* ports, and line writes to 8-, 16-, and 32-bit ports.
*/
//@{
#define BP_FB_CSCRn_BSTW (3U) //!< Bit position for FB_CSCRn_BSTW.
#define BM_FB_CSCRn_BSTW (0x00000008U) //!< Bit mask for FB_CSCRn_BSTW.
#define BS_FB_CSCRn_BSTW (1U) //!< Bit field size in bits for FB_CSCRn_BSTW.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSCRn_BSTW field.
#define BR_FB_CSCRn_BSTW(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTW))
#endif
//! @brief Format value for bitfield FB_CSCRn_BSTW.
#define BF_FB_CSCRn_BSTW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BSTW), uint32_t) & BM_FB_CSCRn_BSTW)
#ifndef __LANGUAGE_ASM__
//! @brief Set the BSTW field to a new value.
#define BW_FB_CSCRn_BSTW(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTW) = (v))
#endif
//@}
/*!
* @name Register FB_CSCRn, field BSTR[4] (RW)
*
* Specifies whether burst reads are enabled for memory associated with each
* chip select.
*
* Values:
* - 0 - Disabled. Data exceeding the specified port size is broken into
* individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit
* port is broken into four 8-bit reads.
* - 1 - Enabled. Enables data burst reads larger than the specified port size,
* including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit
* ports, and line reads from 8-, 16-, and 32-bit ports.
*/
//@{
#define BP_FB_CSCRn_BSTR (4U) //!< Bit position for FB_CSCRn_BSTR.
#define BM_FB_CSCRn_BSTR (0x00000010U) //!< Bit mask for FB_CSCRn_BSTR.
#define BS_FB_CSCRn_BSTR (1U) //!< Bit field size in bits for FB_CSCRn_BSTR.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSCRn_BSTR field.
#define BR_FB_CSCRn_BSTR(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTR))
#endif
//! @brief Format value for bitfield FB_CSCRn_BSTR.
#define BF_FB_CSCRn_BSTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BSTR), uint32_t) & BM_FB_CSCRn_BSTR)
#ifndef __LANGUAGE_ASM__
//! @brief Set the BSTR field to a new value.
#define BW_FB_CSCRn_BSTR(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTR) = (v))
#endif
//@}
/*!
* @name Register FB_CSCRn, field BEM[5] (RW)
*
* Specifies whether the corresponding FB_BE is asserted for read accesses.
* Certain memories have byte enables that must be asserted during reads and writes.
* Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode
* of byte enable support for these SRAMs.
*
* Values:
* - 0 - FB_BE is asserted for data write only.
* - 1 - FB_BE is asserted for data read and write accesses.
*/
//@{
#define BP_FB_CSCRn_BEM (5U) //!< Bit position for FB_CSCRn_BEM.
#define BM_FB_CSCRn_BEM (0x00000020U) //!< Bit mask for FB_CSCRn_BEM.
#define BS_FB_CSCRn_BEM (1U) //!< Bit field size in bits for FB_CSCRn_BEM.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSCRn_BEM field.
#define BR_FB_CSCRn_BEM(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BEM))
#endif
//! @brief Format value for bitfield FB_CSCRn_BEM.
#define BF_FB_CSCRn_BEM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BEM), uint32_t) & BM_FB_CSCRn_BEM)
#ifndef __LANGUAGE_ASM__
//! @brief Set the BEM field to a new value.
#define BW_FB_CSCRn_BEM(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BEM) = (v))
#endif
//@}
/*!
* @name Register FB_CSCRn, field PS[7:6] (RW)
*
* Specifies the data port width of the associated chip-select, and determines
* where data is driven during write cycles and where data is sampled during read
* cycles.
*
* Values:
* - 00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0].
* - 01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when
* BLS is 0b, or FB_D[7:0] when BLS is 1b.
*/
//@{
#define BP_FB_CSCRn_PS (6U) //!< Bit position for FB_CSCRn_PS.
#define BM_FB_CSCRn_PS (0x000000C0U) //!< Bit mask for FB_CSCRn_PS.
#define BS_FB_CSCRn_PS (2U) //!< Bit field size in bits for FB_CSCRn_PS.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSCRn_PS field.
#define BR_FB_CSCRn_PS(n) (HW_FB_CSCRn(n).B.PS)
#endif
//! @brief Format value for bitfield FB_CSCRn_PS.
#define BF_FB_CSCRn_PS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_PS), uint32_t) & BM_FB_CSCRn_PS)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PS field to a new value.
#define BW_FB_CSCRn_PS(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_PS) | BF_FB_CSCRn_PS(v)))
#endif
//@}
/*!
* @name Register FB_CSCRn, field AA[8] (RW)
*
* Asserts the internal transfer acknowledge for accesses specified by the
* chip-select address. If AA is 1b for a corresponding FB_CSn and the external system
* asserts an external FB_TA before the wait-state countdown asserts the
* internal FB_TA, the cycle is terminated. Burst cycles increment the address bus
* between each internal termination. This field must be 1b if CSPMCR disables FB_TA.
*
* Values:
* - 0 - Disabled. No internal transfer acknowledge is asserted and the cycle is
* terminated externally.
* - 1 - Enabled. Internal transfer acknowledge is asserted as specified by WS.
*/
//@{
#define BP_FB_CSCRn_AA (8U) //!< Bit position for FB_CSCRn_AA.
#define BM_FB_CSCRn_AA (0x00000100U) //!< Bit mask for FB_CSCRn_AA.
#define BS_FB_CSCRn_AA (1U) //!< Bit field size in bits for FB_CSCRn_AA.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSCRn_AA field.
#define BR_FB_CSCRn_AA(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_AA))
#endif
//! @brief Format value for bitfield FB_CSCRn_AA.
#define BF_FB_CSCRn_AA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_AA), uint32_t) & BM_FB_CSCRn_AA)
#ifndef __LANGUAGE_ASM__
//! @brief Set the AA field to a new value.
#define BW_FB_CSCRn_AA(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_AA) = (v))
#endif
//@}
/*!
* @name Register FB_CSCRn, field BLS[9] (RW)
*
* Specifies if data on FB_AD appears left-aligned or right-aligned during the
* data phase of a FlexBus access.
*
* Values:
* - 0 - Not shifted. Data is left-aligned on FB_AD.
* - 1 - Shifted. Data is right-aligned on FB_AD.
*/
//@{
#define BP_FB_CSCRn_BLS (9U) //!< Bit position for FB_CSCRn_BLS.
#define BM_FB_CSCRn_BLS (0x00000200U) //!< Bit mask for FB_CSCRn_BLS.
#define BS_FB_CSCRn_BLS (1U) //!< Bit field size in bits for FB_CSCRn_BLS.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSCRn_BLS field.
#define BR_FB_CSCRn_BLS(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BLS))
#endif
//! @brief Format value for bitfield FB_CSCRn_BLS.
#define BF_FB_CSCRn_BLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BLS), uint32_t) & BM_FB_CSCRn_BLS)
#ifndef __LANGUAGE_ASM__
//! @brief Set the BLS field to a new value.
#define BW_FB_CSCRn_BLS(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BLS) = (v))
#endif
//@}
/*!
* @name Register FB_CSCRn, field WS[15:10] (RW)
*
* Specifies the number of wait states inserted after FlexBus asserts the
* associated chip-select and before an internal transfer acknowledge is generated (WS
* = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states).
*/
//@{
#define BP_FB_CSCRn_WS (10U) //!< Bit position for FB_CSCRn_WS.
#define BM_FB_CSCRn_WS (0x0000FC00U) //!< Bit mask for FB_CSCRn_WS.
#define BS_FB_CSCRn_WS (6U) //!< Bit field size in bits for FB_CSCRn_WS.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSCRn_WS field.
#define BR_FB_CSCRn_WS(n) (HW_FB_CSCRn(n).B.WS)
#endif
//! @brief Format value for bitfield FB_CSCRn_WS.
#define BF_FB_CSCRn_WS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_WS), uint32_t) & BM_FB_CSCRn_WS)
#ifndef __LANGUAGE_ASM__
//! @brief Set the WS field to a new value.
#define BW_FB_CSCRn_WS(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_WS) | BF_FB_CSCRn_WS(v)))
#endif
//@}
/*!
* @name Register FB_CSCRn, field WRAH[17:16] (RW)
*
* Controls the address, data, and attribute hold time after the termination of
* a write cycle that hits in the associated chip-select's address space. The
* hold time applies only at the end of a transfer. Therefore, during a burst
* transfer or a transfer to a port size smaller than the transfer size, the hold time
* is only added after the last bus cycle.
*
* Values:
* - 00 - 1 cycle (default for all but FB_CS0 )
* - 01 - 2 cycles
* - 10 - 3 cycles
* - 11 - 4 cycles (default for FB_CS0 )
*/
//@{
#define BP_FB_CSCRn_WRAH (16U) //!< Bit position for FB_CSCRn_WRAH.
#define BM_FB_CSCRn_WRAH (0x00030000U) //!< Bit mask for FB_CSCRn_WRAH.
#define BS_FB_CSCRn_WRAH (2U) //!< Bit field size in bits for FB_CSCRn_WRAH.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSCRn_WRAH field.
#define BR_FB_CSCRn_WRAH(n) (HW_FB_CSCRn(n).B.WRAH)
#endif
//! @brief Format value for bitfield FB_CSCRn_WRAH.
#define BF_FB_CSCRn_WRAH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_WRAH), uint32_t) & BM_FB_CSCRn_WRAH)
#ifndef __LANGUAGE_ASM__
//! @brief Set the WRAH field to a new value.
#define BW_FB_CSCRn_WRAH(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_WRAH) | BF_FB_CSCRn_WRAH(v)))
#endif
//@}
/*!
* @name Register FB_CSCRn, field RDAH[19:18] (RW)
*
* Controls the address and attribute hold time after the termination during a
* read cycle that hits in the associated chip-select's address space. The hold
* time applies only at the end of a transfer. Therefore, during a burst transfer
* or a transfer to a port size smaller than the transfer size, the hold time is
* only added after the last bus cycle. The number of cycles the address and
* attributes are held after FB_CSn deassertion depends on the value of the AA bit.
*
* Values:
* - 00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
* - 01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
* - 10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
* - 11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
*/
//@{
#define BP_FB_CSCRn_RDAH (18U) //!< Bit position for FB_CSCRn_RDAH.
#define BM_FB_CSCRn_RDAH (0x000C0000U) //!< Bit mask for FB_CSCRn_RDAH.
#define BS_FB_CSCRn_RDAH (2U) //!< Bit field size in bits for FB_CSCRn_RDAH.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSCRn_RDAH field.
#define BR_FB_CSCRn_RDAH(n) (HW_FB_CSCRn(n).B.RDAH)
#endif
//! @brief Format value for bitfield FB_CSCRn_RDAH.
#define BF_FB_CSCRn_RDAH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_RDAH), uint32_t) & BM_FB_CSCRn_RDAH)
#ifndef __LANGUAGE_ASM__
//! @brief Set the RDAH field to a new value.
#define BW_FB_CSCRn_RDAH(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_RDAH) | BF_FB_CSCRn_RDAH(v)))
#endif
//@}
/*!
* @name Register FB_CSCRn, field ASET[21:20] (RW)
*
* Controls when the chip-select is asserted with respect to assertion of a
* valid address and attributes.
*
* Values:
* - 00 - Assert FB_CSn on the first rising clock edge after the address is
* asserted (default for all but FB_CS0 ).
* - 01 - Assert FB_CSn on the second rising clock edge after the address is
* asserted.
* - 10 - Assert FB_CSn on the third rising clock edge after the address is
* asserted.
* - 11 - Assert FB_CSn on the fourth rising clock edge after the address is
* asserted (default for FB_CS0 ).
*/
//@{
#define BP_FB_CSCRn_ASET (20U) //!< Bit position for FB_CSCRn_ASET.
#define BM_FB_CSCRn_ASET (0x00300000U) //!< Bit mask for FB_CSCRn_ASET.
#define BS_FB_CSCRn_ASET (2U) //!< Bit field size in bits for FB_CSCRn_ASET.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSCRn_ASET field.
#define BR_FB_CSCRn_ASET(n) (HW_FB_CSCRn(n).B.ASET)
#endif
//! @brief Format value for bitfield FB_CSCRn_ASET.
#define BF_FB_CSCRn_ASET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_ASET), uint32_t) & BM_FB_CSCRn_ASET)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ASET field to a new value.
#define BW_FB_CSCRn_ASET(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_ASET) | BF_FB_CSCRn_ASET(v)))
#endif
//@}
/*!
* @name Register FB_CSCRn, field EXTS[22] (RW)
*
* Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS
* /FB_ALE is asserted.
*
* Values:
* - 0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
* - 1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive clock
* edge after FB_CSn asserts.
*/
//@{
#define BP_FB_CSCRn_EXTS (22U) //!< Bit position for FB_CSCRn_EXTS.
#define BM_FB_CSCRn_EXTS (0x00400000U) //!< Bit mask for FB_CSCRn_EXTS.
#define BS_FB_CSCRn_EXTS (1U) //!< Bit field size in bits for FB_CSCRn_EXTS.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSCRn_EXTS field.
#define BR_FB_CSCRn_EXTS(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_EXTS))
#endif
//! @brief Format value for bitfield FB_CSCRn_EXTS.
#define BF_FB_CSCRn_EXTS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_EXTS), uint32_t) & BM_FB_CSCRn_EXTS)
#ifndef __LANGUAGE_ASM__
//! @brief Set the EXTS field to a new value.
#define BW_FB_CSCRn_EXTS(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_EXTS) = (v))
#endif
//@}
/*!
* @name Register FB_CSCRn, field SWSEN[23] (RW)
*
* Values:
* - 0 - Disabled. A number of wait states (specified by WS) are inserted before
* an internal transfer acknowledge is generated for all transfers.
* - 1 - Enabled. A number of wait states (specified by SWS) are inserted before
* an internal transfer acknowledge is generated for burst transfer
* secondary terminations.
*/
//@{
#define BP_FB_CSCRn_SWSEN (23U) //!< Bit position for FB_CSCRn_SWSEN.
#define BM_FB_CSCRn_SWSEN (0x00800000U) //!< Bit mask for FB_CSCRn_SWSEN.
#define BS_FB_CSCRn_SWSEN (1U) //!< Bit field size in bits for FB_CSCRn_SWSEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSCRn_SWSEN field.
#define BR_FB_CSCRn_SWSEN(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_SWSEN))
#endif
//! @brief Format value for bitfield FB_CSCRn_SWSEN.
#define BF_FB_CSCRn_SWSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_SWSEN), uint32_t) & BM_FB_CSCRn_SWSEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SWSEN field to a new value.
#define BW_FB_CSCRn_SWSEN(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_SWSEN) = (v))
#endif
//@}
/*!
* @name Register FB_CSCRn, field SWS[31:26] (RW)
*
* Used only when the SWSEN bit is 1b. Specifies the number of wait states
* inserted before an internal transfer acknowledge is generated for a burst transfer
* (except for the first termination, which is controlled by WS).
*/
//@{
#define BP_FB_CSCRn_SWS (26U) //!< Bit position for FB_CSCRn_SWS.
#define BM_FB_CSCRn_SWS (0xFC000000U) //!< Bit mask for FB_CSCRn_SWS.
#define BS_FB_CSCRn_SWS (6U) //!< Bit field size in bits for FB_CSCRn_SWS.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSCRn_SWS field.
#define BR_FB_CSCRn_SWS(n) (HW_FB_CSCRn(n).B.SWS)
#endif
//! @brief Format value for bitfield FB_CSCRn_SWS.
#define BF_FB_CSCRn_SWS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_SWS), uint32_t) & BM_FB_CSCRn_SWS)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SWS field to a new value.
#define BW_FB_CSCRn_SWS(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_SWS) | BF_FB_CSCRn_SWS(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_FB_CSPMCR - Chip Select port Multiplexing Control Register (RW)
*
* Reset value: 0x00000000U
*
* Controls the multiplexing of the FlexBus signals. A bus error occurs when you
* do any of the following: Write to a reserved address Write to a reserved
* field in this register, or Access this register using a size other than 32 bits.
*/
typedef union _hw_fb_cspmcr
{
uint32_t U;
struct _hw_fb_cspmcr_bitfields
{
uint32_t RESERVED0 : 12; //!< [11:0]
uint32_t GROUP5 : 4; //!< [15:12] FlexBus Signal Group 5 Multiplex
//! control
uint32_t GROUP4 : 4; //!< [19:16] FlexBus Signal Group 4 Multiplex
//! control
uint32_t GROUP3 : 4; //!< [23:20] FlexBus Signal Group 3 Multiplex
//! control
uint32_t GROUP2 : 4; //!< [27:24] FlexBus Signal Group 2 Multiplex
//! control
uint32_t GROUP1 : 4; //!< [31:28] FlexBus Signal Group 1 Multiplex
//! control
} B;
} hw_fb_cspmcr_t;
#endif
/*!
* @name Constants and macros for entire FB_CSPMCR register
*/
//@{
#define HW_FB_CSPMCR_ADDR (REGS_FB_BASE + 0x60U)
#ifndef __LANGUAGE_ASM__
#define HW_FB_CSPMCR (*(__IO hw_fb_cspmcr_t *) HW_FB_CSPMCR_ADDR)
#define HW_FB_CSPMCR_RD() (HW_FB_CSPMCR.U)
#define HW_FB_CSPMCR_WR(v) (HW_FB_CSPMCR.U = (v))
#define HW_FB_CSPMCR_SET(v) (HW_FB_CSPMCR_WR(HW_FB_CSPMCR_RD() | (v)))
#define HW_FB_CSPMCR_CLR(v) (HW_FB_CSPMCR_WR(HW_FB_CSPMCR_RD() & ~(v)))
#define HW_FB_CSPMCR_TOG(v) (HW_FB_CSPMCR_WR(HW_FB_CSPMCR_RD() ^ (v)))
#endif
//@}
/*
* Constants & macros for individual FB_CSPMCR bitfields
*/
/*!
* @name Register FB_CSPMCR, field GROUP5[15:12] (RW)
*
* Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
* GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
* bus hangs during a transfer.
*
* Values:
* - 0000 - FB_TA
* - 0001 - FB_CS3 . You must also write 1b to CSCR[AA].
* - 0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA].
*/
//@{
#define BP_FB_CSPMCR_GROUP5 (12U) //!< Bit position for FB_CSPMCR_GROUP5.
#define BM_FB_CSPMCR_GROUP5 (0x0000F000U) //!< Bit mask for FB_CSPMCR_GROUP5.
#define BS_FB_CSPMCR_GROUP5 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP5.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSPMCR_GROUP5 field.
#define BR_FB_CSPMCR_GROUP5 (HW_FB_CSPMCR.B.GROUP5)
#endif
//! @brief Format value for bitfield FB_CSPMCR_GROUP5.
#define BF_FB_CSPMCR_GROUP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP5), uint32_t) & BM_FB_CSPMCR_GROUP5)
#ifndef __LANGUAGE_ASM__
//! @brief Set the GROUP5 field to a new value.
#define BW_FB_CSPMCR_GROUP5(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP5) | BF_FB_CSPMCR_GROUP5(v)))
#endif
//@}
/*!
* @name Register FB_CSPMCR, field GROUP4[19:16] (RW)
*
* Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals.
*
* Values:
* - 0000 - FB_TBST
* - 0001 - FB_CS2
* - 0010 - FB_BE_15_8
*/
//@{
#define BP_FB_CSPMCR_GROUP4 (16U) //!< Bit position for FB_CSPMCR_GROUP4.
#define BM_FB_CSPMCR_GROUP4 (0x000F0000U) //!< Bit mask for FB_CSPMCR_GROUP4.
#define BS_FB_CSPMCR_GROUP4 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP4.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSPMCR_GROUP4 field.
#define BR_FB_CSPMCR_GROUP4 (HW_FB_CSPMCR.B.GROUP4)
#endif
//! @brief Format value for bitfield FB_CSPMCR_GROUP4.
#define BF_FB_CSPMCR_GROUP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP4), uint32_t) & BM_FB_CSPMCR_GROUP4)
#ifndef __LANGUAGE_ASM__
//! @brief Set the GROUP4 field to a new value.
#define BW_FB_CSPMCR_GROUP4(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP4) | BF_FB_CSPMCR_GROUP4(v)))
#endif
//@}
/*!
* @name Register FB_CSPMCR, field GROUP3[23:20] (RW)
*
* Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals.
*
* Values:
* - 0000 - FB_CS5
* - 0001 - FB_TSIZ1
* - 0010 - FB_BE_23_16
*/
//@{
#define BP_FB_CSPMCR_GROUP3 (20U) //!< Bit position for FB_CSPMCR_GROUP3.
#define BM_FB_CSPMCR_GROUP3 (0x00F00000U) //!< Bit mask for FB_CSPMCR_GROUP3.
#define BS_FB_CSPMCR_GROUP3 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP3.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSPMCR_GROUP3 field.
#define BR_FB_CSPMCR_GROUP3 (HW_FB_CSPMCR.B.GROUP3)
#endif
//! @brief Format value for bitfield FB_CSPMCR_GROUP3.
#define BF_FB_CSPMCR_GROUP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP3), uint32_t) & BM_FB_CSPMCR_GROUP3)
#ifndef __LANGUAGE_ASM__
//! @brief Set the GROUP3 field to a new value.
#define BW_FB_CSPMCR_GROUP3(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP3) | BF_FB_CSPMCR_GROUP3(v)))
#endif
//@}
/*!
* @name Register FB_CSPMCR, field GROUP2[27:24] (RW)
*
* Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
*
* Values:
* - 0000 - FB_CS4
* - 0001 - FB_TSIZ0
* - 0010 - FB_BE_31_24
*/
//@{
#define BP_FB_CSPMCR_GROUP2 (24U) //!< Bit position for FB_CSPMCR_GROUP2.
#define BM_FB_CSPMCR_GROUP2 (0x0F000000U) //!< Bit mask for FB_CSPMCR_GROUP2.
#define BS_FB_CSPMCR_GROUP2 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP2.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSPMCR_GROUP2 field.
#define BR_FB_CSPMCR_GROUP2 (HW_FB_CSPMCR.B.GROUP2)
#endif
//! @brief Format value for bitfield FB_CSPMCR_GROUP2.
#define BF_FB_CSPMCR_GROUP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP2), uint32_t) & BM_FB_CSPMCR_GROUP2)
#ifndef __LANGUAGE_ASM__
//! @brief Set the GROUP2 field to a new value.
#define BW_FB_CSPMCR_GROUP2(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP2) | BF_FB_CSPMCR_GROUP2(v)))
#endif
//@}
/*!
* @name Register FB_CSPMCR, field GROUP1[31:28] (RW)
*
* Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
*
* Values:
* - 0000 - FB_ALE
* - 0001 - FB_CS1
* - 0010 - FB_TS
*/
//@{
#define BP_FB_CSPMCR_GROUP1 (28U) //!< Bit position for FB_CSPMCR_GROUP1.
#define BM_FB_CSPMCR_GROUP1 (0xF0000000U) //!< Bit mask for FB_CSPMCR_GROUP1.
#define BS_FB_CSPMCR_GROUP1 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP1.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the FB_CSPMCR_GROUP1 field.
#define BR_FB_CSPMCR_GROUP1 (HW_FB_CSPMCR.B.GROUP1)
#endif
//! @brief Format value for bitfield FB_CSPMCR_GROUP1.
#define BF_FB_CSPMCR_GROUP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP1), uint32_t) & BM_FB_CSPMCR_GROUP1)
#ifndef __LANGUAGE_ASM__
//! @brief Set the GROUP1 field to a new value.
#define BW_FB_CSPMCR_GROUP1(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP1) | BF_FB_CSPMCR_GROUP1(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_fb_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All FB module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_fb
{
struct {
__IO hw_fb_csarn_t CSARn; //!< [0x0] Chip Select Address Register
__IO hw_fb_csmrn_t CSMRn; //!< [0x4] Chip Select Mask Register
__IO hw_fb_cscrn_t CSCRn; //!< [0x8] Chip Select Control Register
} CS[6];
uint8_t _reserved0[24];
__IO hw_fb_cspmcr_t CSPMCR; //!< [0x60] Chip Select port Multiplexing Control Register
} hw_fb_t;
#pragma pack()
//! @brief Macro to access all FB registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_FB</code>.
#define HW_FB (*(hw_fb_t *) REGS_FB_BASE)
#endif
#endif // __HW_FB_REGISTERS_H__
// v22/130726/0.9
// EOF

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_GPIO_REGISTERS_H__
#define __HW_GPIO_REGISTERS_H__
#include "regs.h"
/*
* MK64F12 GPIO
*
* General Purpose Input/Output
*
* Registers defined in this header file:
* - HW_GPIO_PDOR - Port Data Output Register
* - HW_GPIO_PSOR - Port Set Output Register
* - HW_GPIO_PCOR - Port Clear Output Register
* - HW_GPIO_PTOR - Port Toggle Output Register
* - HW_GPIO_PDIR - Port Data Input Register
* - HW_GPIO_PDDR - Port Data Direction Register
*
* - hw_gpio_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_GPIO_BASE
#define HW_GPIO_INSTANCE_COUNT (5U) //!< Number of instances of the GPIO module.
#define HW_GPIOA (0U) //!< Instance number for GPIOA.
#define HW_GPIOB (1U) //!< Instance number for GPIOB.
#define HW_GPIOC (2U) //!< Instance number for GPIOC.
#define HW_GPIOD (3U) //!< Instance number for GPIOD.
#define HW_GPIOE (4U) //!< Instance number for GPIOE.
#define REGS_GPIOA_BASE (0x400FF000U) //!< Base address for GPIOA.
#define REGS_GPIOB_BASE (0x400FF040U) //!< Base address for GPIOB.
#define REGS_GPIOC_BASE (0x400FF080U) //!< Base address for GPIOC.
#define REGS_GPIOD_BASE (0x400FF0C0U) //!< Base address for GPIOD.
#define REGS_GPIOE_BASE (0x400FF100U) //!< Base address for GPIOE.
//! @brief Table of base addresses for GPIO instances.
static const uint32_t __g_regs_GPIO_base_addresses[] = {
REGS_GPIOA_BASE,
REGS_GPIOB_BASE,
REGS_GPIOC_BASE,
REGS_GPIOD_BASE,
REGS_GPIOE_BASE,
};
//! @brief Get the base address of GPIO by instance number.
//! @param x GPIO instance number, from 0 through 4.
#define REGS_GPIO_BASE(x) (__g_regs_GPIO_base_addresses[(x)])
//! @brief Get the instance number given a base address.
//! @param b Base address for an instance of GPIO.
#define REGS_GPIO_INSTANCE(b) ((b) == REGS_GPIOA_BASE ? HW_GPIOA : (b) == REGS_GPIOB_BASE ? HW_GPIOB : (b) == REGS_GPIOC_BASE ? HW_GPIOC : (b) == REGS_GPIOD_BASE ? HW_GPIOD : (b) == REGS_GPIOE_BASE ? HW_GPIOE : 0)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_GPIO_PDOR - Port Data Output Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_GPIO_PDOR - Port Data Output Register (RW)
*
* Reset value: 0x00000000U
*
* This register configures the logic levels that are driven on each
* general-purpose output pins. Do not modify pin configuration registers associated with
* pins not available in your selected package. All unbonded pins not available in
* your package will default to DISABLE state for lowest power consumption.
*/
typedef union _hw_gpio_pdor
{
uint32_t U;
struct _hw_gpio_pdor_bitfields
{
uint32_t PDO : 32; //!< [31:0] Port Data Output
} B;
} hw_gpio_pdor_t;
#endif
/*!
* @name Constants and macros for entire GPIO_PDOR register
*/
//@{
#define HW_GPIO_PDOR_ADDR(x) (REGS_GPIO_BASE(x) + 0x0U)
#ifndef __LANGUAGE_ASM__
#define HW_GPIO_PDOR(x) (*(__IO hw_gpio_pdor_t *) HW_GPIO_PDOR_ADDR(x))
#define HW_GPIO_PDOR_RD(x) (HW_GPIO_PDOR(x).U)
#define HW_GPIO_PDOR_WR(x, v) (HW_GPIO_PDOR(x).U = (v))
#define HW_GPIO_PDOR_SET(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) | (v)))
#define HW_GPIO_PDOR_CLR(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) & ~(v)))
#define HW_GPIO_PDOR_TOG(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual GPIO_PDOR bitfields
*/
/*!
* @name Register GPIO_PDOR, field PDO[31:0] (RW)
*
* Register bits for unbonded pins return a undefined value when read.
*
* Values:
* - 0 - Logic level 0 is driven on pin, provided pin is configured for
* general-purpose output.
* - 1 - Logic level 1 is driven on pin, provided pin is configured for
* general-purpose output.
*/
//@{
#define BP_GPIO_PDOR_PDO (0U) //!< Bit position for GPIO_PDOR_PDO.
#define BM_GPIO_PDOR_PDO (0xFFFFFFFFU) //!< Bit mask for GPIO_PDOR_PDO.
#define BS_GPIO_PDOR_PDO (32U) //!< Bit field size in bits for GPIO_PDOR_PDO.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the GPIO_PDOR_PDO field.
#define BR_GPIO_PDOR_PDO(x) (HW_GPIO_PDOR(x).U)
#endif
//! @brief Format value for bitfield GPIO_PDOR_PDO.
#define BF_GPIO_PDOR_PDO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PDOR_PDO), uint32_t) & BM_GPIO_PDOR_PDO)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PDO field to a new value.
#define BW_GPIO_PDOR_PDO(x, v) (HW_GPIO_PDOR_WR(x, v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_GPIO_PSOR - Port Set Output Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_GPIO_PSOR - Port Set Output Register (WORZ)
*
* Reset value: 0x00000000U
*
* This register configures whether to set the fields of the PDOR.
*/
typedef union _hw_gpio_psor
{
uint32_t U;
struct _hw_gpio_psor_bitfields
{
uint32_t PTSO : 32; //!< [31:0] Port Set Output
} B;
} hw_gpio_psor_t;
#endif
/*!
* @name Constants and macros for entire GPIO_PSOR register
*/
//@{
#define HW_GPIO_PSOR_ADDR(x) (REGS_GPIO_BASE(x) + 0x4U)
#ifndef __LANGUAGE_ASM__
#define HW_GPIO_PSOR(x) (*(__O hw_gpio_psor_t *) HW_GPIO_PSOR_ADDR(x))
#define HW_GPIO_PSOR_RD(x) (HW_GPIO_PSOR(x).U)
#define HW_GPIO_PSOR_WR(x, v) (HW_GPIO_PSOR(x).U = (v))
#endif
//@}
/*
* Constants & macros for individual GPIO_PSOR bitfields
*/
/*!
* @name Register GPIO_PSOR, field PTSO[31:0] (WORZ)
*
* Writing to this register will update the contents of the corresponding bit in
* the PDOR as follows:
*
* Values:
* - 0 - Corresponding bit in PDORn does not change.
* - 1 - Corresponding bit in PDORn is set to logic 1.
*/
//@{
#define BP_GPIO_PSOR_PTSO (0U) //!< Bit position for GPIO_PSOR_PTSO.
#define BM_GPIO_PSOR_PTSO (0xFFFFFFFFU) //!< Bit mask for GPIO_PSOR_PTSO.
#define BS_GPIO_PSOR_PTSO (32U) //!< Bit field size in bits for GPIO_PSOR_PTSO.
//! @brief Format value for bitfield GPIO_PSOR_PTSO.
#define BF_GPIO_PSOR_PTSO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PSOR_PTSO), uint32_t) & BM_GPIO_PSOR_PTSO)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PTSO field to a new value.
#define BW_GPIO_PSOR_PTSO(x, v) (HW_GPIO_PSOR_WR(x, v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_GPIO_PCOR - Port Clear Output Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_GPIO_PCOR - Port Clear Output Register (WORZ)
*
* Reset value: 0x00000000U
*
* This register configures whether to clear the fields of PDOR.
*/
typedef union _hw_gpio_pcor
{
uint32_t U;
struct _hw_gpio_pcor_bitfields
{
uint32_t PTCO : 32; //!< [31:0] Port Clear Output
} B;
} hw_gpio_pcor_t;
#endif
/*!
* @name Constants and macros for entire GPIO_PCOR register
*/
//@{
#define HW_GPIO_PCOR_ADDR(x) (REGS_GPIO_BASE(x) + 0x8U)
#ifndef __LANGUAGE_ASM__
#define HW_GPIO_PCOR(x) (*(__O hw_gpio_pcor_t *) HW_GPIO_PCOR_ADDR(x))
#define HW_GPIO_PCOR_RD(x) (HW_GPIO_PCOR(x).U)
#define HW_GPIO_PCOR_WR(x, v) (HW_GPIO_PCOR(x).U = (v))
#endif
//@}
/*
* Constants & macros for individual GPIO_PCOR bitfields
*/
/*!
* @name Register GPIO_PCOR, field PTCO[31:0] (WORZ)
*
* Writing to this register will update the contents of the corresponding bit in
* the Port Data Output Register (PDOR) as follows:
*
* Values:
* - 0 - Corresponding bit in PDORn does not change.
* - 1 - Corresponding bit in PDORn is cleared to logic 0.
*/
//@{
#define BP_GPIO_PCOR_PTCO (0U) //!< Bit position for GPIO_PCOR_PTCO.
#define BM_GPIO_PCOR_PTCO (0xFFFFFFFFU) //!< Bit mask for GPIO_PCOR_PTCO.
#define BS_GPIO_PCOR_PTCO (32U) //!< Bit field size in bits for GPIO_PCOR_PTCO.
//! @brief Format value for bitfield GPIO_PCOR_PTCO.
#define BF_GPIO_PCOR_PTCO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PCOR_PTCO), uint32_t) & BM_GPIO_PCOR_PTCO)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PTCO field to a new value.
#define BW_GPIO_PCOR_PTCO(x, v) (HW_GPIO_PCOR_WR(x, v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_GPIO_PTOR - Port Toggle Output Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_GPIO_PTOR - Port Toggle Output Register (WORZ)
*
* Reset value: 0x00000000U
*/
typedef union _hw_gpio_ptor
{
uint32_t U;
struct _hw_gpio_ptor_bitfields
{
uint32_t PTTO : 32; //!< [31:0] Port Toggle Output
} B;
} hw_gpio_ptor_t;
#endif
/*!
* @name Constants and macros for entire GPIO_PTOR register
*/
//@{
#define HW_GPIO_PTOR_ADDR(x) (REGS_GPIO_BASE(x) + 0xCU)
#ifndef __LANGUAGE_ASM__
#define HW_GPIO_PTOR(x) (*(__O hw_gpio_ptor_t *) HW_GPIO_PTOR_ADDR(x))
#define HW_GPIO_PTOR_RD(x) (HW_GPIO_PTOR(x).U)
#define HW_GPIO_PTOR_WR(x, v) (HW_GPIO_PTOR(x).U = (v))
#endif
//@}
/*
* Constants & macros for individual GPIO_PTOR bitfields
*/
/*!
* @name Register GPIO_PTOR, field PTTO[31:0] (WORZ)
*
* Writing to this register will update the contents of the corresponding bit in
* the PDOR as follows:
*
* Values:
* - 0 - Corresponding bit in PDORn does not change.
* - 1 - Corresponding bit in PDORn is set to the inverse of its existing logic
* state.
*/
//@{
#define BP_GPIO_PTOR_PTTO (0U) //!< Bit position for GPIO_PTOR_PTTO.
#define BM_GPIO_PTOR_PTTO (0xFFFFFFFFU) //!< Bit mask for GPIO_PTOR_PTTO.
#define BS_GPIO_PTOR_PTTO (32U) //!< Bit field size in bits for GPIO_PTOR_PTTO.
//! @brief Format value for bitfield GPIO_PTOR_PTTO.
#define BF_GPIO_PTOR_PTTO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PTOR_PTTO), uint32_t) & BM_GPIO_PTOR_PTTO)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PTTO field to a new value.
#define BW_GPIO_PTOR_PTTO(x, v) (HW_GPIO_PTOR_WR(x, v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_GPIO_PDIR - Port Data Input Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_GPIO_PDIR - Port Data Input Register (RO)
*
* Reset value: 0x00000000U
*
* Do not modify pin configuration registers associated with pins not available
* in your selected package. All unbonded pins not available in your package will
* default to DISABLE state for lowest power consumption.
*/
typedef union _hw_gpio_pdir
{
uint32_t U;
struct _hw_gpio_pdir_bitfields
{
uint32_t PDI : 32; //!< [31:0] Port Data Input
} B;
} hw_gpio_pdir_t;
#endif
/*!
* @name Constants and macros for entire GPIO_PDIR register
*/
//@{
#define HW_GPIO_PDIR_ADDR(x) (REGS_GPIO_BASE(x) + 0x10U)
#ifndef __LANGUAGE_ASM__
#define HW_GPIO_PDIR(x) (*(__I hw_gpio_pdir_t *) HW_GPIO_PDIR_ADDR(x))
#define HW_GPIO_PDIR_RD(x) (HW_GPIO_PDIR(x).U)
#endif
//@}
/*
* Constants & macros for individual GPIO_PDIR bitfields
*/
/*!
* @name Register GPIO_PDIR, field PDI[31:0] (RO)
*
* Reads 0 at the unimplemented pins for a particular device. Pins that are not
* configured for a digital function read 0. If the Port Control and Interrupt
* module is disabled, then the corresponding bit in PDIR does not update.
*
* Values:
* - 0 - Pin logic level is logic 0, or is not configured for use by digital
* function.
* - 1 - Pin logic level is logic 1.
*/
//@{
#define BP_GPIO_PDIR_PDI (0U) //!< Bit position for GPIO_PDIR_PDI.
#define BM_GPIO_PDIR_PDI (0xFFFFFFFFU) //!< Bit mask for GPIO_PDIR_PDI.
#define BS_GPIO_PDIR_PDI (32U) //!< Bit field size in bits for GPIO_PDIR_PDI.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the GPIO_PDIR_PDI field.
#define BR_GPIO_PDIR_PDI(x) (HW_GPIO_PDIR(x).U)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_GPIO_PDDR - Port Data Direction Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_GPIO_PDDR - Port Data Direction Register (RW)
*
* Reset value: 0x00000000U
*
* The PDDR configures the individual port pins for input or output.
*/
typedef union _hw_gpio_pddr
{
uint32_t U;
struct _hw_gpio_pddr_bitfields
{
uint32_t PDD : 32; //!< [31:0] Port Data Direction
} B;
} hw_gpio_pddr_t;
#endif
/*!
* @name Constants and macros for entire GPIO_PDDR register
*/
//@{
#define HW_GPIO_PDDR_ADDR(x) (REGS_GPIO_BASE(x) + 0x14U)
#ifndef __LANGUAGE_ASM__
#define HW_GPIO_PDDR(x) (*(__IO hw_gpio_pddr_t *) HW_GPIO_PDDR_ADDR(x))
#define HW_GPIO_PDDR_RD(x) (HW_GPIO_PDDR(x).U)
#define HW_GPIO_PDDR_WR(x, v) (HW_GPIO_PDDR(x).U = (v))
#define HW_GPIO_PDDR_SET(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) | (v)))
#define HW_GPIO_PDDR_CLR(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) & ~(v)))
#define HW_GPIO_PDDR_TOG(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual GPIO_PDDR bitfields
*/
/*!
* @name Register GPIO_PDDR, field PDD[31:0] (RW)
*
* Configures individual port pins for input or output.
*
* Values:
* - 0 - Pin is configured as general-purpose input, for the GPIO function.
* - 1 - Pin is configured as general-purpose output, for the GPIO function.
*/
//@{
#define BP_GPIO_PDDR_PDD (0U) //!< Bit position for GPIO_PDDR_PDD.
#define BM_GPIO_PDDR_PDD (0xFFFFFFFFU) //!< Bit mask for GPIO_PDDR_PDD.
#define BS_GPIO_PDDR_PDD (32U) //!< Bit field size in bits for GPIO_PDDR_PDD.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the GPIO_PDDR_PDD field.
#define BR_GPIO_PDDR_PDD(x) (HW_GPIO_PDDR(x).U)
#endif
//! @brief Format value for bitfield GPIO_PDDR_PDD.
#define BF_GPIO_PDDR_PDD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PDDR_PDD), uint32_t) & BM_GPIO_PDDR_PDD)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PDD field to a new value.
#define BW_GPIO_PDDR_PDD(x, v) (HW_GPIO_PDDR_WR(x, v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_gpio_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All GPIO module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_gpio
{
__IO hw_gpio_pdor_t PDOR; //!< [0x0] Port Data Output Register
__O hw_gpio_psor_t PSOR; //!< [0x4] Port Set Output Register
__O hw_gpio_pcor_t PCOR; //!< [0x8] Port Clear Output Register
__O hw_gpio_ptor_t PTOR; //!< [0xC] Port Toggle Output Register
__I hw_gpio_pdir_t PDIR; //!< [0x10] Port Data Input Register
__IO hw_gpio_pddr_t PDDR; //!< [0x14] Port Data Direction Register
} hw_gpio_t;
#pragma pack()
//! @brief Macro to access all GPIO registers.
//! @param x GPIO instance number.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_GPIO(0)</code>.
#define HW_GPIO(x) (*(hw_gpio_t *) REGS_GPIO_BASE(x))
#endif
#endif // __HW_GPIO_REGISTERS_H__
// v22/130726/0.9
// EOF

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_LPTMR_REGISTERS_H__
#define __HW_LPTMR_REGISTERS_H__
#include "regs.h"
/*
* MK64F12 LPTMR
*
* Low Power Timer
*
* Registers defined in this header file:
* - HW_LPTMR_CSR - Low Power Timer Control Status Register
* - HW_LPTMR_PSR - Low Power Timer Prescale Register
* - HW_LPTMR_CMR - Low Power Timer Compare Register
* - HW_LPTMR_CNR - Low Power Timer Counter Register
*
* - hw_lptmr_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_LPTMR_BASE
#define HW_LPTMR_INSTANCE_COUNT (1U) //!< Number of instances of the LPTMR module.
#define REGS_LPTMR_BASE (0x40040000U) //!< Base address for LPTMR0.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_LPTMR_CSR - Low Power Timer Control Status Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_LPTMR_CSR - Low Power Timer Control Status Register (RW)
*
* Reset value: 0x00000000U
*/
typedef union _hw_lptmr_csr
{
uint32_t U;
struct _hw_lptmr_csr_bitfields
{
uint32_t TEN : 1; //!< [0] Timer Enable
uint32_t TMS : 1; //!< [1] Timer Mode Select
uint32_t TFC : 1; //!< [2] Timer Free-Running Counter
uint32_t TPP : 1; //!< [3] Timer Pin Polarity
uint32_t TPS : 2; //!< [5:4] Timer Pin Select
uint32_t TIE : 1; //!< [6] Timer Interrupt Enable
uint32_t TCF : 1; //!< [7] Timer Compare Flag
uint32_t RESERVED0 : 24; //!< [31:8]
} B;
} hw_lptmr_csr_t;
#endif
/*!
* @name Constants and macros for entire LPTMR_CSR register
*/
//@{
#define HW_LPTMR_CSR_ADDR (REGS_LPTMR_BASE + 0x0U)
#ifndef __LANGUAGE_ASM__
#define HW_LPTMR_CSR (*(__IO hw_lptmr_csr_t *) HW_LPTMR_CSR_ADDR)
#define HW_LPTMR_CSR_RD() (HW_LPTMR_CSR.U)
#define HW_LPTMR_CSR_WR(v) (HW_LPTMR_CSR.U = (v))
#define HW_LPTMR_CSR_SET(v) (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() | (v)))
#define HW_LPTMR_CSR_CLR(v) (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() & ~(v)))
#define HW_LPTMR_CSR_TOG(v) (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() ^ (v)))
#endif
//@}
/*
* Constants & macros for individual LPTMR_CSR bitfields
*/
/*!
* @name Register LPTMR_CSR, field TEN[0] (RW)
*
* When TEN is clear, it resets the LPTMR internal logic, including the CNR and
* TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field,
* CSR[5:1] must not be altered.
*
* Values:
* - 0 - LPTMR is disabled and internal logic is reset.
* - 1 - LPTMR is enabled.
*/
//@{
#define BP_LPTMR_CSR_TEN (0U) //!< Bit position for LPTMR_CSR_TEN.
#define BM_LPTMR_CSR_TEN (0x00000001U) //!< Bit mask for LPTMR_CSR_TEN.
#define BS_LPTMR_CSR_TEN (1U) //!< Bit field size in bits for LPTMR_CSR_TEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the LPTMR_CSR_TEN field.
#define BR_LPTMR_CSR_TEN (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TEN))
#endif
//! @brief Format value for bitfield LPTMR_CSR_TEN.
#define BF_LPTMR_CSR_TEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TEN), uint32_t) & BM_LPTMR_CSR_TEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TEN field to a new value.
#define BW_LPTMR_CSR_TEN(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TEN) = (v))
#endif
//@}
/*!
* @name Register LPTMR_CSR, field TMS[1] (RW)
*
* Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is
* disabled.
*
* Values:
* - 0 - Time Counter mode.
* - 1 - Pulse Counter mode.
*/
//@{
#define BP_LPTMR_CSR_TMS (1U) //!< Bit position for LPTMR_CSR_TMS.
#define BM_LPTMR_CSR_TMS (0x00000002U) //!< Bit mask for LPTMR_CSR_TMS.
#define BS_LPTMR_CSR_TMS (1U) //!< Bit field size in bits for LPTMR_CSR_TMS.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the LPTMR_CSR_TMS field.
#define BR_LPTMR_CSR_TMS (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TMS))
#endif
//! @brief Format value for bitfield LPTMR_CSR_TMS.
#define BF_LPTMR_CSR_TMS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TMS), uint32_t) & BM_LPTMR_CSR_TMS)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TMS field to a new value.
#define BW_LPTMR_CSR_TMS(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TMS) = (v))
#endif
//@}
/*!
* @name Register LPTMR_CSR, field TFC[2] (RW)
*
* When clear, TFC configures the CNR to reset whenever TCF is set. When set,
* TFC configures the CNR to reset on overflow. TFC must be altered only when the
* LPTMR is disabled.
*
* Values:
* - 0 - CNR is reset whenever TCF is set.
* - 1 - CNR is reset on overflow.
*/
//@{
#define BP_LPTMR_CSR_TFC (2U) //!< Bit position for LPTMR_CSR_TFC.
#define BM_LPTMR_CSR_TFC (0x00000004U) //!< Bit mask for LPTMR_CSR_TFC.
#define BS_LPTMR_CSR_TFC (1U) //!< Bit field size in bits for LPTMR_CSR_TFC.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the LPTMR_CSR_TFC field.
#define BR_LPTMR_CSR_TFC (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TFC))
#endif
//! @brief Format value for bitfield LPTMR_CSR_TFC.
#define BF_LPTMR_CSR_TFC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TFC), uint32_t) & BM_LPTMR_CSR_TFC)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TFC field to a new value.
#define BW_LPTMR_CSR_TFC(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TFC) = (v))
#endif
//@}
/*!
* @name Register LPTMR_CSR, field TPP[3] (RW)
*
* Configures the polarity of the input source in Pulse Counter mode. TPP must
* be changed only when the LPTMR is disabled.
*
* Values:
* - 0 - Pulse Counter input source is active-high, and the CNR will increment
* on the rising-edge.
* - 1 - Pulse Counter input source is active-low, and the CNR will increment on
* the falling-edge.
*/
//@{
#define BP_LPTMR_CSR_TPP (3U) //!< Bit position for LPTMR_CSR_TPP.
#define BM_LPTMR_CSR_TPP (0x00000008U) //!< Bit mask for LPTMR_CSR_TPP.
#define BS_LPTMR_CSR_TPP (1U) //!< Bit field size in bits for LPTMR_CSR_TPP.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the LPTMR_CSR_TPP field.
#define BR_LPTMR_CSR_TPP (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TPP))
#endif
//! @brief Format value for bitfield LPTMR_CSR_TPP.
#define BF_LPTMR_CSR_TPP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TPP), uint32_t) & BM_LPTMR_CSR_TPP)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TPP field to a new value.
#define BW_LPTMR_CSR_TPP(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TPP) = (v))
#endif
//@}
/*!
* @name Register LPTMR_CSR, field TPS[5:4] (RW)
*
* Configures the input source to be used in Pulse Counter mode. TPS must be
* altered only when the LPTMR is disabled. The input connections vary by device.
* See the chip configuration details for information on the connections to these
* inputs.
*
* Values:
* - 00 - Pulse counter input 0 is selected.
* - 01 - Pulse counter input 1 is selected.
* - 10 - Pulse counter input 2 is selected.
* - 11 - Pulse counter input 3 is selected.
*/
//@{
#define BP_LPTMR_CSR_TPS (4U) //!< Bit position for LPTMR_CSR_TPS.
#define BM_LPTMR_CSR_TPS (0x00000030U) //!< Bit mask for LPTMR_CSR_TPS.
#define BS_LPTMR_CSR_TPS (2U) //!< Bit field size in bits for LPTMR_CSR_TPS.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the LPTMR_CSR_TPS field.
#define BR_LPTMR_CSR_TPS (HW_LPTMR_CSR.B.TPS)
#endif
//! @brief Format value for bitfield LPTMR_CSR_TPS.
#define BF_LPTMR_CSR_TPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TPS), uint32_t) & BM_LPTMR_CSR_TPS)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TPS field to a new value.
#define BW_LPTMR_CSR_TPS(v) (HW_LPTMR_CSR_WR((HW_LPTMR_CSR_RD() & ~BM_LPTMR_CSR_TPS) | BF_LPTMR_CSR_TPS(v)))
#endif
//@}
/*!
* @name Register LPTMR_CSR, field TIE[6] (RW)
*
* When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
*
* Values:
* - 0 - Timer interrupt disabled.
* - 1 - Timer interrupt enabled.
*/
//@{
#define BP_LPTMR_CSR_TIE (6U) //!< Bit position for LPTMR_CSR_TIE.
#define BM_LPTMR_CSR_TIE (0x00000040U) //!< Bit mask for LPTMR_CSR_TIE.
#define BS_LPTMR_CSR_TIE (1U) //!< Bit field size in bits for LPTMR_CSR_TIE.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the LPTMR_CSR_TIE field.
#define BR_LPTMR_CSR_TIE (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TIE))
#endif
//! @brief Format value for bitfield LPTMR_CSR_TIE.
#define BF_LPTMR_CSR_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TIE), uint32_t) & BM_LPTMR_CSR_TIE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TIE field to a new value.
#define BW_LPTMR_CSR_TIE(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TIE) = (v))
#endif
//@}
/*!
* @name Register LPTMR_CSR, field TCF[7] (W1C)
*
* TCF is set when the LPTMR is enabled and the CNR equals the CMR and
* increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
*
* Values:
* - 0 - The value of CNR is not equal to CMR and increments.
* - 1 - The value of CNR is equal to CMR and increments.
*/
//@{
#define BP_LPTMR_CSR_TCF (7U) //!< Bit position for LPTMR_CSR_TCF.
#define BM_LPTMR_CSR_TCF (0x00000080U) //!< Bit mask for LPTMR_CSR_TCF.
#define BS_LPTMR_CSR_TCF (1U) //!< Bit field size in bits for LPTMR_CSR_TCF.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the LPTMR_CSR_TCF field.
#define BR_LPTMR_CSR_TCF (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TCF))
#endif
//! @brief Format value for bitfield LPTMR_CSR_TCF.
#define BF_LPTMR_CSR_TCF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TCF), uint32_t) & BM_LPTMR_CSR_TCF)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TCF field to a new value.
#define BW_LPTMR_CSR_TCF(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TCF) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_LPTMR_PSR - Low Power Timer Prescale Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_LPTMR_PSR - Low Power Timer Prescale Register (RW)
*
* Reset value: 0x00000000U
*/
typedef union _hw_lptmr_psr
{
uint32_t U;
struct _hw_lptmr_psr_bitfields
{
uint32_t PCS : 2; //!< [1:0] Prescaler Clock Select
uint32_t PBYP : 1; //!< [2] Prescaler Bypass
uint32_t PRESCALE : 4; //!< [6:3] Prescale Value
uint32_t RESERVED0 : 25; //!< [31:7]
} B;
} hw_lptmr_psr_t;
#endif
/*!
* @name Constants and macros for entire LPTMR_PSR register
*/
//@{
#define HW_LPTMR_PSR_ADDR (REGS_LPTMR_BASE + 0x4U)
#ifndef __LANGUAGE_ASM__
#define HW_LPTMR_PSR (*(__IO hw_lptmr_psr_t *) HW_LPTMR_PSR_ADDR)
#define HW_LPTMR_PSR_RD() (HW_LPTMR_PSR.U)
#define HW_LPTMR_PSR_WR(v) (HW_LPTMR_PSR.U = (v))
#define HW_LPTMR_PSR_SET(v) (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() | (v)))
#define HW_LPTMR_PSR_CLR(v) (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() & ~(v)))
#define HW_LPTMR_PSR_TOG(v) (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() ^ (v)))
#endif
//@}
/*
* Constants & macros for individual LPTMR_PSR bitfields
*/
/*!
* @name Register LPTMR_PSR, field PCS[1:0] (RW)
*
* Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must
* be altered only when the LPTMR is disabled. The clock connections vary by
* device. See the chip configuration details for information on the connections to
* these inputs.
*
* Values:
* - 00 - Prescaler/glitch filter clock 0 selected.
* - 01 - Prescaler/glitch filter clock 1 selected.
* - 10 - Prescaler/glitch filter clock 2 selected.
* - 11 - Prescaler/glitch filter clock 3 selected.
*/
//@{
#define BP_LPTMR_PSR_PCS (0U) //!< Bit position for LPTMR_PSR_PCS.
#define BM_LPTMR_PSR_PCS (0x00000003U) //!< Bit mask for LPTMR_PSR_PCS.
#define BS_LPTMR_PSR_PCS (2U) //!< Bit field size in bits for LPTMR_PSR_PCS.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the LPTMR_PSR_PCS field.
#define BR_LPTMR_PSR_PCS (HW_LPTMR_PSR.B.PCS)
#endif
//! @brief Format value for bitfield LPTMR_PSR_PCS.
#define BF_LPTMR_PSR_PCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PCS), uint32_t) & BM_LPTMR_PSR_PCS)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PCS field to a new value.
#define BW_LPTMR_PSR_PCS(v) (HW_LPTMR_PSR_WR((HW_LPTMR_PSR_RD() & ~BM_LPTMR_PSR_PCS) | BF_LPTMR_PSR_PCS(v)))
#endif
//@}
/*!
* @name Register LPTMR_PSR, field PBYP[2] (RW)
*
* When PBYP is set, the selected prescaler clock in Time Counter mode or
* selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is
* clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP
* must be altered only when the LPTMR is disabled.
*
* Values:
* - 0 - Prescaler/glitch filter is enabled.
* - 1 - Prescaler/glitch filter is bypassed.
*/
//@{
#define BP_LPTMR_PSR_PBYP (2U) //!< Bit position for LPTMR_PSR_PBYP.
#define BM_LPTMR_PSR_PBYP (0x00000004U) //!< Bit mask for LPTMR_PSR_PBYP.
#define BS_LPTMR_PSR_PBYP (1U) //!< Bit field size in bits for LPTMR_PSR_PBYP.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the LPTMR_PSR_PBYP field.
#define BR_LPTMR_PSR_PBYP (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR, BP_LPTMR_PSR_PBYP))
#endif
//! @brief Format value for bitfield LPTMR_PSR_PBYP.
#define BF_LPTMR_PSR_PBYP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PBYP), uint32_t) & BM_LPTMR_PSR_PBYP)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PBYP field to a new value.
#define BW_LPTMR_PSR_PBYP(v) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR, BP_LPTMR_PSR_PBYP) = (v))
#endif
//@}
/*!
* @name Register LPTMR_PSR, field PRESCALE[6:3] (RW)
*
* Configures the size of the Prescaler in Time Counter mode or width of the
* glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR
* is disabled.
*
* Values:
* - 0000 - Prescaler divides the prescaler clock by 2; glitch filter does not
* support this configuration.
* - 0001 - Prescaler divides the prescaler clock by 4; glitch filter recognizes
* change on input pin after 2 rising clock edges.
* - 0010 - Prescaler divides the prescaler clock by 8; glitch filter recognizes
* change on input pin after 4 rising clock edges.
* - 0011 - Prescaler divides the prescaler clock by 16; glitch filter
* recognizes change on input pin after 8 rising clock edges.
* - 0100 - Prescaler divides the prescaler clock by 32; glitch filter
* recognizes change on input pin after 16 rising clock edges.
* - 0101 - Prescaler divides the prescaler clock by 64; glitch filter
* recognizes change on input pin after 32 rising clock edges.
* - 0110 - Prescaler divides the prescaler clock by 128; glitch filter
* recognizes change on input pin after 64 rising clock edges.
* - 0111 - Prescaler divides the prescaler clock by 256; glitch filter
* recognizes change on input pin after 128 rising clock edges.
* - 1000 - Prescaler divides the prescaler clock by 512; glitch filter
* recognizes change on input pin after 256 rising clock edges.
* - 1001 - Prescaler divides the prescaler clock by 1024; glitch filter
* recognizes change on input pin after 512 rising clock edges.
* - 1010 - Prescaler divides the prescaler clock by 2048; glitch filter
* recognizes change on input pin after 1024 rising clock edges.
* - 1011 - Prescaler divides the prescaler clock by 4096; glitch filter
* recognizes change on input pin after 2048 rising clock edges.
* - 1100 - Prescaler divides the prescaler clock by 8192; glitch filter
* recognizes change on input pin after 4096 rising clock edges.
* - 1101 - Prescaler divides the prescaler clock by 16,384; glitch filter
* recognizes change on input pin after 8192 rising clock edges.
* - 1110 - Prescaler divides the prescaler clock by 32,768; glitch filter
* recognizes change on input pin after 16,384 rising clock edges.
* - 1111 - Prescaler divides the prescaler clock by 65,536; glitch filter
* recognizes change on input pin after 32,768 rising clock edges.
*/
//@{
#define BP_LPTMR_PSR_PRESCALE (3U) //!< Bit position for LPTMR_PSR_PRESCALE.
#define BM_LPTMR_PSR_PRESCALE (0x00000078U) //!< Bit mask for LPTMR_PSR_PRESCALE.
#define BS_LPTMR_PSR_PRESCALE (4U) //!< Bit field size in bits for LPTMR_PSR_PRESCALE.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the LPTMR_PSR_PRESCALE field.
#define BR_LPTMR_PSR_PRESCALE (HW_LPTMR_PSR.B.PRESCALE)
#endif
//! @brief Format value for bitfield LPTMR_PSR_PRESCALE.
#define BF_LPTMR_PSR_PRESCALE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PRESCALE), uint32_t) & BM_LPTMR_PSR_PRESCALE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PRESCALE field to a new value.
#define BW_LPTMR_PSR_PRESCALE(v) (HW_LPTMR_PSR_WR((HW_LPTMR_PSR_RD() & ~BM_LPTMR_PSR_PRESCALE) | BF_LPTMR_PSR_PRESCALE(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_LPTMR_CMR - Low Power Timer Compare Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_LPTMR_CMR - Low Power Timer Compare Register (RW)
*
* Reset value: 0x00000000U
*/
typedef union _hw_lptmr_cmr
{
uint32_t U;
struct _hw_lptmr_cmr_bitfields
{
uint32_t COMPARE : 16; //!< [15:0] Compare Value
uint32_t RESERVED0 : 16; //!< [31:16]
} B;
} hw_lptmr_cmr_t;
#endif
/*!
* @name Constants and macros for entire LPTMR_CMR register
*/
//@{
#define HW_LPTMR_CMR_ADDR (REGS_LPTMR_BASE + 0x8U)
#ifndef __LANGUAGE_ASM__
#define HW_LPTMR_CMR (*(__IO hw_lptmr_cmr_t *) HW_LPTMR_CMR_ADDR)
#define HW_LPTMR_CMR_RD() (HW_LPTMR_CMR.U)
#define HW_LPTMR_CMR_WR(v) (HW_LPTMR_CMR.U = (v))
#define HW_LPTMR_CMR_SET(v) (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() | (v)))
#define HW_LPTMR_CMR_CLR(v) (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() & ~(v)))
#define HW_LPTMR_CMR_TOG(v) (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() ^ (v)))
#endif
//@}
/*
* Constants & macros for individual LPTMR_CMR bitfields
*/
/*!
* @name Register LPTMR_CMR, field COMPARE[15:0] (RW)
*
* When the LPTMR is enabled and the CNR equals the value in the CMR and
* increments, TCF is set and the hardware trigger asserts until the next time the CNR
* increments. If the CMR is 0, the hardware trigger will remain asserted until
* the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
* when TCF is set.
*/
//@{
#define BP_LPTMR_CMR_COMPARE (0U) //!< Bit position for LPTMR_CMR_COMPARE.
#define BM_LPTMR_CMR_COMPARE (0x0000FFFFU) //!< Bit mask for LPTMR_CMR_COMPARE.
#define BS_LPTMR_CMR_COMPARE (16U) //!< Bit field size in bits for LPTMR_CMR_COMPARE.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the LPTMR_CMR_COMPARE field.
#define BR_LPTMR_CMR_COMPARE (HW_LPTMR_CMR.B.COMPARE)
#endif
//! @brief Format value for bitfield LPTMR_CMR_COMPARE.
#define BF_LPTMR_CMR_COMPARE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CMR_COMPARE), uint32_t) & BM_LPTMR_CMR_COMPARE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the COMPARE field to a new value.
#define BW_LPTMR_CMR_COMPARE(v) (HW_LPTMR_CMR_WR((HW_LPTMR_CMR_RD() & ~BM_LPTMR_CMR_COMPARE) | BF_LPTMR_CMR_COMPARE(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_LPTMR_CNR - Low Power Timer Counter Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_LPTMR_CNR - Low Power Timer Counter Register (RW)
*
* Reset value: 0x00000000U
*/
typedef union _hw_lptmr_cnr
{
uint32_t U;
struct _hw_lptmr_cnr_bitfields
{
uint32_t COUNTER : 16; //!< [15:0] Counter Value
uint32_t RESERVED0 : 16; //!< [31:16]
} B;
} hw_lptmr_cnr_t;
#endif
/*!
* @name Constants and macros for entire LPTMR_CNR register
*/
//@{
#define HW_LPTMR_CNR_ADDR (REGS_LPTMR_BASE + 0xCU)
#ifndef __LANGUAGE_ASM__
#define HW_LPTMR_CNR (*(__IO hw_lptmr_cnr_t *) HW_LPTMR_CNR_ADDR)
#define HW_LPTMR_CNR_RD() (HW_LPTMR_CNR.U)
#define HW_LPTMR_CNR_WR(v) (HW_LPTMR_CNR.U = (v))
#define HW_LPTMR_CNR_SET(v) (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() | (v)))
#define HW_LPTMR_CNR_CLR(v) (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() & ~(v)))
#define HW_LPTMR_CNR_TOG(v) (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() ^ (v)))
#endif
//@}
/*
* Constants & macros for individual LPTMR_CNR bitfields
*/
/*!
* @name Register LPTMR_CNR, field COUNTER[15:0] (RW)
*/
//@{
#define BP_LPTMR_CNR_COUNTER (0U) //!< Bit position for LPTMR_CNR_COUNTER.
#define BM_LPTMR_CNR_COUNTER (0x0000FFFFU) //!< Bit mask for LPTMR_CNR_COUNTER.
#define BS_LPTMR_CNR_COUNTER (16U) //!< Bit field size in bits for LPTMR_CNR_COUNTER.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the LPTMR_CNR_COUNTER field.
#define BR_LPTMR_CNR_COUNTER (HW_LPTMR_CNR.B.COUNTER)
#endif
//! @brief Format value for bitfield LPTMR_CNR_COUNTER.
#define BF_LPTMR_CNR_COUNTER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CNR_COUNTER), uint32_t) & BM_LPTMR_CNR_COUNTER)
#ifndef __LANGUAGE_ASM__
//! @brief Set the COUNTER field to a new value.
#define BW_LPTMR_CNR_COUNTER(v) (HW_LPTMR_CNR_WR((HW_LPTMR_CNR_RD() & ~BM_LPTMR_CNR_COUNTER) | BF_LPTMR_CNR_COUNTER(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_lptmr_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All LPTMR module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_lptmr
{
__IO hw_lptmr_csr_t CSR; //!< [0x0] Low Power Timer Control Status Register
__IO hw_lptmr_psr_t PSR; //!< [0x4] Low Power Timer Prescale Register
__IO hw_lptmr_cmr_t CMR; //!< [0x8] Low Power Timer Compare Register
__IO hw_lptmr_cnr_t CNR; //!< [0xC] Low Power Timer Counter Register
} hw_lptmr_t;
#pragma pack()
//! @brief Macro to access all LPTMR registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_LPTMR</code>.
#define HW_LPTMR (*(hw_lptmr_t *) REGS_LPTMR_BASE)
#endif
#endif // __HW_LPTMR_REGISTERS_H__
// v22/130726/0.9
// EOF

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_NV_REGISTERS_H__
#define __HW_NV_REGISTERS_H__
#include "regs.h"
/*
* MK64F12 NV
*
* Flash configuration field
*
* Registers defined in this header file:
* - HW_NV_BACKKEY3 - Backdoor Comparison Key 3.
* - HW_NV_BACKKEY2 - Backdoor Comparison Key 2.
* - HW_NV_BACKKEY1 - Backdoor Comparison Key 1.
* - HW_NV_BACKKEY0 - Backdoor Comparison Key 0.
* - HW_NV_BACKKEY7 - Backdoor Comparison Key 7.
* - HW_NV_BACKKEY6 - Backdoor Comparison Key 6.
* - HW_NV_BACKKEY5 - Backdoor Comparison Key 5.
* - HW_NV_BACKKEY4 - Backdoor Comparison Key 4.
* - HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
* - HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
* - HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
* - HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
* - HW_NV_FSEC - Non-volatile Flash Security Register
* - HW_NV_FOPT - Non-volatile Flash Option Register
* - HW_NV_FEPROT - Non-volatile EERAM Protection Register
* - HW_NV_FDPROT - Non-volatile D-Flash Protection Register
*
* - hw_nv_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_NV_BASE
#define HW_NV_INSTANCE_COUNT (1U) //!< Number of instances of the NV module.
#define REGS_NV_BASE (0x400U) //!< Base address for FTFE_FlashConfig.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_NV_BACKKEY3 - Backdoor Comparison Key 3.
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_NV_BACKKEY3 - Backdoor Comparison Key 3. (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_backkey3
{
uint8_t U;
struct _hw_nv_backkey3_bitfields
{
uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
} B;
} hw_nv_backkey3_t;
#endif
/*!
* @name Constants and macros for entire NV_BACKKEY3 register
*/
//@{
#define HW_NV_BACKKEY3_ADDR (REGS_NV_BASE + 0x0U)
#ifndef __LANGUAGE_ASM__
#define HW_NV_BACKKEY3 (*(__I hw_nv_backkey3_t *) HW_NV_BACKKEY3_ADDR)
#define HW_NV_BACKKEY3_RD() (HW_NV_BACKKEY3.U)
#endif
//@}
/*
* Constants & macros for individual NV_BACKKEY3 bitfields
*/
/*!
* @name Register NV_BACKKEY3, field KEY[7:0] (RO)
*/
//@{
#define BP_NV_BACKKEY3_KEY (0U) //!< Bit position for NV_BACKKEY3_KEY.
#define BM_NV_BACKKEY3_KEY (0xFFU) //!< Bit mask for NV_BACKKEY3_KEY.
#define BS_NV_BACKKEY3_KEY (8U) //!< Bit field size in bits for NV_BACKKEY3_KEY.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the NV_BACKKEY3_KEY field.
#define BR_NV_BACKKEY3_KEY (HW_NV_BACKKEY3.U)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_NV_BACKKEY2 - Backdoor Comparison Key 2.
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_NV_BACKKEY2 - Backdoor Comparison Key 2. (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_backkey2
{
uint8_t U;
struct _hw_nv_backkey2_bitfields
{
uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
} B;
} hw_nv_backkey2_t;
#endif
/*!
* @name Constants and macros for entire NV_BACKKEY2 register
*/
//@{
#define HW_NV_BACKKEY2_ADDR (REGS_NV_BASE + 0x1U)
#ifndef __LANGUAGE_ASM__
#define HW_NV_BACKKEY2 (*(__I hw_nv_backkey2_t *) HW_NV_BACKKEY2_ADDR)
#define HW_NV_BACKKEY2_RD() (HW_NV_BACKKEY2.U)
#endif
//@}
/*
* Constants & macros for individual NV_BACKKEY2 bitfields
*/
/*!
* @name Register NV_BACKKEY2, field KEY[7:0] (RO)
*/
//@{
#define BP_NV_BACKKEY2_KEY (0U) //!< Bit position for NV_BACKKEY2_KEY.
#define BM_NV_BACKKEY2_KEY (0xFFU) //!< Bit mask for NV_BACKKEY2_KEY.
#define BS_NV_BACKKEY2_KEY (8U) //!< Bit field size in bits for NV_BACKKEY2_KEY.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the NV_BACKKEY2_KEY field.
#define BR_NV_BACKKEY2_KEY (HW_NV_BACKKEY2.U)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_NV_BACKKEY1 - Backdoor Comparison Key 1.
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_NV_BACKKEY1 - Backdoor Comparison Key 1. (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_backkey1
{
uint8_t U;
struct _hw_nv_backkey1_bitfields
{
uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
} B;
} hw_nv_backkey1_t;
#endif
/*!
* @name Constants and macros for entire NV_BACKKEY1 register
*/
//@{
#define HW_NV_BACKKEY1_ADDR (REGS_NV_BASE + 0x2U)
#ifndef __LANGUAGE_ASM__
#define HW_NV_BACKKEY1 (*(__I hw_nv_backkey1_t *) HW_NV_BACKKEY1_ADDR)
#define HW_NV_BACKKEY1_RD() (HW_NV_BACKKEY1.U)
#endif
//@}
/*
* Constants & macros for individual NV_BACKKEY1 bitfields
*/
/*!
* @name Register NV_BACKKEY1, field KEY[7:0] (RO)
*/
//@{
#define BP_NV_BACKKEY1_KEY (0U) //!< Bit position for NV_BACKKEY1_KEY.
#define BM_NV_BACKKEY1_KEY (0xFFU) //!< Bit mask for NV_BACKKEY1_KEY.
#define BS_NV_BACKKEY1_KEY (8U) //!< Bit field size in bits for NV_BACKKEY1_KEY.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the NV_BACKKEY1_KEY field.
#define BR_NV_BACKKEY1_KEY (HW_NV_BACKKEY1.U)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_NV_BACKKEY0 - Backdoor Comparison Key 0.
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_NV_BACKKEY0 - Backdoor Comparison Key 0. (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_backkey0
{
uint8_t U;
struct _hw_nv_backkey0_bitfields
{
uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
} B;
} hw_nv_backkey0_t;
#endif
/*!
* @name Constants and macros for entire NV_BACKKEY0 register
*/
//@{
#define HW_NV_BACKKEY0_ADDR (REGS_NV_BASE + 0x3U)
#ifndef __LANGUAGE_ASM__
#define HW_NV_BACKKEY0 (*(__I hw_nv_backkey0_t *) HW_NV_BACKKEY0_ADDR)
#define HW_NV_BACKKEY0_RD() (HW_NV_BACKKEY0.U)
#endif
//@}
/*
* Constants & macros for individual NV_BACKKEY0 bitfields
*/
/*!
* @name Register NV_BACKKEY0, field KEY[7:0] (RO)
*/
//@{
#define BP_NV_BACKKEY0_KEY (0U) //!< Bit position for NV_BACKKEY0_KEY.
#define BM_NV_BACKKEY0_KEY (0xFFU) //!< Bit mask for NV_BACKKEY0_KEY.
#define BS_NV_BACKKEY0_KEY (8U) //!< Bit field size in bits for NV_BACKKEY0_KEY.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the NV_BACKKEY0_KEY field.
#define BR_NV_BACKKEY0_KEY (HW_NV_BACKKEY0.U)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_NV_BACKKEY7 - Backdoor Comparison Key 7.
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_NV_BACKKEY7 - Backdoor Comparison Key 7. (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_backkey7
{
uint8_t U;
struct _hw_nv_backkey7_bitfields
{
uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
} B;
} hw_nv_backkey7_t;
#endif
/*!
* @name Constants and macros for entire NV_BACKKEY7 register
*/
//@{
#define HW_NV_BACKKEY7_ADDR (REGS_NV_BASE + 0x4U)
#ifndef __LANGUAGE_ASM__
#define HW_NV_BACKKEY7 (*(__I hw_nv_backkey7_t *) HW_NV_BACKKEY7_ADDR)
#define HW_NV_BACKKEY7_RD() (HW_NV_BACKKEY7.U)
#endif
//@}
/*
* Constants & macros for individual NV_BACKKEY7 bitfields
*/
/*!
* @name Register NV_BACKKEY7, field KEY[7:0] (RO)
*/
//@{
#define BP_NV_BACKKEY7_KEY (0U) //!< Bit position for NV_BACKKEY7_KEY.
#define BM_NV_BACKKEY7_KEY (0xFFU) //!< Bit mask for NV_BACKKEY7_KEY.
#define BS_NV_BACKKEY7_KEY (8U) //!< Bit field size in bits for NV_BACKKEY7_KEY.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the NV_BACKKEY7_KEY field.
#define BR_NV_BACKKEY7_KEY (HW_NV_BACKKEY7.U)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_NV_BACKKEY6 - Backdoor Comparison Key 6.
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_NV_BACKKEY6 - Backdoor Comparison Key 6. (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_backkey6
{
uint8_t U;
struct _hw_nv_backkey6_bitfields
{
uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
} B;
} hw_nv_backkey6_t;
#endif
/*!
* @name Constants and macros for entire NV_BACKKEY6 register
*/
//@{
#define HW_NV_BACKKEY6_ADDR (REGS_NV_BASE + 0x5U)
#ifndef __LANGUAGE_ASM__
#define HW_NV_BACKKEY6 (*(__I hw_nv_backkey6_t *) HW_NV_BACKKEY6_ADDR)
#define HW_NV_BACKKEY6_RD() (HW_NV_BACKKEY6.U)
#endif
//@}
/*
* Constants & macros for individual NV_BACKKEY6 bitfields
*/
/*!
* @name Register NV_BACKKEY6, field KEY[7:0] (RO)
*/
//@{
#define BP_NV_BACKKEY6_KEY (0U) //!< Bit position for NV_BACKKEY6_KEY.
#define BM_NV_BACKKEY6_KEY (0xFFU) //!< Bit mask for NV_BACKKEY6_KEY.
#define BS_NV_BACKKEY6_KEY (8U) //!< Bit field size in bits for NV_BACKKEY6_KEY.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the NV_BACKKEY6_KEY field.
#define BR_NV_BACKKEY6_KEY (HW_NV_BACKKEY6.U)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_NV_BACKKEY5 - Backdoor Comparison Key 5.
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_NV_BACKKEY5 - Backdoor Comparison Key 5. (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_backkey5
{
uint8_t U;
struct _hw_nv_backkey5_bitfields
{
uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
} B;
} hw_nv_backkey5_t;
#endif
/*!
* @name Constants and macros for entire NV_BACKKEY5 register
*/
//@{
#define HW_NV_BACKKEY5_ADDR (REGS_NV_BASE + 0x6U)
#ifndef __LANGUAGE_ASM__
#define HW_NV_BACKKEY5 (*(__I hw_nv_backkey5_t *) HW_NV_BACKKEY5_ADDR)
#define HW_NV_BACKKEY5_RD() (HW_NV_BACKKEY5.U)
#endif
//@}
/*
* Constants & macros for individual NV_BACKKEY5 bitfields
*/
/*!
* @name Register NV_BACKKEY5, field KEY[7:0] (RO)
*/
//@{
#define BP_NV_BACKKEY5_KEY (0U) //!< Bit position for NV_BACKKEY5_KEY.
#define BM_NV_BACKKEY5_KEY (0xFFU) //!< Bit mask for NV_BACKKEY5_KEY.
#define BS_NV_BACKKEY5_KEY (8U) //!< Bit field size in bits for NV_BACKKEY5_KEY.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the NV_BACKKEY5_KEY field.
#define BR_NV_BACKKEY5_KEY (HW_NV_BACKKEY5.U)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_NV_BACKKEY4 - Backdoor Comparison Key 4.
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_NV_BACKKEY4 - Backdoor Comparison Key 4. (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_backkey4
{
uint8_t U;
struct _hw_nv_backkey4_bitfields
{
uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
} B;
} hw_nv_backkey4_t;
#endif
/*!
* @name Constants and macros for entire NV_BACKKEY4 register
*/
//@{
#define HW_NV_BACKKEY4_ADDR (REGS_NV_BASE + 0x7U)
#ifndef __LANGUAGE_ASM__
#define HW_NV_BACKKEY4 (*(__I hw_nv_backkey4_t *) HW_NV_BACKKEY4_ADDR)
#define HW_NV_BACKKEY4_RD() (HW_NV_BACKKEY4.U)
#endif
//@}
/*
* Constants & macros for individual NV_BACKKEY4 bitfields
*/
/*!
* @name Register NV_BACKKEY4, field KEY[7:0] (RO)
*/
//@{
#define BP_NV_BACKKEY4_KEY (0U) //!< Bit position for NV_BACKKEY4_KEY.
#define BM_NV_BACKKEY4_KEY (0xFFU) //!< Bit mask for NV_BACKKEY4_KEY.
#define BS_NV_BACKKEY4_KEY (8U) //!< Bit field size in bits for NV_BACKKEY4_KEY.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the NV_BACKKEY4_KEY field.
#define BR_NV_BACKKEY4_KEY (HW_NV_BACKKEY4.U)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_fprot3
{
uint8_t U;
struct _hw_nv_fprot3_bitfields
{
uint8_t PROT : 8; //!< [7:0] P-Flash Region Protect
} B;
} hw_nv_fprot3_t;
#endif
/*!
* @name Constants and macros for entire NV_FPROT3 register
*/
//@{
#define HW_NV_FPROT3_ADDR (REGS_NV_BASE + 0x8U)
#ifndef __LANGUAGE_ASM__
#define HW_NV_FPROT3 (*(__I hw_nv_fprot3_t *) HW_NV_FPROT3_ADDR)
#define HW_NV_FPROT3_RD() (HW_NV_FPROT3.U)
#endif
//@}
/*
* Constants & macros for individual NV_FPROT3 bitfields
*/
/*!
* @name Register NV_FPROT3, field PROT[7:0] (RO)
*/
//@{
#define BP_NV_FPROT3_PROT (0U) //!< Bit position for NV_FPROT3_PROT.
#define BM_NV_FPROT3_PROT (0xFFU) //!< Bit mask for NV_FPROT3_PROT.
#define BS_NV_FPROT3_PROT (8U) //!< Bit field size in bits for NV_FPROT3_PROT.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the NV_FPROT3_PROT field.
#define BR_NV_FPROT3_PROT (HW_NV_FPROT3.U)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_fprot2
{
uint8_t U;
struct _hw_nv_fprot2_bitfields
{
uint8_t PROT : 8; //!< [7:0] P-Flash Region Protect
} B;
} hw_nv_fprot2_t;
#endif
/*!
* @name Constants and macros for entire NV_FPROT2 register
*/
//@{
#define HW_NV_FPROT2_ADDR (REGS_NV_BASE + 0x9U)
#ifndef __LANGUAGE_ASM__
#define HW_NV_FPROT2 (*(__I hw_nv_fprot2_t *) HW_NV_FPROT2_ADDR)
#define HW_NV_FPROT2_RD() (HW_NV_FPROT2.U)
#endif
//@}
/*
* Constants & macros for individual NV_FPROT2 bitfields
*/
/*!
* @name Register NV_FPROT2, field PROT[7:0] (RO)
*/
//@{
#define BP_NV_FPROT2_PROT (0U) //!< Bit position for NV_FPROT2_PROT.
#define BM_NV_FPROT2_PROT (0xFFU) //!< Bit mask for NV_FPROT2_PROT.
#define BS_NV_FPROT2_PROT (8U) //!< Bit field size in bits for NV_FPROT2_PROT.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the NV_FPROT2_PROT field.
#define BR_NV_FPROT2_PROT (HW_NV_FPROT2.U)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_fprot1
{
uint8_t U;
struct _hw_nv_fprot1_bitfields
{
uint8_t PROT : 8; //!< [7:0] P-Flash Region Protect
} B;
} hw_nv_fprot1_t;
#endif
/*!
* @name Constants and macros for entire NV_FPROT1 register
*/
//@{
#define HW_NV_FPROT1_ADDR (REGS_NV_BASE + 0xAU)
#ifndef __LANGUAGE_ASM__
#define HW_NV_FPROT1 (*(__I hw_nv_fprot1_t *) HW_NV_FPROT1_ADDR)
#define HW_NV_FPROT1_RD() (HW_NV_FPROT1.U)
#endif
//@}
/*
* Constants & macros for individual NV_FPROT1 bitfields
*/
/*!
* @name Register NV_FPROT1, field PROT[7:0] (RO)
*/
//@{
#define BP_NV_FPROT1_PROT (0U) //!< Bit position for NV_FPROT1_PROT.
#define BM_NV_FPROT1_PROT (0xFFU) //!< Bit mask for NV_FPROT1_PROT.
#define BS_NV_FPROT1_PROT (8U) //!< Bit field size in bits for NV_FPROT1_PROT.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the NV_FPROT1_PROT field.
#define BR_NV_FPROT1_PROT (HW_NV_FPROT1.U)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_fprot0
{
uint8_t U;
struct _hw_nv_fprot0_bitfields
{
uint8_t PROT : 8; //!< [7:0] P-Flash Region Protect
} B;
} hw_nv_fprot0_t;
#endif
/*!
* @name Constants and macros for entire NV_FPROT0 register
*/
//@{
#define HW_NV_FPROT0_ADDR (REGS_NV_BASE + 0xBU)
#ifndef __LANGUAGE_ASM__
#define HW_NV_FPROT0 (*(__I hw_nv_fprot0_t *) HW_NV_FPROT0_ADDR)
#define HW_NV_FPROT0_RD() (HW_NV_FPROT0.U)
#endif
//@}
/*
* Constants & macros for individual NV_FPROT0 bitfields
*/
/*!
* @name Register NV_FPROT0, field PROT[7:0] (RO)
*/
//@{
#define BP_NV_FPROT0_PROT (0U) //!< Bit position for NV_FPROT0_PROT.
#define BM_NV_FPROT0_PROT (0xFFU) //!< Bit mask for NV_FPROT0_PROT.
#define BS_NV_FPROT0_PROT (8U) //!< Bit field size in bits for NV_FPROT0_PROT.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the NV_FPROT0_PROT field.
#define BR_NV_FPROT0_PROT (HW_NV_FPROT0.U)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_NV_FSEC - Non-volatile Flash Security Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_NV_FSEC - Non-volatile Flash Security Register (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_fsec
{
uint8_t U;
struct _hw_nv_fsec_bitfields
{
uint8_t SEC : 2; //!< [1:0] Flash Security
uint8_t FSLACC : 2; //!< [3:2] Freescale Failure Analysis Access Code
uint8_t MEEN : 2; //!< [5:4]
uint8_t KEYEN : 2; //!< [7:6] Backdoor Key Security Enable
} B;
} hw_nv_fsec_t;
#endif
/*!
* @name Constants and macros for entire NV_FSEC register
*/
//@{
#define HW_NV_FSEC_ADDR (REGS_NV_BASE + 0xCU)
#ifndef __LANGUAGE_ASM__
#define HW_NV_FSEC (*(__I hw_nv_fsec_t *) HW_NV_FSEC_ADDR)
#define HW_NV_FSEC_RD() (HW_NV_FSEC.U)
#endif
//@}
/*
* Constants & macros for individual NV_FSEC bitfields
*/
/*!
* @name Register NV_FSEC, field SEC[1:0] (RO)
*/
//@{
#define BP_NV_FSEC_SEC (0U) //!< Bit position for NV_FSEC_SEC.
#define BM_NV_FSEC_SEC (0x03U) //!< Bit mask for NV_FSEC_SEC.
#define BS_NV_FSEC_SEC (2U) //!< Bit field size in bits for NV_FSEC_SEC.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the NV_FSEC_SEC field.
#define BR_NV_FSEC_SEC (HW_NV_FSEC.B.SEC)
#endif
//@}
/*!
* @name Register NV_FSEC, field FSLACC[3:2] (RO)
*/
//@{
#define BP_NV_FSEC_FSLACC (2U) //!< Bit position for NV_FSEC_FSLACC.
#define BM_NV_FSEC_FSLACC (0x0CU) //!< Bit mask for NV_FSEC_FSLACC.
#define BS_NV_FSEC_FSLACC (2U) //!< Bit field size in bits for NV_FSEC_FSLACC.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the NV_FSEC_FSLACC field.
#define BR_NV_FSEC_FSLACC (HW_NV_FSEC.B.FSLACC)
#endif
//@}
/*!
* @name Register NV_FSEC, field MEEN[5:4] (RO)
*/
//@{
#define BP_NV_FSEC_MEEN (4U) //!< Bit position for NV_FSEC_MEEN.
#define BM_NV_FSEC_MEEN (0x30U) //!< Bit mask for NV_FSEC_MEEN.
#define BS_NV_FSEC_MEEN (2U) //!< Bit field size in bits for NV_FSEC_MEEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the NV_FSEC_MEEN field.
#define BR_NV_FSEC_MEEN (HW_NV_FSEC.B.MEEN)
#endif
//@}
/*!
* @name Register NV_FSEC, field KEYEN[7:6] (RO)
*/
//@{
#define BP_NV_FSEC_KEYEN (6U) //!< Bit position for NV_FSEC_KEYEN.
#define BM_NV_FSEC_KEYEN (0xC0U) //!< Bit mask for NV_FSEC_KEYEN.
#define BS_NV_FSEC_KEYEN (2U) //!< Bit field size in bits for NV_FSEC_KEYEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the NV_FSEC_KEYEN field.
#define BR_NV_FSEC_KEYEN (HW_NV_FSEC.B.KEYEN)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_NV_FOPT - Non-volatile Flash Option Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_NV_FOPT - Non-volatile Flash Option Register (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_fopt
{
uint8_t U;
struct _hw_nv_fopt_bitfields
{
uint8_t LPBOOT : 1; //!< [0]
uint8_t EZPORT_DIS : 1; //!< [1]
uint8_t RESERVED0 : 6; //!< [7:2]
} B;
} hw_nv_fopt_t;
#endif
/*!
* @name Constants and macros for entire NV_FOPT register
*/
//@{
#define HW_NV_FOPT_ADDR (REGS_NV_BASE + 0xDU)
#ifndef __LANGUAGE_ASM__
#define HW_NV_FOPT (*(__I hw_nv_fopt_t *) HW_NV_FOPT_ADDR)
#define HW_NV_FOPT_RD() (HW_NV_FOPT.U)
#endif
//@}
/*
* Constants & macros for individual NV_FOPT bitfields
*/
/*!
* @name Register NV_FOPT, field LPBOOT[0] (RO)
*/
//@{
#define BP_NV_FOPT_LPBOOT (0U) //!< Bit position for NV_FOPT_LPBOOT.
#define BM_NV_FOPT_LPBOOT (0x01U) //!< Bit mask for NV_FOPT_LPBOOT.
#define BS_NV_FOPT_LPBOOT (1U) //!< Bit field size in bits for NV_FOPT_LPBOOT.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the NV_FOPT_LPBOOT field.
#define BR_NV_FOPT_LPBOOT (BITBAND_ACCESS8(HW_NV_FOPT_ADDR, BP_NV_FOPT_LPBOOT))
#endif
//@}
/*!
* @name Register NV_FOPT, field EZPORT_DIS[1] (RO)
*/
//@{
#define BP_NV_FOPT_EZPORT_DIS (1U) //!< Bit position for NV_FOPT_EZPORT_DIS.
#define BM_NV_FOPT_EZPORT_DIS (0x02U) //!< Bit mask for NV_FOPT_EZPORT_DIS.
#define BS_NV_FOPT_EZPORT_DIS (1U) //!< Bit field size in bits for NV_FOPT_EZPORT_DIS.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the NV_FOPT_EZPORT_DIS field.
#define BR_NV_FOPT_EZPORT_DIS (BITBAND_ACCESS8(HW_NV_FOPT_ADDR, BP_NV_FOPT_EZPORT_DIS))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_NV_FEPROT - Non-volatile EERAM Protection Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_NV_FEPROT - Non-volatile EERAM Protection Register (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_feprot
{
uint8_t U;
struct _hw_nv_feprot_bitfields
{
uint8_t EPROT : 8; //!< [7:0]
} B;
} hw_nv_feprot_t;
#endif
/*!
* @name Constants and macros for entire NV_FEPROT register
*/
//@{
#define HW_NV_FEPROT_ADDR (REGS_NV_BASE + 0xEU)
#ifndef __LANGUAGE_ASM__
#define HW_NV_FEPROT (*(__I hw_nv_feprot_t *) HW_NV_FEPROT_ADDR)
#define HW_NV_FEPROT_RD() (HW_NV_FEPROT.U)
#endif
//@}
/*
* Constants & macros for individual NV_FEPROT bitfields
*/
/*!
* @name Register NV_FEPROT, field EPROT[7:0] (RO)
*/
//@{
#define BP_NV_FEPROT_EPROT (0U) //!< Bit position for NV_FEPROT_EPROT.
#define BM_NV_FEPROT_EPROT (0xFFU) //!< Bit mask for NV_FEPROT_EPROT.
#define BS_NV_FEPROT_EPROT (8U) //!< Bit field size in bits for NV_FEPROT_EPROT.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the NV_FEPROT_EPROT field.
#define BR_NV_FEPROT_EPROT (HW_NV_FEPROT.U)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_NV_FDPROT - Non-volatile D-Flash Protection Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_NV_FDPROT - Non-volatile D-Flash Protection Register (RO)
*
* Reset value: 0xFFU
*/
typedef union _hw_nv_fdprot
{
uint8_t U;
struct _hw_nv_fdprot_bitfields
{
uint8_t DPROT : 8; //!< [7:0] D-Flash Region Protect
} B;
} hw_nv_fdprot_t;
#endif
/*!
* @name Constants and macros for entire NV_FDPROT register
*/
//@{
#define HW_NV_FDPROT_ADDR (REGS_NV_BASE + 0xFU)
#ifndef __LANGUAGE_ASM__
#define HW_NV_FDPROT (*(__I hw_nv_fdprot_t *) HW_NV_FDPROT_ADDR)
#define HW_NV_FDPROT_RD() (HW_NV_FDPROT.U)
#endif
//@}
/*
* Constants & macros for individual NV_FDPROT bitfields
*/
/*!
* @name Register NV_FDPROT, field DPROT[7:0] (RO)
*/
//@{
#define BP_NV_FDPROT_DPROT (0U) //!< Bit position for NV_FDPROT_DPROT.
#define BM_NV_FDPROT_DPROT (0xFFU) //!< Bit mask for NV_FDPROT_DPROT.
#define BS_NV_FDPROT_DPROT (8U) //!< Bit field size in bits for NV_FDPROT_DPROT.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the NV_FDPROT_DPROT field.
#define BR_NV_FDPROT_DPROT (HW_NV_FDPROT.U)
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_nv_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All NV module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_nv
{
__I hw_nv_backkey3_t BACKKEY3; //!< [0x0] Backdoor Comparison Key 3.
__I hw_nv_backkey2_t BACKKEY2; //!< [0x1] Backdoor Comparison Key 2.
__I hw_nv_backkey1_t BACKKEY1; //!< [0x2] Backdoor Comparison Key 1.
__I hw_nv_backkey0_t BACKKEY0; //!< [0x3] Backdoor Comparison Key 0.
__I hw_nv_backkey7_t BACKKEY7; //!< [0x4] Backdoor Comparison Key 7.
__I hw_nv_backkey6_t BACKKEY6; //!< [0x5] Backdoor Comparison Key 6.
__I hw_nv_backkey5_t BACKKEY5; //!< [0x6] Backdoor Comparison Key 5.
__I hw_nv_backkey4_t BACKKEY4; //!< [0x7] Backdoor Comparison Key 4.
__I hw_nv_fprot3_t FPROT3; //!< [0x8] Non-volatile P-Flash Protection 1 - Low Register
__I hw_nv_fprot2_t FPROT2; //!< [0x9] Non-volatile P-Flash Protection 1 - High Register
__I hw_nv_fprot1_t FPROT1; //!< [0xA] Non-volatile P-Flash Protection 0 - Low Register
__I hw_nv_fprot0_t FPROT0; //!< [0xB] Non-volatile P-Flash Protection 0 - High Register
__I hw_nv_fsec_t FSEC; //!< [0xC] Non-volatile Flash Security Register
__I hw_nv_fopt_t FOPT; //!< [0xD] Non-volatile Flash Option Register
__I hw_nv_feprot_t FEPROT; //!< [0xE] Non-volatile EERAM Protection Register
__I hw_nv_fdprot_t FDPROT; //!< [0xF] Non-volatile D-Flash Protection Register
} hw_nv_t;
#pragma pack()
//! @brief Macro to access all NV registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_NV</code>.
#define HW_NV (*(hw_nv_t *) REGS_NV_BASE)
#endif
#endif // __HW_NV_REGISTERS_H__
// v22/130726/0.9
// EOF

302
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_osc.h Normal file
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@ -0,0 +1,302 @@
/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_OSC_REGISTERS_H__
#define __HW_OSC_REGISTERS_H__
#include "regs.h"
/*
* MK64F12 OSC
*
* Oscillator
*
* Registers defined in this header file:
* - HW_OSC_CR - OSC Control Register
*
* - hw_osc_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_OSC_BASE
#define HW_OSC_INSTANCE_COUNT (1U) //!< Number of instances of the OSC module.
#define HW_OSC0 (0U) //!< Instance number for OSC.
#define REGS_OSC0_BASE (0x40065000U) //!< Base address for OSC.
//! @brief Table of base addresses for OSC instances.
static const uint32_t __g_regs_OSC_base_addresses[] = {
REGS_OSC0_BASE,
};
//! @brief Get the base address of OSC by instance number.
//! @param x OSC instance number, from 0 through 0.
#define REGS_OSC_BASE(x) (__g_regs_OSC_base_addresses[(x)])
//! @brief Get the instance number given a base address.
//! @param b Base address for an instance of OSC.
#define REGS_OSC_INSTANCE(b) ((b) == REGS_OSC0_BASE ? HW_OSC0 : 0)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_OSC_CR - OSC Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_OSC_CR - OSC Control Register (RW)
*
* Reset value: 0x00U
*
* After OSC is enabled and starts generating the clocks, the configurations
* such as low power and frequency range, must not be changed.
*/
typedef union _hw_osc_cr
{
uint8_t U;
struct _hw_osc_cr_bitfields
{
uint8_t SC16P : 1; //!< [0] Oscillator 16 pF Capacitor Load Configure
uint8_t SC8P : 1; //!< [1] Oscillator 8 pF Capacitor Load Configure
uint8_t SC4P : 1; //!< [2] Oscillator 4 pF Capacitor Load Configure
uint8_t SC2P : 1; //!< [3] Oscillator 2 pF Capacitor Load Configure
uint8_t RESERVED0 : 1; //!< [4]
uint8_t EREFSTEN : 1; //!< [5] External Reference Stop Enable
uint8_t RESERVED1 : 1; //!< [6]
uint8_t ERCLKEN : 1; //!< [7] External Reference Enable
} B;
} hw_osc_cr_t;
#endif
/*!
* @name Constants and macros for entire OSC_CR register
*/
//@{
#define HW_OSC_CR_ADDR(x) (REGS_OSC_BASE(x) + 0x0U)
#ifndef __LANGUAGE_ASM__
#define HW_OSC_CR(x) (*(__IO hw_osc_cr_t *) HW_OSC_CR_ADDR(x))
#define HW_OSC_CR_RD(x) (HW_OSC_CR(x).U)
#define HW_OSC_CR_WR(x, v) (HW_OSC_CR(x).U = (v))
#define HW_OSC_CR_SET(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) | (v)))
#define HW_OSC_CR_CLR(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) & ~(v)))
#define HW_OSC_CR_TOG(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual OSC_CR bitfields
*/
/*!
* @name Register OSC_CR, field SC16P[0] (RW)
*
* Configures the oscillator load.
*
* Values:
* - 0 - Disable the selection.
* - 1 - Add 16 pF capacitor to the oscillator load.
*/
//@{
#define BP_OSC_CR_SC16P (0U) //!< Bit position for OSC_CR_SC16P.
#define BM_OSC_CR_SC16P (0x01U) //!< Bit mask for OSC_CR_SC16P.
#define BS_OSC_CR_SC16P (1U) //!< Bit field size in bits for OSC_CR_SC16P.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the OSC_CR_SC16P field.
#define BR_OSC_CR_SC16P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P))
#endif
//! @brief Format value for bitfield OSC_CR_SC16P.
#define BF_OSC_CR_SC16P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC16P), uint8_t) & BM_OSC_CR_SC16P)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SC16P field to a new value.
#define BW_OSC_CR_SC16P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P) = (v))
#endif
//@}
/*!
* @name Register OSC_CR, field SC8P[1] (RW)
*
* Configures the oscillator load.
*
* Values:
* - 0 - Disable the selection.
* - 1 - Add 8 pF capacitor to the oscillator load.
*/
//@{
#define BP_OSC_CR_SC8P (1U) //!< Bit position for OSC_CR_SC8P.
#define BM_OSC_CR_SC8P (0x02U) //!< Bit mask for OSC_CR_SC8P.
#define BS_OSC_CR_SC8P (1U) //!< Bit field size in bits for OSC_CR_SC8P.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the OSC_CR_SC8P field.
#define BR_OSC_CR_SC8P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P))
#endif
//! @brief Format value for bitfield OSC_CR_SC8P.
#define BF_OSC_CR_SC8P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC8P), uint8_t) & BM_OSC_CR_SC8P)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SC8P field to a new value.
#define BW_OSC_CR_SC8P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P) = (v))
#endif
//@}
/*!
* @name Register OSC_CR, field SC4P[2] (RW)
*
* Configures the oscillator load.
*
* Values:
* - 0 - Disable the selection.
* - 1 - Add 4 pF capacitor to the oscillator load.
*/
//@{
#define BP_OSC_CR_SC4P (2U) //!< Bit position for OSC_CR_SC4P.
#define BM_OSC_CR_SC4P (0x04U) //!< Bit mask for OSC_CR_SC4P.
#define BS_OSC_CR_SC4P (1U) //!< Bit field size in bits for OSC_CR_SC4P.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the OSC_CR_SC4P field.
#define BR_OSC_CR_SC4P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P))
#endif
//! @brief Format value for bitfield OSC_CR_SC4P.
#define BF_OSC_CR_SC4P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC4P), uint8_t) & BM_OSC_CR_SC4P)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SC4P field to a new value.
#define BW_OSC_CR_SC4P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P) = (v))
#endif
//@}
/*!
* @name Register OSC_CR, field SC2P[3] (RW)
*
* Configures the oscillator load.
*
* Values:
* - 0 - Disable the selection.
* - 1 - Add 2 pF capacitor to the oscillator load.
*/
//@{
#define BP_OSC_CR_SC2P (3U) //!< Bit position for OSC_CR_SC2P.
#define BM_OSC_CR_SC2P (0x08U) //!< Bit mask for OSC_CR_SC2P.
#define BS_OSC_CR_SC2P (1U) //!< Bit field size in bits for OSC_CR_SC2P.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the OSC_CR_SC2P field.
#define BR_OSC_CR_SC2P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P))
#endif
//! @brief Format value for bitfield OSC_CR_SC2P.
#define BF_OSC_CR_SC2P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC2P), uint8_t) & BM_OSC_CR_SC2P)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SC2P field to a new value.
#define BW_OSC_CR_SC2P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P) = (v))
#endif
//@}
/*!
* @name Register OSC_CR, field EREFSTEN[5] (RW)
*
* Controls whether or not the external reference clock (OSCERCLK) remains
* enabled when MCU enters Stop mode.
*
* Values:
* - 0 - External reference clock is disabled in Stop mode.
* - 1 - External reference clock stays enabled in Stop mode if ERCLKEN is set
* before entering Stop mode.
*/
//@{
#define BP_OSC_CR_EREFSTEN (5U) //!< Bit position for OSC_CR_EREFSTEN.
#define BM_OSC_CR_EREFSTEN (0x20U) //!< Bit mask for OSC_CR_EREFSTEN.
#define BS_OSC_CR_EREFSTEN (1U) //!< Bit field size in bits for OSC_CR_EREFSTEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the OSC_CR_EREFSTEN field.
#define BR_OSC_CR_EREFSTEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN))
#endif
//! @brief Format value for bitfield OSC_CR_EREFSTEN.
#define BF_OSC_CR_EREFSTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_EREFSTEN), uint8_t) & BM_OSC_CR_EREFSTEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the EREFSTEN field to a new value.
#define BW_OSC_CR_EREFSTEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN) = (v))
#endif
//@}
/*!
* @name Register OSC_CR, field ERCLKEN[7] (RW)
*
* Enables external reference clock (OSCERCLK).
*
* Values:
* - 0 - External reference clock is inactive.
* - 1 - External reference clock is enabled.
*/
//@{
#define BP_OSC_CR_ERCLKEN (7U) //!< Bit position for OSC_CR_ERCLKEN.
#define BM_OSC_CR_ERCLKEN (0x80U) //!< Bit mask for OSC_CR_ERCLKEN.
#define BS_OSC_CR_ERCLKEN (1U) //!< Bit field size in bits for OSC_CR_ERCLKEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the OSC_CR_ERCLKEN field.
#define BR_OSC_CR_ERCLKEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN))
#endif
//! @brief Format value for bitfield OSC_CR_ERCLKEN.
#define BF_OSC_CR_ERCLKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_ERCLKEN), uint8_t) & BM_OSC_CR_ERCLKEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ERCLKEN field to a new value.
#define BW_OSC_CR_ERCLKEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_osc_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All OSC module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_osc
{
__IO hw_osc_cr_t CR; //!< [0x0] OSC Control Register
} hw_osc_t;
#pragma pack()
//! @brief Macro to access all OSC registers.
//! @param x OSC instance number.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_OSC(0)</code>.
#define HW_OSC(x) (*(hw_osc_t *) REGS_OSC_BASE(x))
#endif
#endif // __HW_OSC_REGISTERS_H__
// v22/130726/0.9
// EOF

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_PIT_REGISTERS_H__
#define __HW_PIT_REGISTERS_H__
#include "regs.h"
/*
* MK64F12 PIT
*
* Periodic Interrupt Timer
*
* Registers defined in this header file:
* - HW_PIT_MCR - PIT Module Control Register
* - HW_PIT_LDVALn - Timer Load Value Register
* - HW_PIT_CVALn - Current Timer Value Register
* - HW_PIT_TCTRLn - Timer Control Register
* - HW_PIT_TFLGn - Timer Flag Register
*
* - hw_pit_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_PIT_BASE
#define HW_PIT_INSTANCE_COUNT (1U) //!< Number of instances of the PIT module.
#define REGS_PIT_BASE (0x40037000U) //!< Base address for PIT.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PIT_MCR - PIT Module Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PIT_MCR - PIT Module Control Register (RW)
*
* Reset value: 0x00000006U
*
* This register enables or disables the PIT timer clocks and controls the
* timers when the PIT enters the Debug mode.
*/
typedef union _hw_pit_mcr
{
uint32_t U;
struct _hw_pit_mcr_bitfields
{
uint32_t FRZ : 1; //!< [0] Freeze
uint32_t MDIS : 1; //!< [1] Module Disable - (PIT section)
uint32_t RESERVED0 : 30; //!< [31:2]
} B;
} hw_pit_mcr_t;
#endif
/*!
* @name Constants and macros for entire PIT_MCR register
*/
//@{
#define HW_PIT_MCR_ADDR (REGS_PIT_BASE + 0x0U)
#ifndef __LANGUAGE_ASM__
#define HW_PIT_MCR (*(__IO hw_pit_mcr_t *) HW_PIT_MCR_ADDR)
#define HW_PIT_MCR_RD() (HW_PIT_MCR.U)
#define HW_PIT_MCR_WR(v) (HW_PIT_MCR.U = (v))
#define HW_PIT_MCR_SET(v) (HW_PIT_MCR_WR(HW_PIT_MCR_RD() | (v)))
#define HW_PIT_MCR_CLR(v) (HW_PIT_MCR_WR(HW_PIT_MCR_RD() & ~(v)))
#define HW_PIT_MCR_TOG(v) (HW_PIT_MCR_WR(HW_PIT_MCR_RD() ^ (v)))
#endif
//@}
/*
* Constants & macros for individual PIT_MCR bitfields
*/
/*!
* @name Register PIT_MCR, field FRZ[0] (RW)
*
* Allows the timers to be stopped when the device enters the Debug mode.
*
* Values:
* - 0 - Timers continue to run in Debug mode.
* - 1 - Timers are stopped in Debug mode.
*/
//@{
#define BP_PIT_MCR_FRZ (0U) //!< Bit position for PIT_MCR_FRZ.
#define BM_PIT_MCR_FRZ (0x00000001U) //!< Bit mask for PIT_MCR_FRZ.
#define BS_PIT_MCR_FRZ (1U) //!< Bit field size in bits for PIT_MCR_FRZ.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PIT_MCR_FRZ field.
#define BR_PIT_MCR_FRZ (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_FRZ))
#endif
//! @brief Format value for bitfield PIT_MCR_FRZ.
#define BF_PIT_MCR_FRZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_MCR_FRZ), uint32_t) & BM_PIT_MCR_FRZ)
#ifndef __LANGUAGE_ASM__
//! @brief Set the FRZ field to a new value.
#define BW_PIT_MCR_FRZ(v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_FRZ) = (v))
#endif
//@}
/*!
* @name Register PIT_MCR, field MDIS[1] (RW)
*
* Disables the standard timers. This field must be enabled before any other
* setup is done.
*
* Values:
* - 0 - Clock for standard PIT timers is enabled.
* - 1 - Clock for standard PIT timers is disabled.
*/
//@{
#define BP_PIT_MCR_MDIS (1U) //!< Bit position for PIT_MCR_MDIS.
#define BM_PIT_MCR_MDIS (0x00000002U) //!< Bit mask for PIT_MCR_MDIS.
#define BS_PIT_MCR_MDIS (1U) //!< Bit field size in bits for PIT_MCR_MDIS.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PIT_MCR_MDIS field.
#define BR_PIT_MCR_MDIS (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_MDIS))
#endif
//! @brief Format value for bitfield PIT_MCR_MDIS.
#define BF_PIT_MCR_MDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_MCR_MDIS), uint32_t) & BM_PIT_MCR_MDIS)
#ifndef __LANGUAGE_ASM__
//! @brief Set the MDIS field to a new value.
#define BW_PIT_MCR_MDIS(v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_MDIS) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PIT_LDVALn - Timer Load Value Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PIT_LDVALn - Timer Load Value Register (RW)
*
* Reset value: 0x00000000U
*
* These registers select the timeout period for the timer interrupts.
*/
typedef union _hw_pit_ldvaln
{
uint32_t U;
struct _hw_pit_ldvaln_bitfields
{
uint32_t TSV : 32; //!< [31:0] Timer Start Value
} B;
} hw_pit_ldvaln_t;
#endif
/*!
* @name Constants and macros for entire PIT_LDVALn register
*/
//@{
#define HW_PIT_LDVALn_COUNT (4U)
#define HW_PIT_LDVALn_ADDR(n) (REGS_PIT_BASE + 0x100U + (0x10U * n))
#ifndef __LANGUAGE_ASM__
#define HW_PIT_LDVALn(n) (*(__IO hw_pit_ldvaln_t *) HW_PIT_LDVALn_ADDR(n))
#define HW_PIT_LDVALn_RD(n) (HW_PIT_LDVALn(n).U)
#define HW_PIT_LDVALn_WR(n, v) (HW_PIT_LDVALn(n).U = (v))
#define HW_PIT_LDVALn_SET(n, v) (HW_PIT_LDVALn_WR(n, HW_PIT_LDVALn_RD(n) | (v)))
#define HW_PIT_LDVALn_CLR(n, v) (HW_PIT_LDVALn_WR(n, HW_PIT_LDVALn_RD(n) & ~(v)))
#define HW_PIT_LDVALn_TOG(n, v) (HW_PIT_LDVALn_WR(n, HW_PIT_LDVALn_RD(n) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual PIT_LDVALn bitfields
*/
/*!
* @name Register PIT_LDVALn, field TSV[31:0] (RW)
*
* Sets the timer start value. The timer will count down until it reaches 0,
* then it will generate an interrupt and load this register value again. Writing a
* new value to this register will not restart the timer; instead the value will
* be loaded after the timer expires. To abort the current cycle and start a
* timer period with the new value, the timer must be disabled and enabled again.
*/
//@{
#define BP_PIT_LDVALn_TSV (0U) //!< Bit position for PIT_LDVALn_TSV.
#define BM_PIT_LDVALn_TSV (0xFFFFFFFFU) //!< Bit mask for PIT_LDVALn_TSV.
#define BS_PIT_LDVALn_TSV (32U) //!< Bit field size in bits for PIT_LDVALn_TSV.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PIT_LDVALn_TSV field.
#define BR_PIT_LDVALn_TSV(n) (HW_PIT_LDVALn(n).U)
#endif
//! @brief Format value for bitfield PIT_LDVALn_TSV.
#define BF_PIT_LDVALn_TSV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_LDVALn_TSV), uint32_t) & BM_PIT_LDVALn_TSV)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TSV field to a new value.
#define BW_PIT_LDVALn_TSV(n, v) (HW_PIT_LDVALn_WR(n, v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PIT_CVALn - Current Timer Value Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PIT_CVALn - Current Timer Value Register (RO)
*
* Reset value: 0x00000000U
*
* These registers indicate the current timer position.
*/
typedef union _hw_pit_cvaln
{
uint32_t U;
struct _hw_pit_cvaln_bitfields
{
uint32_t TVL : 32; //!< [31:0] Current Timer Value
} B;
} hw_pit_cvaln_t;
#endif
/*!
* @name Constants and macros for entire PIT_CVALn register
*/
//@{
#define HW_PIT_CVALn_COUNT (4U)
#define HW_PIT_CVALn_ADDR(n) (REGS_PIT_BASE + 0x104U + (0x10U * n))
#ifndef __LANGUAGE_ASM__
#define HW_PIT_CVALn(n) (*(__I hw_pit_cvaln_t *) HW_PIT_CVALn_ADDR(n))
#define HW_PIT_CVALn_RD(n) (HW_PIT_CVALn(n).U)
#endif
//@}
/*
* Constants & macros for individual PIT_CVALn bitfields
*/
/*!
* @name Register PIT_CVALn, field TVL[31:0] (RO)
*
* Represents the current timer value, if the timer is enabled. If the timer is
* disabled, do not use this field as its value is unreliable. The timer uses a
* downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is set.
*/
//@{
#define BP_PIT_CVALn_TVL (0U) //!< Bit position for PIT_CVALn_TVL.
#define BM_PIT_CVALn_TVL (0xFFFFFFFFU) //!< Bit mask for PIT_CVALn_TVL.
#define BS_PIT_CVALn_TVL (32U) //!< Bit field size in bits for PIT_CVALn_TVL.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PIT_CVALn_TVL field.
#define BR_PIT_CVALn_TVL(n) (HW_PIT_CVALn(n).U)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PIT_TCTRLn - Timer Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PIT_TCTRLn - Timer Control Register (RW)
*
* Reset value: 0x00000000U
*
* These registers contain the control bits for each timer.
*/
typedef union _hw_pit_tctrln
{
uint32_t U;
struct _hw_pit_tctrln_bitfields
{
uint32_t TEN : 1; //!< [0] Timer Enable
uint32_t TIE : 1; //!< [1] Timer Interrupt Enable
uint32_t CHN : 1; //!< [2] Chain Mode
uint32_t RESERVED0 : 29; //!< [31:3]
} B;
} hw_pit_tctrln_t;
#endif
/*!
* @name Constants and macros for entire PIT_TCTRLn register
*/
//@{
#define HW_PIT_TCTRLn_COUNT (4U)
#define HW_PIT_TCTRLn_ADDR(n) (REGS_PIT_BASE + 0x108U + (0x10U * n))
#ifndef __LANGUAGE_ASM__
#define HW_PIT_TCTRLn(n) (*(__IO hw_pit_tctrln_t *) HW_PIT_TCTRLn_ADDR(n))
#define HW_PIT_TCTRLn_RD(n) (HW_PIT_TCTRLn(n).U)
#define HW_PIT_TCTRLn_WR(n, v) (HW_PIT_TCTRLn(n).U = (v))
#define HW_PIT_TCTRLn_SET(n, v) (HW_PIT_TCTRLn_WR(n, HW_PIT_TCTRLn_RD(n) | (v)))
#define HW_PIT_TCTRLn_CLR(n, v) (HW_PIT_TCTRLn_WR(n, HW_PIT_TCTRLn_RD(n) & ~(v)))
#define HW_PIT_TCTRLn_TOG(n, v) (HW_PIT_TCTRLn_WR(n, HW_PIT_TCTRLn_RD(n) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual PIT_TCTRLn bitfields
*/
/*!
* @name Register PIT_TCTRLn, field TEN[0] (RW)
*
* Enables or disables the timer.
*
* Values:
* - 0 - Timer n is disabled.
* - 1 - Timer n is enabled.
*/
//@{
#define BP_PIT_TCTRLn_TEN (0U) //!< Bit position for PIT_TCTRLn_TEN.
#define BM_PIT_TCTRLn_TEN (0x00000001U) //!< Bit mask for PIT_TCTRLn_TEN.
#define BS_PIT_TCTRLn_TEN (1U) //!< Bit field size in bits for PIT_TCTRLn_TEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PIT_TCTRLn_TEN field.
#define BR_PIT_TCTRLn_TEN(n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TEN))
#endif
//! @brief Format value for bitfield PIT_TCTRLn_TEN.
#define BF_PIT_TCTRLn_TEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TCTRLn_TEN), uint32_t) & BM_PIT_TCTRLn_TEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TEN field to a new value.
#define BW_PIT_TCTRLn_TEN(n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TEN) = (v))
#endif
//@}
/*!
* @name Register PIT_TCTRLn, field TIE[1] (RW)
*
* When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt
* will immediately cause an interrupt event. To avoid this, the associated
* TFLGn[TIF] must be cleared first.
*
* Values:
* - 0 - Interrupt requests from Timer n are disabled.
* - 1 - Interrupt will be requested whenever TIF is set.
*/
//@{
#define BP_PIT_TCTRLn_TIE (1U) //!< Bit position for PIT_TCTRLn_TIE.
#define BM_PIT_TCTRLn_TIE (0x00000002U) //!< Bit mask for PIT_TCTRLn_TIE.
#define BS_PIT_TCTRLn_TIE (1U) //!< Bit field size in bits for PIT_TCTRLn_TIE.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PIT_TCTRLn_TIE field.
#define BR_PIT_TCTRLn_TIE(n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TIE))
#endif
//! @brief Format value for bitfield PIT_TCTRLn_TIE.
#define BF_PIT_TCTRLn_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TCTRLn_TIE), uint32_t) & BM_PIT_TCTRLn_TIE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TIE field to a new value.
#define BW_PIT_TCTRLn_TIE(n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TIE) = (v))
#endif
//@}
/*!
* @name Register PIT_TCTRLn, field CHN[2] (RW)
*
* When activated, Timer n-1 needs to expire before timer n can decrement by 1.
* Timer 0 cannot be chained.
*
* Values:
* - 0 - Timer is not chained.
* - 1 - Timer is chained to previous timer. For example, for Channel 2, if this
* field is set, Timer 2 is chained to Timer 1.
*/
//@{
#define BP_PIT_TCTRLn_CHN (2U) //!< Bit position for PIT_TCTRLn_CHN.
#define BM_PIT_TCTRLn_CHN (0x00000004U) //!< Bit mask for PIT_TCTRLn_CHN.
#define BS_PIT_TCTRLn_CHN (1U) //!< Bit field size in bits for PIT_TCTRLn_CHN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PIT_TCTRLn_CHN field.
#define BR_PIT_TCTRLn_CHN(n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_CHN))
#endif
//! @brief Format value for bitfield PIT_TCTRLn_CHN.
#define BF_PIT_TCTRLn_CHN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TCTRLn_CHN), uint32_t) & BM_PIT_TCTRLn_CHN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the CHN field to a new value.
#define BW_PIT_TCTRLn_CHN(n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_CHN) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PIT_TFLGn - Timer Flag Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PIT_TFLGn - Timer Flag Register (RW)
*
* Reset value: 0x00000000U
*
* These registers hold the PIT interrupt flags.
*/
typedef union _hw_pit_tflgn
{
uint32_t U;
struct _hw_pit_tflgn_bitfields
{
uint32_t TIF : 1; //!< [0] Timer Interrupt Flag
uint32_t RESERVED0 : 31; //!< [31:1]
} B;
} hw_pit_tflgn_t;
#endif
/*!
* @name Constants and macros for entire PIT_TFLGn register
*/
//@{
#define HW_PIT_TFLGn_COUNT (4U)
#define HW_PIT_TFLGn_ADDR(n) (REGS_PIT_BASE + 0x10CU + (0x10U * n))
#ifndef __LANGUAGE_ASM__
#define HW_PIT_TFLGn(n) (*(__IO hw_pit_tflgn_t *) HW_PIT_TFLGn_ADDR(n))
#define HW_PIT_TFLGn_RD(n) (HW_PIT_TFLGn(n).U)
#define HW_PIT_TFLGn_WR(n, v) (HW_PIT_TFLGn(n).U = (v))
#define HW_PIT_TFLGn_SET(n, v) (HW_PIT_TFLGn_WR(n, HW_PIT_TFLGn_RD(n) | (v)))
#define HW_PIT_TFLGn_CLR(n, v) (HW_PIT_TFLGn_WR(n, HW_PIT_TFLGn_RD(n) & ~(v)))
#define HW_PIT_TFLGn_TOG(n, v) (HW_PIT_TFLGn_WR(n, HW_PIT_TFLGn_RD(n) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual PIT_TFLGn bitfields
*/
/*!
* @name Register PIT_TFLGn, field TIF[0] (W1C)
*
* Sets to 1 at the end of the timer period. Writing 1 to this flag clears it.
* Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an
* interrupt request.
*
* Values:
* - 0 - Timeout has not yet occurred.
* - 1 - Timeout has occurred.
*/
//@{
#define BP_PIT_TFLGn_TIF (0U) //!< Bit position for PIT_TFLGn_TIF.
#define BM_PIT_TFLGn_TIF (0x00000001U) //!< Bit mask for PIT_TFLGn_TIF.
#define BS_PIT_TFLGn_TIF (1U) //!< Bit field size in bits for PIT_TFLGn_TIF.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PIT_TFLGn_TIF field.
#define BR_PIT_TFLGn_TIF(n) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(n), BP_PIT_TFLGn_TIF))
#endif
//! @brief Format value for bitfield PIT_TFLGn_TIF.
#define BF_PIT_TFLGn_TIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TFLGn_TIF), uint32_t) & BM_PIT_TFLGn_TIF)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TIF field to a new value.
#define BW_PIT_TFLGn_TIF(n, v) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(n), BP_PIT_TFLGn_TIF) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_pit_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All PIT module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_pit
{
__IO hw_pit_mcr_t MCR; //!< [0x0] PIT Module Control Register
uint8_t _reserved0[252];
struct {
__IO hw_pit_ldvaln_t LDVALn; //!< [0x100] Timer Load Value Register
__I hw_pit_cvaln_t CVALn; //!< [0x104] Current Timer Value Register
__IO hw_pit_tctrln_t TCTRLn; //!< [0x108] Timer Control Register
__IO hw_pit_tflgn_t TFLGn; //!< [0x10C] Timer Flag Register
} CHANNEL[4];
} hw_pit_t;
#pragma pack()
//! @brief Macro to access all PIT registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_PIT</code>.
#define HW_PIT (*(hw_pit_t *) REGS_PIT_BASE)
#endif
#endif // __HW_PIT_REGISTERS_H__
// v22/130726/0.9
// EOF

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_PMC_REGISTERS_H__
#define __HW_PMC_REGISTERS_H__
#include "regs.h"
/*
* MK64F12 PMC
*
* Power Management Controller
*
* Registers defined in this header file:
* - HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
* - HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
* - HW_PMC_REGSC - Regulator Status And Control register
*
* - hw_pmc_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_PMC_BASE
#define HW_PMC_INSTANCE_COUNT (1U) //!< Number of instances of the PMC module.
#define REGS_PMC_BASE (0x4007D000U) //!< Base address for PMC.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
*
* Reset value: 0x10U
*
* This register contains status and control bits to support the low voltage
* detect function. This register should be written during the reset initialization
* program to set the desired controls even if the desired settings are the same
* as the reset settings. While the device is in the very low power or low
* leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
* systems that must have LVD always on, configure the Power Mode Protection
* (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
* low leakage modes from being enabled. See the device's data sheet for the
* exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
* register's other bits are reset on Chip Reset Not VLLS. For more information
* about these reset types, refer to the Reset section details.
*/
typedef union _hw_pmc_lvdsc1
{
uint8_t U;
struct _hw_pmc_lvdsc1_bitfields
{
uint8_t LVDV : 2; //!< [1:0] Low-Voltage Detect Voltage Select
uint8_t RESERVED0 : 2; //!< [3:2]
uint8_t LVDRE : 1; //!< [4] Low-Voltage Detect Reset Enable
uint8_t LVDIE : 1; //!< [5] Low-Voltage Detect Interrupt Enable
uint8_t LVDACK : 1; //!< [6] Low-Voltage Detect Acknowledge
uint8_t LVDF : 1; //!< [7] Low-Voltage Detect Flag
} B;
} hw_pmc_lvdsc1_t;
#endif
/*!
* @name Constants and macros for entire PMC_LVDSC1 register
*/
//@{
#define HW_PMC_LVDSC1_ADDR (REGS_PMC_BASE + 0x0U)
#ifndef __LANGUAGE_ASM__
#define HW_PMC_LVDSC1 (*(__IO hw_pmc_lvdsc1_t *) HW_PMC_LVDSC1_ADDR)
#define HW_PMC_LVDSC1_RD() (HW_PMC_LVDSC1.U)
#define HW_PMC_LVDSC1_WR(v) (HW_PMC_LVDSC1.U = (v))
#define HW_PMC_LVDSC1_SET(v) (HW_PMC_LVDSC1_WR(HW_PMC_LVDSC1_RD() | (v)))
#define HW_PMC_LVDSC1_CLR(v) (HW_PMC_LVDSC1_WR(HW_PMC_LVDSC1_RD() & ~(v)))
#define HW_PMC_LVDSC1_TOG(v) (HW_PMC_LVDSC1_WR(HW_PMC_LVDSC1_RD() ^ (v)))
#endif
//@}
/*
* Constants & macros for individual PMC_LVDSC1 bitfields
*/
/*!
* @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
*
* Selects the LVD trip point voltage (V LVD ).
*
* Values:
* - 00 - Low trip point selected (V LVD = V LVDL )
* - 01 - High trip point selected (V LVD = V LVDH )
* - 10 - Reserved
* - 11 - Reserved
*/
//@{
#define BP_PMC_LVDSC1_LVDV (0U) //!< Bit position for PMC_LVDSC1_LVDV.
#define BM_PMC_LVDSC1_LVDV (0x03U) //!< Bit mask for PMC_LVDSC1_LVDV.
#define BS_PMC_LVDSC1_LVDV (2U) //!< Bit field size in bits for PMC_LVDSC1_LVDV.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PMC_LVDSC1_LVDV field.
#define BR_PMC_LVDSC1_LVDV (HW_PMC_LVDSC1.B.LVDV)
#endif
//! @brief Format value for bitfield PMC_LVDSC1_LVDV.
#define BF_PMC_LVDSC1_LVDV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC1_LVDV), uint8_t) & BM_PMC_LVDSC1_LVDV)
#ifndef __LANGUAGE_ASM__
//! @brief Set the LVDV field to a new value.
#define BW_PMC_LVDSC1_LVDV(v) (HW_PMC_LVDSC1_WR((HW_PMC_LVDSC1_RD() & ~BM_PMC_LVDSC1_LVDV) | BF_PMC_LVDSC1_LVDV(v)))
#endif
//@}
/*!
* @name Register PMC_LVDSC1, field LVDRE[4] (RW)
*
* This write-once bit enables LVDF events to generate a hardware reset.
* Additional writes are ignored.
*
* Values:
* - 0 - LVDF does not generate hardware resets
* - 1 - Force an MCU reset when LVDF = 1
*/
//@{
#define BP_PMC_LVDSC1_LVDRE (4U) //!< Bit position for PMC_LVDSC1_LVDRE.
#define BM_PMC_LVDSC1_LVDRE (0x10U) //!< Bit mask for PMC_LVDSC1_LVDRE.
#define BS_PMC_LVDSC1_LVDRE (1U) //!< Bit field size in bits for PMC_LVDSC1_LVDRE.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PMC_LVDSC1_LVDRE field.
#define BR_PMC_LVDSC1_LVDRE (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDRE))
#endif
//! @brief Format value for bitfield PMC_LVDSC1_LVDRE.
#define BF_PMC_LVDSC1_LVDRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC1_LVDRE), uint8_t) & BM_PMC_LVDSC1_LVDRE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the LVDRE field to a new value.
#define BW_PMC_LVDSC1_LVDRE(v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDRE) = (v))
#endif
//@}
/*!
* @name Register PMC_LVDSC1, field LVDIE[5] (RW)
*
* Enables hardware interrupt requests for LVDF.
*
* Values:
* - 0 - Hardware interrupt disabled (use polling)
* - 1 - Request a hardware interrupt when LVDF = 1
*/
//@{
#define BP_PMC_LVDSC1_LVDIE (5U) //!< Bit position for PMC_LVDSC1_LVDIE.
#define BM_PMC_LVDSC1_LVDIE (0x20U) //!< Bit mask for PMC_LVDSC1_LVDIE.
#define BS_PMC_LVDSC1_LVDIE (1U) //!< Bit field size in bits for PMC_LVDSC1_LVDIE.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PMC_LVDSC1_LVDIE field.
#define BR_PMC_LVDSC1_LVDIE (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDIE))
#endif
//! @brief Format value for bitfield PMC_LVDSC1_LVDIE.
#define BF_PMC_LVDSC1_LVDIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC1_LVDIE), uint8_t) & BM_PMC_LVDSC1_LVDIE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the LVDIE field to a new value.
#define BW_PMC_LVDSC1_LVDIE(v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDIE) = (v))
#endif
//@}
/*!
* @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
*
* This write-only field is used to acknowledge low voltage detection errors.
* Write 1 to clear LVDF. Reads always return 0.
*/
//@{
#define BP_PMC_LVDSC1_LVDACK (6U) //!< Bit position for PMC_LVDSC1_LVDACK.
#define BM_PMC_LVDSC1_LVDACK (0x40U) //!< Bit mask for PMC_LVDSC1_LVDACK.
#define BS_PMC_LVDSC1_LVDACK (1U) //!< Bit field size in bits for PMC_LVDSC1_LVDACK.
//! @brief Format value for bitfield PMC_LVDSC1_LVDACK.
#define BF_PMC_LVDSC1_LVDACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC1_LVDACK), uint8_t) & BM_PMC_LVDSC1_LVDACK)
#ifndef __LANGUAGE_ASM__
//! @brief Set the LVDACK field to a new value.
#define BW_PMC_LVDSC1_LVDACK(v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDACK) = (v))
#endif
//@}
/*!
* @name Register PMC_LVDSC1, field LVDF[7] (RO)
*
* This read-only status field indicates a low-voltage detect event.
*
* Values:
* - 0 - Low-voltage event not detected
* - 1 - Low-voltage event detected
*/
//@{
#define BP_PMC_LVDSC1_LVDF (7U) //!< Bit position for PMC_LVDSC1_LVDF.
#define BM_PMC_LVDSC1_LVDF (0x80U) //!< Bit mask for PMC_LVDSC1_LVDF.
#define BS_PMC_LVDSC1_LVDF (1U) //!< Bit field size in bits for PMC_LVDSC1_LVDF.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PMC_LVDSC1_LVDF field.
#define BR_PMC_LVDSC1_LVDF (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDF))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
*
* Reset value: 0x00U
*
* This register contains status and control bits to support the low voltage
* warning function. While the device is in the very low power or low leakage modes,
* the LVD system is disabled regardless of LVDSC2 settings. See the device's
* data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
* and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
* register are reset on Chip Reset Not VLLS. For more information about these
* reset types, refer to the Reset section details.
*/
typedef union _hw_pmc_lvdsc2
{
uint8_t U;
struct _hw_pmc_lvdsc2_bitfields
{
uint8_t LVWV : 2; //!< [1:0] Low-Voltage Warning Voltage Select
uint8_t RESERVED0 : 3; //!< [4:2]
uint8_t LVWIE : 1; //!< [5] Low-Voltage Warning Interrupt Enable
uint8_t LVWACK : 1; //!< [6] Low-Voltage Warning Acknowledge
uint8_t LVWF : 1; //!< [7] Low-Voltage Warning Flag
} B;
} hw_pmc_lvdsc2_t;
#endif
/*!
* @name Constants and macros for entire PMC_LVDSC2 register
*/
//@{
#define HW_PMC_LVDSC2_ADDR (REGS_PMC_BASE + 0x1U)
#ifndef __LANGUAGE_ASM__
#define HW_PMC_LVDSC2 (*(__IO hw_pmc_lvdsc2_t *) HW_PMC_LVDSC2_ADDR)
#define HW_PMC_LVDSC2_RD() (HW_PMC_LVDSC2.U)
#define HW_PMC_LVDSC2_WR(v) (HW_PMC_LVDSC2.U = (v))
#define HW_PMC_LVDSC2_SET(v) (HW_PMC_LVDSC2_WR(HW_PMC_LVDSC2_RD() | (v)))
#define HW_PMC_LVDSC2_CLR(v) (HW_PMC_LVDSC2_WR(HW_PMC_LVDSC2_RD() & ~(v)))
#define HW_PMC_LVDSC2_TOG(v) (HW_PMC_LVDSC2_WR(HW_PMC_LVDSC2_RD() ^ (v)))
#endif
//@}
/*
* Constants & macros for individual PMC_LVDSC2 bitfields
*/
/*!
* @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
*
* Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
* depends on LVDSC1[LVDV].
*
* Values:
* - 00 - Low trip point selected (VLVW = VLVW1)
* - 01 - Mid 1 trip point selected (VLVW = VLVW2)
* - 10 - Mid 2 trip point selected (VLVW = VLVW3)
* - 11 - High trip point selected (VLVW = VLVW4)
*/
//@{
#define BP_PMC_LVDSC2_LVWV (0U) //!< Bit position for PMC_LVDSC2_LVWV.
#define BM_PMC_LVDSC2_LVWV (0x03U) //!< Bit mask for PMC_LVDSC2_LVWV.
#define BS_PMC_LVDSC2_LVWV (2U) //!< Bit field size in bits for PMC_LVDSC2_LVWV.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PMC_LVDSC2_LVWV field.
#define BR_PMC_LVDSC2_LVWV (HW_PMC_LVDSC2.B.LVWV)
#endif
//! @brief Format value for bitfield PMC_LVDSC2_LVWV.
#define BF_PMC_LVDSC2_LVWV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC2_LVWV), uint8_t) & BM_PMC_LVDSC2_LVWV)
#ifndef __LANGUAGE_ASM__
//! @brief Set the LVWV field to a new value.
#define BW_PMC_LVDSC2_LVWV(v) (HW_PMC_LVDSC2_WR((HW_PMC_LVDSC2_RD() & ~BM_PMC_LVDSC2_LVWV) | BF_PMC_LVDSC2_LVWV(v)))
#endif
//@}
/*!
* @name Register PMC_LVDSC2, field LVWIE[5] (RW)
*
* Enables hardware interrupt requests for LVWF.
*
* Values:
* - 0 - Hardware interrupt disabled (use polling)
* - 1 - Request a hardware interrupt when LVWF = 1
*/
//@{
#define BP_PMC_LVDSC2_LVWIE (5U) //!< Bit position for PMC_LVDSC2_LVWIE.
#define BM_PMC_LVDSC2_LVWIE (0x20U) //!< Bit mask for PMC_LVDSC2_LVWIE.
#define BS_PMC_LVDSC2_LVWIE (1U) //!< Bit field size in bits for PMC_LVDSC2_LVWIE.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PMC_LVDSC2_LVWIE field.
#define BR_PMC_LVDSC2_LVWIE (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR, BP_PMC_LVDSC2_LVWIE))
#endif
//! @brief Format value for bitfield PMC_LVDSC2_LVWIE.
#define BF_PMC_LVDSC2_LVWIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC2_LVWIE), uint8_t) & BM_PMC_LVDSC2_LVWIE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the LVWIE field to a new value.
#define BW_PMC_LVDSC2_LVWIE(v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR, BP_PMC_LVDSC2_LVWIE) = (v))
#endif
//@}
/*!
* @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
*
* This write-only field is used to acknowledge low voltage warning errors.
* Write 1 to clear LVWF. Reads always return 0.
*/
//@{
#define BP_PMC_LVDSC2_LVWACK (6U) //!< Bit position for PMC_LVDSC2_LVWACK.
#define BM_PMC_LVDSC2_LVWACK (0x40U) //!< Bit mask for PMC_LVDSC2_LVWACK.
#define BS_PMC_LVDSC2_LVWACK (1U) //!< Bit field size in bits for PMC_LVDSC2_LVWACK.
//! @brief Format value for bitfield PMC_LVDSC2_LVWACK.
#define BF_PMC_LVDSC2_LVWACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC2_LVWACK), uint8_t) & BM_PMC_LVDSC2_LVWACK)
#ifndef __LANGUAGE_ASM__
//! @brief Set the LVWACK field to a new value.
#define BW_PMC_LVDSC2_LVWACK(v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR, BP_PMC_LVDSC2_LVWACK) = (v))
#endif
//@}
/*!
* @name Register PMC_LVDSC2, field LVWF[7] (RO)
*
* This read-only status field indicates a low-voltage warning event. LVWF is
* set when VSupply transitions below the trip point, or after reset and VSupply is
* already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
* interrupt function, before enabling LVWIE, LVWF must be cleared by writing
* LVWACK first.
*
* Values:
* - 0 - Low-voltage warning event not detected
* - 1 - Low-voltage warning event detected
*/
//@{
#define BP_PMC_LVDSC2_LVWF (7U) //!< Bit position for PMC_LVDSC2_LVWF.
#define BM_PMC_LVDSC2_LVWF (0x80U) //!< Bit mask for PMC_LVDSC2_LVWF.
#define BS_PMC_LVDSC2_LVWF (1U) //!< Bit field size in bits for PMC_LVDSC2_LVWF.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PMC_LVDSC2_LVWF field.
#define BR_PMC_LVDSC2_LVWF (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR, BP_PMC_LVDSC2_LVWF))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PMC_REGSC - Regulator Status And Control register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PMC_REGSC - Regulator Status And Control register (RW)
*
* Reset value: 0x04U
*
* The PMC contains an internal voltage regulator. The voltage regulator design
* uses a bandgap reference that is also available through a buffer as input to
* certain internal peripherals, such as the CMP and ADC. The internal regulator
* provides a status bit (REGONS) indicating the regulator is in run regulation.
* This register is reset on Chip Reset Not VLLS and by reset types that trigger
* Chip Reset not VLLS. See the Reset section details for more information.
*/
typedef union _hw_pmc_regsc
{
uint8_t U;
struct _hw_pmc_regsc_bitfields
{
uint8_t BGBE : 1; //!< [0] Bandgap Buffer Enable
uint8_t RESERVED0 : 1; //!< [1]
uint8_t REGONS : 1; //!< [2] Regulator In Run Regulation Status
uint8_t ACKISO : 1; //!< [3] Acknowledge Isolation
uint8_t BGEN : 1; //!< [4] Bandgap Enable In VLPx Operation
uint8_t RESERVED1 : 3; //!< [7:5]
} B;
} hw_pmc_regsc_t;
#endif
/*!
* @name Constants and macros for entire PMC_REGSC register
*/
//@{
#define HW_PMC_REGSC_ADDR (REGS_PMC_BASE + 0x2U)
#ifndef __LANGUAGE_ASM__
#define HW_PMC_REGSC (*(__IO hw_pmc_regsc_t *) HW_PMC_REGSC_ADDR)
#define HW_PMC_REGSC_RD() (HW_PMC_REGSC.U)
#define HW_PMC_REGSC_WR(v) (HW_PMC_REGSC.U = (v))
#define HW_PMC_REGSC_SET(v) (HW_PMC_REGSC_WR(HW_PMC_REGSC_RD() | (v)))
#define HW_PMC_REGSC_CLR(v) (HW_PMC_REGSC_WR(HW_PMC_REGSC_RD() & ~(v)))
#define HW_PMC_REGSC_TOG(v) (HW_PMC_REGSC_WR(HW_PMC_REGSC_RD() ^ (v)))
#endif
//@}
/*
* Constants & macros for individual PMC_REGSC bitfields
*/
/*!
* @name Register PMC_REGSC, field BGBE[0] (RW)
*
* Enables the bandgap buffer.
*
* Values:
* - 0 - Bandgap buffer not enabled
* - 1 - Bandgap buffer enabled
*/
//@{
#define BP_PMC_REGSC_BGBE (0U) //!< Bit position for PMC_REGSC_BGBE.
#define BM_PMC_REGSC_BGBE (0x01U) //!< Bit mask for PMC_REGSC_BGBE.
#define BS_PMC_REGSC_BGBE (1U) //!< Bit field size in bits for PMC_REGSC_BGBE.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PMC_REGSC_BGBE field.
#define BR_PMC_REGSC_BGBE (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_BGBE))
#endif
//! @brief Format value for bitfield PMC_REGSC_BGBE.
#define BF_PMC_REGSC_BGBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_REGSC_BGBE), uint8_t) & BM_PMC_REGSC_BGBE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the BGBE field to a new value.
#define BW_PMC_REGSC_BGBE(v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_BGBE) = (v))
#endif
//@}
/*!
* @name Register PMC_REGSC, field REGONS[2] (RO)
*
* This read-only field provides the current status of the internal voltage
* regulator.
*
* Values:
* - 0 - Regulator is in stop regulation or in transition to/from it
* - 1 - Regulator is in run regulation
*/
//@{
#define BP_PMC_REGSC_REGONS (2U) //!< Bit position for PMC_REGSC_REGONS.
#define BM_PMC_REGSC_REGONS (0x04U) //!< Bit mask for PMC_REGSC_REGONS.
#define BS_PMC_REGSC_REGONS (1U) //!< Bit field size in bits for PMC_REGSC_REGONS.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PMC_REGSC_REGONS field.
#define BR_PMC_REGSC_REGONS (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_REGONS))
#endif
//@}
/*!
* @name Register PMC_REGSC, field ACKISO[3] (W1C)
*
* Reading this field indicates whether certain peripherals and the I/O pads are
* in a latched state as a result of having been in a VLLS mode. Writing 1 to
* this field when it is set releases the I/O pads and certain peripherals to their
* normal run mode state. After recovering from a VLLS mode, user should restore
* chip configuration before clearing ACKISO. In particular, pin configuration
* for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
* being falsely set when ACKISO is cleared.
*
* Values:
* - 0 - Peripherals and I/O pads are in normal run state.
* - 1 - Certain peripherals and I/O pads are in an isolated and latched state.
*/
//@{
#define BP_PMC_REGSC_ACKISO (3U) //!< Bit position for PMC_REGSC_ACKISO.
#define BM_PMC_REGSC_ACKISO (0x08U) //!< Bit mask for PMC_REGSC_ACKISO.
#define BS_PMC_REGSC_ACKISO (1U) //!< Bit field size in bits for PMC_REGSC_ACKISO.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PMC_REGSC_ACKISO field.
#define BR_PMC_REGSC_ACKISO (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_ACKISO))
#endif
//! @brief Format value for bitfield PMC_REGSC_ACKISO.
#define BF_PMC_REGSC_ACKISO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_REGSC_ACKISO), uint8_t) & BM_PMC_REGSC_ACKISO)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ACKISO field to a new value.
#define BW_PMC_REGSC_ACKISO(v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_ACKISO) = (v))
#endif
//@}
/*!
* @name Register PMC_REGSC, field BGEN[4] (RW)
*
* BGEN controls whether the bandgap is enabled in lower power modes of
* operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
* reference in low power modes of operation, set BGEN to continue to enable the
* bandgap operation. When the bandgap voltage reference is not needed in low
* power modes, clear BGEN to avoid excess power consumption.
*
* Values:
* - 0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
* - 1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
*/
//@{
#define BP_PMC_REGSC_BGEN (4U) //!< Bit position for PMC_REGSC_BGEN.
#define BM_PMC_REGSC_BGEN (0x10U) //!< Bit mask for PMC_REGSC_BGEN.
#define BS_PMC_REGSC_BGEN (1U) //!< Bit field size in bits for PMC_REGSC_BGEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PMC_REGSC_BGEN field.
#define BR_PMC_REGSC_BGEN (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_BGEN))
#endif
//! @brief Format value for bitfield PMC_REGSC_BGEN.
#define BF_PMC_REGSC_BGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_REGSC_BGEN), uint8_t) & BM_PMC_REGSC_BGEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the BGEN field to a new value.
#define BW_PMC_REGSC_BGEN(v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_BGEN) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_pmc_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All PMC module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_pmc
{
__IO hw_pmc_lvdsc1_t LVDSC1; //!< [0x0] Low Voltage Detect Status And Control 1 register
__IO hw_pmc_lvdsc2_t LVDSC2; //!< [0x1] Low Voltage Detect Status And Control 2 register
__IO hw_pmc_regsc_t REGSC; //!< [0x2] Regulator Status And Control register
} hw_pmc_t;
#pragma pack()
//! @brief Macro to access all PMC registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_PMC</code>.
#define HW_PMC (*(hw_pmc_t *) REGS_PMC_BASE)
#endif
#endif // __HW_PMC_REGISTERS_H__
// v22/130726/0.9
// EOF

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@ -0,0 +1,957 @@
/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_PORT_REGISTERS_H__
#define __HW_PORT_REGISTERS_H__
#include "regs.h"
/*
* MK64F12 PORT
*
* Pin Control and Interrupts
*
* Registers defined in this header file:
* - HW_PORT_PCRn - Pin Control Register n
* - HW_PORT_GPCLR - Global Pin Control Low Register
* - HW_PORT_GPCHR - Global Pin Control High Register
* - HW_PORT_ISFR - Interrupt Status Flag Register
* - HW_PORT_DFER - Digital Filter Enable Register
* - HW_PORT_DFCR - Digital Filter Clock Register
* - HW_PORT_DFWR - Digital Filter Width Register
*
* - hw_port_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_PORT_BASE
#define HW_PORT_INSTANCE_COUNT (5U) //!< Number of instances of the PORT module.
#define HW_PORTA (0U) //!< Instance number for PORTA.
#define HW_PORTB (1U) //!< Instance number for PORTB.
#define HW_PORTC (2U) //!< Instance number for PORTC.
#define HW_PORTD (3U) //!< Instance number for PORTD.
#define HW_PORTE (4U) //!< Instance number for PORTE.
#define REGS_PORTA_BASE (0x40049000U) //!< Base address for PORTA.
#define REGS_PORTB_BASE (0x4004A000U) //!< Base address for PORTB.
#define REGS_PORTC_BASE (0x4004B000U) //!< Base address for PORTC.
#define REGS_PORTD_BASE (0x4004C000U) //!< Base address for PORTD.
#define REGS_PORTE_BASE (0x4004D000U) //!< Base address for PORTE.
//! @brief Table of base addresses for PORT instances.
static const uint32_t __g_regs_PORT_base_addresses[] = {
REGS_PORTA_BASE,
REGS_PORTB_BASE,
REGS_PORTC_BASE,
REGS_PORTD_BASE,
REGS_PORTE_BASE,
};
//! @brief Get the base address of PORT by instance number.
//! @param x PORT instance number, from 0 through 4.
#define REGS_PORT_BASE(x) (__g_regs_PORT_base_addresses[(x)])
//! @brief Get the instance number given a base address.
//! @param b Base address for an instance of PORT.
#define REGS_PORT_INSTANCE(b) ((b) == REGS_PORTA_BASE ? HW_PORTA : (b) == REGS_PORTB_BASE ? HW_PORTB : (b) == REGS_PORTC_BASE ? HW_PORTC : (b) == REGS_PORTD_BASE ? HW_PORTD : (b) == REGS_PORTE_BASE ? HW_PORTE : 0)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PORT_PCRn - Pin Control Register n
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PORT_PCRn - Pin Control Register n (RW)
*
* Reset value: 0x00000742U
*
* See the Signal Multiplexing and Pin Assignment chapter for the reset value of
* this device. See the GPIO Configuration section for details on the available
* functions for each pin. Do not modify pin configuration registers associated
* with pins not available in your selected package. All unbonded pins not
* available in your package will default to DISABLE state for lowest power consumption.
*/
typedef union _hw_port_pcrn
{
uint32_t U;
struct _hw_port_pcrn_bitfields
{
uint32_t PS : 1; //!< [0] Pull Select
uint32_t PE : 1; //!< [1] Pull Enable
uint32_t SRE : 1; //!< [2] Slew Rate Enable
uint32_t RESERVED0 : 1; //!< [3]
uint32_t PFE : 1; //!< [4] Passive Filter Enable
uint32_t ODE : 1; //!< [5] Open Drain Enable
uint32_t DSE : 1; //!< [6] Drive Strength Enable
uint32_t RESERVED1 : 1; //!< [7]
uint32_t MUX : 3; //!< [10:8] Pin Mux Control
uint32_t RESERVED2 : 4; //!< [14:11]
uint32_t LK : 1; //!< [15] Lock Register
uint32_t IRQC : 4; //!< [19:16] Interrupt Configuration
uint32_t RESERVED3 : 4; //!< [23:20]
uint32_t ISF : 1; //!< [24] Interrupt Status Flag
uint32_t RESERVED4 : 7; //!< [31:25]
} B;
} hw_port_pcrn_t;
#endif
/*!
* @name Constants and macros for entire PORT_PCRn register
*/
//@{
#define HW_PORT_PCRn_COUNT (32U)
#define HW_PORT_PCRn_ADDR(x, n) (REGS_PORT_BASE(x) + 0x0U + (0x4U * n))
#ifndef __LANGUAGE_ASM__
#define HW_PORT_PCRn(x, n) (*(__IO hw_port_pcrn_t *) HW_PORT_PCRn_ADDR(x, n))
#define HW_PORT_PCRn_RD(x, n) (HW_PORT_PCRn(x, n).U)
#define HW_PORT_PCRn_WR(x, n, v) (HW_PORT_PCRn(x, n).U = (v))
#define HW_PORT_PCRn_SET(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) | (v)))
#define HW_PORT_PCRn_CLR(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) & ~(v)))
#define HW_PORT_PCRn_TOG(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual PORT_PCRn bitfields
*/
/*!
* @name Register PORT_PCRn, field PS[0] (RW)
*
* Pull configuration is valid in all digital pin muxing modes.
*
* Values:
* - 0 - Internal pulldown resistor is enabled on the corresponding pin, if the
* corresponding PE field is set.
* - 1 - Internal pullup resistor is enabled on the corresponding pin, if the
* corresponding PE field is set.
*/
//@{
#define BP_PORT_PCRn_PS (0U) //!< Bit position for PORT_PCRn_PS.
#define BM_PORT_PCRn_PS (0x00000001U) //!< Bit mask for PORT_PCRn_PS.
#define BS_PORT_PCRn_PS (1U) //!< Bit field size in bits for PORT_PCRn_PS.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PORT_PCRn_PS field.
#define BR_PORT_PCRn_PS(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS))
#endif
//! @brief Format value for bitfield PORT_PCRn_PS.
#define BF_PORT_PCRn_PS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_PS), uint32_t) & BM_PORT_PCRn_PS)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PS field to a new value.
#define BW_PORT_PCRn_PS(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS) = (v))
#endif
//@}
/*!
* @name Register PORT_PCRn, field PE[1] (RW)
*
* Pull configuration is valid in all digital pin muxing modes.
*
* Values:
* - 0 - Internal pullup or pulldown resistor is not enabled on the
* corresponding pin.
* - 1 - Internal pullup or pulldown resistor is enabled on the corresponding
* pin, if the pin is configured as a digital input.
*/
//@{
#define BP_PORT_PCRn_PE (1U) //!< Bit position for PORT_PCRn_PE.
#define BM_PORT_PCRn_PE (0x00000002U) //!< Bit mask for PORT_PCRn_PE.
#define BS_PORT_PCRn_PE (1U) //!< Bit field size in bits for PORT_PCRn_PE.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PORT_PCRn_PE field.
#define BR_PORT_PCRn_PE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE))
#endif
//! @brief Format value for bitfield PORT_PCRn_PE.
#define BF_PORT_PCRn_PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_PE), uint32_t) & BM_PORT_PCRn_PE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PE field to a new value.
#define BW_PORT_PCRn_PE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE) = (v))
#endif
//@}
/*!
* @name Register PORT_PCRn, field SRE[2] (RW)
*
* Slew rate configuration is valid in all digital pin muxing modes.
*
* Values:
* - 0 - Fast slew rate is configured on the corresponding pin, if the pin is
* configured as a digital output.
* - 1 - Slow slew rate is configured on the corresponding pin, if the pin is
* configured as a digital output.
*/
//@{
#define BP_PORT_PCRn_SRE (2U) //!< Bit position for PORT_PCRn_SRE.
#define BM_PORT_PCRn_SRE (0x00000004U) //!< Bit mask for PORT_PCRn_SRE.
#define BS_PORT_PCRn_SRE (1U) //!< Bit field size in bits for PORT_PCRn_SRE.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PORT_PCRn_SRE field.
#define BR_PORT_PCRn_SRE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE))
#endif
//! @brief Format value for bitfield PORT_PCRn_SRE.
#define BF_PORT_PCRn_SRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_SRE), uint32_t) & BM_PORT_PCRn_SRE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_PORT_PCRn_SRE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE) = (v))
#endif
//@}
/*!
* @name Register PORT_PCRn, field PFE[4] (RW)
*
* Passive filter configuration is valid in all digital pin muxing modes.
*
* Values:
* - 0 - Passive input filter is disabled on the corresponding pin.
* - 1 - Passive input filter is enabled on the corresponding pin, if the pin is
* configured as a digital input. Refer to the device data sheet for filter
* characteristics.
*/
//@{
#define BP_PORT_PCRn_PFE (4U) //!< Bit position for PORT_PCRn_PFE.
#define BM_PORT_PCRn_PFE (0x00000010U) //!< Bit mask for PORT_PCRn_PFE.
#define BS_PORT_PCRn_PFE (1U) //!< Bit field size in bits for PORT_PCRn_PFE.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PORT_PCRn_PFE field.
#define BR_PORT_PCRn_PFE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE))
#endif
//! @brief Format value for bitfield PORT_PCRn_PFE.
#define BF_PORT_PCRn_PFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_PFE), uint32_t) & BM_PORT_PCRn_PFE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PFE field to a new value.
#define BW_PORT_PCRn_PFE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE) = (v))
#endif
//@}
/*!
* @name Register PORT_PCRn, field ODE[5] (RW)
*
* Open drain configuration is valid in all digital pin muxing modes.
*
* Values:
* - 0 - Open drain output is disabled on the corresponding pin.
* - 1 - Open drain output is enabled on the corresponding pin, if the pin is
* configured as a digital output.
*/
//@{
#define BP_PORT_PCRn_ODE (5U) //!< Bit position for PORT_PCRn_ODE.
#define BM_PORT_PCRn_ODE (0x00000020U) //!< Bit mask for PORT_PCRn_ODE.
#define BS_PORT_PCRn_ODE (1U) //!< Bit field size in bits for PORT_PCRn_ODE.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PORT_PCRn_ODE field.
#define BR_PORT_PCRn_ODE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE))
#endif
//! @brief Format value for bitfield PORT_PCRn_ODE.
#define BF_PORT_PCRn_ODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_ODE), uint32_t) & BM_PORT_PCRn_ODE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_PORT_PCRn_ODE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE) = (v))
#endif
//@}
/*!
* @name Register PORT_PCRn, field DSE[6] (RW)
*
* Drive strength configuration is valid in all digital pin muxing modes.
*
* Values:
* - 0 - Low drive strength is configured on the corresponding pin, if pin is
* configured as a digital output.
* - 1 - High drive strength is configured on the corresponding pin, if pin is
* configured as a digital output.
*/
//@{
#define BP_PORT_PCRn_DSE (6U) //!< Bit position for PORT_PCRn_DSE.
#define BM_PORT_PCRn_DSE (0x00000040U) //!< Bit mask for PORT_PCRn_DSE.
#define BS_PORT_PCRn_DSE (1U) //!< Bit field size in bits for PORT_PCRn_DSE.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PORT_PCRn_DSE field.
#define BR_PORT_PCRn_DSE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE))
#endif
//! @brief Format value for bitfield PORT_PCRn_DSE.
#define BF_PORT_PCRn_DSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_DSE), uint32_t) & BM_PORT_PCRn_DSE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_PORT_PCRn_DSE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE) = (v))
#endif
//@}
/*!
* @name Register PORT_PCRn, field MUX[10:8] (RW)
*
* Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
* reserved and may result in configuring the pin for a different pin muxing
* slot. The corresponding pin is configured in the following pin muxing slot as
* follows:
*
* Values:
* - 000 - Pin disabled (analog).
* - 001 - Alternative 1 (GPIO).
* - 010 - Alternative 2 (chip-specific).
* - 011 - Alternative 3 (chip-specific).
* - 100 - Alternative 4 (chip-specific).
* - 101 - Alternative 5 (chip-specific).
* - 110 - Alternative 6 (chip-specific).
* - 111 - Alternative 7 (chip-specific).
*/
//@{
#define BP_PORT_PCRn_MUX (8U) //!< Bit position for PORT_PCRn_MUX.
#define BM_PORT_PCRn_MUX (0x00000700U) //!< Bit mask for PORT_PCRn_MUX.
#define BS_PORT_PCRn_MUX (3U) //!< Bit field size in bits for PORT_PCRn_MUX.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PORT_PCRn_MUX field.
#define BR_PORT_PCRn_MUX(x, n) (HW_PORT_PCRn(x, n).B.MUX)
#endif
//! @brief Format value for bitfield PORT_PCRn_MUX.
#define BF_PORT_PCRn_MUX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_MUX), uint32_t) & BM_PORT_PCRn_MUX)
#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX field to a new value.
#define BW_PORT_PCRn_MUX(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_MUX) | BF_PORT_PCRn_MUX(v)))
#endif
//@}
/*!
* @name Register PORT_PCRn, field LK[15] (RW)
*
* Values:
* - 0 - Pin Control Register fields [15:0] are not locked.
* - 1 - Pin Control Register fields [15:0] are locked and cannot be updated
* until the next system reset.
*/
//@{
#define BP_PORT_PCRn_LK (15U) //!< Bit position for PORT_PCRn_LK.
#define BM_PORT_PCRn_LK (0x00008000U) //!< Bit mask for PORT_PCRn_LK.
#define BS_PORT_PCRn_LK (1U) //!< Bit field size in bits for PORT_PCRn_LK.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PORT_PCRn_LK field.
#define BR_PORT_PCRn_LK(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK))
#endif
//! @brief Format value for bitfield PORT_PCRn_LK.
#define BF_PORT_PCRn_LK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_LK), uint32_t) & BM_PORT_PCRn_LK)
#ifndef __LANGUAGE_ASM__
//! @brief Set the LK field to a new value.
#define BW_PORT_PCRn_LK(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK) = (v))
#endif
//@}
/*!
* @name Register PORT_PCRn, field IRQC[19:16] (RW)
*
* The pin interrupt configuration is valid in all digital pin muxing modes. The
* corresponding pin is configured to generate interrupt/DMA request as follows:
*
* Values:
* - 0000 - Interrupt/DMA request disabled.
* - 0001 - DMA request on rising edge.
* - 0010 - DMA request on falling edge.
* - 0011 - DMA request on either edge.
* - 1000 - Interrupt when logic 0.
* - 1001 - Interrupt on rising-edge.
* - 1010 - Interrupt on falling-edge.
* - 1011 - Interrupt on either edge.
* - 1100 - Interrupt when logic 1.
*/
//@{
#define BP_PORT_PCRn_IRQC (16U) //!< Bit position for PORT_PCRn_IRQC.
#define BM_PORT_PCRn_IRQC (0x000F0000U) //!< Bit mask for PORT_PCRn_IRQC.
#define BS_PORT_PCRn_IRQC (4U) //!< Bit field size in bits for PORT_PCRn_IRQC.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PORT_PCRn_IRQC field.
#define BR_PORT_PCRn_IRQC(x, n) (HW_PORT_PCRn(x, n).B.IRQC)
#endif
//! @brief Format value for bitfield PORT_PCRn_IRQC.
#define BF_PORT_PCRn_IRQC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_IRQC), uint32_t) & BM_PORT_PCRn_IRQC)
#ifndef __LANGUAGE_ASM__
//! @brief Set the IRQC field to a new value.
#define BW_PORT_PCRn_IRQC(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_IRQC) | BF_PORT_PCRn_IRQC(v)))
#endif
//@}
/*!
* @name Register PORT_PCRn, field ISF[24] (W1C)
*
* The pin interrupt configuration is valid in all digital pin muxing modes.
*
* Values:
* - 0 - Configured interrupt is not detected.
* - 1 - Configured interrupt is detected. If the pin is configured to generate
* a DMA request, then the corresponding flag will be cleared automatically
* at the completion of the requested DMA transfer. Otherwise, the flag
* remains set until a logic 1 is written to the flag. If the pin is configured for
* a level sensitive interrupt and the pin remains asserted, then the flag
* is set again immediately after it is cleared.
*/
//@{
#define BP_PORT_PCRn_ISF (24U) //!< Bit position for PORT_PCRn_ISF.
#define BM_PORT_PCRn_ISF (0x01000000U) //!< Bit mask for PORT_PCRn_ISF.
#define BS_PORT_PCRn_ISF (1U) //!< Bit field size in bits for PORT_PCRn_ISF.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PORT_PCRn_ISF field.
#define BR_PORT_PCRn_ISF(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF))
#endif
//! @brief Format value for bitfield PORT_PCRn_ISF.
#define BF_PORT_PCRn_ISF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_ISF), uint32_t) & BM_PORT_PCRn_ISF)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ISF field to a new value.
#define BW_PORT_PCRn_ISF(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PORT_GPCLR - Global Pin Control Low Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PORT_GPCLR - Global Pin Control Low Register (WORZ)
*
* Reset value: 0x00000000U
*
* Only 32-bit writes are supported to this register.
*/
typedef union _hw_port_gpclr
{
uint32_t U;
struct _hw_port_gpclr_bitfields
{
uint32_t GPWD : 16; //!< [15:0] Global Pin Write Data
uint32_t GPWE : 16; //!< [31:16] Global Pin Write Enable
} B;
} hw_port_gpclr_t;
#endif
/*!
* @name Constants and macros for entire PORT_GPCLR register
*/
//@{
#define HW_PORT_GPCLR_ADDR(x) (REGS_PORT_BASE(x) + 0x80U)
#ifndef __LANGUAGE_ASM__
#define HW_PORT_GPCLR(x) (*(__O hw_port_gpclr_t *) HW_PORT_GPCLR_ADDR(x))
#define HW_PORT_GPCLR_RD(x) (HW_PORT_GPCLR(x).U)
#define HW_PORT_GPCLR_WR(x, v) (HW_PORT_GPCLR(x).U = (v))
#endif
//@}
/*
* Constants & macros for individual PORT_GPCLR bitfields
*/
/*!
* @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
*
* Write value that is written to all Pin Control Registers bits [15:0] that are
* selected by GPWE.
*/
//@{
#define BP_PORT_GPCLR_GPWD (0U) //!< Bit position for PORT_GPCLR_GPWD.
#define BM_PORT_GPCLR_GPWD (0x0000FFFFU) //!< Bit mask for PORT_GPCLR_GPWD.
#define BS_PORT_GPCLR_GPWD (16U) //!< Bit field size in bits for PORT_GPCLR_GPWD.
//! @brief Format value for bitfield PORT_GPCLR_GPWD.
#define BF_PORT_GPCLR_GPWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCLR_GPWD), uint32_t) & BM_PORT_GPCLR_GPWD)
#ifndef __LANGUAGE_ASM__
//! @brief Set the GPWD field to a new value.
#define BW_PORT_GPCLR_GPWD(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWD) | BF_PORT_GPCLR_GPWD(v)))
#endif
//@}
/*!
* @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
*
* Selects which Pin Control Registers (15 through 0) bits [15:0] update with
* the value in GPWD. If a selected Pin Control Register is locked then the write
* to that register is ignored.
*
* Values:
* - 0 - Corresponding Pin Control Register is not updated with the value in
* GPWD.
* - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
*/
//@{
#define BP_PORT_GPCLR_GPWE (16U) //!< Bit position for PORT_GPCLR_GPWE.
#define BM_PORT_GPCLR_GPWE (0xFFFF0000U) //!< Bit mask for PORT_GPCLR_GPWE.
#define BS_PORT_GPCLR_GPWE (16U) //!< Bit field size in bits for PORT_GPCLR_GPWE.
//! @brief Format value for bitfield PORT_GPCLR_GPWE.
#define BF_PORT_GPCLR_GPWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCLR_GPWE), uint32_t) & BM_PORT_GPCLR_GPWE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the GPWE field to a new value.
#define BW_PORT_GPCLR_GPWE(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWE) | BF_PORT_GPCLR_GPWE(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PORT_GPCHR - Global Pin Control High Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PORT_GPCHR - Global Pin Control High Register (WORZ)
*
* Reset value: 0x00000000U
*
* Only 32-bit writes are supported to this register.
*/
typedef union _hw_port_gpchr
{
uint32_t U;
struct _hw_port_gpchr_bitfields
{
uint32_t GPWD : 16; //!< [15:0] Global Pin Write Data
uint32_t GPWE : 16; //!< [31:16] Global Pin Write Enable
} B;
} hw_port_gpchr_t;
#endif
/*!
* @name Constants and macros for entire PORT_GPCHR register
*/
//@{
#define HW_PORT_GPCHR_ADDR(x) (REGS_PORT_BASE(x) + 0x84U)
#ifndef __LANGUAGE_ASM__
#define HW_PORT_GPCHR(x) (*(__O hw_port_gpchr_t *) HW_PORT_GPCHR_ADDR(x))
#define HW_PORT_GPCHR_RD(x) (HW_PORT_GPCHR(x).U)
#define HW_PORT_GPCHR_WR(x, v) (HW_PORT_GPCHR(x).U = (v))
#endif
//@}
/*
* Constants & macros for individual PORT_GPCHR bitfields
*/
/*!
* @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
*
* Write value that is written to all Pin Control Registers bits [15:0] that are
* selected by GPWE.
*/
//@{
#define BP_PORT_GPCHR_GPWD (0U) //!< Bit position for PORT_GPCHR_GPWD.
#define BM_PORT_GPCHR_GPWD (0x0000FFFFU) //!< Bit mask for PORT_GPCHR_GPWD.
#define BS_PORT_GPCHR_GPWD (16U) //!< Bit field size in bits for PORT_GPCHR_GPWD.
//! @brief Format value for bitfield PORT_GPCHR_GPWD.
#define BF_PORT_GPCHR_GPWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCHR_GPWD), uint32_t) & BM_PORT_GPCHR_GPWD)
#ifndef __LANGUAGE_ASM__
//! @brief Set the GPWD field to a new value.
#define BW_PORT_GPCHR_GPWD(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWD) | BF_PORT_GPCHR_GPWD(v)))
#endif
//@}
/*!
* @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
*
* Selects which Pin Control Registers (31 through 16) bits [15:0] update with
* the value in GPWD. If a selected Pin Control Register is locked then the write
* to that register is ignored.
*
* Values:
* - 0 - Corresponding Pin Control Register is not updated with the value in
* GPWD.
* - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
*/
//@{
#define BP_PORT_GPCHR_GPWE (16U) //!< Bit position for PORT_GPCHR_GPWE.
#define BM_PORT_GPCHR_GPWE (0xFFFF0000U) //!< Bit mask for PORT_GPCHR_GPWE.
#define BS_PORT_GPCHR_GPWE (16U) //!< Bit field size in bits for PORT_GPCHR_GPWE.
//! @brief Format value for bitfield PORT_GPCHR_GPWE.
#define BF_PORT_GPCHR_GPWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCHR_GPWE), uint32_t) & BM_PORT_GPCHR_GPWE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the GPWE field to a new value.
#define BW_PORT_GPCHR_GPWE(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWE) | BF_PORT_GPCHR_GPWE(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PORT_ISFR - Interrupt Status Flag Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PORT_ISFR - Interrupt Status Flag Register (W1C)
*
* Reset value: 0x00000000U
*
* The pin interrupt configuration is valid in all digital pin muxing modes. The
* Interrupt Status Flag for each pin is also visible in the corresponding Pin
* Control Register, and each flag can be cleared in either location.
*/
typedef union _hw_port_isfr
{
uint32_t U;
struct _hw_port_isfr_bitfields
{
uint32_t ISF : 32; //!< [31:0] Interrupt Status Flag
} B;
} hw_port_isfr_t;
#endif
/*!
* @name Constants and macros for entire PORT_ISFR register
*/
//@{
#define HW_PORT_ISFR_ADDR(x) (REGS_PORT_BASE(x) + 0xA0U)
#ifndef __LANGUAGE_ASM__
#define HW_PORT_ISFR(x) (*(__IO hw_port_isfr_t *) HW_PORT_ISFR_ADDR(x))
#define HW_PORT_ISFR_RD(x) (HW_PORT_ISFR(x).U)
#define HW_PORT_ISFR_WR(x, v) (HW_PORT_ISFR(x).U = (v))
#define HW_PORT_ISFR_SET(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) | (v)))
#define HW_PORT_ISFR_CLR(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) & ~(v)))
#define HW_PORT_ISFR_TOG(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual PORT_ISFR bitfields
*/
/*!
* @name Register PORT_ISFR, field ISF[31:0] (W1C)
*
* Each bit in the field indicates the detection of the configured interrupt of
* the same number as the field.
*
* Values:
* - 0 - Configured interrupt is not detected.
* - 1 - Configured interrupt is detected. If the pin is configured to generate
* a DMA request, then the corresponding flag will be cleared automatically
* at the completion of the requested DMA transfer. Otherwise, the flag
* remains set until a logic 1 is written to the flag. If the pin is configured for
* a level sensitive interrupt and the pin remains asserted, then the flag
* is set again immediately after it is cleared.
*/
//@{
#define BP_PORT_ISFR_ISF (0U) //!< Bit position for PORT_ISFR_ISF.
#define BM_PORT_ISFR_ISF (0xFFFFFFFFU) //!< Bit mask for PORT_ISFR_ISF.
#define BS_PORT_ISFR_ISF (32U) //!< Bit field size in bits for PORT_ISFR_ISF.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PORT_ISFR_ISF field.
#define BR_PORT_ISFR_ISF(x) (HW_PORT_ISFR(x).U)
#endif
//! @brief Format value for bitfield PORT_ISFR_ISF.
#define BF_PORT_ISFR_ISF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_ISFR_ISF), uint32_t) & BM_PORT_ISFR_ISF)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ISF field to a new value.
#define BW_PORT_ISFR_ISF(x, v) (HW_PORT_ISFR_WR(x, v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PORT_DFER - Digital Filter Enable Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PORT_DFER - Digital Filter Enable Register (RW)
*
* Reset value: 0x00000000U
*
* The corresponding bit is read only for pins that do not support a digital
* filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
* the pins that support digital filter. The digital filter configuration is valid
* in all digital pin muxing modes.
*/
typedef union _hw_port_dfer
{
uint32_t U;
struct _hw_port_dfer_bitfields
{
uint32_t DFE : 32; //!< [31:0] Digital Filter Enable
} B;
} hw_port_dfer_t;
#endif
/*!
* @name Constants and macros for entire PORT_DFER register
*/
//@{
#define HW_PORT_DFER_ADDR(x) (REGS_PORT_BASE(x) + 0xC0U)
#ifndef __LANGUAGE_ASM__
#define HW_PORT_DFER(x) (*(__IO hw_port_dfer_t *) HW_PORT_DFER_ADDR(x))
#define HW_PORT_DFER_RD(x) (HW_PORT_DFER(x).U)
#define HW_PORT_DFER_WR(x, v) (HW_PORT_DFER(x).U = (v))
#define HW_PORT_DFER_SET(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) | (v)))
#define HW_PORT_DFER_CLR(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) & ~(v)))
#define HW_PORT_DFER_TOG(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual PORT_DFER bitfields
*/
/*!
* @name Register PORT_DFER, field DFE[31:0] (RW)
*
* The digital filter configuration is valid in all digital pin muxing modes.
* The output of each digital filter is reset to zero at system reset and whenever
* the digital filter is disabled. Each bit in the field enables the digital
* filter of the same number as the field.
*
* Values:
* - 0 - Digital filter is disabled on the corresponding pin and output of the
* digital filter is reset to zero.
* - 1 - Digital filter is enabled on the corresponding pin, if the pin is
* configured as a digital input.
*/
//@{
#define BP_PORT_DFER_DFE (0U) //!< Bit position for PORT_DFER_DFE.
#define BM_PORT_DFER_DFE (0xFFFFFFFFU) //!< Bit mask for PORT_DFER_DFE.
#define BS_PORT_DFER_DFE (32U) //!< Bit field size in bits for PORT_DFER_DFE.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PORT_DFER_DFE field.
#define BR_PORT_DFER_DFE(x) (HW_PORT_DFER(x).U)
#endif
//! @brief Format value for bitfield PORT_DFER_DFE.
#define BF_PORT_DFER_DFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_DFER_DFE), uint32_t) & BM_PORT_DFER_DFE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the DFE field to a new value.
#define BW_PORT_DFER_DFE(x, v) (HW_PORT_DFER_WR(x, v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PORT_DFCR - Digital Filter Clock Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PORT_DFCR - Digital Filter Clock Register (RW)
*
* Reset value: 0x00000000U
*
* This register is read only for ports that do not support a digital filter.
* The digital filter configuration is valid in all digital pin muxing modes.
*/
typedef union _hw_port_dfcr
{
uint32_t U;
struct _hw_port_dfcr_bitfields
{
uint32_t CS : 1; //!< [0] Clock Source
uint32_t RESERVED0 : 31; //!< [31:1]
} B;
} hw_port_dfcr_t;
#endif
/*!
* @name Constants and macros for entire PORT_DFCR register
*/
//@{
#define HW_PORT_DFCR_ADDR(x) (REGS_PORT_BASE(x) + 0xC4U)
#ifndef __LANGUAGE_ASM__
#define HW_PORT_DFCR(x) (*(__IO hw_port_dfcr_t *) HW_PORT_DFCR_ADDR(x))
#define HW_PORT_DFCR_RD(x) (HW_PORT_DFCR(x).U)
#define HW_PORT_DFCR_WR(x, v) (HW_PORT_DFCR(x).U = (v))
#define HW_PORT_DFCR_SET(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) | (v)))
#define HW_PORT_DFCR_CLR(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) & ~(v)))
#define HW_PORT_DFCR_TOG(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual PORT_DFCR bitfields
*/
/*!
* @name Register PORT_DFCR, field CS[0] (RW)
*
* The digital filter configuration is valid in all digital pin muxing modes.
* Configures the clock source for the digital input filters. Changing the filter
* clock source must be done only when all digital filters are disabled.
*
* Values:
* - 0 - Digital filters are clocked by the bus clock.
* - 1 - Digital filters are clocked by the 1 kHz LPO clock.
*/
//@{
#define BP_PORT_DFCR_CS (0U) //!< Bit position for PORT_DFCR_CS.
#define BM_PORT_DFCR_CS (0x00000001U) //!< Bit mask for PORT_DFCR_CS.
#define BS_PORT_DFCR_CS (1U) //!< Bit field size in bits for PORT_DFCR_CS.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PORT_DFCR_CS field.
#define BR_PORT_DFCR_CS(x) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS))
#endif
//! @brief Format value for bitfield PORT_DFCR_CS.
#define BF_PORT_DFCR_CS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_DFCR_CS), uint32_t) & BM_PORT_DFCR_CS)
#ifndef __LANGUAGE_ASM__
//! @brief Set the CS field to a new value.
#define BW_PORT_DFCR_CS(x, v) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_PORT_DFWR - Digital Filter Width Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_PORT_DFWR - Digital Filter Width Register (RW)
*
* Reset value: 0x00000000U
*
* This register is read only for ports that do not support a digital filter.
* The digital filter configuration is valid in all digital pin muxing modes.
*/
typedef union _hw_port_dfwr
{
uint32_t U;
struct _hw_port_dfwr_bitfields
{
uint32_t FILT : 5; //!< [4:0] Filter Length
uint32_t RESERVED0 : 27; //!< [31:5]
} B;
} hw_port_dfwr_t;
#endif
/*!
* @name Constants and macros for entire PORT_DFWR register
*/
//@{
#define HW_PORT_DFWR_ADDR(x) (REGS_PORT_BASE(x) + 0xC8U)
#ifndef __LANGUAGE_ASM__
#define HW_PORT_DFWR(x) (*(__IO hw_port_dfwr_t *) HW_PORT_DFWR_ADDR(x))
#define HW_PORT_DFWR_RD(x) (HW_PORT_DFWR(x).U)
#define HW_PORT_DFWR_WR(x, v) (HW_PORT_DFWR(x).U = (v))
#define HW_PORT_DFWR_SET(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) | (v)))
#define HW_PORT_DFWR_CLR(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) & ~(v)))
#define HW_PORT_DFWR_TOG(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual PORT_DFWR bitfields
*/
/*!
* @name Register PORT_DFWR, field FILT[4:0] (RW)
*
* The digital filter configuration is valid in all digital pin muxing modes.
* Configures the maximum size of the glitches, in clock cycles, that the digital
* filter absorbs for the enabled digital filters. Glitches that are longer than
* this register setting will pass through the digital filter, and glitches that
* are equal to or less than this register setting are filtered. Changing the
* filter length must be done only after all filters are disabled.
*/
//@{
#define BP_PORT_DFWR_FILT (0U) //!< Bit position for PORT_DFWR_FILT.
#define BM_PORT_DFWR_FILT (0x0000001FU) //!< Bit mask for PORT_DFWR_FILT.
#define BS_PORT_DFWR_FILT (5U) //!< Bit field size in bits for PORT_DFWR_FILT.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the PORT_DFWR_FILT field.
#define BR_PORT_DFWR_FILT(x) (HW_PORT_DFWR(x).B.FILT)
#endif
//! @brief Format value for bitfield PORT_DFWR_FILT.
#define BF_PORT_DFWR_FILT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_DFWR_FILT), uint32_t) & BM_PORT_DFWR_FILT)
#ifndef __LANGUAGE_ASM__
//! @brief Set the FILT field to a new value.
#define BW_PORT_DFWR_FILT(x, v) (HW_PORT_DFWR_WR(x, (HW_PORT_DFWR_RD(x) & ~BM_PORT_DFWR_FILT) | BF_PORT_DFWR_FILT(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_port_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All PORT module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_port
{
__IO hw_port_pcrn_t PCRn[32]; //!< [0x0] Pin Control Register n
__O hw_port_gpclr_t GPCLR; //!< [0x80] Global Pin Control Low Register
__O hw_port_gpchr_t GPCHR; //!< [0x84] Global Pin Control High Register
uint8_t _reserved0[24];
__IO hw_port_isfr_t ISFR; //!< [0xA0] Interrupt Status Flag Register
uint8_t _reserved1[28];
__IO hw_port_dfer_t DFER; //!< [0xC0] Digital Filter Enable Register
__IO hw_port_dfcr_t DFCR; //!< [0xC4] Digital Filter Clock Register
__IO hw_port_dfwr_t DFWR; //!< [0xC8] Digital Filter Width Register
} hw_port_t;
#pragma pack()
//! @brief Macro to access all PORT registers.
//! @param x PORT instance number.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_PORT(0)</code>.
#define HW_PORT(x) (*(hw_port_t *) REGS_PORT_BASE(x))
#endif
#endif // __HW_PORT_REGISTERS_H__
// v22/130726/0.9
// EOF

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_RCM_REGISTERS_H__
#define __HW_RCM_REGISTERS_H__
#include "regs.h"
/*
* MK64F12 RCM
*
* Reset Control Module
*
* Registers defined in this header file:
* - HW_RCM_SRS0 - System Reset Status Register 0
* - HW_RCM_SRS1 - System Reset Status Register 1
* - HW_RCM_RPFC - Reset Pin Filter Control register
* - HW_RCM_RPFW - Reset Pin Filter Width register
* - HW_RCM_MR - Mode Register
*
* - hw_rcm_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_RCM_BASE
#define HW_RCM_INSTANCE_COUNT (1U) //!< Number of instances of the RCM module.
#define REGS_RCM_BASE (0x4007F000U) //!< Base address for RCM.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_RCM_SRS0 - System Reset Status Register 0
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_RCM_SRS0 - System Reset Status Register 0 (RO)
*
* Reset value: 0x82U
*
* This register includes read-only status flags to indicate the source of the
* most recent reset. The reset state of these bits depends on what caused the MCU
* to reset. The reset value of this register depends on the reset source: POR
* (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET
* pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other
* reset - a bit is set if its corresponding reset source caused the reset
*/
typedef union _hw_rcm_srs0
{
uint8_t U;
struct _hw_rcm_srs0_bitfields
{
uint8_t WAKEUP : 1; //!< [0] Low Leakage Wakeup Reset
uint8_t LVD : 1; //!< [1] Low-Voltage Detect Reset
uint8_t LOC : 1; //!< [2] Loss-of-Clock Reset
uint8_t LOL : 1; //!< [3] Loss-of-Lock Reset
uint8_t RESERVED0 : 1; //!< [4]
uint8_t WDOGb : 1; //!< [5] Watchdog
uint8_t PIN : 1; //!< [6] External Reset Pin
uint8_t POR : 1; //!< [7] Power-On Reset
} B;
} hw_rcm_srs0_t;
#endif
/*!
* @name Constants and macros for entire RCM_SRS0 register
*/
//@{
#define HW_RCM_SRS0_ADDR (REGS_RCM_BASE + 0x0U)
#ifndef __LANGUAGE_ASM__
#define HW_RCM_SRS0 (*(__I hw_rcm_srs0_t *) HW_RCM_SRS0_ADDR)
#define HW_RCM_SRS0_RD() (HW_RCM_SRS0.U)
#endif
//@}
/*
* Constants & macros for individual RCM_SRS0 bitfields
*/
/*!
* @name Register RCM_SRS0, field WAKEUP[0] (RO)
*
* Indicates a reset has been caused by an enabled LLWU module wakeup source
* while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
* wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
* mode causes a reset. This bit is cleared by any reset except WAKEUP.
*
* Values:
* - 0 - Reset not caused by LLWU module wakeup source
* - 1 - Reset caused by LLWU module wakeup source
*/
//@{
#define BP_RCM_SRS0_WAKEUP (0U) //!< Bit position for RCM_SRS0_WAKEUP.
#define BM_RCM_SRS0_WAKEUP (0x01U) //!< Bit mask for RCM_SRS0_WAKEUP.
#define BS_RCM_SRS0_WAKEUP (1U) //!< Bit field size in bits for RCM_SRS0_WAKEUP.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RCM_SRS0_WAKEUP field.
#define BR_RCM_SRS0_WAKEUP (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_WAKEUP))
#endif
//@}
/*!
* @name Register RCM_SRS0, field LVD[1] (RO)
*
* If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
* an LVD reset occurs. This field is also set by POR.
*
* Values:
* - 0 - Reset not caused by LVD trip or POR
* - 1 - Reset caused by LVD trip or POR
*/
//@{
#define BP_RCM_SRS0_LVD (1U) //!< Bit position for RCM_SRS0_LVD.
#define BM_RCM_SRS0_LVD (0x02U) //!< Bit mask for RCM_SRS0_LVD.
#define BS_RCM_SRS0_LVD (1U) //!< Bit field size in bits for RCM_SRS0_LVD.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RCM_SRS0_LVD field.
#define BR_RCM_SRS0_LVD (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LVD))
#endif
//@}
/*!
* @name Register RCM_SRS0, field LOC[2] (RO)
*
* Indicates a reset has been caused by a loss of external clock. The MCG clock
* monitor must be enabled for a loss of clock to be detected. Refer to the
* detailed MCG description for information on enabling the clock monitor.
*
* Values:
* - 0 - Reset not caused by a loss of external clock.
* - 1 - Reset caused by a loss of external clock.
*/
//@{
#define BP_RCM_SRS0_LOC (2U) //!< Bit position for RCM_SRS0_LOC.
#define BM_RCM_SRS0_LOC (0x04U) //!< Bit mask for RCM_SRS0_LOC.
#define BS_RCM_SRS0_LOC (1U) //!< Bit field size in bits for RCM_SRS0_LOC.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RCM_SRS0_LOC field.
#define BR_RCM_SRS0_LOC (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LOC))
#endif
//@}
/*!
* @name Register RCM_SRS0, field LOL[3] (RO)
*
* Indicates a reset has been caused by a loss of lock in the MCG PLL. See the
* MCG description for information on the loss-of-clock event.
*
* Values:
* - 0 - Reset not caused by a loss of lock in the PLL
* - 1 - Reset caused by a loss of lock in the PLL
*/
//@{
#define BP_RCM_SRS0_LOL (3U) //!< Bit position for RCM_SRS0_LOL.
#define BM_RCM_SRS0_LOL (0x08U) //!< Bit mask for RCM_SRS0_LOL.
#define BS_RCM_SRS0_LOL (1U) //!< Bit field size in bits for RCM_SRS0_LOL.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RCM_SRS0_LOL field.
#define BR_RCM_SRS0_LOL (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LOL))
#endif
//@}
/*!
* @name Register RCM_SRS0, field WDOG[5] (RO)
*
* Indicates a reset has been caused by the watchdog timer Computer Operating
* Properly (COP) timing out. This reset source can be blocked by disabling the COP
* watchdog: write 00 to SIM_COPCTRL[COPT].
*
* Values:
* - 0 - Reset not caused by watchdog timeout
* - 1 - Reset caused by watchdog timeout
*/
//@{
#define BP_RCM_SRS0_WDOG (5U) //!< Bit position for RCM_SRS0_WDOG.
#define BM_RCM_SRS0_WDOG (0x20U) //!< Bit mask for RCM_SRS0_WDOG.
#define BS_RCM_SRS0_WDOG (1U) //!< Bit field size in bits for RCM_SRS0_WDOG.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RCM_SRS0_WDOG field.
#define BR_RCM_SRS0_WDOG (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_WDOG))
#endif
//@}
/*!
* @name Register RCM_SRS0, field PIN[6] (RO)
*
* Indicates a reset has been caused by an active-low level on the external
* RESET pin.
*
* Values:
* - 0 - Reset not caused by external reset pin
* - 1 - Reset caused by external reset pin
*/
//@{
#define BP_RCM_SRS0_PIN (6U) //!< Bit position for RCM_SRS0_PIN.
#define BM_RCM_SRS0_PIN (0x40U) //!< Bit mask for RCM_SRS0_PIN.
#define BS_RCM_SRS0_PIN (1U) //!< Bit field size in bits for RCM_SRS0_PIN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RCM_SRS0_PIN field.
#define BR_RCM_SRS0_PIN (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_PIN))
#endif
//@}
/*!
* @name Register RCM_SRS0, field POR[7] (RO)
*
* Indicates a reset has been caused by the power-on detection logic. Because
* the internal supply voltage was ramping up at the time, the low-voltage reset
* (LVD) status bit is also set to indicate that the reset occurred while the
* internal supply was below the LVD threshold.
*
* Values:
* - 0 - Reset not caused by POR
* - 1 - Reset caused by POR
*/
//@{
#define BP_RCM_SRS0_POR (7U) //!< Bit position for RCM_SRS0_POR.
#define BM_RCM_SRS0_POR (0x80U) //!< Bit mask for RCM_SRS0_POR.
#define BS_RCM_SRS0_POR (1U) //!< Bit field size in bits for RCM_SRS0_POR.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RCM_SRS0_POR field.
#define BR_RCM_SRS0_POR (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_POR))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_RCM_SRS1 - System Reset Status Register 1
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_RCM_SRS1 - System Reset Status Register 1 (RO)
*
* Reset value: 0x00U
*
* This register includes read-only status flags to indicate the source of the
* most recent reset. The reset state of these bits depends on what caused the MCU
* to reset. The reset value of this register depends on the reset source: POR
* (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other
* reset - a bit is set if its corresponding reset source caused the reset
*/
typedef union _hw_rcm_srs1
{
uint8_t U;
struct _hw_rcm_srs1_bitfields
{
uint8_t JTAG : 1; //!< [0] JTAG Generated Reset
uint8_t LOCKUP : 1; //!< [1] Core Lockup
uint8_t SW : 1; //!< [2] Software
uint8_t MDM_AP : 1; //!< [3] MDM-AP System Reset Request
uint8_t EZPT : 1; //!< [4] EzPort Reset
uint8_t SACKERR : 1; //!< [5] Stop Mode Acknowledge Error Reset
uint8_t RESERVED0 : 2; //!< [7:6]
} B;
} hw_rcm_srs1_t;
#endif
/*!
* @name Constants and macros for entire RCM_SRS1 register
*/
//@{
#define HW_RCM_SRS1_ADDR (REGS_RCM_BASE + 0x1U)
#ifndef __LANGUAGE_ASM__
#define HW_RCM_SRS1 (*(__I hw_rcm_srs1_t *) HW_RCM_SRS1_ADDR)
#define HW_RCM_SRS1_RD() (HW_RCM_SRS1.U)
#endif
//@}
/*
* Constants & macros for individual RCM_SRS1 bitfields
*/
/*!
* @name Register RCM_SRS1, field JTAG[0] (RO)
*
* Indicates a reset has been caused by JTAG selection of certain IR codes:
* EZPORT, EXTEST, HIGHZ, and CLAMP.
*
* Values:
* - 0 - Reset not caused by JTAG
* - 1 - Reset caused by JTAG
*/
//@{
#define BP_RCM_SRS1_JTAG (0U) //!< Bit position for RCM_SRS1_JTAG.
#define BM_RCM_SRS1_JTAG (0x01U) //!< Bit mask for RCM_SRS1_JTAG.
#define BS_RCM_SRS1_JTAG (1U) //!< Bit field size in bits for RCM_SRS1_JTAG.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RCM_SRS1_JTAG field.
#define BR_RCM_SRS1_JTAG (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_JTAG))
#endif
//@}
/*!
* @name Register RCM_SRS1, field LOCKUP[1] (RO)
*
* Indicates a reset has been caused by the ARM core indication of a LOCKUP
* event.
*
* Values:
* - 0 - Reset not caused by core LOCKUP event
* - 1 - Reset caused by core LOCKUP event
*/
//@{
#define BP_RCM_SRS1_LOCKUP (1U) //!< Bit position for RCM_SRS1_LOCKUP.
#define BM_RCM_SRS1_LOCKUP (0x02U) //!< Bit mask for RCM_SRS1_LOCKUP.
#define BS_RCM_SRS1_LOCKUP (1U) //!< Bit field size in bits for RCM_SRS1_LOCKUP.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RCM_SRS1_LOCKUP field.
#define BR_RCM_SRS1_LOCKUP (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_LOCKUP))
#endif
//@}
/*!
* @name Register RCM_SRS1, field SW[2] (RO)
*
* Indicates a reset has been caused by software setting of SYSRESETREQ bit in
* Application Interrupt and Reset Control Register in the ARM core.
*
* Values:
* - 0 - Reset not caused by software setting of SYSRESETREQ bit
* - 1 - Reset caused by software setting of SYSRESETREQ bit
*/
//@{
#define BP_RCM_SRS1_SW (2U) //!< Bit position for RCM_SRS1_SW.
#define BM_RCM_SRS1_SW (0x04U) //!< Bit mask for RCM_SRS1_SW.
#define BS_RCM_SRS1_SW (1U) //!< Bit field size in bits for RCM_SRS1_SW.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RCM_SRS1_SW field.
#define BR_RCM_SRS1_SW (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_SW))
#endif
//@}
/*!
* @name Register RCM_SRS1, field MDM_AP[3] (RO)
*
* Indicates a reset has been caused by the host debugger system setting of the
* System Reset Request bit in the MDM-AP Control Register.
*
* Values:
* - 0 - Reset not caused by host debugger system setting of the System Reset
* Request bit
* - 1 - Reset caused by host debugger system setting of the System Reset
* Request bit
*/
//@{
#define BP_RCM_SRS1_MDM_AP (3U) //!< Bit position for RCM_SRS1_MDM_AP.
#define BM_RCM_SRS1_MDM_AP (0x08U) //!< Bit mask for RCM_SRS1_MDM_AP.
#define BS_RCM_SRS1_MDM_AP (1U) //!< Bit field size in bits for RCM_SRS1_MDM_AP.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RCM_SRS1_MDM_AP field.
#define BR_RCM_SRS1_MDM_AP (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_MDM_AP))
#endif
//@}
/*!
* @name Register RCM_SRS1, field EZPT[4] (RO)
*
* Indicates a reset has been caused by EzPort receiving the RESET command while
* the device is in EzPort mode.
*
* Values:
* - 0 - Reset not caused by EzPort receiving the RESET command while the device
* is in EzPort mode
* - 1 - Reset caused by EzPort receiving the RESET command while the device is
* in EzPort mode
*/
//@{
#define BP_RCM_SRS1_EZPT (4U) //!< Bit position for RCM_SRS1_EZPT.
#define BM_RCM_SRS1_EZPT (0x10U) //!< Bit mask for RCM_SRS1_EZPT.
#define BS_RCM_SRS1_EZPT (1U) //!< Bit field size in bits for RCM_SRS1_EZPT.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RCM_SRS1_EZPT field.
#define BR_RCM_SRS1_EZPT (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_EZPT))
#endif
//@}
/*!
* @name Register RCM_SRS1, field SACKERR[5] (RO)
*
* Indicates that after an attempt to enter Stop mode, a reset has been caused
* by a failure of one or more peripherals to acknowledge within approximately one
* second to enter stop mode.
*
* Values:
* - 0 - Reset not caused by peripheral failure to acknowledge attempt to enter
* stop mode
* - 1 - Reset caused by peripheral failure to acknowledge attempt to enter stop
* mode
*/
//@{
#define BP_RCM_SRS1_SACKERR (5U) //!< Bit position for RCM_SRS1_SACKERR.
#define BM_RCM_SRS1_SACKERR (0x20U) //!< Bit mask for RCM_SRS1_SACKERR.
#define BS_RCM_SRS1_SACKERR (1U) //!< Bit field size in bits for RCM_SRS1_SACKERR.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RCM_SRS1_SACKERR field.
#define BR_RCM_SRS1_SACKERR (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_SACKERR))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_RCM_RPFC - Reset Pin Filter Control register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_RCM_RPFC - Reset Pin Filter Control register (RW)
*
* Reset value: 0x00U
*
* The reset values of bits 2-0 are for Chip POR only. They are unaffected by
* other reset types. The bus clock filter is reset when disabled or when entering
* stop mode. The LPO filter is reset when disabled or when entering any low
* leakage stop mode .
*/
typedef union _hw_rcm_rpfc
{
uint8_t U;
struct _hw_rcm_rpfc_bitfields
{
uint8_t RSTFLTSRW : 2; //!< [1:0] Reset Pin Filter Select in Run and
//! Wait Modes
uint8_t RSTFLTSS : 1; //!< [2] Reset Pin Filter Select in Stop Mode
uint8_t RESERVED0 : 5; //!< [7:3]
} B;
} hw_rcm_rpfc_t;
#endif
/*!
* @name Constants and macros for entire RCM_RPFC register
*/
//@{
#define HW_RCM_RPFC_ADDR (REGS_RCM_BASE + 0x4U)
#ifndef __LANGUAGE_ASM__
#define HW_RCM_RPFC (*(__IO hw_rcm_rpfc_t *) HW_RCM_RPFC_ADDR)
#define HW_RCM_RPFC_RD() (HW_RCM_RPFC.U)
#define HW_RCM_RPFC_WR(v) (HW_RCM_RPFC.U = (v))
#define HW_RCM_RPFC_SET(v) (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() | (v)))
#define HW_RCM_RPFC_CLR(v) (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() & ~(v)))
#define HW_RCM_RPFC_TOG(v) (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() ^ (v)))
#endif
//@}
/*
* Constants & macros for individual RCM_RPFC bitfields
*/
/*!
* @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW)
*
* Selects how the reset pin filter is enabled in run and wait modes.
*
* Values:
* - 00 - All filtering disabled
* - 01 - Bus clock filter enabled for normal operation
* - 10 - LPO clock filter enabled for normal operation
* - 11 - Reserved
*/
//@{
#define BP_RCM_RPFC_RSTFLTSRW (0U) //!< Bit position for RCM_RPFC_RSTFLTSRW.
#define BM_RCM_RPFC_RSTFLTSRW (0x03U) //!< Bit mask for RCM_RPFC_RSTFLTSRW.
#define BS_RCM_RPFC_RSTFLTSRW (2U) //!< Bit field size in bits for RCM_RPFC_RSTFLTSRW.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RCM_RPFC_RSTFLTSRW field.
#define BR_RCM_RPFC_RSTFLTSRW (HW_RCM_RPFC.B.RSTFLTSRW)
#endif
//! @brief Format value for bitfield RCM_RPFC_RSTFLTSRW.
#define BF_RCM_RPFC_RSTFLTSRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFC_RSTFLTSRW), uint8_t) & BM_RCM_RPFC_RSTFLTSRW)
#ifndef __LANGUAGE_ASM__
//! @brief Set the RSTFLTSRW field to a new value.
#define BW_RCM_RPFC_RSTFLTSRW(v) (HW_RCM_RPFC_WR((HW_RCM_RPFC_RD() & ~BM_RCM_RPFC_RSTFLTSRW) | BF_RCM_RPFC_RSTFLTSRW(v)))
#endif
//@}
/*!
* @name Register RCM_RPFC, field RSTFLTSS[2] (RW)
*
* Selects how the reset pin filter is enabled in Stop and VLPS modes
*
* Values:
* - 0 - All filtering disabled
* - 1 - LPO clock filter enabled
*/
//@{
#define BP_RCM_RPFC_RSTFLTSS (2U) //!< Bit position for RCM_RPFC_RSTFLTSS.
#define BM_RCM_RPFC_RSTFLTSS (0x04U) //!< Bit mask for RCM_RPFC_RSTFLTSS.
#define BS_RCM_RPFC_RSTFLTSS (1U) //!< Bit field size in bits for RCM_RPFC_RSTFLTSS.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RCM_RPFC_RSTFLTSS field.
#define BR_RCM_RPFC_RSTFLTSS (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR, BP_RCM_RPFC_RSTFLTSS))
#endif
//! @brief Format value for bitfield RCM_RPFC_RSTFLTSS.
#define BF_RCM_RPFC_RSTFLTSS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFC_RSTFLTSS), uint8_t) & BM_RCM_RPFC_RSTFLTSS)
#ifndef __LANGUAGE_ASM__
//! @brief Set the RSTFLTSS field to a new value.
#define BW_RCM_RPFC_RSTFLTSS(v) (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR, BP_RCM_RPFC_RSTFLTSS) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_RCM_RPFW - Reset Pin Filter Width register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_RCM_RPFW - Reset Pin Filter Width register (RW)
*
* Reset value: 0x00U
*
* The reset values of the bits in the RSTFLTSEL field are for Chip POR only.
* They are unaffected by other reset types.
*/
typedef union _hw_rcm_rpfw
{
uint8_t U;
struct _hw_rcm_rpfw_bitfields
{
uint8_t RSTFLTSEL : 5; //!< [4:0] Reset Pin Filter Bus Clock Select
uint8_t RESERVED0 : 3; //!< [7:5]
} B;
} hw_rcm_rpfw_t;
#endif
/*!
* @name Constants and macros for entire RCM_RPFW register
*/
//@{
#define HW_RCM_RPFW_ADDR (REGS_RCM_BASE + 0x5U)
#ifndef __LANGUAGE_ASM__
#define HW_RCM_RPFW (*(__IO hw_rcm_rpfw_t *) HW_RCM_RPFW_ADDR)
#define HW_RCM_RPFW_RD() (HW_RCM_RPFW.U)
#define HW_RCM_RPFW_WR(v) (HW_RCM_RPFW.U = (v))
#define HW_RCM_RPFW_SET(v) (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() | (v)))
#define HW_RCM_RPFW_CLR(v) (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() & ~(v)))
#define HW_RCM_RPFW_TOG(v) (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() ^ (v)))
#endif
//@}
/*
* Constants & macros for individual RCM_RPFW bitfields
*/
/*!
* @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW)
*
* Selects the reset pin bus clock filter width.
*
* Values:
* - 00000 - Bus clock filter count is 1
* - 00001 - Bus clock filter count is 2
* - 00010 - Bus clock filter count is 3
* - 00011 - Bus clock filter count is 4
* - 00100 - Bus clock filter count is 5
* - 00101 - Bus clock filter count is 6
* - 00110 - Bus clock filter count is 7
* - 00111 - Bus clock filter count is 8
* - 01000 - Bus clock filter count is 9
* - 01001 - Bus clock filter count is 10
* - 01010 - Bus clock filter count is 11
* - 01011 - Bus clock filter count is 12
* - 01100 - Bus clock filter count is 13
* - 01101 - Bus clock filter count is 14
* - 01110 - Bus clock filter count is 15
* - 01111 - Bus clock filter count is 16
* - 10000 - Bus clock filter count is 17
* - 10001 - Bus clock filter count is 18
* - 10010 - Bus clock filter count is 19
* - 10011 - Bus clock filter count is 20
* - 10100 - Bus clock filter count is 21
* - 10101 - Bus clock filter count is 22
* - 10110 - Bus clock filter count is 23
* - 10111 - Bus clock filter count is 24
* - 11000 - Bus clock filter count is 25
* - 11001 - Bus clock filter count is 26
* - 11010 - Bus clock filter count is 27
* - 11011 - Bus clock filter count is 28
* - 11100 - Bus clock filter count is 29
* - 11101 - Bus clock filter count is 30
* - 11110 - Bus clock filter count is 31
* - 11111 - Bus clock filter count is 32
*/
//@{
#define BP_RCM_RPFW_RSTFLTSEL (0U) //!< Bit position for RCM_RPFW_RSTFLTSEL.
#define BM_RCM_RPFW_RSTFLTSEL (0x1FU) //!< Bit mask for RCM_RPFW_RSTFLTSEL.
#define BS_RCM_RPFW_RSTFLTSEL (5U) //!< Bit field size in bits for RCM_RPFW_RSTFLTSEL.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RCM_RPFW_RSTFLTSEL field.
#define BR_RCM_RPFW_RSTFLTSEL (HW_RCM_RPFW.B.RSTFLTSEL)
#endif
//! @brief Format value for bitfield RCM_RPFW_RSTFLTSEL.
#define BF_RCM_RPFW_RSTFLTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFW_RSTFLTSEL), uint8_t) & BM_RCM_RPFW_RSTFLTSEL)
#ifndef __LANGUAGE_ASM__
//! @brief Set the RSTFLTSEL field to a new value.
#define BW_RCM_RPFW_RSTFLTSEL(v) (HW_RCM_RPFW_WR((HW_RCM_RPFW_RD() & ~BM_RCM_RPFW_RSTFLTSEL) | BF_RCM_RPFW_RSTFLTSEL(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_RCM_MR - Mode Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_RCM_MR - Mode Register (RO)
*
* Reset value: 0x00U
*
* This register includes read-only status flags to indicate the state of the
* mode pins during the last Chip Reset.
*/
typedef union _hw_rcm_mr
{
uint8_t U;
struct _hw_rcm_mr_bitfields
{
uint8_t RESERVED0 : 1; //!< [0]
uint8_t EZP_MS : 1; //!< [1] EZP_MS_B pin state
uint8_t RESERVED1 : 6; //!< [7:2]
} B;
} hw_rcm_mr_t;
#endif
/*!
* @name Constants and macros for entire RCM_MR register
*/
//@{
#define HW_RCM_MR_ADDR (REGS_RCM_BASE + 0x7U)
#ifndef __LANGUAGE_ASM__
#define HW_RCM_MR (*(__I hw_rcm_mr_t *) HW_RCM_MR_ADDR)
#define HW_RCM_MR_RD() (HW_RCM_MR.U)
#endif
//@}
/*
* Constants & macros for individual RCM_MR bitfields
*/
/*!
* @name Register RCM_MR, field EZP_MS[1] (RO)
*
* Reflects the state of the EZP_MS pin during the last Chip Reset
*
* Values:
* - 0 - Pin deasserted (logic 1)
* - 1 - Pin asserted (logic 0)
*/
//@{
#define BP_RCM_MR_EZP_MS (1U) //!< Bit position for RCM_MR_EZP_MS.
#define BM_RCM_MR_EZP_MS (0x02U) //!< Bit mask for RCM_MR_EZP_MS.
#define BS_RCM_MR_EZP_MS (1U) //!< Bit field size in bits for RCM_MR_EZP_MS.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RCM_MR_EZP_MS field.
#define BR_RCM_MR_EZP_MS (BITBAND_ACCESS8(HW_RCM_MR_ADDR, BP_RCM_MR_EZP_MS))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_rcm_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All RCM module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_rcm
{
__I hw_rcm_srs0_t SRS0; //!< [0x0] System Reset Status Register 0
__I hw_rcm_srs1_t SRS1; //!< [0x1] System Reset Status Register 1
uint8_t _reserved0[2];
__IO hw_rcm_rpfc_t RPFC; //!< [0x4] Reset Pin Filter Control register
__IO hw_rcm_rpfw_t RPFW; //!< [0x5] Reset Pin Filter Width register
uint8_t _reserved1[1];
__I hw_rcm_mr_t MR; //!< [0x7] Mode Register
} hw_rcm_t;
#pragma pack()
//! @brief Macro to access all RCM registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_RCM</code>.
#define HW_RCM (*(hw_rcm_t *) REGS_RCM_BASE)
#endif
#endif // __HW_RCM_REGISTERS_H__
// v22/130726/0.9
// EOF

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_RFSYS_REGISTERS_H__
#define __HW_RFSYS_REGISTERS_H__
#include "regs.h"
/*
* MK64F12 RFSYS
*
* System register file
*
* Registers defined in this header file:
* - HW_RFSYS_REGn - Register file register
*
* - hw_rfsys_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_RFSYS_BASE
#define HW_RFSYS_INSTANCE_COUNT (1U) //!< Number of instances of the RFSYS module.
#define REGS_RFSYS_BASE (0x40041000U) //!< Base address for RFSYS.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_RFSYS_REGn - Register file register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_RFSYS_REGn - Register file register (RW)
*
* Reset value: 0x00000000U
*
* Each register can be accessed as 8-, 16-, or 32-bits.
*/
typedef union _hw_rfsys_regn
{
uint32_t U;
struct _hw_rfsys_regn_bitfields
{
uint32_t LL : 8; //!< [7:0]
uint32_t LH : 8; //!< [15:8]
uint32_t HL : 8; //!< [23:16]
uint32_t HH : 8; //!< [31:24]
} B;
} hw_rfsys_regn_t;
#endif
/*!
* @name Constants and macros for entire RFSYS_REGn register
*/
//@{
#define HW_RFSYS_REGn_COUNT (8U)
#define HW_RFSYS_REGn_ADDR(n) (REGS_RFSYS_BASE + 0x0U + (0x4U * n))
#ifndef __LANGUAGE_ASM__
#define HW_RFSYS_REGn(n) (*(__IO hw_rfsys_regn_t *) HW_RFSYS_REGn_ADDR(n))
#define HW_RFSYS_REGn_RD(n) (HW_RFSYS_REGn(n).U)
#define HW_RFSYS_REGn_WR(n, v) (HW_RFSYS_REGn(n).U = (v))
#define HW_RFSYS_REGn_SET(n, v) (HW_RFSYS_REGn_WR(n, HW_RFSYS_REGn_RD(n) | (v)))
#define HW_RFSYS_REGn_CLR(n, v) (HW_RFSYS_REGn_WR(n, HW_RFSYS_REGn_RD(n) & ~(v)))
#define HW_RFSYS_REGn_TOG(n, v) (HW_RFSYS_REGn_WR(n, HW_RFSYS_REGn_RD(n) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual RFSYS_REGn bitfields
*/
/*!
* @name Register RFSYS_REGn, field LL[7:0] (RW)
*
* Low lower byte
*/
//@{
#define BP_RFSYS_REGn_LL (0U) //!< Bit position for RFSYS_REGn_LL.
#define BM_RFSYS_REGn_LL (0x000000FFU) //!< Bit mask for RFSYS_REGn_LL.
#define BS_RFSYS_REGn_LL (8U) //!< Bit field size in bits for RFSYS_REGn_LL.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RFSYS_REGn_LL field.
#define BR_RFSYS_REGn_LL(n) (HW_RFSYS_REGn(n).B.LL)
#endif
//! @brief Format value for bitfield RFSYS_REGn_LL.
#define BF_RFSYS_REGn_LL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFSYS_REGn_LL), uint32_t) & BM_RFSYS_REGn_LL)
#ifndef __LANGUAGE_ASM__
//! @brief Set the LL field to a new value.
#define BW_RFSYS_REGn_LL(n, v) (HW_RFSYS_REGn_WR(n, (HW_RFSYS_REGn_RD(n) & ~BM_RFSYS_REGn_LL) | BF_RFSYS_REGn_LL(v)))
#endif
//@}
/*!
* @name Register RFSYS_REGn, field LH[15:8] (RW)
*
* Low higher byte
*/
//@{
#define BP_RFSYS_REGn_LH (8U) //!< Bit position for RFSYS_REGn_LH.
#define BM_RFSYS_REGn_LH (0x0000FF00U) //!< Bit mask for RFSYS_REGn_LH.
#define BS_RFSYS_REGn_LH (8U) //!< Bit field size in bits for RFSYS_REGn_LH.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RFSYS_REGn_LH field.
#define BR_RFSYS_REGn_LH(n) (HW_RFSYS_REGn(n).B.LH)
#endif
//! @brief Format value for bitfield RFSYS_REGn_LH.
#define BF_RFSYS_REGn_LH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFSYS_REGn_LH), uint32_t) & BM_RFSYS_REGn_LH)
#ifndef __LANGUAGE_ASM__
//! @brief Set the LH field to a new value.
#define BW_RFSYS_REGn_LH(n, v) (HW_RFSYS_REGn_WR(n, (HW_RFSYS_REGn_RD(n) & ~BM_RFSYS_REGn_LH) | BF_RFSYS_REGn_LH(v)))
#endif
//@}
/*!
* @name Register RFSYS_REGn, field HL[23:16] (RW)
*
* High lower byte
*/
//@{
#define BP_RFSYS_REGn_HL (16U) //!< Bit position for RFSYS_REGn_HL.
#define BM_RFSYS_REGn_HL (0x00FF0000U) //!< Bit mask for RFSYS_REGn_HL.
#define BS_RFSYS_REGn_HL (8U) //!< Bit field size in bits for RFSYS_REGn_HL.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RFSYS_REGn_HL field.
#define BR_RFSYS_REGn_HL(n) (HW_RFSYS_REGn(n).B.HL)
#endif
//! @brief Format value for bitfield RFSYS_REGn_HL.
#define BF_RFSYS_REGn_HL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFSYS_REGn_HL), uint32_t) & BM_RFSYS_REGn_HL)
#ifndef __LANGUAGE_ASM__
//! @brief Set the HL field to a new value.
#define BW_RFSYS_REGn_HL(n, v) (HW_RFSYS_REGn_WR(n, (HW_RFSYS_REGn_RD(n) & ~BM_RFSYS_REGn_HL) | BF_RFSYS_REGn_HL(v)))
#endif
//@}
/*!
* @name Register RFSYS_REGn, field HH[31:24] (RW)
*
* High higher byte
*/
//@{
#define BP_RFSYS_REGn_HH (24U) //!< Bit position for RFSYS_REGn_HH.
#define BM_RFSYS_REGn_HH (0xFF000000U) //!< Bit mask for RFSYS_REGn_HH.
#define BS_RFSYS_REGn_HH (8U) //!< Bit field size in bits for RFSYS_REGn_HH.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RFSYS_REGn_HH field.
#define BR_RFSYS_REGn_HH(n) (HW_RFSYS_REGn(n).B.HH)
#endif
//! @brief Format value for bitfield RFSYS_REGn_HH.
#define BF_RFSYS_REGn_HH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFSYS_REGn_HH), uint32_t) & BM_RFSYS_REGn_HH)
#ifndef __LANGUAGE_ASM__
//! @brief Set the HH field to a new value.
#define BW_RFSYS_REGn_HH(n, v) (HW_RFSYS_REGn_WR(n, (HW_RFSYS_REGn_RD(n) & ~BM_RFSYS_REGn_HH) | BF_RFSYS_REGn_HH(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_rfsys_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All RFSYS module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_rfsys
{
__IO hw_rfsys_regn_t REGn[8]; //!< [0x0] Register file register
} hw_rfsys_t;
#pragma pack()
//! @brief Macro to access all RFSYS registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_RFSYS</code>.
#define HW_RFSYS (*(hw_rfsys_t *) REGS_RFSYS_BASE)
#endif
#endif // __HW_RFSYS_REGISTERS_H__
// v22/130726/0.9
// EOF

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_RFVBAT_REGISTERS_H__
#define __HW_RFVBAT_REGISTERS_H__
#include "regs.h"
/*
* MK64F12 RFVBAT
*
* VBAT register file
*
* Registers defined in this header file:
* - HW_RFVBAT_REGn - VBAT register file register
*
* - hw_rfvbat_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_RFVBAT_BASE
#define HW_RFVBAT_INSTANCE_COUNT (1U) //!< Number of instances of the RFVBAT module.
#define REGS_RFVBAT_BASE (0x4003E000U) //!< Base address for RFVBAT.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_RFVBAT_REGn - VBAT register file register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_RFVBAT_REGn - VBAT register file register (RW)
*
* Reset value: 0x00000000U
*
* Each register can be accessed as 8-, 16-, or 32-bits.
*/
typedef union _hw_rfvbat_regn
{
uint32_t U;
struct _hw_rfvbat_regn_bitfields
{
uint32_t LL : 8; //!< [7:0]
uint32_t LH : 8; //!< [15:8]
uint32_t HL : 8; //!< [23:16]
uint32_t HH : 8; //!< [31:24]
} B;
} hw_rfvbat_regn_t;
#endif
/*!
* @name Constants and macros for entire RFVBAT_REGn register
*/
//@{
#define HW_RFVBAT_REGn_COUNT (8U)
#define HW_RFVBAT_REGn_ADDR(n) (REGS_RFVBAT_BASE + 0x0U + (0x4U * n))
#ifndef __LANGUAGE_ASM__
#define HW_RFVBAT_REGn(n) (*(__IO hw_rfvbat_regn_t *) HW_RFVBAT_REGn_ADDR(n))
#define HW_RFVBAT_REGn_RD(n) (HW_RFVBAT_REGn(n).U)
#define HW_RFVBAT_REGn_WR(n, v) (HW_RFVBAT_REGn(n).U = (v))
#define HW_RFVBAT_REGn_SET(n, v) (HW_RFVBAT_REGn_WR(n, HW_RFVBAT_REGn_RD(n) | (v)))
#define HW_RFVBAT_REGn_CLR(n, v) (HW_RFVBAT_REGn_WR(n, HW_RFVBAT_REGn_RD(n) & ~(v)))
#define HW_RFVBAT_REGn_TOG(n, v) (HW_RFVBAT_REGn_WR(n, HW_RFVBAT_REGn_RD(n) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual RFVBAT_REGn bitfields
*/
/*!
* @name Register RFVBAT_REGn, field LL[7:0] (RW)
*
* Low lower byte
*/
//@{
#define BP_RFVBAT_REGn_LL (0U) //!< Bit position for RFVBAT_REGn_LL.
#define BM_RFVBAT_REGn_LL (0x000000FFU) //!< Bit mask for RFVBAT_REGn_LL.
#define BS_RFVBAT_REGn_LL (8U) //!< Bit field size in bits for RFVBAT_REGn_LL.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RFVBAT_REGn_LL field.
#define BR_RFVBAT_REGn_LL(n) (HW_RFVBAT_REGn(n).B.LL)
#endif
//! @brief Format value for bitfield RFVBAT_REGn_LL.
#define BF_RFVBAT_REGn_LL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFVBAT_REGn_LL), uint32_t) & BM_RFVBAT_REGn_LL)
#ifndef __LANGUAGE_ASM__
//! @brief Set the LL field to a new value.
#define BW_RFVBAT_REGn_LL(n, v) (HW_RFVBAT_REGn_WR(n, (HW_RFVBAT_REGn_RD(n) & ~BM_RFVBAT_REGn_LL) | BF_RFVBAT_REGn_LL(v)))
#endif
//@}
/*!
* @name Register RFVBAT_REGn, field LH[15:8] (RW)
*
* Low higher byte
*/
//@{
#define BP_RFVBAT_REGn_LH (8U) //!< Bit position for RFVBAT_REGn_LH.
#define BM_RFVBAT_REGn_LH (0x0000FF00U) //!< Bit mask for RFVBAT_REGn_LH.
#define BS_RFVBAT_REGn_LH (8U) //!< Bit field size in bits for RFVBAT_REGn_LH.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RFVBAT_REGn_LH field.
#define BR_RFVBAT_REGn_LH(n) (HW_RFVBAT_REGn(n).B.LH)
#endif
//! @brief Format value for bitfield RFVBAT_REGn_LH.
#define BF_RFVBAT_REGn_LH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFVBAT_REGn_LH), uint32_t) & BM_RFVBAT_REGn_LH)
#ifndef __LANGUAGE_ASM__
//! @brief Set the LH field to a new value.
#define BW_RFVBAT_REGn_LH(n, v) (HW_RFVBAT_REGn_WR(n, (HW_RFVBAT_REGn_RD(n) & ~BM_RFVBAT_REGn_LH) | BF_RFVBAT_REGn_LH(v)))
#endif
//@}
/*!
* @name Register RFVBAT_REGn, field HL[23:16] (RW)
*
* High lower byte
*/
//@{
#define BP_RFVBAT_REGn_HL (16U) //!< Bit position for RFVBAT_REGn_HL.
#define BM_RFVBAT_REGn_HL (0x00FF0000U) //!< Bit mask for RFVBAT_REGn_HL.
#define BS_RFVBAT_REGn_HL (8U) //!< Bit field size in bits for RFVBAT_REGn_HL.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RFVBAT_REGn_HL field.
#define BR_RFVBAT_REGn_HL(n) (HW_RFVBAT_REGn(n).B.HL)
#endif
//! @brief Format value for bitfield RFVBAT_REGn_HL.
#define BF_RFVBAT_REGn_HL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFVBAT_REGn_HL), uint32_t) & BM_RFVBAT_REGn_HL)
#ifndef __LANGUAGE_ASM__
//! @brief Set the HL field to a new value.
#define BW_RFVBAT_REGn_HL(n, v) (HW_RFVBAT_REGn_WR(n, (HW_RFVBAT_REGn_RD(n) & ~BM_RFVBAT_REGn_HL) | BF_RFVBAT_REGn_HL(v)))
#endif
//@}
/*!
* @name Register RFVBAT_REGn, field HH[31:24] (RW)
*
* High higher byte
*/
//@{
#define BP_RFVBAT_REGn_HH (24U) //!< Bit position for RFVBAT_REGn_HH.
#define BM_RFVBAT_REGn_HH (0xFF000000U) //!< Bit mask for RFVBAT_REGn_HH.
#define BS_RFVBAT_REGn_HH (8U) //!< Bit field size in bits for RFVBAT_REGn_HH.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RFVBAT_REGn_HH field.
#define BR_RFVBAT_REGn_HH(n) (HW_RFVBAT_REGn(n).B.HH)
#endif
//! @brief Format value for bitfield RFVBAT_REGn_HH.
#define BF_RFVBAT_REGn_HH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFVBAT_REGn_HH), uint32_t) & BM_RFVBAT_REGn_HH)
#ifndef __LANGUAGE_ASM__
//! @brief Set the HH field to a new value.
#define BW_RFVBAT_REGn_HH(n, v) (HW_RFVBAT_REGn_WR(n, (HW_RFVBAT_REGn_RD(n) & ~BM_RFVBAT_REGn_HH) | BF_RFVBAT_REGn_HH(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_rfvbat_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All RFVBAT module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_rfvbat
{
__IO hw_rfvbat_regn_t REGn[8]; //!< [0x0] VBAT register file register
} hw_rfvbat_t;
#pragma pack()
//! @brief Macro to access all RFVBAT registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_RFVBAT</code>.
#define HW_RFVBAT (*(hw_rfvbat_t *) REGS_RFVBAT_BASE)
#endif
#endif // __HW_RFVBAT_REGISTERS_H__
// v22/130726/0.9
// EOF

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_RNG_REGISTERS_H__
#define __HW_RNG_REGISTERS_H__
#include "regs.h"
/*
* MK64F12 RNG
*
* Random Number Generator Accelerator
*
* Registers defined in this header file:
* - HW_RNG_CR - RNGA Control Register
* - HW_RNG_SR - RNGA Status Register
* - HW_RNG_ER - RNGA Entropy Register
* - HW_RNG_OR - RNGA Output Register
*
* - hw_rng_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_RNG_BASE
#define HW_RNG_INSTANCE_COUNT (1U) //!< Number of instances of the RNG module.
#define REGS_RNG_BASE (0x40029000U) //!< Base address for RNG.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_RNG_CR - RNGA Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_RNG_CR - RNGA Control Register (RW)
*
* Reset value: 0x00000000U
*
* Controls the operation of RNGA.
*/
typedef union _hw_rng_cr
{
uint32_t U;
struct _hw_rng_cr_bitfields
{
uint32_t GO : 1; //!< [0] Go
uint32_t HA : 1; //!< [1] High Assurance
uint32_t INTM : 1; //!< [2] Interrupt Mask
uint32_t CLRI : 1; //!< [3] Clear Interrupt
uint32_t SLP : 1; //!< [4] Sleep
uint32_t RESERVED0 : 27; //!< [31:5]
} B;
} hw_rng_cr_t;
#endif
/*!
* @name Constants and macros for entire RNG_CR register
*/
//@{
#define HW_RNG_CR_ADDR (REGS_RNG_BASE + 0x0U)
#ifndef __LANGUAGE_ASM__
#define HW_RNG_CR (*(__IO hw_rng_cr_t *) HW_RNG_CR_ADDR)
#define HW_RNG_CR_RD() (HW_RNG_CR.U)
#define HW_RNG_CR_WR(v) (HW_RNG_CR.U = (v))
#define HW_RNG_CR_SET(v) (HW_RNG_CR_WR(HW_RNG_CR_RD() | (v)))
#define HW_RNG_CR_CLR(v) (HW_RNG_CR_WR(HW_RNG_CR_RD() & ~(v)))
#define HW_RNG_CR_TOG(v) (HW_RNG_CR_WR(HW_RNG_CR_RD() ^ (v)))
#endif
//@}
/*
* Constants & macros for individual RNG_CR bitfields
*/
/*!
* @name Register RNG_CR, field GO[0] (RW)
*
* Specifies whether random-data generation and loading (into OR[RANDOUT]) is
* enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
* OR[RANDOUT] with data.
*
* Values:
* - 0 - Disabled
* - 1 - Enabled
*/
//@{
#define BP_RNG_CR_GO (0U) //!< Bit position for RNG_CR_GO.
#define BM_RNG_CR_GO (0x00000001U) //!< Bit mask for RNG_CR_GO.
#define BS_RNG_CR_GO (1U) //!< Bit field size in bits for RNG_CR_GO.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RNG_CR_GO field.
#define BR_RNG_CR_GO (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_GO))
#endif
//! @brief Format value for bitfield RNG_CR_GO.
#define BF_RNG_CR_GO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_GO), uint32_t) & BM_RNG_CR_GO)
#ifndef __LANGUAGE_ASM__
//! @brief Set the GO field to a new value.
#define BW_RNG_CR_GO(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_GO) = (v))
#endif
//@}
/*!
* @name Register RNG_CR, field HA[1] (RW)
*
* Enables notification of security violations (via SR[SECV]). A security
* violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky.
* After enabling notification of security violations, you must reset RNGA to
* disable them again.
*
* Values:
* - 0 - Disabled
* - 1 - Enabled
*/
//@{
#define BP_RNG_CR_HA (1U) //!< Bit position for RNG_CR_HA.
#define BM_RNG_CR_HA (0x00000002U) //!< Bit mask for RNG_CR_HA.
#define BS_RNG_CR_HA (1U) //!< Bit field size in bits for RNG_CR_HA.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RNG_CR_HA field.
#define BR_RNG_CR_HA (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_HA))
#endif
//! @brief Format value for bitfield RNG_CR_HA.
#define BF_RNG_CR_HA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_HA), uint32_t) & BM_RNG_CR_HA)
#ifndef __LANGUAGE_ASM__
//! @brief Set the HA field to a new value.
#define BW_RNG_CR_HA(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_HA) = (v))
#endif
//@}
/*!
* @name Register RNG_CR, field INTM[2] (RW)
*
* Masks the triggering of an error interrupt to the interrupt controller when
* an OR underflow condition occurs. An OR underflow condition occurs when you
* read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description.
*
* Values:
* - 0 - Not masked
* - 1 - Masked
*/
//@{
#define BP_RNG_CR_INTM (2U) //!< Bit position for RNG_CR_INTM.
#define BM_RNG_CR_INTM (0x00000004U) //!< Bit mask for RNG_CR_INTM.
#define BS_RNG_CR_INTM (1U) //!< Bit field size in bits for RNG_CR_INTM.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RNG_CR_INTM field.
#define BR_RNG_CR_INTM (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_INTM))
#endif
//! @brief Format value for bitfield RNG_CR_INTM.
#define BF_RNG_CR_INTM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_INTM), uint32_t) & BM_RNG_CR_INTM)
#ifndef __LANGUAGE_ASM__
//! @brief Set the INTM field to a new value.
#define BW_RNG_CR_INTM(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_INTM) = (v))
#endif
//@}
/*!
* @name Register RNG_CR, field CLRI[3] (WORZ)
*
* Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]).
*
* Values:
* - 0 - Do not clear the interrupt.
* - 1 - Clear the interrupt. When you write 1 to this field, RNGA then resets
* the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
*/
//@{
#define BP_RNG_CR_CLRI (3U) //!< Bit position for RNG_CR_CLRI.
#define BM_RNG_CR_CLRI (0x00000008U) //!< Bit mask for RNG_CR_CLRI.
#define BS_RNG_CR_CLRI (1U) //!< Bit field size in bits for RNG_CR_CLRI.
//! @brief Format value for bitfield RNG_CR_CLRI.
#define BF_RNG_CR_CLRI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_CLRI), uint32_t) & BM_RNG_CR_CLRI)
#ifndef __LANGUAGE_ASM__
//! @brief Set the CLRI field to a new value.
#define BW_RNG_CR_CLRI(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_CLRI) = (v))
#endif
//@}
/*!
* @name Register RNG_CR, field SLP[4] (RW)
*
* Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
* mode by asserting the DOZE signal.
*
* Values:
* - 0 - Normal mode
* - 1 - Sleep (low-power) mode
*/
//@{
#define BP_RNG_CR_SLP (4U) //!< Bit position for RNG_CR_SLP.
#define BM_RNG_CR_SLP (0x00000010U) //!< Bit mask for RNG_CR_SLP.
#define BS_RNG_CR_SLP (1U) //!< Bit field size in bits for RNG_CR_SLP.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RNG_CR_SLP field.
#define BR_RNG_CR_SLP (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_SLP))
#endif
//! @brief Format value for bitfield RNG_CR_SLP.
#define BF_RNG_CR_SLP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_SLP), uint32_t) & BM_RNG_CR_SLP)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SLP field to a new value.
#define BW_RNG_CR_SLP(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_SLP) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_RNG_SR - RNGA Status Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_RNG_SR - RNGA Status Register (RO)
*
* Reset value: 0x00010000U
*
* Indicates the status of RNGA. This register is read-only.
*/
typedef union _hw_rng_sr
{
uint32_t U;
struct _hw_rng_sr_bitfields
{
uint32_t SECV : 1; //!< [0] Security Violation
uint32_t LRS : 1; //!< [1] Last Read Status
uint32_t ORU : 1; //!< [2] Output Register Underflow
uint32_t ERRI : 1; //!< [3] Error Interrupt
uint32_t SLP : 1; //!< [4] Sleep
uint32_t RESERVED0 : 3; //!< [7:5]
uint32_t OREG_LVL : 8; //!< [15:8] Output Register Level
uint32_t OREG_SIZE : 8; //!< [23:16] Output Register Size
uint32_t RESERVED1 : 8; //!< [31:24]
} B;
} hw_rng_sr_t;
#endif
/*!
* @name Constants and macros for entire RNG_SR register
*/
//@{
#define HW_RNG_SR_ADDR (REGS_RNG_BASE + 0x4U)
#ifndef __LANGUAGE_ASM__
#define HW_RNG_SR (*(__I hw_rng_sr_t *) HW_RNG_SR_ADDR)
#define HW_RNG_SR_RD() (HW_RNG_SR.U)
#endif
//@}
/*
* Constants & macros for individual RNG_SR bitfields
*/
/*!
* @name Register RNG_SR, field SECV[0] (RO)
*
* Used only when high assurance is enabled (CR[HA]). Indicates that a security
* violation has occurred.This field is sticky. To clear SR[SECV], you must reset
* RNGA.
*
* Values:
* - 0 - No security violation
* - 1 - Security violation
*/
//@{
#define BP_RNG_SR_SECV (0U) //!< Bit position for RNG_SR_SECV.
#define BM_RNG_SR_SECV (0x00000001U) //!< Bit mask for RNG_SR_SECV.
#define BS_RNG_SR_SECV (1U) //!< Bit field size in bits for RNG_SR_SECV.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RNG_SR_SECV field.
#define BR_RNG_SR_SECV (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_SECV))
#endif
//@}
/*!
* @name Register RNG_SR, field LRS[1] (RO)
*
* Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow
* condition, regardless of whether the error interrupt is masked (CR[INTM]). An
* OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0.
* After you read this register, RNGA writes 0 to this field.
*
* Values:
* - 0 - No underflow
* - 1 - Underflow
*/
//@{
#define BP_RNG_SR_LRS (1U) //!< Bit position for RNG_SR_LRS.
#define BM_RNG_SR_LRS (0x00000002U) //!< Bit mask for RNG_SR_LRS.
#define BS_RNG_SR_LRS (1U) //!< Bit field size in bits for RNG_SR_LRS.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RNG_SR_LRS field.
#define BR_RNG_SR_LRS (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_LRS))
#endif
//@}
/*!
* @name Register RNG_SR, field ORU[2] (RO)
*
* Indicates whether an OR underflow condition has occurred since you last read
* this register (SR) or RNGA was reset, regardless of whether the error
* interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read
* OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this
* field.
*
* Values:
* - 0 - No underflow
* - 1 - Underflow
*/
//@{
#define BP_RNG_SR_ORU (2U) //!< Bit position for RNG_SR_ORU.
#define BM_RNG_SR_ORU (0x00000004U) //!< Bit mask for RNG_SR_ORU.
#define BS_RNG_SR_ORU (1U) //!< Bit field size in bits for RNG_SR_ORU.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RNG_SR_ORU field.
#define BR_RNG_SR_ORU (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_ORU))
#endif
//@}
/*!
* @name Register RNG_SR, field ERRI[3] (RO)
*
* Indicates whether an OR underflow condition has occurred since you last
* cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the
* error interrupt is masked (CR[INTM]). An OR underflow condition occurs when
* you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt
* indicator (via CR[CLRI]), RNGA writes 0 to this field.
*
* Values:
* - 0 - No underflow
* - 1 - Underflow
*/
//@{
#define BP_RNG_SR_ERRI (3U) //!< Bit position for RNG_SR_ERRI.
#define BM_RNG_SR_ERRI (0x00000008U) //!< Bit mask for RNG_SR_ERRI.
#define BS_RNG_SR_ERRI (1U) //!< Bit field size in bits for RNG_SR_ERRI.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RNG_SR_ERRI field.
#define BR_RNG_SR_ERRI (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_ERRI))
#endif
//@}
/*!
* @name Register RNG_SR, field SLP[4] (RO)
*
* Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
* mode by asserting the DOZE signal.
*
* Values:
* - 0 - Normal mode
* - 1 - Sleep (low-power) mode
*/
//@{
#define BP_RNG_SR_SLP (4U) //!< Bit position for RNG_SR_SLP.
#define BM_RNG_SR_SLP (0x00000010U) //!< Bit mask for RNG_SR_SLP.
#define BS_RNG_SR_SLP (1U) //!< Bit field size in bits for RNG_SR_SLP.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RNG_SR_SLP field.
#define BR_RNG_SR_SLP (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_SLP))
#endif
//@}
/*!
* @name Register RNG_SR, field OREG_LVL[15:8] (RO)
*
* Indicates the number of random-data words that are in OR[RANDOUT], which
* indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
* is not 0, then the contents of a random number contained in OR[RANDOUT] are
* returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
*
* Values:
* - 0 - No words (empty)
* - 1 - One word (valid)
*/
//@{
#define BP_RNG_SR_OREG_LVL (8U) //!< Bit position for RNG_SR_OREG_LVL.
#define BM_RNG_SR_OREG_LVL (0x0000FF00U) //!< Bit mask for RNG_SR_OREG_LVL.
#define BS_RNG_SR_OREG_LVL (8U) //!< Bit field size in bits for RNG_SR_OREG_LVL.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RNG_SR_OREG_LVL field.
#define BR_RNG_SR_OREG_LVL (HW_RNG_SR.B.OREG_LVL)
#endif
//@}
/*!
* @name Register RNG_SR, field OREG_SIZE[23:16] (RO)
*
* Indicates the size of the Output (OR) register in terms of the number of
* 32-bit random-data words it can hold.
*
* Values:
* - 1 - One word (this value is fixed)
*/
//@{
#define BP_RNG_SR_OREG_SIZE (16U) //!< Bit position for RNG_SR_OREG_SIZE.
#define BM_RNG_SR_OREG_SIZE (0x00FF0000U) //!< Bit mask for RNG_SR_OREG_SIZE.
#define BS_RNG_SR_OREG_SIZE (8U) //!< Bit field size in bits for RNG_SR_OREG_SIZE.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RNG_SR_OREG_SIZE field.
#define BR_RNG_SR_OREG_SIZE (HW_RNG_SR.B.OREG_SIZE)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_RNG_ER - RNGA Entropy Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_RNG_ER - RNGA Entropy Register (WORZ)
*
* Reset value: 0x00000000U
*
* Specifies an entropy value that RNGA uses in addition to its ring oscillators
* to seed its pseudorandom algorithm. This is a write-only register; reads
* return all zeros.
*/
typedef union _hw_rng_er
{
uint32_t U;
struct _hw_rng_er_bitfields
{
uint32_t EXT_ENT : 32; //!< [31:0] External Entropy
} B;
} hw_rng_er_t;
#endif
/*!
* @name Constants and macros for entire RNG_ER register
*/
//@{
#define HW_RNG_ER_ADDR (REGS_RNG_BASE + 0x8U)
#ifndef __LANGUAGE_ASM__
#define HW_RNG_ER (*(__O hw_rng_er_t *) HW_RNG_ER_ADDR)
#define HW_RNG_ER_RD() (HW_RNG_ER.U)
#define HW_RNG_ER_WR(v) (HW_RNG_ER.U = (v))
#endif
//@}
/*
* Constants & macros for individual RNG_ER bitfields
*/
/*!
* @name Register RNG_ER, field EXT_ENT[31:0] (WORZ)
*
* Specifies an entropy value that RNGA uses in addition to its ring oscillators
* to seed its pseudorandom algorithm.Specifying a value for this field is
* optional but recommended. You can write to this field at any time during operation.
*/
//@{
#define BP_RNG_ER_EXT_ENT (0U) //!< Bit position for RNG_ER_EXT_ENT.
#define BM_RNG_ER_EXT_ENT (0xFFFFFFFFU) //!< Bit mask for RNG_ER_EXT_ENT.
#define BS_RNG_ER_EXT_ENT (32U) //!< Bit field size in bits for RNG_ER_EXT_ENT.
//! @brief Format value for bitfield RNG_ER_EXT_ENT.
#define BF_RNG_ER_EXT_ENT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_ER_EXT_ENT), uint32_t) & BM_RNG_ER_EXT_ENT)
#ifndef __LANGUAGE_ASM__
//! @brief Set the EXT_ENT field to a new value.
#define BW_RNG_ER_EXT_ENT(v) (HW_RNG_ER_WR(v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_RNG_OR - RNGA Output Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_RNG_OR - RNGA Output Register (RO)
*
* Reset value: 0x00000000U
*
* Stores a random-data word generated by RNGA.
*/
typedef union _hw_rng_or
{
uint32_t U;
struct _hw_rng_or_bitfields
{
uint32_t RANDOUT : 32; //!< [31:0] Random Output
} B;
} hw_rng_or_t;
#endif
/*!
* @name Constants and macros for entire RNG_OR register
*/
//@{
#define HW_RNG_OR_ADDR (REGS_RNG_BASE + 0xCU)
#ifndef __LANGUAGE_ASM__
#define HW_RNG_OR (*(__I hw_rng_or_t *) HW_RNG_OR_ADDR)
#define HW_RNG_OR_RD() (HW_RNG_OR.U)
#endif
//@}
/*
* Constants & macros for individual RNG_OR bitfields
*/
/*!
* @name Register RNG_OR, field RANDOUT[31:0] (RO)
*
* Stores a random-data word generated by RNGA. This is a read-only field.Before
* reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1).
*
* Values:
* - 0 - Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is
* 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error
* interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt
* request to the interrupt controller).
*/
//@{
#define BP_RNG_OR_RANDOUT (0U) //!< Bit position for RNG_OR_RANDOUT.
#define BM_RNG_OR_RANDOUT (0xFFFFFFFFU) //!< Bit mask for RNG_OR_RANDOUT.
#define BS_RNG_OR_RANDOUT (32U) //!< Bit field size in bits for RNG_OR_RANDOUT.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the RNG_OR_RANDOUT field.
#define BR_RNG_OR_RANDOUT (HW_RNG_OR.U)
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_rng_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All RNG module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_rng
{
__IO hw_rng_cr_t CR; //!< [0x0] RNGA Control Register
__I hw_rng_sr_t SR; //!< [0x4] RNGA Status Register
__O hw_rng_er_t ER; //!< [0x8] RNGA Entropy Register
__I hw_rng_or_t OR; //!< [0xC] RNGA Output Register
} hw_rng_t;
#pragma pack()
//! @brief Macro to access all RNG registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_RNG</code>.
#define HW_RNG (*(hw_rng_t *) REGS_RNG_BASE)
#endif
#endif // __HW_RNG_REGISTERS_H__
// v22/130726/0.9
// EOF

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_SMC_REGISTERS_H__
#define __HW_SMC_REGISTERS_H__
#include "regs.h"
/*
* MK64F12 SMC
*
* System Mode Controller
*
* Registers defined in this header file:
* - HW_SMC_PMPROT - Power Mode Protection register
* - HW_SMC_PMCTRL - Power Mode Control register
* - HW_SMC_VLLSCTRL - VLLS Control register
* - HW_SMC_PMSTAT - Power Mode Status register
*
* - hw_smc_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_SMC_BASE
#define HW_SMC_INSTANCE_COUNT (1U) //!< Number of instances of the SMC module.
#define REGS_SMC_BASE (0x4007E000U) //!< Base address for SMC.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_SMC_PMPROT - Power Mode Protection register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_SMC_PMPROT - Power Mode Protection register (RW)
*
* Reset value: 0x00U
*
* This register provides protection for entry into any low-power run or stop
* mode. The enabling of the low-power run or stop mode occurs by configuring the
* Power Mode Control register (PMCTRL). The PMPROT register can be written only
* once after any system reset. If the MCU is configured for a disallowed or
* reserved power mode, the MCU remains in its current power mode. For example, if the
* MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
* PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
* still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
* reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
* that do not trigger Chip Reset not VLLS. See the Reset section details for more
* information.
*/
typedef union _hw_smc_pmprot
{
uint8_t U;
struct _hw_smc_pmprot_bitfields
{
uint8_t RESERVED0 : 1; //!< [0]
uint8_t AVLLS : 1; //!< [1] Allow Very-Low-Leakage Stop Mode
uint8_t RESERVED1 : 1; //!< [2]
uint8_t ALLS : 1; //!< [3] Allow Low-Leakage Stop Mode
uint8_t RESERVED2 : 1; //!< [4]
uint8_t AVLP : 1; //!< [5] Allow Very-Low-Power Modes
uint8_t RESERVED3 : 2; //!< [7:6]
} B;
} hw_smc_pmprot_t;
#endif
/*!
* @name Constants and macros for entire SMC_PMPROT register
*/
//@{
#define HW_SMC_PMPROT_ADDR (REGS_SMC_BASE + 0x0U)
#ifndef __LANGUAGE_ASM__
#define HW_SMC_PMPROT (*(__IO hw_smc_pmprot_t *) HW_SMC_PMPROT_ADDR)
#define HW_SMC_PMPROT_RD() (HW_SMC_PMPROT.U)
#define HW_SMC_PMPROT_WR(v) (HW_SMC_PMPROT.U = (v))
#define HW_SMC_PMPROT_SET(v) (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() | (v)))
#define HW_SMC_PMPROT_CLR(v) (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() & ~(v)))
#define HW_SMC_PMPROT_TOG(v) (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() ^ (v)))
#endif
//@}
/*
* Constants & macros for individual SMC_PMPROT bitfields
*/
/*!
* @name Register SMC_PMPROT, field AVLLS[1] (RW)
*
* Provided the appropriate control bits are set up in PMCTRL, this write once
* bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
*
* Values:
* - 0 - Any VLLSx mode is not allowed
* - 1 - Any VLLSx mode is allowed
*/
//@{
#define BP_SMC_PMPROT_AVLLS (1U) //!< Bit position for SMC_PMPROT_AVLLS.
#define BM_SMC_PMPROT_AVLLS (0x02U) //!< Bit mask for SMC_PMPROT_AVLLS.
#define BS_SMC_PMPROT_AVLLS (1U) //!< Bit field size in bits for SMC_PMPROT_AVLLS.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the SMC_PMPROT_AVLLS field.
#define BR_SMC_PMPROT_AVLLS (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLLS))
#endif
//! @brief Format value for bitfield SMC_PMPROT_AVLLS.
#define BF_SMC_PMPROT_AVLLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_AVLLS), uint8_t) & BM_SMC_PMPROT_AVLLS)
#ifndef __LANGUAGE_ASM__
//! @brief Set the AVLLS field to a new value.
#define BW_SMC_PMPROT_AVLLS(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLLS) = (v))
#endif
//@}
/*!
* @name Register SMC_PMPROT, field ALLS[3] (RW)
*
* Provided the appropriate control bits are set up in PMCTRL, this write-once
* field allows the MCU to enter any low-leakage stop mode (LLS).
*
* Values:
* - 0 - LLS is not allowed
* - 1 - LLS is allowed
*/
//@{
#define BP_SMC_PMPROT_ALLS (3U) //!< Bit position for SMC_PMPROT_ALLS.
#define BM_SMC_PMPROT_ALLS (0x08U) //!< Bit mask for SMC_PMPROT_ALLS.
#define BS_SMC_PMPROT_ALLS (1U) //!< Bit field size in bits for SMC_PMPROT_ALLS.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the SMC_PMPROT_ALLS field.
#define BR_SMC_PMPROT_ALLS (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_ALLS))
#endif
//! @brief Format value for bitfield SMC_PMPROT_ALLS.
#define BF_SMC_PMPROT_ALLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_ALLS), uint8_t) & BM_SMC_PMPROT_ALLS)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ALLS field to a new value.
#define BW_SMC_PMPROT_ALLS(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_ALLS) = (v))
#endif
//@}
/*!
* @name Register SMC_PMPROT, field AVLP[5] (RW)
*
* Provided the appropriate control bits are set up in PMCTRL, this write-once
* field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
*
* Values:
* - 0 - VLPR, VLPW, and VLPS are not allowed.
* - 1 - VLPR, VLPW, and VLPS are allowed.
*/
//@{
#define BP_SMC_PMPROT_AVLP (5U) //!< Bit position for SMC_PMPROT_AVLP.
#define BM_SMC_PMPROT_AVLP (0x20U) //!< Bit mask for SMC_PMPROT_AVLP.
#define BS_SMC_PMPROT_AVLP (1U) //!< Bit field size in bits for SMC_PMPROT_AVLP.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the SMC_PMPROT_AVLP field.
#define BR_SMC_PMPROT_AVLP (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLP))
#endif
//! @brief Format value for bitfield SMC_PMPROT_AVLP.
#define BF_SMC_PMPROT_AVLP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_AVLP), uint8_t) & BM_SMC_PMPROT_AVLP)
#ifndef __LANGUAGE_ASM__
//! @brief Set the AVLP field to a new value.
#define BW_SMC_PMPROT_AVLP(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLP) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_SMC_PMCTRL - Power Mode Control register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_SMC_PMCTRL - Power Mode Control register (RW)
*
* Reset value: 0x00U
*
* The PMCTRL register controls entry into low-power Run and Stop modes,
* provided that the selected power mode is allowed via an appropriate setting of the
* protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
* reset types that trigger Chip POR not VLLS. It is unaffected by reset types
* that do not trigger Chip POR not VLLS. See the Reset section details for more
* information.
*/
typedef union _hw_smc_pmctrl
{
uint8_t U;
struct _hw_smc_pmctrl_bitfields
{
uint8_t STOPM : 3; //!< [2:0] Stop Mode Control
uint8_t STOPA : 1; //!< [3] Stop Aborted
uint8_t RESERVED0 : 1; //!< [4]
uint8_t RUNM : 2; //!< [6:5] Run Mode Control
uint8_t LPWUI : 1; //!< [7] Low-Power Wake Up On Interrupt
} B;
} hw_smc_pmctrl_t;
#endif
/*!
* @name Constants and macros for entire SMC_PMCTRL register
*/
//@{
#define HW_SMC_PMCTRL_ADDR (REGS_SMC_BASE + 0x1U)
#ifndef __LANGUAGE_ASM__
#define HW_SMC_PMCTRL (*(__IO hw_smc_pmctrl_t *) HW_SMC_PMCTRL_ADDR)
#define HW_SMC_PMCTRL_RD() (HW_SMC_PMCTRL.U)
#define HW_SMC_PMCTRL_WR(v) (HW_SMC_PMCTRL.U = (v))
#define HW_SMC_PMCTRL_SET(v) (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() | (v)))
#define HW_SMC_PMCTRL_CLR(v) (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() & ~(v)))
#define HW_SMC_PMCTRL_TOG(v) (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() ^ (v)))
#endif
//@}
/*
* Constants & macros for individual SMC_PMCTRL bitfields
*/
/*!
* @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
*
* When written, controls entry into the selected stop mode when Sleep-Now or
* Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
* blocked if the protection level has not been enabled using the PMPROT register.
* After any system reset, this field is cleared by hardware on any successful write
* to the PMPROT register. When set to VLLSx, the VLLSM field in the VLLSCTRL
* register is used to further select the particular VLLS submode which will be
* entered.
*
* Values:
* - 000 - Normal Stop (STOP)
* - 001 - Reserved
* - 010 - Very-Low-Power Stop (VLPS)
* - 011 - Low-Leakage Stop (LLS)
* - 100 - Very-Low-Leakage Stop (VLLSx)
* - 101 - Reserved
* - 110 - Reseved
* - 111 - Reserved
*/
//@{
#define BP_SMC_PMCTRL_STOPM (0U) //!< Bit position for SMC_PMCTRL_STOPM.
#define BM_SMC_PMCTRL_STOPM (0x07U) //!< Bit mask for SMC_PMCTRL_STOPM.
#define BS_SMC_PMCTRL_STOPM (3U) //!< Bit field size in bits for SMC_PMCTRL_STOPM.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the SMC_PMCTRL_STOPM field.
#define BR_SMC_PMCTRL_STOPM (HW_SMC_PMCTRL.B.STOPM)
#endif
//! @brief Format value for bitfield SMC_PMCTRL_STOPM.
#define BF_SMC_PMCTRL_STOPM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_STOPM), uint8_t) & BM_SMC_PMCTRL_STOPM)
#ifndef __LANGUAGE_ASM__
//! @brief Set the STOPM field to a new value.
#define BW_SMC_PMCTRL_STOPM(v) (HW_SMC_PMCTRL_WR((HW_SMC_PMCTRL_RD() & ~BM_SMC_PMCTRL_STOPM) | BF_SMC_PMCTRL_STOPM(v)))
#endif
//@}
/*!
* @name Register SMC_PMCTRL, field STOPA[3] (RO)
*
* When set, this read-only status bit indicates an interrupt or reset occured
* during the previous stop mode entry sequence, preventing the system from
* entering that mode. This field is cleared by hardware at the beginning of any stop
* mode entry sequence and is set if the sequence was aborted.
*
* Values:
* - 0 - The previous stop mode entry was successsful.
* - 1 - The previous stop mode entry was aborted.
*/
//@{
#define BP_SMC_PMCTRL_STOPA (3U) //!< Bit position for SMC_PMCTRL_STOPA.
#define BM_SMC_PMCTRL_STOPA (0x08U) //!< Bit mask for SMC_PMCTRL_STOPA.
#define BS_SMC_PMCTRL_STOPA (1U) //!< Bit field size in bits for SMC_PMCTRL_STOPA.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the SMC_PMCTRL_STOPA field.
#define BR_SMC_PMCTRL_STOPA (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_STOPA))
#endif
//@}
/*!
* @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
*
* When written, causes entry into the selected run mode. Writes to this field
* are blocked if the protection level has not been enabled using the PMPROT
* register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
* VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR.
*
* Values:
* - 00 - Normal Run mode (RUN)
* - 01 - Reserved
* - 10 - Very-Low-Power Run mode (VLPR)
* - 11 - Reserved
*/
//@{
#define BP_SMC_PMCTRL_RUNM (5U) //!< Bit position for SMC_PMCTRL_RUNM.
#define BM_SMC_PMCTRL_RUNM (0x60U) //!< Bit mask for SMC_PMCTRL_RUNM.
#define BS_SMC_PMCTRL_RUNM (2U) //!< Bit field size in bits for SMC_PMCTRL_RUNM.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the SMC_PMCTRL_RUNM field.
#define BR_SMC_PMCTRL_RUNM (HW_SMC_PMCTRL.B.RUNM)
#endif
//! @brief Format value for bitfield SMC_PMCTRL_RUNM.
#define BF_SMC_PMCTRL_RUNM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_RUNM), uint8_t) & BM_SMC_PMCTRL_RUNM)
#ifndef __LANGUAGE_ASM__
//! @brief Set the RUNM field to a new value.
#define BW_SMC_PMCTRL_RUNM(v) (HW_SMC_PMCTRL_WR((HW_SMC_PMCTRL_RD() & ~BM_SMC_PMCTRL_RUNM) | BF_SMC_PMCTRL_RUNM(v)))
#endif
//@}
/*!
* @name Register SMC_PMCTRL, field LPWUI[7] (RW)
*
* Causes the SMC to exit to normal RUN mode when any active MCU interrupt
* occurs while in a VLP mode (VLPR, VLPW or VLPS). If VLPS mode was entered directly
* from RUN mode, the SMC will always exit back to normal RUN mode regardless of
* the LPWUI setting. LPWUI must be modified only while the system is in RUN
* mode, that is, when PMSTAT=RUN.
*
* Values:
* - 0 - The system remains in a VLP mode on an interrupt
* - 1 - The system exits to Normal RUN mode on an interrupt
*/
//@{
#define BP_SMC_PMCTRL_LPWUI (7U) //!< Bit position for SMC_PMCTRL_LPWUI.
#define BM_SMC_PMCTRL_LPWUI (0x80U) //!< Bit mask for SMC_PMCTRL_LPWUI.
#define BS_SMC_PMCTRL_LPWUI (1U) //!< Bit field size in bits for SMC_PMCTRL_LPWUI.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the SMC_PMCTRL_LPWUI field.
#define BR_SMC_PMCTRL_LPWUI (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_LPWUI))
#endif
//! @brief Format value for bitfield SMC_PMCTRL_LPWUI.
#define BF_SMC_PMCTRL_LPWUI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_LPWUI), uint8_t) & BM_SMC_PMCTRL_LPWUI)
#ifndef __LANGUAGE_ASM__
//! @brief Set the LPWUI field to a new value.
#define BW_SMC_PMCTRL_LPWUI(v) (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_LPWUI) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_SMC_VLLSCTRL - VLLS Control register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_SMC_VLLSCTRL - VLLS Control register (RW)
*
* Reset value: 0x03U
*
* The VLLSCTRL register controls features related to VLLS modes. This register
* is reset on Chip POR not VLLS and by reset types that trigger Chip POR not
* VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See
* the Reset section details for more information.
*/
typedef union _hw_smc_vllsctrl
{
uint8_t U;
struct _hw_smc_vllsctrl_bitfields
{
uint8_t VLLSM : 3; //!< [2:0] VLLS Mode Control
uint8_t RESERVED0 : 2; //!< [4:3]
uint8_t PORPO : 1; //!< [5] POR Power Option
uint8_t RESERVED1 : 2; //!< [7:6]
} B;
} hw_smc_vllsctrl_t;
#endif
/*!
* @name Constants and macros for entire SMC_VLLSCTRL register
*/
//@{
#define HW_SMC_VLLSCTRL_ADDR (REGS_SMC_BASE + 0x2U)
#ifndef __LANGUAGE_ASM__
#define HW_SMC_VLLSCTRL (*(__IO hw_smc_vllsctrl_t *) HW_SMC_VLLSCTRL_ADDR)
#define HW_SMC_VLLSCTRL_RD() (HW_SMC_VLLSCTRL.U)
#define HW_SMC_VLLSCTRL_WR(v) (HW_SMC_VLLSCTRL.U = (v))
#define HW_SMC_VLLSCTRL_SET(v) (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() | (v)))
#define HW_SMC_VLLSCTRL_CLR(v) (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() & ~(v)))
#define HW_SMC_VLLSCTRL_TOG(v) (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() ^ (v)))
#endif
//@}
/*
* Constants & macros for individual SMC_VLLSCTRL bitfields
*/
/*!
* @name Register SMC_VLLSCTRL, field VLLSM[2:0] (RW)
*
* Controls which VLLS sub-mode to enter if STOPM=VLLS.
*
* Values:
* - 000 - VLLS0
* - 001 - VLLS1
* - 010 - VLLS2
* - 011 - VLLS3
* - 100 - Reserved
* - 101 - Reserved
* - 110 - Reserved
* - 111 - Reserved
*/
//@{
#define BP_SMC_VLLSCTRL_VLLSM (0U) //!< Bit position for SMC_VLLSCTRL_VLLSM.
#define BM_SMC_VLLSCTRL_VLLSM (0x07U) //!< Bit mask for SMC_VLLSCTRL_VLLSM.
#define BS_SMC_VLLSCTRL_VLLSM (3U) //!< Bit field size in bits for SMC_VLLSCTRL_VLLSM.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the SMC_VLLSCTRL_VLLSM field.
#define BR_SMC_VLLSCTRL_VLLSM (HW_SMC_VLLSCTRL.B.VLLSM)
#endif
//! @brief Format value for bitfield SMC_VLLSCTRL_VLLSM.
#define BF_SMC_VLLSCTRL_VLLSM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_VLLSCTRL_VLLSM), uint8_t) & BM_SMC_VLLSCTRL_VLLSM)
#ifndef __LANGUAGE_ASM__
//! @brief Set the VLLSM field to a new value.
#define BW_SMC_VLLSCTRL_VLLSM(v) (HW_SMC_VLLSCTRL_WR((HW_SMC_VLLSCTRL_RD() & ~BM_SMC_VLLSCTRL_VLLSM) | BF_SMC_VLLSCTRL_VLLSM(v)))
#endif
//@}
/*!
* @name Register SMC_VLLSCTRL, field PORPO[5] (RW)
*
* Controls whether the POR detect circuit (for brown-out detection) is enabled
* in VLLS0 mode.
*
* Values:
* - 0 - POR detect circuit is enabled in VLLS0.
* - 1 - POR detect circuit is disabled in VLLS0.
*/
//@{
#define BP_SMC_VLLSCTRL_PORPO (5U) //!< Bit position for SMC_VLLSCTRL_PORPO.
#define BM_SMC_VLLSCTRL_PORPO (0x20U) //!< Bit mask for SMC_VLLSCTRL_PORPO.
#define BS_SMC_VLLSCTRL_PORPO (1U) //!< Bit field size in bits for SMC_VLLSCTRL_PORPO.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the SMC_VLLSCTRL_PORPO field.
#define BR_SMC_VLLSCTRL_PORPO (BITBAND_ACCESS8(HW_SMC_VLLSCTRL_ADDR, BP_SMC_VLLSCTRL_PORPO))
#endif
//! @brief Format value for bitfield SMC_VLLSCTRL_PORPO.
#define BF_SMC_VLLSCTRL_PORPO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_VLLSCTRL_PORPO), uint8_t) & BM_SMC_VLLSCTRL_PORPO)
#ifndef __LANGUAGE_ASM__
//! @brief Set the PORPO field to a new value.
#define BW_SMC_VLLSCTRL_PORPO(v) (BITBAND_ACCESS8(HW_SMC_VLLSCTRL_ADDR, BP_SMC_VLLSCTRL_PORPO) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_SMC_PMSTAT - Power Mode Status register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_SMC_PMSTAT - Power Mode Status register (RO)
*
* Reset value: 0x01U
*
* PMSTAT is a read-only, one-hot register which indicates the current power
* mode of the system. This register is reset on Chip POR not VLLS and by reset
* types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
* trigger Chip POR not VLLS. See the Reset section details for more information.
*/
typedef union _hw_smc_pmstat
{
uint8_t U;
struct _hw_smc_pmstat_bitfields
{
uint8_t PMSTAT : 7; //!< [6:0]
uint8_t RESERVED0 : 1; //!< [7]
} B;
} hw_smc_pmstat_t;
#endif
/*!
* @name Constants and macros for entire SMC_PMSTAT register
*/
//@{
#define HW_SMC_PMSTAT_ADDR (REGS_SMC_BASE + 0x3U)
#ifndef __LANGUAGE_ASM__
#define HW_SMC_PMSTAT (*(__I hw_smc_pmstat_t *) HW_SMC_PMSTAT_ADDR)
#define HW_SMC_PMSTAT_RD() (HW_SMC_PMSTAT.U)
#endif
//@}
/*
* Constants & macros for individual SMC_PMSTAT bitfields
*/
/*!
* @name Register SMC_PMSTAT, field PMSTAT[6:0] (RO)
*
* When debug is enabled, the PMSTAT will not update to STOP or VLPS
*/
//@{
#define BP_SMC_PMSTAT_PMSTAT (0U) //!< Bit position for SMC_PMSTAT_PMSTAT.
#define BM_SMC_PMSTAT_PMSTAT (0x7FU) //!< Bit mask for SMC_PMSTAT_PMSTAT.
#define BS_SMC_PMSTAT_PMSTAT (7U) //!< Bit field size in bits for SMC_PMSTAT_PMSTAT.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the SMC_PMSTAT_PMSTAT field.
#define BR_SMC_PMSTAT_PMSTAT (HW_SMC_PMSTAT.B.PMSTAT)
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_smc_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All SMC module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_smc
{
__IO hw_smc_pmprot_t PMPROT; //!< [0x0] Power Mode Protection register
__IO hw_smc_pmctrl_t PMCTRL; //!< [0x1] Power Mode Control register
__IO hw_smc_vllsctrl_t VLLSCTRL; //!< [0x2] VLLS Control register
__I hw_smc_pmstat_t PMSTAT; //!< [0x3] Power Mode Status register
} hw_smc_t;
#pragma pack()
//! @brief Macro to access all SMC registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_SMC</code>.
#define HW_SMC (*(hw_smc_t *) REGS_SMC_BASE)
#endif
#endif // __HW_SMC_REGISTERS_H__
// v22/130726/0.9
// EOF

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_USBDCD_REGISTERS_H__
#define __HW_USBDCD_REGISTERS_H__
#include "regs.h"
/*
* MK64F12 USBDCD
*
* USB Device Charger Detection module
*
* Registers defined in this header file:
* - HW_USBDCD_CONTROL - Control register
* - HW_USBDCD_CLOCK - Clock register
* - HW_USBDCD_STATUS - Status register
* - HW_USBDCD_TIMER0 - TIMER0 register
* - HW_USBDCD_TIMER1 - TIMER1 register
* - HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register
* - HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register
*
* - hw_usbdcd_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_USBDCD_BASE
#define HW_USBDCD_INSTANCE_COUNT (1U) //!< Number of instances of the USBDCD module.
#define HW_USBDCD0 (0U) //!< Instance number for USBDCD.
#define REGS_USBDCD0_BASE (0x40035000U) //!< Base address for USBDCD.
//! @brief Table of base addresses for USBDCD instances.
static const uint32_t __g_regs_USBDCD_base_addresses[] = {
REGS_USBDCD0_BASE,
};
//! @brief Get the base address of USBDCD by instance number.
//! @param x USBDCD instance number, from 0 through 0.
#define REGS_USBDCD_BASE(x) (__g_regs_USBDCD_base_addresses[(x)])
//! @brief Get the instance number given a base address.
//! @param b Base address for an instance of USBDCD.
#define REGS_USBDCD_INSTANCE(b) ((b) == REGS_USBDCD0_BASE ? HW_USBDCD0 : 0)
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_USBDCD_CONTROL - Control register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_USBDCD_CONTROL - Control register (RW)
*
* Reset value: 0x00010000U
*
* Contains the control and interrupt bit fields.
*/
typedef union _hw_usbdcd_control
{
uint32_t U;
struct _hw_usbdcd_control_bitfields
{
uint32_t IACK : 1; //!< [0] Interrupt Acknowledge
uint32_t RESERVED0 : 7; //!< [7:1]
uint32_t IF : 1; //!< [8] Interrupt Flag
uint32_t RESERVED1 : 7; //!< [15:9]
uint32_t IE : 1; //!< [16] Interrupt Enable
uint32_t BC12 : 1; //!< [17]
uint32_t RESERVED2 : 6; //!< [23:18]
uint32_t START : 1; //!< [24] Start Change Detection Sequence
uint32_t SR : 1; //!< [25] Software Reset
uint32_t RESERVED3 : 6; //!< [31:26]
} B;
} hw_usbdcd_control_t;
#endif
/*!
* @name Constants and macros for entire USBDCD_CONTROL register
*/
//@{
#define HW_USBDCD_CONTROL_ADDR(x) (REGS_USBDCD_BASE(x) + 0x0U)
#ifndef __LANGUAGE_ASM__
#define HW_USBDCD_CONTROL(x) (*(__IO hw_usbdcd_control_t *) HW_USBDCD_CONTROL_ADDR(x))
#define HW_USBDCD_CONTROL_RD(x) (HW_USBDCD_CONTROL(x).U)
#define HW_USBDCD_CONTROL_WR(x, v) (HW_USBDCD_CONTROL(x).U = (v))
#define HW_USBDCD_CONTROL_SET(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) | (v)))
#define HW_USBDCD_CONTROL_CLR(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) & ~(v)))
#define HW_USBDCD_CONTROL_TOG(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual USBDCD_CONTROL bitfields
*/
/*!
* @name Register USBDCD_CONTROL, field IACK[0] (WORZ)
*
* Determines whether the interrupt is cleared.
*
* Values:
* - 0 - Do not clear the interrupt.
* - 1 - Clear the IF bit (interrupt flag).
*/
//@{
#define BP_USBDCD_CONTROL_IACK (0U) //!< Bit position for USBDCD_CONTROL_IACK.
#define BM_USBDCD_CONTROL_IACK (0x00000001U) //!< Bit mask for USBDCD_CONTROL_IACK.
#define BS_USBDCD_CONTROL_IACK (1U) //!< Bit field size in bits for USBDCD_CONTROL_IACK.
//! @brief Format value for bitfield USBDCD_CONTROL_IACK.
#define BF_USBDCD_CONTROL_IACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_IACK), uint32_t) & BM_USBDCD_CONTROL_IACK)
#ifndef __LANGUAGE_ASM__
//! @brief Set the IACK field to a new value.
#define BW_USBDCD_CONTROL_IACK(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IACK) = (v))
#endif
//@}
/*!
* @name Register USBDCD_CONTROL, field IF[8] (RO)
*
* Determines whether an interrupt is pending.
*
* Values:
* - 0 - No interrupt is pending.
* - 1 - An interrupt is pending.
*/
//@{
#define BP_USBDCD_CONTROL_IF (8U) //!< Bit position for USBDCD_CONTROL_IF.
#define BM_USBDCD_CONTROL_IF (0x00000100U) //!< Bit mask for USBDCD_CONTROL_IF.
#define BS_USBDCD_CONTROL_IF (1U) //!< Bit field size in bits for USBDCD_CONTROL_IF.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the USBDCD_CONTROL_IF field.
#define BR_USBDCD_CONTROL_IF(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IF))
#endif
//@}
/*!
* @name Register USBDCD_CONTROL, field IE[16] (RW)
*
* Enables/disables interrupts to the system.
*
* Values:
* - 0 - Disable interrupts to the system.
* - 1 - Enable interrupts to the system.
*/
//@{
#define BP_USBDCD_CONTROL_IE (16U) //!< Bit position for USBDCD_CONTROL_IE.
#define BM_USBDCD_CONTROL_IE (0x00010000U) //!< Bit mask for USBDCD_CONTROL_IE.
#define BS_USBDCD_CONTROL_IE (1U) //!< Bit field size in bits for USBDCD_CONTROL_IE.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the USBDCD_CONTROL_IE field.
#define BR_USBDCD_CONTROL_IE(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IE))
#endif
//! @brief Format value for bitfield USBDCD_CONTROL_IE.
#define BF_USBDCD_CONTROL_IE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_IE), uint32_t) & BM_USBDCD_CONTROL_IE)
#ifndef __LANGUAGE_ASM__
//! @brief Set the IE field to a new value.
#define BW_USBDCD_CONTROL_IE(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IE) = (v))
#endif
//@}
/*!
* @name Register USBDCD_CONTROL, field BC12[17] (RW)
*
* BC1.2 compatibility. This bit cannot be changed after start detection.
*
* Values:
* - 0 - Compatible with BC1.1 (default)
* - 1 - Compatible with BC1.2
*/
//@{
#define BP_USBDCD_CONTROL_BC12 (17U) //!< Bit position for USBDCD_CONTROL_BC12.
#define BM_USBDCD_CONTROL_BC12 (0x00020000U) //!< Bit mask for USBDCD_CONTROL_BC12.
#define BS_USBDCD_CONTROL_BC12 (1U) //!< Bit field size in bits for USBDCD_CONTROL_BC12.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the USBDCD_CONTROL_BC12 field.
#define BR_USBDCD_CONTROL_BC12(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_BC12))
#endif
//! @brief Format value for bitfield USBDCD_CONTROL_BC12.
#define BF_USBDCD_CONTROL_BC12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_BC12), uint32_t) & BM_USBDCD_CONTROL_BC12)
#ifndef __LANGUAGE_ASM__
//! @brief Set the BC12 field to a new value.
#define BW_USBDCD_CONTROL_BC12(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_BC12) = (v))
#endif
//@}
/*!
* @name Register USBDCD_CONTROL, field START[24] (WORZ)
*
* Determines whether the charger detection sequence is initiated.
*
* Values:
* - 0 - Do not start the sequence. Writes of this value have no effect.
* - 1 - Initiate the charger detection sequence. If the sequence is already
* running, writes of this value have no effect.
*/
//@{
#define BP_USBDCD_CONTROL_START (24U) //!< Bit position for USBDCD_CONTROL_START.
#define BM_USBDCD_CONTROL_START (0x01000000U) //!< Bit mask for USBDCD_CONTROL_START.
#define BS_USBDCD_CONTROL_START (1U) //!< Bit field size in bits for USBDCD_CONTROL_START.
//! @brief Format value for bitfield USBDCD_CONTROL_START.
#define BF_USBDCD_CONTROL_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_START), uint32_t) & BM_USBDCD_CONTROL_START)
#ifndef __LANGUAGE_ASM__
//! @brief Set the START field to a new value.
#define BW_USBDCD_CONTROL_START(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_START) = (v))
#endif
//@}
/*!
* @name Register USBDCD_CONTROL, field SR[25] (WORZ)
*
* Determines whether a software reset is performed.
*
* Values:
* - 0 - Do not perform a software reset.
* - 1 - Perform a software reset.
*/
//@{
#define BP_USBDCD_CONTROL_SR (25U) //!< Bit position for USBDCD_CONTROL_SR.
#define BM_USBDCD_CONTROL_SR (0x02000000U) //!< Bit mask for USBDCD_CONTROL_SR.
#define BS_USBDCD_CONTROL_SR (1U) //!< Bit field size in bits for USBDCD_CONTROL_SR.
//! @brief Format value for bitfield USBDCD_CONTROL_SR.
#define BF_USBDCD_CONTROL_SR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_SR), uint32_t) & BM_USBDCD_CONTROL_SR)
#ifndef __LANGUAGE_ASM__
//! @brief Set the SR field to a new value.
#define BW_USBDCD_CONTROL_SR(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_SR) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_USBDCD_CLOCK - Clock register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_USBDCD_CLOCK - Clock register (RW)
*
* Reset value: 0x000000C1U
*/
typedef union _hw_usbdcd_clock
{
uint32_t U;
struct _hw_usbdcd_clock_bitfields
{
uint32_t CLOCK_UNIT : 1; //!< [0] Unit of Measurement Encoding for
//! Clock Speed
uint32_t RESERVED0 : 1; //!< [1]
uint32_t CLOCK_SPEED : 10; //!< [11:2] Numerical Value of Clock Speed
//! in Binary
uint32_t RESERVED1 : 20; //!< [31:12]
} B;
} hw_usbdcd_clock_t;
#endif
/*!
* @name Constants and macros for entire USBDCD_CLOCK register
*/
//@{
#define HW_USBDCD_CLOCK_ADDR(x) (REGS_USBDCD_BASE(x) + 0x4U)
#ifndef __LANGUAGE_ASM__
#define HW_USBDCD_CLOCK(x) (*(__IO hw_usbdcd_clock_t *) HW_USBDCD_CLOCK_ADDR(x))
#define HW_USBDCD_CLOCK_RD(x) (HW_USBDCD_CLOCK(x).U)
#define HW_USBDCD_CLOCK_WR(x, v) (HW_USBDCD_CLOCK(x).U = (v))
#define HW_USBDCD_CLOCK_SET(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) | (v)))
#define HW_USBDCD_CLOCK_CLR(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) & ~(v)))
#define HW_USBDCD_CLOCK_TOG(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual USBDCD_CLOCK bitfields
*/
/*!
* @name Register USBDCD_CLOCK, field CLOCK_UNIT[0] (RW)
*
* Specifies the unit of measure for the clock speed.
*
* Values:
* - 0 - kHz Speed (between 1 kHz and 1023 kHz)
* - 1 - MHz Speed (between 1 MHz and 1023 MHz)
*/
//@{
#define BP_USBDCD_CLOCK_CLOCK_UNIT (0U) //!< Bit position for USBDCD_CLOCK_CLOCK_UNIT.
#define BM_USBDCD_CLOCK_CLOCK_UNIT (0x00000001U) //!< Bit mask for USBDCD_CLOCK_CLOCK_UNIT.
#define BS_USBDCD_CLOCK_CLOCK_UNIT (1U) //!< Bit field size in bits for USBDCD_CLOCK_CLOCK_UNIT.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the USBDCD_CLOCK_CLOCK_UNIT field.
#define BR_USBDCD_CLOCK_CLOCK_UNIT(x) (BITBAND_ACCESS32(HW_USBDCD_CLOCK_ADDR(x), BP_USBDCD_CLOCK_CLOCK_UNIT))
#endif
//! @brief Format value for bitfield USBDCD_CLOCK_CLOCK_UNIT.
#define BF_USBDCD_CLOCK_CLOCK_UNIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CLOCK_CLOCK_UNIT), uint32_t) & BM_USBDCD_CLOCK_CLOCK_UNIT)
#ifndef __LANGUAGE_ASM__
//! @brief Set the CLOCK_UNIT field to a new value.
#define BW_USBDCD_CLOCK_CLOCK_UNIT(x, v) (BITBAND_ACCESS32(HW_USBDCD_CLOCK_ADDR(x), BP_USBDCD_CLOCK_CLOCK_UNIT) = (v))
#endif
//@}
/*!
* @name Register USBDCD_CLOCK, field CLOCK_SPEED[11:2] (RW)
*
* The unit of measure is programmed in CLOCK_UNIT. The valid range is from 1 to
* 1023 when clock unit is MHz and 4 to 1023 when clock unit is kHz. Examples
* with CLOCK_UNIT = 1: For 48 MHz: 0b00_0011_0000 (48) (Default) For 24 MHz:
* 0b00_0001_1000 (24) Examples with CLOCK_UNIT = 0: For 100 kHz: 0b00_0110_0100 (100)
* For 500 kHz: 0b01_1111_0100 (500)
*/
//@{
#define BP_USBDCD_CLOCK_CLOCK_SPEED (2U) //!< Bit position for USBDCD_CLOCK_CLOCK_SPEED.
#define BM_USBDCD_CLOCK_CLOCK_SPEED (0x00000FFCU) //!< Bit mask for USBDCD_CLOCK_CLOCK_SPEED.
#define BS_USBDCD_CLOCK_CLOCK_SPEED (10U) //!< Bit field size in bits for USBDCD_CLOCK_CLOCK_SPEED.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the USBDCD_CLOCK_CLOCK_SPEED field.
#define BR_USBDCD_CLOCK_CLOCK_SPEED(x) (HW_USBDCD_CLOCK(x).B.CLOCK_SPEED)
#endif
//! @brief Format value for bitfield USBDCD_CLOCK_CLOCK_SPEED.
#define BF_USBDCD_CLOCK_CLOCK_SPEED(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CLOCK_CLOCK_SPEED), uint32_t) & BM_USBDCD_CLOCK_CLOCK_SPEED)
#ifndef __LANGUAGE_ASM__
//! @brief Set the CLOCK_SPEED field to a new value.
#define BW_USBDCD_CLOCK_CLOCK_SPEED(x, v) (HW_USBDCD_CLOCK_WR(x, (HW_USBDCD_CLOCK_RD(x) & ~BM_USBDCD_CLOCK_CLOCK_SPEED) | BF_USBDCD_CLOCK_CLOCK_SPEED(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_USBDCD_STATUS - Status register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_USBDCD_STATUS - Status register (RO)
*
* Reset value: 0x00000000U
*
* Provides the current state of the module for system software monitoring.
*/
typedef union _hw_usbdcd_status
{
uint32_t U;
struct _hw_usbdcd_status_bitfields
{
uint32_t RESERVED0 : 16; //!< [15:0]
uint32_t SEQ_RES : 2; //!< [17:16] Charger Detection Sequence Results
uint32_t SEQ_STAT : 2; //!< [19:18] Charger Detection Sequence Status
uint32_t ERR : 1; //!< [20] Error Flag
uint32_t TO : 1; //!< [21] Timeout Flag
uint32_t ACTIVE : 1; //!< [22] Active Status Indicator
uint32_t RESERVED1 : 9; //!< [31:23]
} B;
} hw_usbdcd_status_t;
#endif
/*!
* @name Constants and macros for entire USBDCD_STATUS register
*/
//@{
#define HW_USBDCD_STATUS_ADDR(x) (REGS_USBDCD_BASE(x) + 0x8U)
#ifndef __LANGUAGE_ASM__
#define HW_USBDCD_STATUS(x) (*(__I hw_usbdcd_status_t *) HW_USBDCD_STATUS_ADDR(x))
#define HW_USBDCD_STATUS_RD(x) (HW_USBDCD_STATUS(x).U)
#endif
//@}
/*
* Constants & macros for individual USBDCD_STATUS bitfields
*/
/*!
* @name Register USBDCD_STATUS, field SEQ_RES[17:16] (RO)
*
* Reports how the charger detection is attached.
*
* Values:
* - 00 - No results to report.
* - 01 - Attached to a standard host. Must comply with USB 2.0 by drawing only
* 2.5 mA (max) until connected.
* - 10 - Attached to a charging port. The exact meaning depends on bit 18: 0:
* Attached to either a charging host or a dedicated charger. The charger type
* detection has not completed. 1: Attached to a charging host. The charger
* type detection has completed.
* - 11 - Attached to a dedicated charger.
*/
//@{
#define BP_USBDCD_STATUS_SEQ_RES (16U) //!< Bit position for USBDCD_STATUS_SEQ_RES.
#define BM_USBDCD_STATUS_SEQ_RES (0x00030000U) //!< Bit mask for USBDCD_STATUS_SEQ_RES.
#define BS_USBDCD_STATUS_SEQ_RES (2U) //!< Bit field size in bits for USBDCD_STATUS_SEQ_RES.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the USBDCD_STATUS_SEQ_RES field.
#define BR_USBDCD_STATUS_SEQ_RES(x) (HW_USBDCD_STATUS(x).B.SEQ_RES)
#endif
//@}
/*!
* @name Register USBDCD_STATUS, field SEQ_STAT[19:18] (RO)
*
* Indicates the status of the charger detection sequence.
*
* Values:
* - 00 - The module is either not enabled, or the module is enabled but the
* data pins have not yet been detected.
* - 01 - Data pin contact detection is complete.
* - 10 - Charging port detection is complete.
* - 11 - Charger type detection is complete.
*/
//@{
#define BP_USBDCD_STATUS_SEQ_STAT (18U) //!< Bit position for USBDCD_STATUS_SEQ_STAT.
#define BM_USBDCD_STATUS_SEQ_STAT (0x000C0000U) //!< Bit mask for USBDCD_STATUS_SEQ_STAT.
#define BS_USBDCD_STATUS_SEQ_STAT (2U) //!< Bit field size in bits for USBDCD_STATUS_SEQ_STAT.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the USBDCD_STATUS_SEQ_STAT field.
#define BR_USBDCD_STATUS_SEQ_STAT(x) (HW_USBDCD_STATUS(x).B.SEQ_STAT)
#endif
//@}
/*!
* @name Register USBDCD_STATUS, field ERR[20] (RO)
*
* Indicates whether there is an error in the detection sequence.
*
* Values:
* - 0 - No sequence errors.
* - 1 - Error in the detection sequence. See the SEQ_STAT field to determine
* the phase in which the error occurred.
*/
//@{
#define BP_USBDCD_STATUS_ERR (20U) //!< Bit position for USBDCD_STATUS_ERR.
#define BM_USBDCD_STATUS_ERR (0x00100000U) //!< Bit mask for USBDCD_STATUS_ERR.
#define BS_USBDCD_STATUS_ERR (1U) //!< Bit field size in bits for USBDCD_STATUS_ERR.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the USBDCD_STATUS_ERR field.
#define BR_USBDCD_STATUS_ERR(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_ERR))
#endif
//@}
/*!
* @name Register USBDCD_STATUS, field TO[21] (RO)
*
* Indicates whether the detection sequence has passed the timeout threshhold.
*
* Values:
* - 0 - The detection sequence has not been running for over 1 s.
* - 1 - It has been over 1 s since the data pin contact was detected and
* debounced.
*/
//@{
#define BP_USBDCD_STATUS_TO (21U) //!< Bit position for USBDCD_STATUS_TO.
#define BM_USBDCD_STATUS_TO (0x00200000U) //!< Bit mask for USBDCD_STATUS_TO.
#define BS_USBDCD_STATUS_TO (1U) //!< Bit field size in bits for USBDCD_STATUS_TO.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the USBDCD_STATUS_TO field.
#define BR_USBDCD_STATUS_TO(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_TO))
#endif
//@}
/*!
* @name Register USBDCD_STATUS, field ACTIVE[22] (RO)
*
* Indicates whether the sequence is running.
*
* Values:
* - 0 - The sequence is not running.
* - 1 - The sequence is running.
*/
//@{
#define BP_USBDCD_STATUS_ACTIVE (22U) //!< Bit position for USBDCD_STATUS_ACTIVE.
#define BM_USBDCD_STATUS_ACTIVE (0x00400000U) //!< Bit mask for USBDCD_STATUS_ACTIVE.
#define BS_USBDCD_STATUS_ACTIVE (1U) //!< Bit field size in bits for USBDCD_STATUS_ACTIVE.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the USBDCD_STATUS_ACTIVE field.
#define BR_USBDCD_STATUS_ACTIVE(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_ACTIVE))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_USBDCD_TIMER0 - TIMER0 register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_USBDCD_TIMER0 - TIMER0 register (RW)
*
* Reset value: 0x00100000U
*
* TIMER0 has an TSEQ_INIT field that represents the system latency in ms.
* Latency is measured from the time when VBUS goes active until the time system
* software initiates charger detection sequence in USBDCD module. When software sets
* the CONTROL[START] bit, the Unit Connection Timer (TUNITCON) is initialized
* with the value of TSEQ_INIT. Valid values are 0-1023, however the USB Battery
* Charging Specification requires the entire sequence, including TSEQ_INIT, to be
* completed in 1s or less.
*/
typedef union _hw_usbdcd_timer0
{
uint32_t U;
struct _hw_usbdcd_timer0_bitfields
{
uint32_t TUNITCON : 12; //!< [11:0] Unit Connection Timer Elapse (in
//! ms)
uint32_t RESERVED0 : 4; //!< [15:12]
uint32_t TSEQ_INIT : 10; //!< [25:16] Sequence Initiation Time
uint32_t RESERVED1 : 6; //!< [31:26]
} B;
} hw_usbdcd_timer0_t;
#endif
/*!
* @name Constants and macros for entire USBDCD_TIMER0 register
*/
//@{
#define HW_USBDCD_TIMER0_ADDR(x) (REGS_USBDCD_BASE(x) + 0x10U)
#ifndef __LANGUAGE_ASM__
#define HW_USBDCD_TIMER0(x) (*(__IO hw_usbdcd_timer0_t *) HW_USBDCD_TIMER0_ADDR(x))
#define HW_USBDCD_TIMER0_RD(x) (HW_USBDCD_TIMER0(x).U)
#define HW_USBDCD_TIMER0_WR(x, v) (HW_USBDCD_TIMER0(x).U = (v))
#define HW_USBDCD_TIMER0_SET(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) | (v)))
#define HW_USBDCD_TIMER0_CLR(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) & ~(v)))
#define HW_USBDCD_TIMER0_TOG(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual USBDCD_TIMER0 bitfields
*/
/*!
* @name Register USBDCD_TIMER0, field TUNITCON[11:0] (RO)
*
* Displays the amount of elapsed time since the event of setting the START bit
* plus the value of TSEQ_INIT. The timer is automatically initialized with the
* value of TSEQ_INIT before starting to count. This timer enables compliance with
* the maximum time allowed to connect T UNIT_CON under the USB Battery Charging
* Specification. If the timer reaches the one second limit, the module triggers
* an interrupt and sets the error flag STATUS[ERR]. The timer continues
* counting throughout the charger detection sequence, even when control has been passed
* to software. As long as the module is active, the timer continues to count
* until it reaches the maximum value of 0xFFF (4095 ms). The timer does not
* rollover to zero. A software reset clears the timer.
*/
//@{
#define BP_USBDCD_TIMER0_TUNITCON (0U) //!< Bit position for USBDCD_TIMER0_TUNITCON.
#define BM_USBDCD_TIMER0_TUNITCON (0x00000FFFU) //!< Bit mask for USBDCD_TIMER0_TUNITCON.
#define BS_USBDCD_TIMER0_TUNITCON (12U) //!< Bit field size in bits for USBDCD_TIMER0_TUNITCON.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the USBDCD_TIMER0_TUNITCON field.
#define BR_USBDCD_TIMER0_TUNITCON(x) (HW_USBDCD_TIMER0(x).B.TUNITCON)
#endif
//@}
/*!
* @name Register USBDCD_TIMER0, field TSEQ_INIT[25:16] (RW)
*
* TSEQ_INIT represents the system latency (in ms) measured from the time VBUS
* goes active to the time system software initiates the charger detection
* sequence in the USBDCD module. When software sets the CONTROL[START] bit, the Unit
* Connection Timer (TUNITCON) is initialized with the value of TSEQ_INIT. Valid
* values are 0-1023, but the USB Battery Charging Specification requires the
* entire sequence, including TSEQ_INIT, to be completed in 1s or less.
*/
//@{
#define BP_USBDCD_TIMER0_TSEQ_INIT (16U) //!< Bit position for USBDCD_TIMER0_TSEQ_INIT.
#define BM_USBDCD_TIMER0_TSEQ_INIT (0x03FF0000U) //!< Bit mask for USBDCD_TIMER0_TSEQ_INIT.
#define BS_USBDCD_TIMER0_TSEQ_INIT (10U) //!< Bit field size in bits for USBDCD_TIMER0_TSEQ_INIT.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the USBDCD_TIMER0_TSEQ_INIT field.
#define BR_USBDCD_TIMER0_TSEQ_INIT(x) (HW_USBDCD_TIMER0(x).B.TSEQ_INIT)
#endif
//! @brief Format value for bitfield USBDCD_TIMER0_TSEQ_INIT.
#define BF_USBDCD_TIMER0_TSEQ_INIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER0_TSEQ_INIT), uint32_t) & BM_USBDCD_TIMER0_TSEQ_INIT)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TSEQ_INIT field to a new value.
#define BW_USBDCD_TIMER0_TSEQ_INIT(x, v) (HW_USBDCD_TIMER0_WR(x, (HW_USBDCD_TIMER0_RD(x) & ~BM_USBDCD_TIMER0_TSEQ_INIT) | BF_USBDCD_TIMER0_TSEQ_INIT(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_USBDCD_TIMER1 - TIMER1 register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_USBDCD_TIMER1 - TIMER1 register (RW)
*
* Reset value: 0x000A0028U
*
* TIMER1 contains timing parameters. Note that register values can be written
* that are not compliant with the USB Battery Charging Specification, so care
* should be taken when overwriting the default values.
*/
typedef union _hw_usbdcd_timer1
{
uint32_t U;
struct _hw_usbdcd_timer1_bitfields
{
uint32_t TVDPSRC_ON : 10; //!< [9:0] Time Period Comparator Enabled
uint32_t RESERVED0 : 6; //!< [15:10]
uint32_t TDCD_DBNC : 10; //!< [25:16] Time Period to Debounce D+
//! Signal
uint32_t RESERVED1 : 6; //!< [31:26]
} B;
} hw_usbdcd_timer1_t;
#endif
/*!
* @name Constants and macros for entire USBDCD_TIMER1 register
*/
//@{
#define HW_USBDCD_TIMER1_ADDR(x) (REGS_USBDCD_BASE(x) + 0x14U)
#ifndef __LANGUAGE_ASM__
#define HW_USBDCD_TIMER1(x) (*(__IO hw_usbdcd_timer1_t *) HW_USBDCD_TIMER1_ADDR(x))
#define HW_USBDCD_TIMER1_RD(x) (HW_USBDCD_TIMER1(x).U)
#define HW_USBDCD_TIMER1_WR(x, v) (HW_USBDCD_TIMER1(x).U = (v))
#define HW_USBDCD_TIMER1_SET(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) | (v)))
#define HW_USBDCD_TIMER1_CLR(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) & ~(v)))
#define HW_USBDCD_TIMER1_TOG(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual USBDCD_TIMER1 bitfields
*/
/*!
* @name Register USBDCD_TIMER1, field TVDPSRC_ON[9:0] (RW)
*
* This timing parameter is used after detection of the data pin. See "Charging
* Port Detection". Valid values are 1-1023, but the USB Battery Charging
* Specification requires a minimum value of 40 ms.
*/
//@{
#define BP_USBDCD_TIMER1_TVDPSRC_ON (0U) //!< Bit position for USBDCD_TIMER1_TVDPSRC_ON.
#define BM_USBDCD_TIMER1_TVDPSRC_ON (0x000003FFU) //!< Bit mask for USBDCD_TIMER1_TVDPSRC_ON.
#define BS_USBDCD_TIMER1_TVDPSRC_ON (10U) //!< Bit field size in bits for USBDCD_TIMER1_TVDPSRC_ON.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the USBDCD_TIMER1_TVDPSRC_ON field.
#define BR_USBDCD_TIMER1_TVDPSRC_ON(x) (HW_USBDCD_TIMER1(x).B.TVDPSRC_ON)
#endif
//! @brief Format value for bitfield USBDCD_TIMER1_TVDPSRC_ON.
#define BF_USBDCD_TIMER1_TVDPSRC_ON(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER1_TVDPSRC_ON), uint32_t) & BM_USBDCD_TIMER1_TVDPSRC_ON)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TVDPSRC_ON field to a new value.
#define BW_USBDCD_TIMER1_TVDPSRC_ON(x, v) (HW_USBDCD_TIMER1_WR(x, (HW_USBDCD_TIMER1_RD(x) & ~BM_USBDCD_TIMER1_TVDPSRC_ON) | BF_USBDCD_TIMER1_TVDPSRC_ON(v)))
#endif
//@}
/*!
* @name Register USBDCD_TIMER1, field TDCD_DBNC[25:16] (RW)
*
* Sets the time period (ms) to debounce the D+ signal during the data pin
* contact detection phase. See "Debouncing the data pin contact" Valid values are
* 1-1023, but the USB Battery Charging Specification requires a minimum value of 10
* ms.
*/
//@{
#define BP_USBDCD_TIMER1_TDCD_DBNC (16U) //!< Bit position for USBDCD_TIMER1_TDCD_DBNC.
#define BM_USBDCD_TIMER1_TDCD_DBNC (0x03FF0000U) //!< Bit mask for USBDCD_TIMER1_TDCD_DBNC.
#define BS_USBDCD_TIMER1_TDCD_DBNC (10U) //!< Bit field size in bits for USBDCD_TIMER1_TDCD_DBNC.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the USBDCD_TIMER1_TDCD_DBNC field.
#define BR_USBDCD_TIMER1_TDCD_DBNC(x) (HW_USBDCD_TIMER1(x).B.TDCD_DBNC)
#endif
//! @brief Format value for bitfield USBDCD_TIMER1_TDCD_DBNC.
#define BF_USBDCD_TIMER1_TDCD_DBNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER1_TDCD_DBNC), uint32_t) & BM_USBDCD_TIMER1_TDCD_DBNC)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TDCD_DBNC field to a new value.
#define BW_USBDCD_TIMER1_TDCD_DBNC(x, v) (HW_USBDCD_TIMER1_WR(x, (HW_USBDCD_TIMER1_RD(x) & ~BM_USBDCD_TIMER1_TDCD_DBNC) | BF_USBDCD_TIMER1_TDCD_DBNC(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register (RW)
*
* Reset value: 0x00280001U
*
* TIMER2_BC11 contains timing parameters for USB Battery Charging
* Specification, v1.1. Register values can be written that are not compliant with the USB
* Battery Charging Specification, so care should be taken when overwriting the
* default values.
*/
typedef union _hw_usbdcd_timer2_bc11
{
uint32_t U;
struct _hw_usbdcd_timer2_bc11_bitfields
{
uint32_t CHECK_DM : 4; //!< [3:0] Time Before Check of D- Line
uint32_t RESERVED0 : 12; //!< [15:4]
uint32_t TVDPSRC_CON : 10; //!< [25:16] Time Period Before Enabling
//! D+ Pullup
uint32_t RESERVED1 : 6; //!< [31:26]
} B;
} hw_usbdcd_timer2_bc11_t;
#endif
/*!
* @name Constants and macros for entire USBDCD_TIMER2_BC11 register
*/
//@{
#define HW_USBDCD_TIMER2_BC11_ADDR(x) (REGS_USBDCD_BASE(x) + 0x18U)
#ifndef __LANGUAGE_ASM__
#define HW_USBDCD_TIMER2_BC11(x) (*(__IO hw_usbdcd_timer2_bc11_t *) HW_USBDCD_TIMER2_BC11_ADDR(x))
#define HW_USBDCD_TIMER2_BC11_RD(x) (HW_USBDCD_TIMER2_BC11(x).U)
#define HW_USBDCD_TIMER2_BC11_WR(x, v) (HW_USBDCD_TIMER2_BC11(x).U = (v))
#define HW_USBDCD_TIMER2_BC11_SET(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) | (v)))
#define HW_USBDCD_TIMER2_BC11_CLR(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) & ~(v)))
#define HW_USBDCD_TIMER2_BC11_TOG(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual USBDCD_TIMER2_BC11 bitfields
*/
/*!
* @name Register USBDCD_TIMER2_BC11, field CHECK_DM[3:0] (RW)
*
* Sets the amount of time (in ms) that the module waits after the device
* connects to the USB bus until checking the state of the D- line to determine the
* type of charging port. See "Charger Type Detection." Valid values are 1-15ms.
*/
//@{
#define BP_USBDCD_TIMER2_BC11_CHECK_DM (0U) //!< Bit position for USBDCD_TIMER2_BC11_CHECK_DM.
#define BM_USBDCD_TIMER2_BC11_CHECK_DM (0x0000000FU) //!< Bit mask for USBDCD_TIMER2_BC11_CHECK_DM.
#define BS_USBDCD_TIMER2_BC11_CHECK_DM (4U) //!< Bit field size in bits for USBDCD_TIMER2_BC11_CHECK_DM.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the USBDCD_TIMER2_BC11_CHECK_DM field.
#define BR_USBDCD_TIMER2_BC11_CHECK_DM(x) (HW_USBDCD_TIMER2_BC11(x).B.CHECK_DM)
#endif
//! @brief Format value for bitfield USBDCD_TIMER2_BC11_CHECK_DM.
#define BF_USBDCD_TIMER2_BC11_CHECK_DM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER2_BC11_CHECK_DM), uint32_t) & BM_USBDCD_TIMER2_BC11_CHECK_DM)
#ifndef __LANGUAGE_ASM__
//! @brief Set the CHECK_DM field to a new value.
#define BW_USBDCD_TIMER2_BC11_CHECK_DM(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, (HW_USBDCD_TIMER2_BC11_RD(x) & ~BM_USBDCD_TIMER2_BC11_CHECK_DM) | BF_USBDCD_TIMER2_BC11_CHECK_DM(v)))
#endif
//@}
/*!
* @name Register USBDCD_TIMER2_BC11, field TVDPSRC_CON[25:16] (RW)
*
* Sets the time period (ms) that the module waits after charging port detection
* before system software must enable the D+ pullup to connect to the USB host.
* Valid values are 1-1023, but the USB Battery Charging Specification requires a
* minimum value of 40 ms.
*/
//@{
#define BP_USBDCD_TIMER2_BC11_TVDPSRC_CON (16U) //!< Bit position for USBDCD_TIMER2_BC11_TVDPSRC_CON.
#define BM_USBDCD_TIMER2_BC11_TVDPSRC_CON (0x03FF0000U) //!< Bit mask for USBDCD_TIMER2_BC11_TVDPSRC_CON.
#define BS_USBDCD_TIMER2_BC11_TVDPSRC_CON (10U) //!< Bit field size in bits for USBDCD_TIMER2_BC11_TVDPSRC_CON.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the USBDCD_TIMER2_BC11_TVDPSRC_CON field.
#define BR_USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (HW_USBDCD_TIMER2_BC11(x).B.TVDPSRC_CON)
#endif
//! @brief Format value for bitfield USBDCD_TIMER2_BC11_TVDPSRC_CON.
#define BF_USBDCD_TIMER2_BC11_TVDPSRC_CON(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER2_BC11_TVDPSRC_CON), uint32_t) & BM_USBDCD_TIMER2_BC11_TVDPSRC_CON)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TVDPSRC_CON field to a new value.
#define BW_USBDCD_TIMER2_BC11_TVDPSRC_CON(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, (HW_USBDCD_TIMER2_BC11_RD(x) & ~BM_USBDCD_TIMER2_BC11_TVDPSRC_CON) | BF_USBDCD_TIMER2_BC11_TVDPSRC_CON(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register (RW)
*
* Reset value: 0x00010028U
*
* TIMER2_BC12 contains timing parameters for USB Battery Charging
* Specification, v1.2. Register values can be written that are not compliant with the USB
* Battery Charging Specification, so care should be taken when overwriting the
* default values.
*/
typedef union _hw_usbdcd_timer2_bc12
{
uint32_t U;
struct _hw_usbdcd_timer2_bc12_bitfields
{
uint32_t TVDMSRC_ON : 10; //!< [9:0]
uint32_t RESERVED0 : 6; //!< [15:10]
uint32_t TWAIT_AFTER_PRD : 10; //!< [25:16]
uint32_t RESERVED1 : 6; //!< [31:26]
} B;
} hw_usbdcd_timer2_bc12_t;
#endif
/*!
* @name Constants and macros for entire USBDCD_TIMER2_BC12 register
*/
//@{
#define HW_USBDCD_TIMER2_BC12_ADDR(x) (REGS_USBDCD_BASE(x) + 0x18U)
#ifndef __LANGUAGE_ASM__
#define HW_USBDCD_TIMER2_BC12(x) (*(__IO hw_usbdcd_timer2_bc12_t *) HW_USBDCD_TIMER2_BC12_ADDR(x))
#define HW_USBDCD_TIMER2_BC12_RD(x) (HW_USBDCD_TIMER2_BC12(x).U)
#define HW_USBDCD_TIMER2_BC12_WR(x, v) (HW_USBDCD_TIMER2_BC12(x).U = (v))
#define HW_USBDCD_TIMER2_BC12_SET(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) | (v)))
#define HW_USBDCD_TIMER2_BC12_CLR(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) & ~(v)))
#define HW_USBDCD_TIMER2_BC12_TOG(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) ^ (v)))
#endif
//@}
/*
* Constants & macros for individual USBDCD_TIMER2_BC12 bitfields
*/
/*!
* @name Register USBDCD_TIMER2_BC12, field TVDMSRC_ON[9:0] (RW)
*
* Sets the amount of time (in ms) that the module enables the VDM_SRC. Valid
* values are 0-40ms.
*/
//@{
#define BP_USBDCD_TIMER2_BC12_TVDMSRC_ON (0U) //!< Bit position for USBDCD_TIMER2_BC12_TVDMSRC_ON.
#define BM_USBDCD_TIMER2_BC12_TVDMSRC_ON (0x000003FFU) //!< Bit mask for USBDCD_TIMER2_BC12_TVDMSRC_ON.
#define BS_USBDCD_TIMER2_BC12_TVDMSRC_ON (10U) //!< Bit field size in bits for USBDCD_TIMER2_BC12_TVDMSRC_ON.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the USBDCD_TIMER2_BC12_TVDMSRC_ON field.
#define BR_USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (HW_USBDCD_TIMER2_BC12(x).B.TVDMSRC_ON)
#endif
//! @brief Format value for bitfield USBDCD_TIMER2_BC12_TVDMSRC_ON.
#define BF_USBDCD_TIMER2_BC12_TVDMSRC_ON(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER2_BC12_TVDMSRC_ON), uint32_t) & BM_USBDCD_TIMER2_BC12_TVDMSRC_ON)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TVDMSRC_ON field to a new value.
#define BW_USBDCD_TIMER2_BC12_TVDMSRC_ON(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, (HW_USBDCD_TIMER2_BC12_RD(x) & ~BM_USBDCD_TIMER2_BC12_TVDMSRC_ON) | BF_USBDCD_TIMER2_BC12_TVDMSRC_ON(v)))
#endif
//@}
/*!
* @name Register USBDCD_TIMER2_BC12, field TWAIT_AFTER_PRD[25:16] (RW)
*
* Sets the amount of time (in ms) that the module waits after primary detection
* before start to secondary detection. Valid values are 1-1023ms. Default is
* 1ms.
*/
//@{
#define BP_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (16U) //!< Bit position for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD.
#define BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (0x03FF0000U) //!< Bit mask for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD.
#define BS_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (10U) //!< Bit field size in bits for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD field.
#define BR_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (HW_USBDCD_TIMER2_BC12(x).B.TWAIT_AFTER_PRD)
#endif
//! @brief Format value for bitfield USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD.
#define BF_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD), uint32_t) & BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TWAIT_AFTER_PRD field to a new value.
#define BW_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, (HW_USBDCD_TIMER2_BC12_RD(x) & ~BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD) | BF_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(v)))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_usbdcd_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All USBDCD module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_usbdcd
{
__IO hw_usbdcd_control_t CONTROL; //!< [0x0] Control register
__IO hw_usbdcd_clock_t CLOCK; //!< [0x4] Clock register
__I hw_usbdcd_status_t STATUS; //!< [0x8] Status register
uint8_t _reserved0[4];
__IO hw_usbdcd_timer0_t TIMER0; //!< [0x10] TIMER0 register
__IO hw_usbdcd_timer1_t TIMER1; //!< [0x14] TIMER1 register
union {
__IO hw_usbdcd_timer2_bc11_t TIMER2_BC11; //!< [0x18] TIMER2_BC11 register
__IO hw_usbdcd_timer2_bc12_t TIMER2_BC12; //!< [0x18] TIMER2_BC12 register
};
} hw_usbdcd_t;
#pragma pack()
//! @brief Macro to access all USBDCD registers.
//! @param x USBDCD instance number.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_USBDCD(0)</code>.
#define HW_USBDCD(x) (*(hw_usbdcd_t *) REGS_USBDCD_BASE(x))
#endif
#endif // __HW_USBDCD_REGISTERS_H__
// v22/130726/0.9
// EOF

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_VREF_REGISTERS_H__
#define __HW_VREF_REGISTERS_H__
#include "regs.h"
/*
* MK64F12 VREF
*
* Voltage Reference
*
* Registers defined in this header file:
* - HW_VREF_TRM - VREF Trim Register
* - HW_VREF_SC - VREF Status and Control Register
*
* - hw_vref_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_VREF_BASE
#define HW_VREF_INSTANCE_COUNT (1U) //!< Number of instances of the VREF module.
#define REGS_VREF_BASE (0x40074000U) //!< Base address for VREF.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_VREF_TRM - VREF Trim Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_VREF_TRM - VREF Trim Register (RW)
*
* Reset value: 0x00U
*
* This register contains bits that contain the trim data for the Voltage
* Reference.
*/
typedef union _hw_vref_trm
{
uint8_t U;
struct _hw_vref_trm_bitfields
{
uint8_t TRIM : 6; //!< [5:0] Trim bits
uint8_t CHOPEN : 1; //!< [6] Chop oscillator enable. When set,
//! internal chopping operation is enabled and the internal analog offset will
//! be minimized.
uint8_t RESERVED0 : 1; //!< [7]
} B;
} hw_vref_trm_t;
#endif
/*!
* @name Constants and macros for entire VREF_TRM register
*/
//@{
#define HW_VREF_TRM_ADDR (REGS_VREF_BASE + 0x0U)
#ifndef __LANGUAGE_ASM__
#define HW_VREF_TRM (*(__IO hw_vref_trm_t *) HW_VREF_TRM_ADDR)
#define HW_VREF_TRM_RD() (HW_VREF_TRM.U)
#define HW_VREF_TRM_WR(v) (HW_VREF_TRM.U = (v))
#define HW_VREF_TRM_SET(v) (HW_VREF_TRM_WR(HW_VREF_TRM_RD() | (v)))
#define HW_VREF_TRM_CLR(v) (HW_VREF_TRM_WR(HW_VREF_TRM_RD() & ~(v)))
#define HW_VREF_TRM_TOG(v) (HW_VREF_TRM_WR(HW_VREF_TRM_RD() ^ (v)))
#endif
//@}
/*
* Constants & macros for individual VREF_TRM bitfields
*/
/*!
* @name Register VREF_TRM, field TRIM[5:0] (RW)
*
* These bits change the resulting VREF by approximately +/- 0.5 mV for each
* step. Min = minimum and max = maximum voltage reference output. For minimum and
* maximum voltage reference output values, refer to the Data Sheet for this chip.
*
* Values:
* - 000000 - Min
* - 111111 - Max
*/
//@{
#define BP_VREF_TRM_TRIM (0U) //!< Bit position for VREF_TRM_TRIM.
#define BM_VREF_TRM_TRIM (0x3FU) //!< Bit mask for VREF_TRM_TRIM.
#define BS_VREF_TRM_TRIM (6U) //!< Bit field size in bits for VREF_TRM_TRIM.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the VREF_TRM_TRIM field.
#define BR_VREF_TRM_TRIM (HW_VREF_TRM.B.TRIM)
#endif
//! @brief Format value for bitfield VREF_TRM_TRIM.
#define BF_VREF_TRM_TRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_TRM_TRIM), uint8_t) & BM_VREF_TRM_TRIM)
#ifndef __LANGUAGE_ASM__
//! @brief Set the TRIM field to a new value.
#define BW_VREF_TRM_TRIM(v) (HW_VREF_TRM_WR((HW_VREF_TRM_RD() & ~BM_VREF_TRM_TRIM) | BF_VREF_TRM_TRIM(v)))
#endif
//@}
/*!
* @name Register VREF_TRM, field CHOPEN[6] (RW)
*
* This bit is set during factory trimming of the VREF voltage. This bit should
* be written to 1 to achieve the performance stated in the data sheet.
*
* Values:
* - 0 - Chop oscillator is disabled.
* - 1 - Chop oscillator is enabled.
*/
//@{
#define BP_VREF_TRM_CHOPEN (6U) //!< Bit position for VREF_TRM_CHOPEN.
#define BM_VREF_TRM_CHOPEN (0x40U) //!< Bit mask for VREF_TRM_CHOPEN.
#define BS_VREF_TRM_CHOPEN (1U) //!< Bit field size in bits for VREF_TRM_CHOPEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the VREF_TRM_CHOPEN field.
#define BR_VREF_TRM_CHOPEN (BITBAND_ACCESS8(HW_VREF_TRM_ADDR, BP_VREF_TRM_CHOPEN))
#endif
//! @brief Format value for bitfield VREF_TRM_CHOPEN.
#define BF_VREF_TRM_CHOPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_TRM_CHOPEN), uint8_t) & BM_VREF_TRM_CHOPEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the CHOPEN field to a new value.
#define BW_VREF_TRM_CHOPEN(v) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR, BP_VREF_TRM_CHOPEN) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_VREF_SC - VREF Status and Control Register
//-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_VREF_SC - VREF Status and Control Register (RW)
*
* Reset value: 0x00U
*
* This register contains the control bits used to enable the internal voltage
* reference and to select the buffer mode to be used.
*/
typedef union _hw_vref_sc
{
uint8_t U;
struct _hw_vref_sc_bitfields
{
uint8_t MODE_LV : 2; //!< [1:0] Buffer Mode selection
uint8_t VREFST : 1; //!< [2] Internal Voltage Reference stable
uint8_t RESERVED0 : 2; //!< [4:3]
uint8_t ICOMPEN : 1; //!< [5] Second order curvature compensation
//! enable
uint8_t REGEN : 1; //!< [6] Regulator enable
uint8_t VREFEN : 1; //!< [7] Internal Voltage Reference enable
} B;
} hw_vref_sc_t;
#endif
/*!
* @name Constants and macros for entire VREF_SC register
*/
//@{
#define HW_VREF_SC_ADDR (REGS_VREF_BASE + 0x1U)
#ifndef __LANGUAGE_ASM__
#define HW_VREF_SC (*(__IO hw_vref_sc_t *) HW_VREF_SC_ADDR)
#define HW_VREF_SC_RD() (HW_VREF_SC.U)
#define HW_VREF_SC_WR(v) (HW_VREF_SC.U = (v))
#define HW_VREF_SC_SET(v) (HW_VREF_SC_WR(HW_VREF_SC_RD() | (v)))
#define HW_VREF_SC_CLR(v) (HW_VREF_SC_WR(HW_VREF_SC_RD() & ~(v)))
#define HW_VREF_SC_TOG(v) (HW_VREF_SC_WR(HW_VREF_SC_RD() ^ (v)))
#endif
//@}
/*
* Constants & macros for individual VREF_SC bitfields
*/
/*!
* @name Register VREF_SC, field MODE_LV[1:0] (RW)
*
* These bits select the buffer modes for the Voltage Reference module.
*
* Values:
* - 00 - Bandgap on only, for stabilization and startup
* - 01 - High power buffer mode enabled
* - 10 - Low-power buffer mode enabled
* - 11 - Reserved
*/
//@{
#define BP_VREF_SC_MODE_LV (0U) //!< Bit position for VREF_SC_MODE_LV.
#define BM_VREF_SC_MODE_LV (0x03U) //!< Bit mask for VREF_SC_MODE_LV.
#define BS_VREF_SC_MODE_LV (2U) //!< Bit field size in bits for VREF_SC_MODE_LV.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the VREF_SC_MODE_LV field.
#define BR_VREF_SC_MODE_LV (HW_VREF_SC.B.MODE_LV)
#endif
//! @brief Format value for bitfield VREF_SC_MODE_LV.
#define BF_VREF_SC_MODE_LV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_MODE_LV), uint8_t) & BM_VREF_SC_MODE_LV)
#ifndef __LANGUAGE_ASM__
//! @brief Set the MODE_LV field to a new value.
#define BW_VREF_SC_MODE_LV(v) (HW_VREF_SC_WR((HW_VREF_SC_RD() & ~BM_VREF_SC_MODE_LV) | BF_VREF_SC_MODE_LV(v)))
#endif
//@}
/*!
* @name Register VREF_SC, field VREFST[2] (RO)
*
* This bit indicates that the bandgap reference within the Voltage Reference
* module has completed its startup and stabilization.
*
* Values:
* - 0 - The module is disabled or not stable.
* - 1 - The module is stable.
*/
//@{
#define BP_VREF_SC_VREFST (2U) //!< Bit position for VREF_SC_VREFST.
#define BM_VREF_SC_VREFST (0x04U) //!< Bit mask for VREF_SC_VREFST.
#define BS_VREF_SC_VREFST (1U) //!< Bit field size in bits for VREF_SC_VREFST.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the VREF_SC_VREFST field.
#define BR_VREF_SC_VREFST (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFST))
#endif
//@}
/*!
* @name Register VREF_SC, field ICOMPEN[5] (RW)
*
* This bit is set during factory trimming of the VREF voltage. This bit should
* be written to 1 to achieve the performance stated in the data sheet.
*
* Values:
* - 0 - Disabled
* - 1 - Enabled
*/
//@{
#define BP_VREF_SC_ICOMPEN (5U) //!< Bit position for VREF_SC_ICOMPEN.
#define BM_VREF_SC_ICOMPEN (0x20U) //!< Bit mask for VREF_SC_ICOMPEN.
#define BS_VREF_SC_ICOMPEN (1U) //!< Bit field size in bits for VREF_SC_ICOMPEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the VREF_SC_ICOMPEN field.
#define BR_VREF_SC_ICOMPEN (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_ICOMPEN))
#endif
//! @brief Format value for bitfield VREF_SC_ICOMPEN.
#define BF_VREF_SC_ICOMPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_ICOMPEN), uint8_t) & BM_VREF_SC_ICOMPEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the ICOMPEN field to a new value.
#define BW_VREF_SC_ICOMPEN(v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_ICOMPEN) = (v))
#endif
//@}
/*!
* @name Register VREF_SC, field REGEN[6] (RW)
*
* This bit is used to enable the internal 1.75 V regulator to produce a
* constant internal voltage supply in order to reduce the sensitivity to external
* supply noise and variation. If it is desired to keep the regulator enabled in very
* low power modes, refer to the Chip Configuration details for a description on
* how this can be achieved. This bit is set during factory trimming of the VREF
* voltage. This bit should be written to 1 to achieve the performance stated in
* the data sheet.
*
* Values:
* - 0 - Internal 1.75 V regulator is disabled.
* - 1 - Internal 1.75 V regulator is enabled.
*/
//@{
#define BP_VREF_SC_REGEN (6U) //!< Bit position for VREF_SC_REGEN.
#define BM_VREF_SC_REGEN (0x40U) //!< Bit mask for VREF_SC_REGEN.
#define BS_VREF_SC_REGEN (1U) //!< Bit field size in bits for VREF_SC_REGEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the VREF_SC_REGEN field.
#define BR_VREF_SC_REGEN (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_REGEN))
#endif
//! @brief Format value for bitfield VREF_SC_REGEN.
#define BF_VREF_SC_REGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_REGEN), uint8_t) & BM_VREF_SC_REGEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the REGEN field to a new value.
#define BW_VREF_SC_REGEN(v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_REGEN) = (v))
#endif
//@}
/*!
* @name Register VREF_SC, field VREFEN[7] (RW)
*
* This bit is used to enable the bandgap reference within the Voltage Reference
* module. After the VREF is enabled, turning off the clock to the VREF module
* via the corresponding clock gate register will not disable the VREF. VREF must
* be disabled via this VREFEN bit.
*
* Values:
* - 0 - The module is disabled.
* - 1 - The module is enabled.
*/
//@{
#define BP_VREF_SC_VREFEN (7U) //!< Bit position for VREF_SC_VREFEN.
#define BM_VREF_SC_VREFEN (0x80U) //!< Bit mask for VREF_SC_VREFEN.
#define BS_VREF_SC_VREFEN (1U) //!< Bit field size in bits for VREF_SC_VREFEN.
#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the VREF_SC_VREFEN field.
#define BR_VREF_SC_VREFEN (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFEN))
#endif
//! @brief Format value for bitfield VREF_SC_VREFEN.
#define BF_VREF_SC_VREFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_VREFEN), uint8_t) & BM_VREF_SC_VREFEN)
#ifndef __LANGUAGE_ASM__
//! @brief Set the VREFEN field to a new value.
#define BW_VREF_SC_VREFEN(v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFEN) = (v))
#endif
//@}
//-------------------------------------------------------------------------------------------
// hw_vref_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All VREF module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_vref
{
__IO hw_vref_trm_t TRM; //!< [0x0] VREF Trim Register
__IO hw_vref_sc_t SC; //!< [0x1] VREF Status and Control Register
} hw_vref_t;
#pragma pack()
//! @brief Macro to access all VREF registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//! use the '&' operator, like <code>&HW_VREF</code>.
#define HW_VREF (*(hw_vref_t *) REGS_VREF_BASE)
#endif
#endif // __HW_VREF_REGISTERS_H__
// v22/130726/0.9
// EOF

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
#ifndef _REGS_H
#define _REGS_H 1
#include <stdint.h>
#include <stdlib.h>
//
// define base address of the register block only if it is not already
// defined, which allows the compiler to override at build time for
// users who've mapped their registers to locations other than the
// physical location
//
#include <stdint.h>
#ifndef REGS_BASE
#define REGS_BASE 0x00000000
#endif
//
// common register types
//
#ifndef __LANGUAGE_ASM__
typedef unsigned char reg8_t;
typedef unsigned short reg16_t;
typedef unsigned int reg32_t;
#endif
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
#define BME_AND_MASK (1<<26)
#define BME_OR_MASK (1<<27)
#define BME_XOR_MASK (3<<26)
#define BME_BFI_MASK(BIT,WIDTH) (1<<28) | (BIT<<23) | ((WIDTH-1)<<19)
#define BME_UBFX_MASK(BIT,WIDTH) (1<<28) | (BIT<<23) | ((WIDTH-1)<<19)
/**
* @brief Macro to access a single bit of a 32-bit peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
/**
* @brief Macro to access a single bit of a 16-bit peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_ACCESS16(Reg,Bit) (*((uint16_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
/**
* @brief Macro to access a single bit of an 8-bit peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
//
// Typecast macro for C or asm. In C, the cast is applied, while in asm it is excluded. This is
// used to simplify macro definitions in the module register headers.
//
#ifndef __REG_VALUE_TYPE
#ifndef __LANGUAGE_ASM__
#define __REG_VALUE_TYPE(v, t) ((t)(v))
#else
#define __REG_VALUE_TYPE(v, t) (v)
#endif
#endif
//
// macros for single instance registers
//
#define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field)
#define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field)
#define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field)
#define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v))
#define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v))
#define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v))
#define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
#define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym
#define BF_RD(reg, field) HW_##reg.B.field
#define BF_WR(reg, field, v) BW_##reg##_##field(v)
#define BF_CS1(reg, f1, v1) \
(HW_##reg##_CLR(BM_##reg##_##f1), \
HW_##reg##_SET(BF_##reg##_##f1(v1)))
#define BF_CS2(reg, f1, v1, f2, v2) \
(HW_##reg##_CLR(BM_##reg##_##f1 | \
BM_##reg##_##f2), \
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2)))
#define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \
(HW_##reg##_CLR(BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3), \
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3)))
#define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \
(HW_##reg##_CLR(BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4), \
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4)))
#define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
(HW_##reg##_CLR(BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5), \
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5)))
#define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
(HW_##reg##_CLR(BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6), \
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6)))
#define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
(HW_##reg##_CLR(BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6 | \
BM_##reg##_##f7), \
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6) | \
BF_##reg##_##f7(v7)))
#define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
(HW_##reg##_CLR(BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6 | \
BM_##reg##_##f7 | \
BM_##reg##_##f8), \
HW_##reg##_SET(BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6) | \
BF_##reg##_##f7(v7) | \
BF_##reg##_##f8(v8)))
//
// macros for multiple instance registers
//
#define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field)
#define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field)
#define BF_TOGn(reg, n, field) HW_##reg##_TOG(n, BM_##reg##_##field)
#define BF_SETVn(reg, n, field, v) HW_##reg##_SET(n, BF_##reg##_##field(v))
#define BF_CLRVn(reg, n, field, v) HW_##reg##_CLR(n, BF_##reg##_##field(v))
#define BF_TOGVn(reg, n, field, v) HW_##reg##_TOG(n, BF_##reg##_##field(v))
#define BV_FLDn(reg, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
#define BV_VALn(reg, n, field, sym) BV_##reg##_##field##__##sym
#define BF_RDn(reg, n, field) HW_##reg(n).B.field
#define BF_WRn(reg, n, field, v) BW_##reg##_##field(n, v)
#define BF_CS1n(reg, n, f1, v1) \
(HW_##reg##_CLR(n, (BM_##reg##_##f1)), \
HW_##reg##_SET(n, (BF_##reg##_##f1(v1))))
#define BF_CS2n(reg, n, f1, v1, f2, v2) \
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
BM_##reg##_##f2)), \
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2))))
#define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3)), \
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3))))
#define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4)), \
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4))))
#define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5)), \
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5))))
#define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6)), \
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6))))
#define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6 | \
BM_##reg##_##f7)), \
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6) | \
BF_##reg##_##f7(v7))))
#define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
(HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6 | \
BM_##reg##_##f7 | \
BM_##reg##_##f8)), \
HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6) | \
BF_##reg##_##f7(v7) | \
BF_##reg##_##f8(v8))))
//
// macros for single instance MULTI-BLOCK registers
//
#define BFn_SET(reg, blk, field) HW_##reg##_SET(blk, BM_##reg##_##field)
#define BFn_CLR(reg, blk, field) HW_##reg##_CLR(blk, BM_##reg##_##field)
#define BFn_TOG(reg, blk, field) HW_##reg##_TOG(blk, BM_##reg##_##field)
#define BFn_SETV(reg, blk, field, v) HW_##reg##_SET(blk, BF_##reg##_##field(v))
#define BFn_CLRV(reg, blk, field, v) HW_##reg##_CLR(blk, BF_##reg##_##field(v))
#define BFn_TOGV(reg, blk, field, v) HW_##reg##_TOG(blk, BF_##reg##_##field(v))
#define BVn_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
#define BVn_VAL(reg, field, sym) BV_##reg##_##field##__##sym
#define BFn_RD(reg, blk, field) HW_##reg(blk).B.field
#define BFn_WR(reg, blk, field, v) BW_##reg##_##field(blk, v)
#define BFn_CS1(reg, blk, f1, v1) \
(HW_##reg##_CLR(blk, BM_##reg##_##f1), \
HW_##reg##_SET(blk, BF_##reg##_##f1(v1)))
#define BFn_CS2(reg, blk, f1, v1, f2, v2) \
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
BM_##reg##_##f2), \
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2)))
#define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3) \
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3), \
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3)))
#define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4) \
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4), \
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4)))
#define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5), \
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5)))
#define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6), \
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6)))
#define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6 | \
BM_##reg##_##f7), \
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6) | \
BF_##reg##_##f7(v7)))
#define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
(HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6 | \
BM_##reg##_##f7 | \
BM_##reg##_##f8), \
HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6) | \
BF_##reg##_##f7(v7) | \
BF_##reg##_##f8(v8)))
//
// macros for MULTI-BLOCK multiple instance registers
//
#define BFn_SETn(reg, blk, n, field) HW_##reg##_SET(blk, n, BM_##reg##_##field)
#define BFn_CLRn(reg, blk, n, field) HW_##reg##_CLR(blk, n, BM_##reg##_##field)
#define BFn_TOGn(reg, blk, n, field) HW_##reg##_TOG(blk, n, BM_##reg##_##field)
#define BFn_SETVn(reg, blk, n, field, v) HW_##reg##_SET(blk, n, BF_##reg##_##field(v))
#define BFn_CLRVn(reg, blk, n, field, v) HW_##reg##_CLR(blk, n, BF_##reg##_##field(v))
#define BFn_TOGVn(reg, blk, n, field, v) HW_##reg##_TOG(blk, n, BF_##reg##_##field(v))
#define BVn_FLDn(reg, blk, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
#define BVn_VALn(reg, blk, n, field, sym) BV_##reg##_##field##__##sym
#define BFn_RDn(reg, blk, n, field) HW_##reg(n).B.field
#define BFn_WRn(reg, blk, n, field, v) BW_##reg##_##field(n, v)
#define BFn_CS1n(reg, blk, n, f1, v1) \
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)), \
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1))))
#define BFn_CS2n(reg, blk, n, f1, v1, f2, v2) \
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
BM_##reg##_##f2)), \
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2))))
#define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3) \
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3)), \
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3))))
#define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4) \
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4)), \
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4))))
#define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5)), \
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5))))
#define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6)), \
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6))))
#define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6 | \
BM_##reg##_##f7)), \
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6) | \
BF_##reg##_##f7(v7))))
#define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
(HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
BM_##reg##_##f2 | \
BM_##reg##_##f3 | \
BM_##reg##_##f4 | \
BM_##reg##_##f5 | \
BM_##reg##_##f6 | \
BM_##reg##_##f7 | \
BM_##reg##_##f8)), \
HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
BF_##reg##_##f2(v2) | \
BF_##reg##_##f3(v3) | \
BF_##reg##_##f4(v4) | \
BF_##reg##_##f5(v5) | \
BF_##reg##_##f6(v6) | \
BF_##reg##_##f7(v7) | \
BF_##reg##_##f8(v8))))
#endif // _REGS_H
////////////////////////////////////////////////////////////////////////////////

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@ -0,0 +1,169 @@
/*
** ###################################################################
** Processor: MK64FN1M0VMD12
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
** Version: rev. 2.3, 2014-01-24
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2014 Freescale, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2013-08-12)
** Initial version.
** - rev. 2.0 (2013-10-29)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** System initialization updated.
** MCG - registers updated.
** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
** - rev. 2.1 (2013-10-29)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** - rev. 2.2 (2013-12-09)
** DMA - EARS register removed.
** AIPS0, AIPS1 - MPRA register updated.
** - rev. 2.3 (2014-01-24)
** Update according to reference manual rev. 2
** ENET, MCG, MCM, SIM, USB - registers updated
**
** ###################################################################
*/
/*!
* @file MK64F12
* @version 2.3
* @date 2014-01-24
* @brief Device specific configuration file for MK64F12 (header file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#ifndef SYSTEM_MK64F12_H_
#define SYSTEM_MK64F12_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#define DISABLE_WDOG 1
#ifndef CLOCK_SETUP
#define CLOCK_SETUP 4
#endif
/* Predefined clock setups
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
Default part configuration.
Reference clock source for MCG module is the slow internal clock source 32.768kHz
Core clock = 20.97MHz, BusClock = 20.97MHz
1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
Maximum achievable clock frequency configuration.
Reference clock source for MCG module is an external clock source 50MHz
Core clock = 120MHz, BusClock = 60MHz
2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power Internal (BLPI) mode
Core clock/Bus clock derived directly from an fast internal clock 4MHz with no multiplication
The clock settings is ready for Very Low Power Run mode.
Core clock = 4MHz, BusClock = 4MHz
3 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
Core clock/Bus clock derived directly from the RTC oscillator clock source 32.768kHz
The clock settings is ready for Very Low Power Run mode.
Core clock = 32.768kHz, BusClock = 32.768kHz
4 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
USB clock setup
USB clock divider is set for USB to receive 48MHz input clock.
Reference clock source for MCG module is an external clock source 50MHz
USB clock divider is set for USB to receive 48MHz input clock.
Core clock = 120MHz, BusClock = 60MHz
*/
/*----------------------------------------------------------------------------
Define clock source values
*----------------------------------------------------------------------------*/
#if (CLOCK_SETUP == 0)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 20485760u /* Default System clock value */
#elif (CLOCK_SETUP == 1)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
#elif (CLOCK_SETUP == 2)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
#elif (CLOCK_SETUP == 3)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
#elif (CLOCK_SETUP == 4)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
#endif /* (CLOCK_SETUP == 4) */
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit (void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* #if !defined(SYSTEM_MK64F12_H_) */

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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __FSL_DEVICE_REGISTERS_H__
#define __FSL_DEVICE_REGISTERS_H__
/*
* Include the cpu specific register header files.
*
* The CPU macro should be declared in the project or makefile.
*/
#if (defined(CPU_MK22FN512VDC12))
#define K22F51212_SERIES
/* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/
#include "device/MK22F51212/MK22F51212_adc.h"
#include "device/MK22F51212/MK22F51212_aips.h"
#include "device/MK22F51212/MK22F51212_cmp.h"
#include "device/MK22F51212/MK22F51212_crc.h"
#include "device/MK22F51212/MK22F51212_dac.h"
#include "device/MK22F51212/MK22F51212_dma.h"
#include "device/MK22F51212/MK22F51212_dmamux.h"
#include "device/MK22F51212/MK22F51212_ewm.h"
#include "device/MK22F51212/MK22F51212_fb.h"
#include "device/MK22F51212/MK22F51212_fmc.h"
#include "device/MK22F51212/MK22F51212_ftfa.h"
#include "device/MK22F51212/MK22F51212_ftm.h"
#include "device/MK22F51212/MK22F51212_gpio.h"
#include "device/MK22F51212/MK22F51212_i2c.h"
#include "device/MK22F51212/MK22F51212_i2s.h"
#include "device/MK22F51212/MK22F51212_llwu.h"
#include "device/MK22F51212/MK22F51212_lptmr.h"
#include "device/MK22F51212/MK22F51212_mcg.h"
#include "device/MK22F51212/MK22F51212_mcm.h"
#include "device/MK22F51212/MK22F51212_nv.h"
#include "device/MK22F51212/MK22F51212_osc.h"
#include "device/MK22F51212/MK22F51212_pdb.h"
#include "device/MK22F51212/MK22F51212_pit.h"
#include "device/MK22F51212/MK22F51212_pmc.h"
#include "device/MK22F51212/MK22F51212_port.h"
#include "device/MK22F51212/MK22F51212_rcm.h"
#include "device/MK22F51212/MK22F51212_rfsys.h"
#include "device/MK22F51212/MK22F51212_rfvbat.h"
#include "device/MK22F51212/MK22F51212_rng.h"
#include "device/MK22F51212/MK22F51212_rtc.h"
#include "device/MK22F51212/MK22F51212_sim.h"
#include "device/MK22F51212/MK22F51212_smc.h"
#include "device/MK22F51212/MK22F51212_spi.h"
#include "device/MK22F51212/MK22F51212_uart.h"
#include "device/MK22F51212/MK22F51212_usb.h"
#include "device/MK22F51212/MK22F51212_vref.h"
#include "device/MK22F51212/MK22F51212_wdog.h"
/* CMSIS-style register definitions*/
#include "device/MK22F51212/MK22F51212.h"
#elif (defined(CPU_MK24FN1M0VLQ12))
/* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/
#include "device/MK24F12/MK24F12_adc.h"
#include "device/MK24F12/MK24F12_aips.h"
#include "device/MK24F12/MK24F12_axbs.h"
#include "device/MK24F12/MK24F12_can.h"
#include "device/MK24F12/MK24F12_cau.h"
#include "device/MK24F12/MK24F12_cmp.h"
#include "device/MK24F12/MK24F12_cmt.h"
#include "device/MK24F12/MK24F12_crc.h"
#include "device/MK24F12/MK24F12_dac.h"
#include "device/MK24F12/MK24F12_dma.h"
#include "device/MK24F12/MK24F12_dmamux.h"
#include "device/MK24F12/MK24F12_ewm.h"
#include "device/MK24F12/MK24F12_fb.h"
#include "device/MK24F12/MK24F12_fmc.h"
#include "device/MK24F12/MK24F12_ftfe.h"
#include "device/MK24F12/MK24F12_ftm.h"
#include "device/MK24F12/MK24F12_gpio.h"
#include "device/MK24F12/MK24F12_i2c.h"
#include "device/MK24F12/MK24F12_i2s.h"
#include "device/MK24F12/MK24F12_llwu.h"
#include "device/MK24F12/MK24F12_lptmr.h"
#include "device/MK24F12/MK24F12_mcg.h"
#include "device/MK24F12/MK24F12_mcm.h"
#include "device/MK24F12/MK24F12_mpu.h"
#include "device/MK24F12/MK24F12_nv.h"
#include "device/MK24F12/MK24F12_osc.h"
#include "device/MK24F12/MK24F12_pdb.h"
#include "device/MK24F12/MK24F12_pit.h"
#include "device/MK24F12/MK24F12_pmc.h"
#include "device/MK24F12/MK24F12_port.h"
#include "device/MK24F12/MK24F12_rcm.h"
#include "device/MK24F12/MK24F12_rfsys.h"
#include "device/MK24F12/MK24F12_rfvbat.h"
#include "device/MK24F12/MK24F12_rng.h"
#include "device/MK24F12/MK24F12_rtc.h"
#include "device/MK24F12/MK24F12_sdhc.h"
#include "device/MK24F12/MK24F12_sim.h"
#include "device/MK24F12/MK24F12_smc.h"
#include "device/MK24F12/MK24F12_spi.h"
#include "device/MK24F12/MK24F12_uart.h"
#include "device/MK24F12/MK24F12_usb.h"
#include "device/MK24F12/MK24F12_usbdcd.h"
#include "device/MK24F12/MK24F12_vref.h"
#include "device/MK24F12/MK24F12_wdog.h"
/* CMSIS-style register definitions*/
#include "device/MK24F12/MK24F12.h"
#elif (defined(CPU_MK63FN1M0VMD12))
/* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/
#include "device/MK63F12/MK63F12_adc.h"
#include "device/MK63F12/MK63F12_aips.h"
#include "device/MK63F12/MK63F12_axbs.h"
#include "device/MK63F12/MK63F12_can.h"
#include "device/MK63F12/MK63F12_cau.h"
#include "device/MK63F12/MK63F12_cmp.h"
#include "device/MK63F12/MK63F12_cmt.h"
#include "device/MK63F12/MK63F12_crc.h"
#include "device/MK63F12/MK63F12_dac.h"
#include "device/MK63F12/MK63F12_dma.h"
#include "device/MK63F12/MK63F12_dmamux.h"
#include "device/MK63F12/MK63F12_enet.h"
#include "device/MK63F12/MK63F12_ewm.h"
#include "device/MK63F12/MK63F12_fb.h"
#include "device/MK63F12/MK63F12_fmc.h"
#include "device/MK63F12/MK63F12_ftfe.h"
#include "device/MK63F12/MK63F12_ftm.h"
#include "device/MK63F12/MK63F12_gpio.h"
#include "device/MK63F12/MK63F12_i2c.h"
#include "device/MK63F12/MK63F12_i2s.h"
#include "device/MK63F12/MK63F12_llwu.h"
#include "device/MK63F12/MK63F12_lptmr.h"
#include "device/MK63F12/MK63F12_mcg.h"
#include "device/MK63F12/MK63F12_mcm.h"
#include "device/MK63F12/MK63F12_mpu.h"
#include "device/MK63F12/MK63F12_nv.h"
#include "device/MK63F12/MK63F12_osc.h"
#include "device/MK63F12/MK63F12_pdb.h"
#include "device/MK63F12/MK63F12_pit.h"
#include "device/MK63F12/MK63F12_pmc.h"
#include "device/MK63F12/MK63F12_port.h"
#include "device/MK63F12/MK63F12_rcm.h"
#include "device/MK63F12/MK63F12_rfsys.h"
#include "device/MK63F12/MK63F12_rfvbat.h"
#include "device/MK63F12/MK63F12_rng.h"
#include "device/MK63F12/MK63F12_rtc.h"
#include "device/MK63F12/MK63F12_sdhc.h"
#include "device/MK63F12/MK63F12_sim.h"
#include "device/MK63F12/MK63F12_smc.h"
#include "device/MK63F12/MK63F12_spi.h"
#include "device/MK63F12/MK63F12_uart.h"
#include "device/MK63F12/MK63F12_usb.h"
#include "device/MK63F12/MK63F12_usbdcd.h"
#include "device/MK63F12/MK63F12_vref.h"
#include "device/MK63F12/MK63F12_wdog.h"
/* CMSIS-style register definitions*/
#include "device/MK63F12/MK63F12.h"
#elif (defined(CPU_MK63FN1M0VMD12WS))
/* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/
#include "device/MK63F12WS/MK63F12WS_adc.h"
#include "device/MK63F12WS/MK63F12WS_aips.h"
#include "device/MK63F12WS/MK63F12WS_axbs.h"
#include "device/MK63F12WS/MK63F12WS_can.h"
#include "device/MK63F12WS/MK63F12WS_cau.h"
#include "device/MK63F12WS/MK63F12WS_cmp.h"
#include "device/MK63F12WS/MK63F12WS_cmt.h"
#include "device/MK63F12WS/MK63F12WS_crc.h"
#include "device/MK63F12WS/MK63F12WS_dac.h"
#include "device/MK63F12WS/MK63F12WS_dma.h"
#include "device/MK63F12WS/MK63F12WS_dmamux.h"
#include "device/MK63F12WS/MK63F12WS_dry.h"
#include "device/MK63F12WS/MK63F12WS_enet.h"
#include "device/MK63F12WS/MK63F12WS_ewm.h"
#include "device/MK63F12WS/MK63F12WS_fb.h"
#include "device/MK63F12WS/MK63F12WS_fmc.h"
#include "device/MK63F12WS/MK63F12WS_ftfe.h"
#include "device/MK63F12WS/MK63F12WS_ftm.h"
#include "device/MK63F12WS/MK63F12WS_gpio.h"
#include "device/MK63F12WS/MK63F12WS_i2c.h"
#include "device/MK63F12WS/MK63F12WS_i2s.h"
#include "device/MK63F12WS/MK63F12WS_llwu.h"
#include "device/MK63F12WS/MK63F12WS_lptmr.h"
#include "device/MK63F12WS/MK63F12WS_mcg.h"
#include "device/MK63F12WS/MK63F12WS_mcm.h"
#include "device/MK63F12WS/MK63F12WS_mpu.h"
#include "device/MK63F12WS/MK63F12WS_nv.h"
#include "device/MK63F12WS/MK63F12WS_osc.h"
#include "device/MK63F12WS/MK63F12WS_pdb.h"
#include "device/MK63F12WS/MK63F12WS_pit.h"
#include "device/MK63F12WS/MK63F12WS_pmc.h"
#include "device/MK63F12WS/MK63F12WS_port.h"
#include "device/MK63F12WS/MK63F12WS_rcm.h"
#include "device/MK63F12WS/MK63F12WS_rfsys.h"
#include "device/MK63F12WS/MK63F12WS_rfvbat.h"
#include "device/MK63F12WS/MK63F12WS_rng.h"
#include "device/MK63F12WS/MK63F12WS_rtc.h"
#include "device/MK63F12WS/MK63F12WS_sdhc.h"
#include "device/MK63F12WS/MK63F12WS_sim.h"
#include "device/MK63F12WS/MK63F12WS_smc.h"
#include "device/MK63F12WS/MK63F12WS_spi.h"
#include "device/MK63F12WS/MK63F12WS_uart.h"
#include "device/MK63F12WS/MK63F12WS_usb.h"
#include "device/MK63F12WS/MK63F12WS_usbdcd.h"
#include "device/MK63F12WS/MK63F12WS_vref.h"
#include "device/MK63F12WS/MK63F12WS_wdog.h"
/* CMSIS-style register definitions*/
#include "device/MK63F12WS/MK63F12WS.h"
#elif (defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12))
#define K64F12_SERIES
/* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/
#include "device/MK64F12/MK64F12_adc.h"
#include "device/MK64F12/MK64F12_aips.h"
#include "device/MK64F12/MK64F12_axbs.h"
#include "device/MK64F12/MK64F12_can.h"
#include "device/MK64F12/MK64F12_cau.h"
#include "device/MK64F12/MK64F12_cmp.h"
#include "device/MK64F12/MK64F12_cmt.h"
#include "device/MK64F12/MK64F12_crc.h"
#include "device/MK64F12/MK64F12_dac.h"
#include "device/MK64F12/MK64F12_dma.h"
#include "device/MK64F12/MK64F12_dmamux.h"
#include "device/MK64F12/MK64F12_enet.h"
#include "device/MK64F12/MK64F12_ewm.h"
#include "device/MK64F12/MK64F12_fb.h"
#include "device/MK64F12/MK64F12_fmc.h"
#include "device/MK64F12/MK64F12_ftfe.h"
#include "device/MK64F12/MK64F12_ftm.h"
#include "device/MK64F12/MK64F12_gpio.h"
#include "device/MK64F12/MK64F12_i2c.h"
#include "device/MK64F12/MK64F12_i2s.h"
#include "device/MK64F12/MK64F12_llwu.h"
#include "device/MK64F12/MK64F12_lptmr.h"
#include "device/MK64F12/MK64F12_mcg.h"
#include "device/MK64F12/MK64F12_mcm.h"
#include "device/MK64F12/MK64F12_mpu.h"
#include "device/MK64F12/MK64F12_nv.h"
#include "device/MK64F12/MK64F12_osc.h"
#include "device/MK64F12/MK64F12_pdb.h"
#include "device/MK64F12/MK64F12_pit.h"
#include "device/MK64F12/MK64F12_pmc.h"
#include "device/MK64F12/MK64F12_port.h"
#include "device/MK64F12/MK64F12_rcm.h"
#include "device/MK64F12/MK64F12_rfsys.h"
#include "device/MK64F12/MK64F12_rfvbat.h"
#include "device/MK64F12/MK64F12_rng.h"
#include "device/MK64F12/MK64F12_rtc.h"
#include "device/MK64F12/MK64F12_sdhc.h"
#include "device/MK64F12/MK64F12_sim.h"
#include "device/MK64F12/MK64F12_smc.h"
#include "device/MK64F12/MK64F12_spi.h"
#include "device/MK64F12/MK64F12_uart.h"
#include "device/MK64F12/MK64F12_usb.h"
#include "device/MK64F12/MK64F12_usbdcd.h"
#include "device/MK64F12/MK64F12_vref.h"
#include "device/MK64F12/MK64F12_wdog.h"
/* CMSIS-style register definitions*/
#include "device/MK64F12/MK64F12.h"
#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \
defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \
defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15))
#define K70F12_SERIES
/* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/
#include "device/MK70F12/MK70F12_adc.h"
#include "device/MK70F12/MK70F12_aips.h"
#include "device/MK70F12/MK70F12_axbs.h"
#include "device/MK70F12/MK70F12_can.h"
#include "device/MK70F12/MK70F12_cau.h"
#include "device/MK70F12/MK70F12_cmp.h"
#include "device/MK70F12/MK70F12_cmt.h"
#include "device/MK70F12/MK70F12_crc.h"
#include "device/MK70F12/MK70F12_dac.h"
#include "device/MK70F12/MK70F12_ddr.h"
#include "device/MK70F12/MK70F12_dma.h"
#include "device/MK70F12/MK70F12_dmamux.h"
#include "device/MK70F12/MK70F12_enet.h"
#include "device/MK70F12/MK70F12_ewm.h"
#include "device/MK70F12/MK70F12_fb.h"
#include "device/MK70F12/MK70F12_fmc.h"
#include "device/MK70F12/MK70F12_ftfe.h"
#include "device/MK70F12/MK70F12_ftm.h"
#include "device/MK70F12/MK70F12_gpio.h"
#include "device/MK70F12/MK70F12_i2c.h"
#include "device/MK70F12/MK70F12_i2s.h"
#include "device/MK70F12/MK70F12_lcdc.h"
#include "device/MK70F12/MK70F12_llwu.h"
#include "device/MK70F12/MK70F12_lmem.h"
#include "device/MK70F12/MK70F12_lptmr.h"
#include "device/MK70F12/MK70F12_mcg.h"
#include "device/MK70F12/MK70F12_mcm.h"
#include "device/MK70F12/MK70F12_mpu.h"
#include "device/MK70F12/MK70F12_nfc.h"
#include "device/MK70F12/MK70F12_nv.h"
#include "device/MK70F12/MK70F12_osc.h"
#include "device/MK70F12/MK70F12_pdb.h"
#include "device/MK70F12/MK70F12_pit.h"
#include "device/MK70F12/MK70F12_pmc.h"
#include "device/MK70F12/MK70F12_port.h"
#include "device/MK70F12/MK70F12_rcm.h"
#include "device/MK70F12/MK70F12_rfsys.h"
#include "device/MK70F12/MK70F12_rfvbat.h"
#include "device/MK70F12/MK70F12_rng.h"
#include "device/MK70F12/MK70F12_rtc.h"
#include "device/MK70F12/MK70F12_sdhc.h"
#include "device/MK70F12/MK70F12_sim.h"
#include "device/MK70F12/MK70F12_smc.h"
#include "device/MK70F12/MK70F12_spi.h"
#include "device/MK70F12/MK70F12_tsi.h"
#include "device/MK70F12/MK70F12_uart.h"
#include "device/MK70F12/MK70F12_usb.h"
#include "device/MK70F12/MK70F12_usbdcd.h"
#include "device/MK70F12/MK70F12_usbhs.h"
#include "device/MK70F12/MK70F12_vref.h"
#include "device/MK70F12/MK70F12_wdog.h"
/* CMSIS-style register definitions*/
#include "device/MK70F12/MK70F12.h"
#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \
defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \
defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15))
/* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/
#include "device/MK70F15/MK70F15_adc.h"
#include "device/MK70F15/MK70F15_aips.h"
#include "device/MK70F15/MK70F15_axbs.h"
#include "device/MK70F15/MK70F15_can.h"
#include "device/MK70F15/MK70F15_cau.h"
#include "device/MK70F15/MK70F15_cmp.h"
#include "device/MK70F15/MK70F15_cmt.h"
#include "device/MK70F15/MK70F15_crc.h"
#include "device/MK70F15/MK70F15_dac.h"
#include "device/MK70F15/MK70F15_ddr.h"
#include "device/MK70F15/MK70F15_dma.h"
#include "device/MK70F15/MK70F15_dmamux.h"
#include "device/MK70F15/MK70F15_enet.h"
#include "device/MK70F15/MK70F15_ewm.h"
#include "device/MK70F15/MK70F15_fb.h"
#include "device/MK70F15/MK70F15_fmc.h"
#include "device/MK70F15/MK70F15_ftfe.h"
#include "device/MK70F15/MK70F15_ftm.h"
#include "device/MK70F15/MK70F15_gpio.h"
#include "device/MK70F15/MK70F15_i2c.h"
#include "device/MK70F15/MK70F15_i2s.h"
#include "device/MK70F15/MK70F15_lcdc.h"
#include "device/MK70F15/MK70F15_llwu.h"
#include "device/MK70F15/MK70F15_lmem.h"
#include "device/MK70F15/MK70F15_lptmr.h"
#include "device/MK70F15/MK70F15_mcg.h"
#include "device/MK70F15/MK70F15_mcm.h"
#include "device/MK70F15/MK70F15_mpu.h"
#include "device/MK70F15/MK70F15_nfc.h"
#include "device/MK70F15/MK70F15_nv.h"
#include "device/MK70F15/MK70F15_osc.h"
#include "device/MK70F15/MK70F15_pdb.h"
#include "device/MK70F15/MK70F15_pit.h"
#include "device/MK70F15/MK70F15_pmc.h"
#include "device/MK70F15/MK70F15_port.h"
#include "device/MK70F15/MK70F15_rcm.h"
#include "device/MK70F15/MK70F15_rfsys.h"
#include "device/MK70F15/MK70F15_rfvbat.h"
#include "device/MK70F15/MK70F15_rng.h"
#include "device/MK70F15/MK70F15_rtc.h"
#include "device/MK70F15/MK70F15_sdhc.h"
#include "device/MK70F15/MK70F15_sim.h"
#include "device/MK70F15/MK70F15_smc.h"
#include "device/MK70F15/MK70F15_spi.h"
#include "device/MK70F15/MK70F15_tsi.h"
#include "device/MK70F15/MK70F15_uart.h"
#include "device/MK70F15/MK70F15_usb.h"
#include "device/MK70F15/MK70F15_usbdcd.h"
#include "device/MK70F15/MK70F15_usbhs.h"
#include "device/MK70F15/MK70F15_vref.h"
#include "device/MK70F15/MK70F15_wdog.h"
/* CMSIS-style register definitions*/
#include "device/MK70F15/MK70F15.h"
#elif (defined(CPU_MK70FN1M0VMJ12WS) || defined(CPU_MK70FX512VMJ12WS) || defined(CPU_MK70FN1M0VMJ15WS) || \
defined(CPU_MK70FX512VMJ15WS))
/* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/
#include "device/MK70F12WS/MK70F12WS_adc.h"
#include "device/MK70F12WS/MK70F12WS_aips.h"
#include "device/MK70F12WS/MK70F12WS_axbs.h"
#include "device/MK70F12WS/MK70F12WS_can.h"
#include "device/MK70F12WS/MK70F12WS_cau.h"
#include "device/MK70F12WS/MK70F12WS_cmp.h"
#include "device/MK70F12WS/MK70F12WS_cmt.h"
#include "device/MK70F12WS/MK70F12WS_crc.h"
#include "device/MK70F12WS/MK70F12WS_dac.h"
#include "device/MK70F12WS/MK70F12WS_ddr.h"
#include "device/MK70F12WS/MK70F12WS_dma.h"
#include "device/MK70F12WS/MK70F12WS_dmamux.h"
#include "device/MK70F12WS/MK70F12WS_dry.h"
#include "device/MK70F12WS/MK70F12WS_enet.h"
#include "device/MK70F12WS/MK70F12WS_ewm.h"
#include "device/MK70F12WS/MK70F12WS_fb.h"
#include "device/MK70F12WS/MK70F12WS_fmc.h"
#include "device/MK70F12WS/MK70F12WS_ftfe.h"
#include "device/MK70F12WS/MK70F12WS_ftm.h"
#include "device/MK70F12WS/MK70F12WS_gpio.h"
#include "device/MK70F12WS/MK70F12WS_i2c.h"
#include "device/MK70F12WS/MK70F12WS_i2s.h"
#include "device/MK70F12WS/MK70F12WS_lcdc.h"
#include "device/MK70F12WS/MK70F12WS_llwu.h"
#include "device/MK70F12WS/MK70F12WS_lmem.h"
#include "device/MK70F12WS/MK70F12WS_lptmr.h"
#include "device/MK70F12WS/MK70F12WS_mcg.h"
#include "device/MK70F12WS/MK70F12WS_mcm.h"
#include "device/MK70F12WS/MK70F12WS_mpu.h"
#include "device/MK70F12WS/MK70F12WS_nfc.h"
#include "device/MK70F12WS/MK70F12WS_nv.h"
#include "device/MK70F12WS/MK70F12WS_osc.h"
#include "device/MK70F12WS/MK70F12WS_pdb.h"
#include "device/MK70F12WS/MK70F12WS_pit.h"
#include "device/MK70F12WS/MK70F12WS_pmc.h"
#include "device/MK70F12WS/MK70F12WS_port.h"
#include "device/MK70F12WS/MK70F12WS_rcm.h"
#include "device/MK70F12WS/MK70F12WS_rfsys.h"
#include "device/MK70F12WS/MK70F12WS_rfvbat.h"
#include "device/MK70F12WS/MK70F12WS_rng.h"
#include "device/MK70F12WS/MK70F12WS_rtc.h"
#include "device/MK70F12WS/MK70F12WS_sdhc.h"
#include "device/MK70F12WS/MK70F12WS_sim.h"
#include "device/MK70F12WS/MK70F12WS_smc.h"
#include "device/MK70F12WS/MK70F12WS_spi.h"
#include "device/MK70F12WS/MK70F12WS_tsi.h"
#include "device/MK70F12WS/MK70F12WS_uart.h"
#include "device/MK70F12WS/MK70F12WS_usb.h"
#include "device/MK70F12WS/MK70F12WS_usbdcd.h"
#include "device/MK70F12WS/MK70F12WS_usbhs.h"
#include "device/MK70F12WS/MK70F12WS_vref.h"
#include "device/MK70F12WS/MK70F12WS_wdog.h"
/* CMSIS-style register definitions*/
#include "device/MK70F12WS/MK70F12WS.h"
#elif (defined(CPU_MK70FN1M0VMJ12WS) || defined(CPU_MK70FX512VMJ12WS) || defined(CPU_MK70FN1M0VMJ15WS) || \
defined(CPU_MK70FX512VMJ15WS))
/* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/
#include "device/MK70F15WS/MK70F15WS_adc.h"
#include "device/MK70F15WS/MK70F15WS_aips.h"
#include "device/MK70F15WS/MK70F15WS_axbs.h"
#include "device/MK70F15WS/MK70F15WS_can.h"
#include "device/MK70F15WS/MK70F15WS_cau.h"
#include "device/MK70F15WS/MK70F15WS_cmp.h"
#include "device/MK70F15WS/MK70F15WS_cmt.h"
#include "device/MK70F15WS/MK70F15WS_crc.h"
#include "device/MK70F15WS/MK70F15WS_dac.h"
#include "device/MK70F15WS/MK70F15WS_ddr.h"
#include "device/MK70F15WS/MK70F15WS_dma.h"
#include "device/MK70F15WS/MK70F15WS_dmamux.h"
#include "device/MK70F15WS/MK70F15WS_dry.h"
#include "device/MK70F15WS/MK70F15WS_enet.h"
#include "device/MK70F15WS/MK70F15WS_ewm.h"
#include "device/MK70F15WS/MK70F15WS_fb.h"
#include "device/MK70F15WS/MK70F15WS_fmc.h"
#include "device/MK70F15WS/MK70F15WS_ftfe.h"
#include "device/MK70F15WS/MK70F15WS_ftm.h"
#include "device/MK70F15WS/MK70F15WS_gpio.h"
#include "device/MK70F15WS/MK70F15WS_i2c.h"
#include "device/MK70F15WS/MK70F15WS_i2s.h"
#include "device/MK70F15WS/MK70F15WS_lcdc.h"
#include "device/MK70F15WS/MK70F15WS_llwu.h"
#include "device/MK70F15WS/MK70F15WS_lmem.h"
#include "device/MK70F15WS/MK70F15WS_lptmr.h"
#include "device/MK70F15WS/MK70F15WS_mcg.h"
#include "device/MK70F15WS/MK70F15WS_mcm.h"
#include "device/MK70F15WS/MK70F15WS_mpu.h"
#include "device/MK70F15WS/MK70F15WS_nfc.h"
#include "device/MK70F15WS/MK70F15WS_nv.h"
#include "device/MK70F15WS/MK70F15WS_osc.h"
#include "device/MK70F15WS/MK70F15WS_pdb.h"
#include "device/MK70F15WS/MK70F15WS_pit.h"
#include "device/MK70F15WS/MK70F15WS_pmc.h"
#include "device/MK70F15WS/MK70F15WS_port.h"
#include "device/MK70F15WS/MK70F15WS_rcm.h"
#include "device/MK70F15WS/MK70F15WS_rfsys.h"
#include "device/MK70F15WS/MK70F15WS_rfvbat.h"
#include "device/MK70F15WS/MK70F15WS_rng.h"
#include "device/MK70F15WS/MK70F15WS_rtc.h"
#include "device/MK70F15WS/MK70F15WS_sdhc.h"
#include "device/MK70F15WS/MK70F15WS_sim.h"
#include "device/MK70F15WS/MK70F15WS_smc.h"
#include "device/MK70F15WS/MK70F15WS_spi.h"
#include "device/MK70F15WS/MK70F15WS_tsi.h"
#include "device/MK70F15WS/MK70F15WS_uart.h"
#include "device/MK70F15WS/MK70F15WS_usb.h"
#include "device/MK70F15WS/MK70F15WS_usbdcd.h"
#include "device/MK70F15WS/MK70F15WS_usbhs.h"
#include "device/MK70F15WS/MK70F15WS_vref.h"
#include "device/MK70F15WS/MK70F15WS_wdog.h"
/* CMSIS-style register definitions*/
#include "device/MK70F15WS/MK70F15WS.h"
#elif (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \
defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4))
#define KL25Z4_SERIES
/* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/
#include "device/MKL25Z4/MKL25Z4_adc.h"
#include "device/MKL25Z4/MKL25Z4_cmp.h"
#include "device/MKL25Z4/MKL25Z4_dac.h"
#include "device/MKL25Z4/MKL25Z4_dma.h"
#include "device/MKL25Z4/MKL25Z4_dmamux.h"
#include "device/MKL25Z4/MKL25Z4_fgpio.h"
#include "device/MKL25Z4/MKL25Z4_ftfa.h"
#include "device/MKL25Z4/MKL25Z4_gpio.h"
#include "device/MKL25Z4/MKL25Z4_i2c.h"
#include "device/MKL25Z4/MKL25Z4_llwu.h"
#include "device/MKL25Z4/MKL25Z4_lptmr.h"
#include "device/MKL25Z4/MKL25Z4_mcg.h"
#include "device/MKL25Z4/MKL25Z4_mcm.h"
#include "device/MKL25Z4/MKL25Z4_mtb.h"
#include "device/MKL25Z4/MKL25Z4_mtbdwt.h"
#include "device/MKL25Z4/MKL25Z4_nv.h"
#include "device/MKL25Z4/MKL25Z4_osc.h"
#include "device/MKL25Z4/MKL25Z4_pit.h"
#include "device/MKL25Z4/MKL25Z4_pmc.h"
#include "device/MKL25Z4/MKL25Z4_port.h"
#include "device/MKL25Z4/MKL25Z4_rcm.h"
#include "device/MKL25Z4/MKL25Z4_rom.h"
#include "device/MKL25Z4/MKL25Z4_rtc.h"
#include "device/MKL25Z4/MKL25Z4_sim.h"
#include "device/MKL25Z4/MKL25Z4_smc.h"
#include "device/MKL25Z4/MKL25Z4_spi.h"
#include "device/MKL25Z4/MKL25Z4_tpm.h"
#include "device/MKL25Z4/MKL25Z4_tsi.h"
#include "device/MKL25Z4/MKL25Z4_uart.h"
#include "device/MKL25Z4/MKL25Z4_uart0.h"
#include "device/MKL25Z4/MKL25Z4_usb.h"
/* CMSIS-style register definitions*/
#include "device/MKL25Z4/MKL25Z4.h"
#else
#error "No valid CPU defined!"
#endif
#endif /* __FSL_DEVICE_REGISTERS_H__*/
/*******************************************************************************
* EOF
******************************************************************************/

57
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/gpio_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_api.h"
#include "pinmap.h"
#include "fsl_port_hal.h"
#include "fsl_gpio_hal.h"
#include "fsl_sim_hal.h"
uint32_t gpio_set(PinName pin) {
uint32_t pin_num = pin & 0xFF;
pin_function(pin, (int)kPortMuxAsGpio);
return 1 << pin_num;
}
void gpio_init(gpio_t *obj, PinName pin) {
if (pin == NC) {
return;
}
obj->pinName = pin;
uint32_t port = pin >> GPIO_PORT_SHIFT;
uint32_t pin_num = pin & 0xFF;
clock_hal_set_gate(kSimClockModulePORT, port, true);
port_hal_mux_control(port, pin_num, kPortMuxAsGpio);
}
void gpio_mode(gpio_t *obj, PinMode mode) {
pin_mode(obj->pinName, mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction) {
uint32_t port = obj->pinName >> GPIO_PORT_SHIFT;
uint32_t pin_num = obj->pinName & 0xFF;
switch (direction) {
case PIN_INPUT:
gpio_hal_set_pin_direction(port, pin_num, kGpioDigitalInput);
break;
case PIN_OUTPUT:
gpio_hal_set_pin_direction(port, pin_num, kGpioDigitalOutput);
break;
}
}

214
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/gpio_irq_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "cmsis.h"
#include "gpio_irq_api.h"
#include "gpio_api.h"
#include "fsl_gpio_hal.h"
#include "fsl_port_hal.h"
#include "error.h"
#define CHANNEL_NUM 160
static uint32_t channel_ids[CHANNEL_NUM] = {0};
static gpio_irq_handler irq_handler;
#define IRQ_DISABLED (0)
#define IRQ_RAISING_EDGE (9)
#define IRQ_FALLING_EDGE (10)
#define IRQ_EITHER_EDGE (11)
static void handle_interrupt_in(PortName port, int ch_base) {
uint32_t i;
for (i = 0; i < 32; i++) {
if (port_hal_read_pin_interrupt_flag(port, i)) {
uint32_t id = channel_ids[ch_base + i];
if (id == 0) {
continue;
}
gpio_irq_event event = IRQ_NONE;
switch (BR_PORT_PCRn_IRQC(port, i)) {
case IRQ_RAISING_EDGE:
event = IRQ_RISE;
break;
case IRQ_FALLING_EDGE:
event = IRQ_FALL;
break;
case IRQ_EITHER_EDGE:
event = (gpio_hal_read_pin_input(port, i)) ? (IRQ_RISE) : (IRQ_FALL);
break;
}
if (event != IRQ_NONE) {
irq_handler(id, event);
}
}
}
port_hal_clear_port_interrupt_flag(port);
}
void gpio_irqA(void) {handle_interrupt_in(PortA, 0);}
void gpio_irqB(void) {handle_interrupt_in(PortB, 32);}
void gpio_irqC(void) {handle_interrupt_in(PortC, 64);}
void gpio_irqD(void) {handle_interrupt_in(PortD, 96);}
void gpio_irqE(void) {handle_interrupt_in(PortE, 128);}
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
if (pin == NC) {
return -1;
}
irq_handler = handler;
obj->port = pin >> GPIO_PORT_SHIFT;
obj->pin = pin & 0x7F;
uint32_t ch_base, vector;
IRQn_Type irq_n;
switch (obj->port) {
case PortA:
ch_base = 0;
irq_n = PORTA_IRQn;
vector = (uint32_t)gpio_irqA;
break;
case PortB:
ch_base = 32;
irq_n = PORTB_IRQn;
vector = (uint32_t)gpio_irqB;
break;
case PortC:
ch_base = 64;
irq_n = PORTC_IRQn;
vector = (uint32_t)gpio_irqC;
break;
case PortD:
ch_base = 96;
irq_n = PORTD_IRQn;
vector = (uint32_t)gpio_irqD;
break;
case PortE:
ch_base = 128;
irq_n = PORTE_IRQn;
vector = (uint32_t)gpio_irqE;
break;
default:
error("gpio_irq only supported on port A-E.\n");
break;
}
NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n);
obj->ch = ch_base + obj->pin;
channel_ids[obj->ch] = id;
return 0;
}
void gpio_irq_free(gpio_irq_t *obj) {
channel_ids[obj->ch] = 0;
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
port_interrupt_config_t irq_settings = kPortIntDisabled;
switch (BR_PORT_PCRn_IRQC(obj->port, obj->pin)) {
case IRQ_DISABLED:
if (enable)
irq_settings = (event == IRQ_RISE) ? (kPortIntRisingEdge) : (kPortIntFallingEdge);
break;
case IRQ_RAISING_EDGE:
if (enable) {
irq_settings = (event == IRQ_RISE) ? (kPortIntRisingEdge) : (kPortIntEitherEdge);
} else {
if (event == IRQ_FALL)
irq_settings = kPortIntRisingEdge;
}
break;
case IRQ_FALLING_EDGE:
if (enable) {
irq_settings = (event == IRQ_FALL) ? (kPortIntFallingEdge) : (kPortIntEitherEdge);
} else {
if (event == IRQ_RISE)
irq_settings = kPortIntFallingEdge;
}
break;
case IRQ_EITHER_EDGE:
if (enable) {
irq_settings = kPortIntEitherEdge;
} else {
irq_settings = (event == IRQ_RISE) ? (kPortIntFallingEdge) : (kPortIntRisingEdge);
}
break;
}
port_hal_configure_pin_interrupt(obj->port, obj->pin, irq_settings);
port_hal_clear_pin_interrupt_flag(obj->port, obj->pin);
}
void gpio_irq_enable(gpio_irq_t *obj) {
switch (obj->port) {
case PortA:
NVIC_EnableIRQ(PORTA_IRQn);
break;
case PortB:
NVIC_EnableIRQ(PORTB_IRQn);
break;
case PortC:
NVIC_EnableIRQ(PORTC_IRQn);
break;
case PortD:
NVIC_EnableIRQ(PORTD_IRQn);
break;
case PortE:
NVIC_EnableIRQ(PORTE_IRQn);
break;
}
}
void gpio_irq_disable(gpio_irq_t *obj) {
switch (obj->port) {
case PortA:
NVIC_DisableIRQ(PORTA_IRQn);
break;
case PortB:
NVIC_DisableIRQ(PORTB_IRQn);
break;
case PortC:
NVIC_DisableIRQ(PORTC_IRQn);
break;
case PortD:
NVIC_DisableIRQ(PORTD_IRQn);
break;
case PortE:
NVIC_DisableIRQ(PORTE_IRQn);
break;
}
}
// Change the NMI pin to an input. This allows NMI pin to
// be used as a low power mode wakeup. The application will
// need to change the pin back to NMI_b or wakeup only occurs once!
void NMI_Handler(void) {
gpio_t gpio;
gpio_init_in(&gpio, PTA4);
}

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libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/gpio_object.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#include "fsl_gpio_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
PinName pinName;
} gpio_t;
static inline void gpio_write(gpio_t *obj, int value) {
uint32_t port = obj->pinName >> GPIO_PORT_SHIFT;
uint32_t pin = obj->pinName & 0xFF;
gpio_hal_write_pin_output(port, pin, value);
}
static inline int gpio_read(gpio_t *obj) {
uint32_t port = obj->pinName >> GPIO_PORT_SHIFT;
uint32_t pin = obj->pinName & 0xFF;
return (int)gpio_hal_read_pin_input(port, pin);
}
#ifdef __cplusplus
}
#endif
#endif

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libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/i2c_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "i2c_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
#include "fsl_clock_manager.h"
#include "fsl_i2c_hal.h"
static const PinMap PinMap_I2C_SDA[] = {
{PTE25, I2C_0, 5},
{PTB1 , I2C_0, 2},
{PTB3 , I2C_0, 2},
{PTC11, I2C_1, 2},
{PTA13, I2C_2, 5},
{PTD3 , I2C_0, 7},
{PTE0 , I2C_1, 6},
{NC , NC , 0}
};
static const PinMap PinMap_I2C_SCL[] = {
{PTE24, I2C_0, 5},
{PTB0 , I2C_0, 2},
{PTB2 , I2C_0, 2},
{PTC10, I2C_1, 2},
{PTA12, I2C_2, 5},
{PTA14, I2C_2, 5},
{PTD2 , I2C_0, 7},
{PTE1 , I2C_1, 6},
{NC , NC , 0}
};
static uint8_t first_read;
void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL);
obj->instance = pinmap_merge(i2c_sda, i2c_scl);
if ((int)obj->instance == NC) {
error("I2C pin mapping failed");
}
clock_manager_set_gate(kClockModuleI2C, obj->instance, true);
i2c_hal_enable(obj->instance);
i2c_frequency(obj, 100000);
pinmap_pinout(sda, PinMap_I2C_SDA);
pinmap_pinout(scl, PinMap_I2C_SCL);
first_read = 1;
}
int i2c_start(i2c_t *obj) {
i2c_hal_send_start(obj->instance);
first_read = 1;
return 0;
}
int i2c_stop(i2c_t *obj) {
volatile uint32_t n = 0;
i2c_hal_send_stop(obj->instance);
// It seems that there are timing problems
// when there is no waiting time after a STOP.
// This wait is also included on the samples
// code provided with the freedom board
for (n = 0; n < 100; n++) __NOP();
first_read = 1;
return 0;
}
static int timeout_status_poll(i2c_t *obj, uint32_t mask) {
uint32_t i, timeout = 1000;
for (i = 0; i < timeout; i++) {
if (HW_I2C_S_RD(obj->instance) & mask)
return 0;
}
return 1;
}
// this function waits the end of a tx transfer and return the status of the transaction:
// 0: OK ack received
// 1: OK ack not received
// 2: failure
static int i2c_wait_end_tx_transfer(i2c_t *obj) {
// wait for the interrupt flag
if (timeout_status_poll(obj, I2C_S_IICIF_MASK)) {
return 2;
}
i2c_hal_clear_interrupt(obj->instance);
// wait transfer complete
if (timeout_status_poll(obj, I2C_S_TCF_MASK)) {
return 2;
}
// check if we received the ACK or not
return i2c_hal_get_receive_ack(obj->instance) ? 0 : 1;
}
// this function waits the end of a rx transfer and return the status of the transaction:
// 0: OK
// 1: failure
static int i2c_wait_end_rx_transfer(i2c_t *obj) {
// wait for the end of the rx transfer
if (timeout_status_poll(obj, I2C_S_IICIF_MASK)) {
return 1;
}
i2c_hal_clear_interrupt(obj->instance);
return 0;
}
static int i2c_do_write(i2c_t *obj, int value) {
i2c_hal_write(obj->instance, value);
// init and wait the end of the transfer
return i2c_wait_end_tx_transfer(obj);
}
static int i2c_do_read(i2c_t *obj, char * data, int last) {
if (last) {
i2c_hal_send_nak(obj->instance);
} else {
i2c_hal_send_ack(obj->instance);
}
*data = (i2c_hal_read(obj->instance) & 0xFF);
// start rx transfer and wait the end of the transfer
return i2c_wait_end_rx_transfer(obj);
}
void i2c_frequency(i2c_t *obj, int hz) {
uint32_t busClock;
clock_manager_error_code_t error = clock_manager_get_frequency(kBusClock, &busClock);
if (error == kClockManagerSuccess) {
i2c_hal_set_baud(obj->instance, busClock, hz / 1000, NULL);
}
}
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
int count;
char dummy_read, *ptr;
if (i2c_start(obj)) {
i2c_stop(obj);
return I2C_ERROR_BUS_BUSY;
}
if (i2c_do_write(obj, (address | 0x01))) {
i2c_stop(obj);
return I2C_ERROR_NO_SLAVE;
}
// set rx mode
i2c_hal_set_direction(obj->instance, kI2CReceive);
// Read in bytes
for (count = 0; count < (length); count++) {
ptr = (count == 0) ? &dummy_read : &data[count - 1];
uint8_t stop_ = (count == (length - 1)) ? 1 : 0;
if (i2c_do_read(obj, ptr, stop_)) {
i2c_stop(obj);
return count;
}
}
// If not repeated start, send stop.
if (stop)
i2c_stop(obj);
// last read
data[count-1] = i2c_hal_read(obj->instance);
return length;
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
int i;
if (i2c_start(obj)) {
i2c_stop(obj);
return I2C_ERROR_BUS_BUSY;
}
if (i2c_do_write(obj, (address & 0xFE))) {
i2c_stop(obj);
return I2C_ERROR_NO_SLAVE;
}
for (i = 0; i < length; i++) {
if(i2c_do_write(obj, data[i])) {
i2c_stop(obj);
return i;
}
}
if (stop)
i2c_stop(obj);
return length;
}
void i2c_reset(i2c_t *obj) {
i2c_stop(obj);
}
int i2c_byte_read(i2c_t *obj, int last) {
char data;
// set rx mode
i2c_hal_set_direction(obj->instance, kI2CReceive);
if(first_read) {
// first dummy read
i2c_do_read(obj, &data, 0);
first_read = 0;
}
if (last) {
// set tx mode
i2c_hal_set_direction(obj->instance, kI2CTransmit);
return i2c_hal_read(obj->instance);
}
i2c_do_read(obj, &data, last);
return data;
}
int i2c_byte_write(i2c_t *obj, int data) {
first_read = 1;
// set tx mode
i2c_hal_set_direction(obj->instance, kI2CTransmit);
return !i2c_do_write(obj, (data & 0xFF));
}
#if DEVICE_I2CSLAVE
void i2c_slave_mode(i2c_t *obj, int enable_slave) {
if (enable_slave) {
// set slave mode
BW_I2C_C1_MST(obj->instance, 0);
i2c_hal_enable_interrupt(obj->instance);
} else {
// set master mode
BW_I2C_C1_MST(obj->instance, 1);
}
}
int i2c_slave_receive(i2c_t *obj) {
switch(HW_I2C_S_RD(obj->instance)) {
// read addressed
case 0xE6:
return 1;
// write addressed
case 0xE2:
return 3;
default:
return 0;
}
}
int i2c_slave_read(i2c_t *obj, char *data, int length) {
uint8_t dummy_read;
uint8_t *ptr;
int count;
// set rx mode
i2c_hal_set_direction(obj->instance, kI2CTransmit);
// first dummy read
dummy_read = i2c_hal_read(obj->instance);
if (i2c_wait_end_rx_transfer(obj))
return 0;
// read address
dummy_read = i2c_hal_read(obj->instance);
if (i2c_wait_end_rx_transfer(obj))
return 0;
// read (length - 1) bytes
for (count = 0; count < (length - 1); count++) {
data[count] = i2c_hal_read(obj->instance);
if (i2c_wait_end_rx_transfer(obj))
return count;
}
// read last byte
ptr = (length == 0) ? &dummy_read : (uint8_t *)&data[count];
*ptr = i2c_hal_read(obj->instance);
return (length) ? (count + 1) : 0;
}
int i2c_slave_write(i2c_t *obj, const char *data, int length) {
int i, count = 0;
// set tx mode
i2c_hal_set_direction(obj->instance, kI2CTransmit);
for (i = 0; i < length; i++) {
if (i2c_do_write(obj, data[count++]) == 2)
return i;
}
// set rx mode
i2c_hal_set_direction(obj->instance, kI2CReceive);
// dummy rx transfer needed
// otherwise the master cannot generate a stop bit
i2c_hal_read(obj->instance);
if (i2c_wait_end_rx_transfer(obj) == 2)
return count;
return count;
}
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
i2c_hal_set_upper_slave_address_7bit(obj->instance, address & 0xfe);
}
#endif

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libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/objects.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
struct gpio_irq_s {
uint32_t port;
uint32_t pin;
uint32_t ch;
};
struct port_s {
PortName port;
uint32_t mask;
};
struct pwmout_s {
PWMName pwm_name;
};
struct serial_s {
int index;
};
struct analogin_s {
ADCName adc;
};
struct i2c_s {
uint32_t instance;
};
struct spi_s {
uint32_t instance;
};
struct dac_s {
DACName dac;
};
#include "gpio_object.h"
#ifdef __cplusplus
}
#endif
#endif

54
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/pinmap.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "pinmap.h"
#include "error.h"
#include "fsl_clock_manager.h"
#include "fsl_port_hal.h"
void pin_function(PinName pin, int function) {
if (pin == (PinName)NC) {
return;
}
clock_manager_set_gate(kClockModulePORT, pin >> GPIO_PORT_SHIFT, true);
port_hal_mux_control(pin >> GPIO_PORT_SHIFT, pin & 0xFF, (port_mux_t)function);
}
void pin_mode(PinName pin, PinMode mode) {
if (pin == (PinName)NC) {
return;
}
uint32_t instance = pin >> GPIO_PORT_SHIFT;
uint32_t pinName = pin & 0xFF;
switch (mode) {
case PullNone:
port_hal_configure_pull(instance, pinName, false);
port_hal_pull_select(instance, pinName, kPortPullDown);
break;
case PullDown:
port_hal_configure_pull(instance, pinName, true);
port_hal_pull_select(instance, pinName, kPortPullDown);
break;
case PullUp:
port_hal_configure_pull(instance, pinName, true);
port_hal_pull_select(instance, pinName, kPortPullUp);
break;
default:
break;
}
}

65
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/port_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "port_api.h"
#include "pinmap.h"
#include "gpio_api.h"
PinName port_pin(PortName port, int pin_n) {
return (PinName)((port << GPIO_PORT_SHIFT) | pin_n);
}
void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
obj->port = port;
obj->mask = mask;
// The function is set per pin: reuse gpio logic
for (uint32_t i = 0; i < 32; i++) {
if (obj->mask & (1 << i)) {
gpio_set(port_pin(obj->port, i));
}
}
port_dir(obj, dir);
}
void port_mode(port_t *obj, PinMode mode) {
// The mode is set per pin: reuse pinmap logic
for (uint32_t i = 0; i < 32; i++) {
if (obj->mask & (1 << i)) {
pin_mode(port_pin(obj->port, i), mode);
}
}
}
void port_dir(port_t *obj, PinDirection dir) {
switch (dir) {
case PIN_INPUT :
gpio_hal_set_port_direction((uint32_t)obj->port, kGpioDigitalInput);
break;
case PIN_OUTPUT:
gpio_hal_set_port_direction((uint32_t)obj->port, kGpioDigitalOutput);
break;
}
}
void port_write(port_t *obj, int value) {
gpio_hal_write_port_output((uint32_t)obj->port, (uint32_t)(value & obj->mask));
}
int port_read(port_t *obj) {
return (int)(gpio_hal_read_port_input((uint32_t)obj->port) & obj->mask);
}

110
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/pwmout_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "pwmout_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
#include "fsl_ftm_hal.h"
#include "fsl_mcg_hal.h"
#include "fsl_clock_manager.h"
static const PinMap PinMap_PWM[] = {
{PTB18, PWM_17, 3},
{NC , NC , 0}
};
static float pwm_clock;
void pwmout_init(pwmout_t* obj, PinName pin) {
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
if (pwm == (PWMName)NC) {
error("PwmOut pin mapping failed");
}
obj->pwm_name = pwm;
float clkval = clock_hal_get_fllclk() / 1000000.0f;
uint32_t clkdiv = 0;
while (clkval > 1) {
clkdiv++;
clkval /= 2.0f;
if (clkdiv == 7) {
break;
}
}
uint32_t channel = pwm & 0xF;
uint32_t instance = pwm >> TPM_SHIFT;
clock_manager_set_gate(kClockModuleFTM, instance, true);
ftm_hal_set_clock_ps(instance, (ftm_clock_ps_t)clkdiv);
ftm_hal_set_clock_source(instance, kClock_source_FTM_SystemClk);
ftm_hal_set_channel_edge_level(instance, channel, 2);
// default to 20ms: standard for servos, and fine for e.g. brightness control
pwmout_period_ms(obj, 20);
pwmout_write (obj, 0);
// Wire pinout
pinmap_pinout(pin, PinMap_PWM);
}
void pwmout_free(pwmout_t* obj) {
}
void pwmout_write(pwmout_t* obj, float value) {
if (value < 0.0f) {
value = 0.0f;
} else if (value > 1.0f) {
value = 1.0f;
}
uint16_t mod = ftm_hal_get_mod(obj->pwm_name >> TPM_SHIFT);
uint32_t new_count = (uint32_t)((float)(mod) * value);
ftm_hal_set_channel_count_value(obj->pwm_name >> TPM_SHIFT, obj->pwm_name & 0xF, new_count);
}
float pwmout_read(pwmout_t* obj) {
uint16_t count = ftm_hal_get_channel_count_value(obj->pwm_name >> TPM_SHIFT, obj->pwm_name & 0xF, 0);
uint16_t mod = ftm_hal_get_mod(obj->pwm_name >> TPM_SHIFT);
float v = (float)(count) / (float)(mod);
return (v > 1.0f) ? (1.0f) : (v);
}
void pwmout_period(pwmout_t* obj, float seconds) {
pwmout_period_us(obj, seconds * 1000000.0f);
}
void pwmout_period_ms(pwmout_t* obj, int ms) {
pwmout_period_us(obj, ms * 1000);
}
// Set the PWM period, keeping the duty cycle the same.
void pwmout_period_us(pwmout_t* obj, int us) {
float dc = pwmout_read(obj);
ftm_hal_set_mod(obj->pwm_name >> TPM_SHIFT, (uint32_t)(pwm_clock * (float)us));
pwmout_write(obj, dc);
}
void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
pwmout_pulsewidth_us(obj, ms * 1000);
}
void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
uint32_t value = (uint32_t)(pwm_clock * (float)us);
ftm_hal_set_channel_count_value(obj->pwm_name >> TPM_SHIFT, obj->pwm_name & 0xF, value);
}

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libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/rtc_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "rtc_api.h"
#include "pinmap.h"
#include "fsl_rtc_hal.h"
#include "fsl_clock_manager.h"
const PinMap PinMap_RTC[] = {
{NC, OSC32KCLK, 0},
};
void rtc_init(void) {
rtc_hal_init_config_t hal_config = {0};
hal_config.disableClockOutToPeripheral = true;
if (PinMap_RTC[0].pin == NC) {
hal_config.enable32kOscillator = true;
}
clock_manager_set_gate(kClockModuleRTC, 0U, true);
hal_config.startSecondsCounterAt = 1; /* TSR = 1 */
rtc_hal_init(&hal_config);
// select RTC clock source
SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(PinMap_RTC[0].peripheral);
rtc_hal_config_oscillator(true);
rtc_hal_counter_enable(true);
}
void rtc_free(void) {
// [TODO]
}
/*
* Little check routine to see if the RTC has been enabled
* 0 = Disabled, 1 = Enabled
*/
int rtc_isenabled(void) {
clock_manager_set_gate(kClockModuleRTC, 0U, true);
return (int)rtc_hal_is_counter_enabled();
}
time_t rtc_read(void) {
return BR_RTC_TSR_TSR;
}
void rtc_write(time_t t) {
if (t == 0) {
t = 1;
}
rtc_hal_counter_enable(false);
BW_RTC_TSR_TSR(t);
rtc_hal_counter_enable(true);
}

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libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/serial_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "serial_api.h"
// math.h required for floating point operations for baud rate calculation
#include <math.h>
#include <string.h>
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
#include "fsl_uart_hal.h"
#include "fsl_clock_manager.h"
#include "fsl_uart_features.h"
/* TODO:
putchar/getchar 9 and 10 bits support
*/
static const PinMap PinMap_UART_TX[] = {
{PTB17, UART_0, 3},
{PTC17, UART_3, 3},
{PTD7 , UART_0, 3},
{PTD3 , UART_2, 3},
{PTC4 , UART_1, 3},
{PTC15, UART_4, 3},
{PTB11, UART_3, 3},
{PTA14, UART_0, 3},
{PTE24, UART_4, 3},
{PTE4 , UART_3, 3},
{PTE0, UART_1, 3},
{NC , NC , 0}
};
static const PinMap PinMap_UART_RX[] = {
{PTB16, UART_0, 3},
{PTE1 , UART_1, 3},
{PTE5 , UART_3, 3},
{PTE25, UART_4, 3},
{PTA15, UART_0, 3},
{PTC16, UART_3, 3},
{PTB10, UART_3, 3},
{PTC3 , UART_1, 3},
{PTC14, UART_4, 3},
{PTD2 , UART_2, 3},
{PTC6 , UART_0, 3},
{NC , NC , 0}
};
#define UART_NUM 4
static uint32_t serial_irq_ids[UART_NUM] = {0};
static uart_irq_handler irq_handler;
int stdio_uart_inited = 0;
serial_t stdio_uart;
static uint32_t serial_get_clock(uint32_t uart_instance)
{
uint32_t uartSourceClock;
if ((uart_instance == 0) || (uart_instance == 1)) {
clock_manager_get_frequency(kSystemClock, &uartSourceClock);
} else {
clock_manager_get_frequency(kBusClock, &uartSourceClock);
}
return uartSourceClock;
}
void serial_init(serial_t *obj, PinName tx, PinName rx) {
uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
obj->index = (UARTName)pinmap_merge(uart_tx, uart_rx);
if ((int)obj->index == NC) {
error("Serial pinout mapping failed");
}
uart_config_t uart_config;
uart_config.baudRate = 9600;
uart_config.bitCountPerChar = kUart8BitsPerChar;
uart_config.parityMode = kUartParityDisabled;
uart_config.rxDataInvert = 0;
uart_config.stopBitCount = kUartOneStopBit;
uart_config.txDataInvert = 0;
uart_config.uartSourceClockInHz = serial_get_clock(obj->index);
clock_manager_set_gate(kClockModuleUART, obj->index, true);
uart_hal_init(obj->index, &uart_config);
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
pin_mode(tx, PullUp);
pin_mode(rx, PullUp);
if (obj->index == STDIO_UART) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
void serial_free(serial_t *obj) {
serial_irq_ids[obj->index] = 0;
}
void serial_baud(serial_t *obj, int baudrate) {
uart_hal_set_baud_rate(obj->index, serial_get_clock(obj->index), (uint32_t)baudrate);
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
uart_hal_configure_bit_count_per_char(obj->index, (uart_bit_count_per_char_t)data_bits);
uart_hal_configure_parity_mode(obj->index, (uart_parity_mode_t)parity);
uart_hal_configure_stop_bit_count(obj->index, (uart_stop_bit_count_t)stop_bits);
}
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) {
if (serial_irq_ids[index] != 0) {
if (transmit_empty)
irq_handler(serial_irq_ids[index], TxIrq);
if (receive_full)
irq_handler(serial_irq_ids[index], RxIrq);
}
}
void uart0_irq() {
uart_irq(uart_hal_is_transmit_data_register_empty(0), uart_hal_is_receive_data_register_full(0), 0);
if (uart_hal_is_receive_overrun_detected(0))
uart_hal_clear_status_flag(0, kUartReceiveOverrun);
}
void uart1_irq() {
uart_irq(uart_hal_is_transmit_data_register_empty(1), uart_hal_is_receive_data_register_full(1), 1);
}
void uart2_irq() {
uart_irq(uart_hal_is_transmit_data_register_empty(2), uart_hal_is_receive_data_register_full(2), 2);
}
void uart3_irq() {
uart_irq(uart_hal_is_transmit_data_register_empty(3), uart_hal_is_receive_data_register_full(3), 3);
}
void uart4_irq() {
uart_irq(uart_hal_is_transmit_data_register_empty(4), uart_hal_is_receive_data_register_full(4), 4);
}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0;
switch (obj->index) {
case 0: irq_n=UART0_RX_TX_IRQn; vector = (uint32_t)&uart0_irq; break;
case 1: irq_n=UART1_RX_TX_IRQn; vector = (uint32_t)&uart1_irq; break;
case 2: irq_n=UART2_RX_TX_IRQn; vector = (uint32_t)&uart2_irq; break;
case 3: irq_n=UART3_RX_TX_IRQn; vector = (uint32_t)&uart3_irq; break;
case 4: irq_n=UART4_RX_TX_IRQn; vector = (uint32_t)&uart4_irq; break;
}
if (enable) {
switch (irq) {
case RxIrq: uart_hal_enable_rx_data_register_full_interrupt(obj->index); break;
case TxIrq: uart_hal_enable_tx_data_register_empty_interrupt(obj->index); break;
}
NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n);
} else { // disable
int all_disabled = 0;
SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
switch (irq) {
case RxIrq: uart_hal_disable_rx_data_register_full_interrupt(obj->index); break;
case TxIrq: uart_hal_enable_tx_data_register_empty_interrupt(obj->index); break;
}
switch (other_irq) {
case RxIrq: all_disabled = uart_hal_is_receive_data_full_interrupt_enabled(obj->index) == 0; break;
case TxIrq: all_disabled = uart_hal_is_tx_data_register_empty_interrupt_enabled(obj->index) == 0; break;
}
if (all_disabled)
NVIC_DisableIRQ(irq_n);
}
}
int serial_getc(serial_t *obj) {
while (!serial_readable(obj));
uint8_t data;
uart_hal_getchar(obj->index, &data);
return data;
}
void serial_putc(serial_t *obj, int c) {
while (!serial_writable(obj));
uart_hal_putchar(obj->index, (uint8_t)c);
}
int serial_readable(serial_t *obj) {
if (uart_hal_is_receive_overrun_detected(obj->index))
uart_hal_clear_status_flag(obj->index, kUartReceiveOverrun);
return uart_hal_is_receive_data_register_full(obj->index);
}
int serial_writable(serial_t *obj) {
if (uart_hal_is_receive_overrun_detected(obj->index))
uart_hal_clear_status_flag(obj->index, kUartReceiveOverrun);
return uart_hal_is_transmit_data_register_empty(obj->index);
}
void serial_clear(serial_t *obj) {
}
void serial_pinout_tx(PinName tx) {
pinmap_pinout(tx, PinMap_UART_TX);
}
void serial_break_set(serial_t *obj) {
uart_hal_queue_break_char_to_send(obj->index, true);
}
void serial_break_clear(serial_t *obj) {
uart_hal_queue_break_char_to_send(obj->index, false);
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "sleep_api.h"
#include "cmsis.h"
#include "fsl_mcg_hal.h"
#include "fsl_smc_hal.h"
void sleep(void) {
smc_power_mode_protection_config_t sleep_config = {true};
smc_hal_config_power_mode_protection(&sleep_config);
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
__WFI();
}
void deepsleep(void) {
mcg_clock_select_t mcg_clock = clock_get_clks();
smc_power_mode_protection_config_t sleep_config = {true};
smc_hal_config_power_mode_protection(&sleep_config);
SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
//Deep sleep for ARM core:
SCB->SCR = 1 << SCB_SCR_SLEEPDEEP_Pos;
__WFI();
//Switch back to PLL as clock source if needed
//The interrupt that woke up the device will run at reduced speed
if (mcg_clock == kMcgClockSelectOut) {
if (clock_get_plls() == kMcgPllSelectPllcs) {
while (clock_get_lock0() == kMcgLockUnlocked);
}
clock_set_clks(kMcgClockSelectOut);
}
}

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/* mbed Microcontroller Library
* Copyright (c) 2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "spi_api.h"
#include <math.h>
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
#include "fsl_clock_manager.h"
#include "fsl_dspi_hal.h"
static const PinMap PinMap_SPI_SCLK[] = {
{PTD1 , SPI_0, 2},
{PTE2 , SPI_1, 2},
{PTA15, SPI_0, 2},
{PTB11, SPI_1, 2},
{PTB21, SPI_2, 2},
{PTC5 , SPI_0, 2},
{PTD5 , SPI_1, 7},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MOSI[] = {
{PTD2 , SPI_0, 2},
{PTE1 , SPI_1, 2},
{PTE3 , SPI_1, 7},
{PTA16, SPI_0, 2},
{PTB16, SPI_1, 2},
{PTB22, SPI_2, 2},
{PTC6 , SPI_0, 2},
{PTD2 , SPI_0, 2},
{PTD6 , SPI_0, 7},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MISO[] = {
{PTD3 , SPI_0, 2},
{PTE1 , SPI_1, 7},
{PTE3 , SPI_1, 2},
{PTA17, SPI_0, 2},
{PTB17, SPI_1, 2},
{PTB23, SPI_2, 2},
{PTC7 , SPI_0, 2},
{PTD3 , SPI_0, 2},
{PTD7 , SPI_1, 7},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_SSEL[] = {
{PTD0 , SPI_0, 2},
{PTE4 , SPI_1, 2},
{PTA14, SPI_0, 2},
{PTB10, SPI_1, 2},
{PTB20, SPI_2, 2},
{PTC4 , SPI_0, 2},
{PTD4 , SPI_1, 7},
{NC , NC , 0}
};
static void spi_set_delays(uint32_t instance) {
dspi_delay_settings_config_t delay_config;
delay_config.pcsToSck = 1; /*!< PCS to SCK delay (CSSCK): initialize the scalar
* value to '1' to provide the master with a little
* more data-in read setup time.
*/
delay_config.pcsToSckPre = 0; /*!< PCS to SCK delay prescalar (PCSSCK) */
delay_config.afterSckPre = 0; /*!< After SCK delay prescalar (PASC)*/
delay_config.afterSck = 0; /*!< After SCK delay scalar (ASC)*/
delay_config.afterTransferPre = 0; /*!< Delay after transfer prescalar (PDT)*/
delay_config.afterTransfer = 0;
dspi_hal_configure_delays(instance, kDspiCtar0, &delay_config);
}
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
// determine the SPI to use
uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
obj->instance = pinmap_merge(spi_data, spi_cntl);
if ((int)obj->instance == NC) {
error("SPI pinout mapping failed");
}
// enable power and clocking
clock_manager_set_gate(kClockModuleSPI, obj->instance, true);
dspi_hal_disable(obj->instance);
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_set_delays(obj->instance);
spi_frequency(obj, 1000000);
dspi_hal_enable(obj->instance);
dspi_hal_start_transfer(obj->instance);
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if (ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
}
void spi_free(spi_t *obj) {
// [TODO]
}
void spi_format(spi_t *obj, int bits, int mode, int slave) {
dspi_data_format_config_t config = {0};
config.bitsPerFrame = (uint32_t)bits;
config.clkPolarity = (mode & 0x2) ? kDspiClockPolarity_ActiveLow : kDspiClockPolarity_ActiveHigh;
config.clkPhase = (mode & 0x1) ? kDspiClockPhase_SecondEdge : kDspiClockPhase_FirstEdge;
config.direction = kDspiMsbFirst;
dspi_status_t result = dspi_hal_configure_data_format(obj->instance, kDspiCtar0, &config);
if (result != kStatus_DSPI_Success) {
error("Failed to configure SPI data format");
}
if (slave) {
dspi_hal_set_master_slave(obj->instance, kDspiSlave);
} else {
dspi_hal_set_master_slave(obj->instance, kDspiMaster);
}
}
void spi_frequency(spi_t *obj, int hz) {
uint32_t busClock;
clock_manager_get_frequency(kBusClock, &busClock);
dspi_hal_set_baud(obj->instance, kDspiCtar0, (uint32_t)hz, busClock);
}
static inline int spi_writeable(spi_t * obj) {
return dspi_hal_get_status_flag(obj->instance, kDspiTxFifoFillRequest);
}
static inline int spi_readable(spi_t * obj) {
return dspi_hal_get_status_flag(obj->instance, kDspiRxFifoDrainRequest);
}
int spi_master_write(spi_t *obj, int value) {
// wait tx buffer empty
while(!spi_writeable(obj));
dspi_command_config_t command = {0};
command.isEndOfQueue = true;
command.isChipSelectContinuous = 0;
dspi_hal_write_data_master_mode(obj->instance, &command, (uint16_t)value);
dspi_hal_clear_status_flag(obj->instance, kDspiTxFifoFillRequest);
// wait rx buffer full
while (!spi_readable(obj));
dspi_hal_clear_status_flag(obj->instance, kDspiRxFifoDrainRequest);
return dspi_hal_read_data(obj->instance) & 0xff;
}
int spi_slave_receive(spi_t *obj) {
return spi_readable(obj);
}
int spi_slave_read(spi_t *obj) {
return dspi_hal_read_data(obj->instance);
}
void spi_slave_write(spi_t *obj, int value) {
while (!spi_writeable(obj));
dspi_hal_write_data_slave_mode(obj->instance, (uint32_t)value);
}

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libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/us_ticker.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "us_ticker_api.h"
#include "PeripheralNames.h"
#include "fsl_pit_hal.h"
#include "fsl_sim_hal.h"
#include "fsl_clock_manager.h"
#include "fsl_clock_configs.h"
static void pit_init(void);
static void lptmr_init(void);
static int us_ticker_inited = 0;
void us_ticker_init(void) {
if (us_ticker_inited) {
return;
}
us_ticker_inited = 1;
pit_init();
lptmr_init();
}
uint32_t us_ticker_read() {
if (!us_ticker_inited) {
us_ticker_init();
}
return ~(pit_hal_read_timer_count(1));
}
/******************************************************************************
* Timer for us timing.
******************************************************************************/
static void pit_init(void) {
uint32_t busClock;
clock_hal_set_gate(kSimClockModulePIT, 0, true);
pit_hal_enable();
clock_manager_get_frequency(kBusClock, &busClock);
pit_hal_set_timer_period_count(0, busClock / 1000000 - 1);
pit_hal_set_timer_period_count(1, 0xFFFFFFFF);
pit_hal_configure_timer_chain(1, true);
pit_hal_timer_start(0);
pit_hal_timer_start(1);
}
/******************************************************************************
* Timer Event
*
* It schedules interrupts at given (32bit)us interval of time.
* It is implemented used the 16bit Low Power Timer that remains powered in all
* power modes.
******************************************************************************/
static void lptmr_isr(void);
static void lptmr_init(void) {
clock_hal_set_gate(kSimClockModuleLPTIMER, 0, true);
/* Set interrupt handler */
NVIC_SetVector(LPTimer_IRQn, (uint32_t)lptmr_isr);
NVIC_EnableIRQ(LPTimer_IRQn);
/* TODO: check clock manager, due to nonstandard 50 MHz */
//No suitable external oscillator clock -> Use fast internal oscillator (4MHz / divider)
MCG->C1 |= MCG_C1_IRCLKEN_MASK;
MCG->C2 |= MCG_C2_IRCS_MASK;
LPTMR0->PSR = LPTMR_PSR_PCS(0);
switch (MCG->SC & MCG_SC_FCRDIV_MASK) {
case MCG_SC_FCRDIV(0): //4MHz
LPTMR0->PSR |= LPTMR_PSR_PRESCALE(1);
break;
case MCG_SC_FCRDIV(1): //2MHz
LPTMR0->PSR |= LPTMR_PSR_PRESCALE(0);
break;
default: //1MHz or anything else, in which case we put it on 1MHz
MCG->SC &= ~MCG_SC_FCRDIV_MASK;
MCG->SC |= MCG_SC_FCRDIV(2);
LPTMR0->PSR |= LPTMR_PSR_PBYP_MASK;
}
}
void us_ticker_disable_interrupt(void) {
BW_LPTMR_CSR_TIE(0);
}
void us_ticker_clear_interrupt(void) {
// we already clear interrupt in lptmr_isr
}
static uint32_t us_ticker_int_counter = 0;
static uint16_t us_ticker_int_remainder = 0;
static void lptmr_set(unsigned short count) {
HW_LPTMR_CSR_WR(0);
BW_LPTMR_CMR_COMPARE(count);
BW_LPTMR_CSR_TIE(1);
BW_LPTMR_CSR_TEN(1);
}
static void lptmr_isr(void) {
// write 1 to TCF to clear the LPT timer compare flag
BW_LPTMR_CSR_TCF(1);
if (us_ticker_int_counter > 0) {
lptmr_set(0xFFFF);
us_ticker_int_counter--;
} else {
if (us_ticker_int_remainder > 0) {
lptmr_set(us_ticker_int_remainder);
us_ticker_int_remainder = 0;
} else {
// This function is going to disable the interrupts if there are
// no other events in the queue
us_ticker_irq_handler();
}
}
}
void us_ticker_set_interrupt(unsigned int timestamp) {
int delta = (int)(timestamp - us_ticker_read());
if (delta <= 0) {
// This event was in the past:
us_ticker_irq_handler();
return;
}
us_ticker_int_counter = (uint32_t)(delta >> 16);
us_ticker_int_remainder = (uint16_t)(0xFFFF & delta);
if (us_ticker_int_counter > 0) {
lptmr_set(0xFFFF);
us_ticker_int_counter--;
} else {
lptmr_set(us_ticker_int_remainder);
us_ticker_int_remainder = 0;
}
}

228
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/clock/fsl_clock_configs.h Normal file
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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__FSL_CLOCK_CONFIGS_H__)
#define __FSL_CLOCK_CONFIGS_H__
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @addtogroup clock_manager*/
/*! @{*/
#if defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FN1M0VMJ15)
#define CLOCK_SETUP 1
/*! @brief Predefined clock setups for K70*/
/*
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
Reference clock source for MCG module is the slow internal clock source 32.768kHz
Core clock = 41.94MHz, BusClock = 41.94MHz
1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
Reference clock source for MCG module is an external reference clock source 50MHz
Core clock = 120MHz, BusClock = 60MHz
2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
Core clock/Bus clock derived directly from an external reference clock source 50MHz with no multiplication
Core clock = 50MHz, BusClock = 50MHz
*/
/*! @brief Define clock source values for K70*/
#if (CLOCK_SETUP == 0)
#define CPU_XTAL0_CLK_HZ 50000000u /* external crystal or osc clock frequency in Hz connected to System Oscillator 0*/
#define CPU_XTAL1_CLK_HZ 8000000u /* external crystal or osc clock frequency in Hz connected to System Oscillator 1*/
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz*/
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz*/
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz*/
#define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value*/
#elif (CLOCK_SETUP == 1)
#define CPU_XTAL0_CLK_HZ 50000000u /* external crystal or osc clock frequency in Hz connected to System Oscillator 0*/
#define CPU_XTAL1_CLK_HZ 8000000u /* external crystal or osc clock frequency in Hz connected to System Oscillator 1*/
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz*/
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz*/
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz*/
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value*/
#elif (CLOCK_SETUP == 2)
#define CPU_XTAL0_CLK_HZ 50000000u /* external crystal or osc clock frequency in Hz connected to System Oscillator 0*/
#define CPU_XTAL1_CLK_HZ 8000000u /* external crystal or osc clock frequency in Hz connected to System Oscillator 1*/
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz*/
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz*/
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz*/
#define DEFAULT_SYSTEM_CLOCK 50000000u /* Default System clock value*/
#endif /* (CLOCK_SETUP == 2)*/
#elif defined(CPU_MKL25Z128VLK4)
#define CLOCK_SETUP 1
/*! @brief Predefined clock setups for KL25*/
/*
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
Reference clock source for MCG module is the slow internal clock source 32.768kHz
Core clock = 41.94MHz, BusClock = 13.98MHz
1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
Reference clock source for MCG module is an external crystal 8MHz
Core clock = 48MHz, BusClock = 24MHz
2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
Core clock = 8MHz, BusClock = 8MHz
*/
/*! @brief Define clock source values for KL25*/
#if (CLOCK_SETUP == 0)
#define CPU_XTAL_CLK_HZ 8000000u /* external crystal or oscillator clock frequency in Hz*/
#define CPU_INT_SLOW_CLK_HZ 32768u /* slow internal oscillator clock frequency in Hz*/
#define CPU_INT_FAST_CLK_HZ 4000000u /* fast internal oscillator clock frequency in Hz*/
#define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value*/
#elif (CLOCK_SETUP == 1)
#define CPU_XTAL_CLK_HZ 8000000u /* external crystal or oscillator clock frequency in Hz*/
#define CPU_INT_SLOW_CLK_HZ 32768u /* slow internal oscillator clock frequency in Hz*/
#define CPU_INT_FAST_CLK_HZ 4000000u /* fast internal oscillator clock frequency in Hz*/
#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value*/
#elif (CLOCK_SETUP == 2)
#define CPU_XTAL_CLK_HZ 8000000u /* external crystal or oscillator clock frequency in Hz*/
#define CPU_INT_SLOW_CLK_HZ 32768u /* slow internal oscillator clock frequency in Hz*/
#define CPU_INT_FAST_CLK_HZ 4000000u /* fast internal oscillator clock frequency in Hz*/
#define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value*/
#endif /*(CLOCK_SETUP == 2)*/
#elif defined(CPU_MK64FN1M0VMD12)
#define DISABLE_WDOG 1
#define CLOCK_SETUP 1
/* Predefined clock setups
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
Reference clock source for MCG module is the slow internal clock source 32.768kHz
Core clock = 20.97MHz, BusClock = 20.97MHz
1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
Reference clock source for MCG module is an external clock source 50MHz
USB clock divider is set for USB to receive 48MHz input clock.
Core clock = 120MHz, BusClock = 60MHz
3 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power Internal (BLPI) mode
Core clock/Bus clock derived directly from an fast internal clock 4MHz with no multiplication
The clock settings is ready for Very Low Power Run mode.
Core clock = 4MHz, BusClock = 4MHz
*/
/*----------------------------------------------------------------------------
Define clock source values
*----------------------------------------------------------------------------*/
#if (CLOCK_SETUP == 0)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 20485760u /* Default System clock value */
#elif (CLOCK_SETUP == 1)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
#elif (CLOCK_SETUP == 3)
#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
#endif /* (CLOCK_SETUP == 3) */
#elif defined(CPU_MK22FN512VDC12)
#define DISABLE_WDOG 1
#define CLOCK_SETUP 1
/* Predefined clock setups
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
Reference clock source for MCG module is the slow internal clock source 32.768kHz
Core clock = 41.94MHz, BusClock = 41.94MHz
1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
Reference clock source for MCG module is an external crystal 8MHz
Core clock = 100MHz, BusClock = 50MHz
2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
Core clock = 8MHz, BusClock = 8MHz
3 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
Reference clock source for MCG module is an external crystal 8MHz
Core clock = 120MHz, BusClock = 60MHz
*/
/*----------------------------------------------------------------------------
Define clock source values
*----------------------------------------------------------------------------*/
#if (CLOCK_SETUP == 0)
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
#elif (CLOCK_SETUP == 1)
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 100000000u /* Default System clock value */
#elif (CLOCK_SETUP == 2)
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
#elif (CLOCK_SETUP == 3)
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
#endif /* (CLOCK_SETUP == 3) */
#endif /* CPU types*/
/*! @}*/
#endif /* __FSL_CLOCK_CONFIGS_H__*/
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__FSL_CLOCK_MANAGER_H__)
#define __FSL_CLOCK_MANAGER_H__
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
/*! @addtogroup clock_manager*/
/*! @{*/
/*! @file*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Clock names */
typedef enum _clock_names {
/* default system clocks*/
kCoreClock, /**/
kSystemClock, /**/
kPlatformClock, /**/
kBusClock, /**/
kFlexBusClock, /**/
kFlashClock, /**/
/* other internal clocks used by peripherals*/
/* osc clock*/
kOsc32kClock,
kOsc0ErClock,
kOsc1ErClock,
/* irc 48Mhz clock */
kIrc48mClock,
/* rtc clock*/
kRtc32kClock,
kRtc1hzClock,
/* lpo clcok*/
kLpoClock,
/* mcg clocks*/
kMcgFllClock,
kMcgPll0Clock,
kMcgPll1Clock,
kMcgOutClock,
kMcgIrClock,
/* constant clocks (provided in other header files?)*/
kSDHC0_CLKIN,
kENET_1588_CLKIN,
kEXTAL_Clock,
kEXTAL1_Clock,
kUSB_CLKIN,
/* reserved value*/
kReserved,
/* clock name max */
kClockNameCount
} clock_names_t;
/*! @brief Clock gate module names */
typedef enum _clock_gate_module_names {
/* System modules*/
kClockModuleDMA, /**/
kClockModuleDMAMUX, /* instance 0, 1*/
kClockModulePORT, /* instance 0 - 5 (A - F)*/
kClockModuleMPU, /**/
kClockModuleLLWU, /**/
kClockModuleEWM, /**/
/* Clocks*/
kClockModuleOSC1, /**/
/* Memory and memory interfaces*/
kClockModuleFTF, /* Flash memory control clock*/
kClockModuleNFC, /* NAND flash control clock*/
kClockModuleFLEXBUS, /**/
kClockModuleDDR, /**/
/* Security*/
kClockModuleCRC, /**/
kClockModuleRNGA, /**/
kClockModuleREGFILE, /**/
kClockModuleDRYICESECREG, /**/
kClockModuleDRYICE, /**/
/* Analog*/
kClockModuleADC, /* instance 0 - 3*/
kClockModuleCMP, /* */
kClockModuleDAC, /* instance 0, 1*/
kClockModuleVREF, /* */
kClockModuleSAI, /* instance 0, 1*/
/* Timers*/
kClockModuleTPM, /* TPM timers 0 - 2*/
kClockModulePDB, /* */
kClockModuleFTM, /* instance 0 - 3*/
kClockModulePIT, /**/
kClockModuleLPTIMER, /**/
kClockModuleCMT, /**/
kClockModuleRTC, /**/
/* Communication Interfaces*/
kClockModuleENET, /**/
kClockModuleUSBHS, /**/
kClockModuleUSBFS, /**/
kClockModuleUSBDCD, /**/
kClockModuleFLEXCAN, /* instance 0, 1*/
kClockModuleSPI, /* instance 0 - 2*/
kClockModuleI2C, /* instance 0, 1*/
kClockModuleUART, /* instance 0 - 5*/
kClockModuleESDHC, /**/
kClockModuleLPUART, /**/
/* Human-machine Interfaces*/
kClockModuleTSI, /**/
kClockModuleLCDC, /**/
kClockModuleMax
} clock_gate_module_names_t;
/*! @brief Clock source and SEL names */
typedef enum _clock_source_names {
kClockNfcSrc, /* NFCSRC*/
kClockEsdhcSrc, /* ESDHCSRC K70*/
kClockSdhcSrc, /* SDHCSRC K64*/
kClockLcdcSrc, /* LCDCSRC*/
kClockTimeSrc, /* TIMESRC*/
kClockRmiiSrc, /* RMIISRC*/
kClockUsbfSrc, /* USBFSRC K70*/
kClockUsbSrc, /* USBSRC K64, KL25, KV31, and K22*/
kClockUsbhSrc, /* USBHSRC*/
kClockUart0Src, /* UART0SRC*/
kClockTpmSrc, /* TPMSRC*/
kClockOsc32kSel, /* OSC32KSEL*/
kClockUsbfSel, /* USBF_CLKSEL*/
kClockPllfllSel, /* PLLFLLSEL*/
kClockNfcSel, /* NFC_CLKSEL*/
kClockLcdcSel, /* LCDC_CLKSEL*/
kClockTraceSel, /* TRACE_CLKSEL*/
kClockClkoutSel, /* CLKOUTSEL*/
kClockRtcClkoutSel, /* RTCCLKOUTSEL */
kClockSourceMax
} clock_source_names_t;
/*!
* @brief Error code definition for the clock manager APIs
*/
typedef enum _clock_manager_error_code {
kClockManagerSuccess, /*!< success */
kClockManagerNoSuchClockName, /*!< cannot find the clock name */
kClockManagerNoSuchClockModule, /*!< cannot find the clock module name */
kClockManagerNoSuchClockSource, /*!< cannot find the clock source name */
kClockManagerNoSuchDivider, /*!< cannot find the divider name */
kClockManagerUnknown /*!< unknown error*/
} clock_manager_error_code_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*! @name Clock Gating*/
/*@{*/
/*!
* @brief Enables or disables the clock for a specific clock module.
*
* This function enables/disables the clock for a specified clock module and
* instance. See the clock_gate_module_names_t for supported clock module names
* for a specific function and see the Reference Manual for supported clock module
* name for a specific chip family. Most module drivers call this function
* to gate(disable)/ungate(enable) the clock for a module. However, the application
* can also call this function as needed. Disabling the clock causes the module
* to stop working. See the Reference Manual to properly enable
* and disable the clock for a device module.
*
* @param moduleName Gate control module name defined in clock_gate_module_names_t
* @param instance Instance of the module
* @param enable Enable or disable the clock for the module
* - true: Enable
* - false: Disable
* @return status Error code defined in clock_manager_error_code_t
*/
clock_manager_error_code_t clock_manager_set_gate(clock_gate_module_names_t moduleName,
uint8_t instance, bool enable);
/*!
* @brief Gets the current clock gate status for a specific clock module.
*
* This function returns the current clock gate status for a specific clock
* module. See clock_gate_module_names_t for supported clock module name.
*
* @param moduleName Gate control module name defined in clock_gate_module_names_t
* @param instance Instance of the module
* @param isEnabled Status of the module clock
* - true: Enabled
* - false: Disabled
* @return status Error code defined in clock_manager_error_code_t
*/
clock_manager_error_code_t clock_manager_get_gate(clock_gate_module_names_t moduleName,
uint8_t instance, bool *isEnabled);
/*@}*/
/*! @name Clock Frequencies*/
/*@{*/
/*!
* @brief Gets the clock frequency for a specific clock name.
*
* This function checks the current clock configurations and then calculates
* the clock frequency for a specific clock name defined in clock_names_t.
* The MCG must be properly configured before using this function. See
* the Reference Manual for supported clock names for different chip families.
* The returned value is in Hertz. If it cannot find the clock name
* or the name is not supported for a specific chip family, it returns an
* error.
*
* @param clockName Clock names defined in clock_names_t
* @param frequency Returned clock frequency value in Hertz
* @return status Error code defined in clock_manager_error_code_t
*/
clock_manager_error_code_t clock_manager_get_frequency(clock_names_t clockName,
uint32_t *frequency);
/*!
* @brief Gets the clock frequency for a specified clock source.
*
* This function gets the specified clock source setting and converts it
* into a clock name. It calls the internal function to get the value
* for that clock name. The returned value is in Hertz.
* If it cannot find the clock source or the source is not supported for the
* specific chip family, it returns an error.
*
* @param clockSource Clock source names defined in clock_source_names_t
* @param frequency Returned clock frequency value in Hertz
* @return status Error code defined in clock_manager_error_code_t
*/
clock_manager_error_code_t clock_manager_get_frequency_by_source(
clock_source_names_t clockSource, uint32_t *frequency);
/*@}*/
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*! @}*/
#endif /* __FSL_CLOCK_MANAGER_H__*/
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_device_registers.h"
#include "fsl_sim_hal.h"
#include "fsl_clock_manager.h"
#include "fsl_clock_manager_private.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* internal function for clock manager. see function header for details */
static clock_manager_error_code_t clock_manager_get_frequency_by_name(sim_clock_names_t clockName,
uint32_t *frequency);
/*******************************************************************************
* Code
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : clock_manager_get_system_clock
* Description : Internal function to get the system clock frequency
* This function will check the clock name configuration table for specific
* chip family and find out the supported clock name for that chip family
* then it will call the mcg hal function to get the basic system clock,
* calculate the clock frequency for specified clock name.
*
*END**************************************************************************/
clock_manager_error_code_t clock_manager_get_system_clock(sim_clock_names_t clockName,
uint32_t *frequency)
{
/* system clock out divider*/
uint32_t divider;
uint32_t i = 0;
const sim_clock_name_config_t *table = NULL;
/* search through whole name table*/
while (kSimClockNameConfigTable[i].clockName != kSimClockNameCount)
{
/* find only the match with name*/
if (kSimClockNameConfigTable[i].clockName == clockName)
{
/* return the table pointer*/
table = &kSimClockNameConfigTable[i];
break;
}
i++;
}
/* if the configuration table doesn't exist, return error */
if (table == NULL)
{
return kClockManagerNoSuchClockName;
}
/* check if we need to use a reference clock*/
if (table->useOtherRefClock)
{
/* get other specified ref clock*/
if ( kClockManagerSuccess != clock_manager_get_frequency_by_name(table->otherRefClockName,
frequency) )
{
return kClockManagerNoSuchClockName;
}
}
else
{
/* get default ref clock */
*frequency = clock_hal_get_outclk();
}
/* get system clock divider*/
if ( clock_hal_get_clock_divider(table->dividerName, &divider) == kSimHalSuccess)
{
/* get the frequency for the specified clock*/
*frequency = (*frequency) / (divider + 1);
return kClockManagerSuccess;
}
else
{
return kClockManagerNoSuchDivider;
}
}
/*FUNCTION**********************************************************************
*
* Function Name : clock_manager_set_gate
* Description : Enable or disable the clock for specified clock module
* This function will enable/disable the clock for specified clock module and
* instance. Refer to clock_gate_module_names_t for supported clock module name
* by this function and refer to reference manual for supported clock moulde
* name for a specified chip family. Most module driver will call this function
* to gate(disable)/ungate(enable) the clock for that module, but application
* can also call this function as needed. Disable the clock will make the module
* stop working. Refer to the reference maunal for proper procedure of enalbing
* and disabling the clock for the device module.
*
*END**************************************************************************/
clock_manager_error_code_t clock_manager_set_gate(clock_gate_module_names_t moduleName,
uint8_t instance, bool enable)
{
/* calling hal api, to set(Enable/Disable) the clock module gate */
if (clock_hal_set_gate(kClockModuleNameSimMap[moduleName], instance, enable) == kSimHalSuccess)
{
return kClockManagerSuccess;
}
else
{
return kClockManagerNoSuchClockModule;
}
}
/*FUNCTION**********************************************************************
*
* Function Name : clock_manager_get_gate
* Description : Get the current clock gate status for specified clock module
* This function will return the current clock gate status for specified clock
* module. Refer to clock_gate_module_names_t for supported clock module name.
*
*END**************************************************************************/
clock_manager_error_code_t clock_manager_get_gate(clock_gate_module_names_t moduleName,
uint8_t instance, bool *isEnabled)
{
/* calling the hal function to get the clock module gate status */
if (clock_hal_get_gate(kClockModuleNameSimMap[moduleName], instance, isEnabled)
== kSimHalSuccess)
{
return kClockManagerSuccess;
}
else
{
return kClockManagerNoSuchClockModule;
}
}
/*FUNCTION**********************************************************************
*
* Function Name : clock_manager_get_frequency
* Description : Get the clock frequency for specified clock name
* This function will check the current clock configurations and then calculate
* the clock frequency for specified clock name defined in clock_names_t.
* The MCG must be properly configured before using this function. Also check
* the reference manual for supported clock names on different chip falmily.
* The returned value will be in herz. And if it cannot find the clock name
* or the name is not supported on specific chip family, it will return an
* error.
*
*END**************************************************************************/
clock_manager_error_code_t clock_manager_get_frequency(clock_names_t clockName,
uint32_t *frequency)
{
/* convert clock manager clock name to sim clock name */
sim_clock_names_t simClockName = kClockNameSimMap[clockName];
/* calling internal get frequency by name function */
return clock_manager_get_frequency_by_name(simClockName, frequency);
}
/*FUNCTION**********************************************************************
*
* Function Name : clock_manager_get_frequency_by_name
* Description : Internal function to get the frequency by clock name
* This function will get/calculate the clock frequency based on clock name
* and current configuration of clock generator.
*
*END**************************************************************************/
clock_manager_error_code_t static clock_manager_get_frequency_by_name(sim_clock_names_t clockName,
uint32_t *frequency)
{
/* branch according to clock name */
switch(clockName)
{
/* osc clock*/
case kSimOsc32kClock:
/* *frequency = CPU_XTAL32k_CLK_HZ; // or should provided by osc module??*/
*frequency = 32768;
break;
case kSimOsc0ErClock:
/* *frequency = CPU_XTAL_CLK_HZ; // or should provided by osc module??*/
*frequency = 80000; /* for testing purpose only*/
break;
case kSimOsc1ErClock:
/* *frequency = CPU_XTAL_CLK_HZ; // or should provided by osc module??*/
*frequency = 80001; /* for testing purpose only*/
break;
/* irc clock*/
case kSimIrc48mClock:
/* *frequency = CPU_INT_IRC_CLK_HZ; // or should provided by irc module??*/
*frequency = 48000;
break;
/* rtc clock*/
case kSimRtc32kClock:
/* *frequency = CPU_XTAL32k_CLK_HZ; // or should provided by rtc module??*/
*frequency = 32768;
break;
case kSimRtc1hzClock:
/* *frequency = CPU_XTAL1hz_CLK_HZ; // or should provided by rtc module??*/
*frequency = 1;
break;
/* lpo clcok*/
case kSimLpoClock:
/* *frequency = 1000; // where should we define this constant??*/
*frequency = 1000;
break;
/* mcg clocks, calling mcg clock functions */
case kSimMcgFllClock:
*frequency = clock_hal_get_fllclk();
break;
case kSimMcgPll0Clock:
*frequency = clock_hal_get_pll0clk();
break;
case kSimMcgOutClock:
*frequency = clock_hal_get_outclk();
break;
case kSimMcgIrClock:
*frequency = clock_hal_get_irclk();
break;
/* constant clocks (provided in other header files - TBD)*/
case kSimSDHC0_CLKIN:
*frequency = 11111; /* for testing use purpose*/
break;
case kSimENET_1588_CLKIN:
*frequency = 22222; /* for testing use purpose*/
break;
case kSimEXTAL_Clock:
/* *frequency = CPU_XTAL_CLK_HZ; // is this correct??*/
*frequency = 33333; /* for testing use purpose*/
break;
case kSimEXTAL1_Clock:
/* *frequency = CPU_XTAL_CLK_HZ; // is this correct??*/
*frequency = 33334; /* for testing use purpose*/
break;
case kSimUSB_CLKIN:
*frequency = 44444; /* for testing use purpose*/
break;
/* system clocks */
case kSimCoreClock:
case kSimSystemClock:
case kSimPlatformClock:
case kSimBusClock:
case kSimFlexBusClock:
case kSimFlashClock:
return clock_manager_get_system_clock(clockName, frequency);
/* reserved value*/
case kSimReserved:
default:
*frequency = 55555; /* for testing use purpose*/
return kClockManagerNoSuchClockName;
}
return kClockManagerSuccess;
}
/*FUNCTION**********************************************************************
*
* Function Name : clock_manager_get_frequency_by_source
* Description : Get the clock frequency for specified clock source
* This function will get the specified clock source setting and convert it
* into a clock name, then calling the internal function to find out the value
* for that clock name. Also the returned value is in herz.
* If it cannot find the clock source or the source is not supported on the
* specific chip family, it will return an error.
*
*END**************************************************************************/
clock_manager_error_code_t clock_manager_get_frequency_by_source(clock_source_names_t clockSource,
uint32_t *frequency)
{
uint8_t setting;
uint8_t subsetting1;
uint8_t subsetting2;
uint32_t frac = 0;
uint32_t divider = 0;
sim_clock_names_t simClockName;
sim_clock_source_names_t simClockSource;
sim_clock_divider_names_t dividerName;
const sim_clock_source_value_t *valueTable = NULL;
const sim_clock_source_value_t *subValueTable1 = NULL;
const sim_clock_source_value_t *subValueTable2 = NULL;
assert (clockSource < kClockSourceMax);
/* convert clock manager clock source to sim clock source*/
simClockSource = kClockSourceNameSimMap[clockSource];
/* check to see if we need to use clock sel for specified clock source (see if CLKSEL exists)*/
switch (simClockSource)
{
case kSimClockNfcSrc: /* NFCSRC*/
simClockSource = kSimClockNfcSel;
break;
case kSimClockLcdcSrc: /* LCDCSRC*/
simClockSource = kSimClockLcdcSel;
break;
case kSimClockUsbfSrc: /* USBFSRC K70*/
simClockSource = kSimClockUsbfSel;
break;
default:
break;
}
/* get the sim clock source setting*/
if (clock_hal_get_clock_source(simClockSource, &setting) != kSimHalSuccess)
{
return kClockManagerNoSuchClockSource;
}
/* get the value index table for the clock source*/
valueTable = kSimClockSourceValueTable[simClockSource];
/* if the source exists*/
if (valueTable == NULL)
{
return kClockManagerNoSuchClockSource;
}
/* check if it is a clock name or selection*/
if (valueTable[setting].isSel)
{
/* if it is a selection, then convert the selection into a clock name*/
/* get the config table for the clock source*/
if (clock_hal_get_clock_source(valueTable[setting].clockSelName, &subsetting1)
!= kSimHalSuccess)
{
return kClockManagerNoSuchClockSource;
}
/* get the value index table for the clock source*/
subValueTable1 = kSimClockSourceValueTable[valueTable[setting].clockSelName];
/* check if there's bad data*/
if (subValueTable1 == NULL)
{
return kClockManagerNoSuchClockSource;
}
/* check if there's further clock select*/
if (subValueTable1[subsetting1].isSel)
{
/* if it is a selection, then convert the selection into a clock name*/
/* get the config table for the clock source*/
if (clock_hal_get_clock_source(subValueTable1[subsetting1].clockSelName, &subsetting2)
!= kSimHalSuccess)
{
return kClockManagerNoSuchClockSource;
}
/* get the value index table for the clock source*/
subValueTable2 = kSimClockSourceValueTable[subValueTable1[subsetting1].clockSelName];
/* check if there's bad data*/
if (subValueTable2 == NULL)
{
return kClockManagerNoSuchClockSource;
}
/* further convert the subvalue to clock name */
simClockName = subValueTable2[subsetting2].clockName;
}
else
{
/* further convert the subvalue to clock name */
simClockName = subValueTable1[subsetting1].clockName;
}
}
else
{
/* convert the value to clock name */
simClockName = valueTable[setting].clockName;
}
/* get/calculate the frequency for the specified clock name*/
if ( clock_manager_get_frequency_by_name(simClockName, frequency) != kClockManagerSuccess)
{
return kClockManagerNoSuchClockName;
}
/* find the first available divider*/
if (valueTable[setting].hasDivider)
{
/* get the diviver name */
dividerName = valueTable[setting].dividerName;
}
else if ((subValueTable1 != NULL) && (subValueTable1[subsetting1].hasDivider))
{
/* get the diviver name */
dividerName = subValueTable1[subsetting1].dividerName;
}
else if ((subValueTable2 != NULL) && (subValueTable2[subsetting2].hasDivider))
{
/* get the diviver name */
dividerName = subValueTable2[subsetting2].dividerName;
}
else
{
return kClockManagerSuccess;
}
/* get the divider value*/
switch (dividerName)
{
case kSimClockDividerNfcDiv: /* NFCSRC*/
clock_hal_get_clock_divider(kSimClockDividerNfcDiv, &divider);
clock_hal_get_clock_divider(kSimClockDividerNfcFrac, &frac);
break;
case kSimClockDividerLcdcDiv: /* LCDCSRC*/
clock_hal_get_clock_divider(kSimClockDividerLcdcDiv, &divider);
clock_hal_get_clock_divider(kSimClockDividerLcdcFrac, &frac);
break;
case kSimClockDividerUsbfsDiv: /* USBFSRC K70*/
clock_hal_get_clock_divider(kSimClockDividerUsbfsDiv, &divider);
clock_hal_get_clock_divider(kSimClockDividerUsbfsFrac, &frac);
break;
case kSimClockDividerUsbDiv: /* USBSRC K64, KL25, KV31, and K22*/
clock_hal_get_clock_divider(kSimClockDividerUsbDiv, &divider);
clock_hal_get_clock_divider(kSimClockDividerUsbFrac, &frac);
break;
case kSimClockDividerUsbhsDiv: /* USBHSRC K70*/
clock_hal_get_clock_divider(kSimClockDividerUsbhsDiv, &divider);
clock_hal_get_clock_divider(kSimClockDividerUsbhsFrac, &frac);
break;
case kSimClockDividerSpecial1: /* Special KL25 divider 2*/
clock_hal_get_clock_divider(kSimClockDividerSpecial1, &divider);
break;
default:
break;
}
/* Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ]*/
*frequency = (*frequency) * (frac + 1) / (divider + 1);
return kClockManagerSuccess;
}
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__FSL_CLOCK_MANAGER_PRIVATE_H__)
#define __FSL_CLOCK_MANAGER_PRIVATE_H__
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
/*! @addtogroup clock_manager*/
/*! @{*/
/*! @file*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Clock manager clock names mapping into the SIM clock name*/
sim_clock_names_t kClockNameSimMap[kClockNameCount] = {
/* default clocks*/
kSimCoreClock, /**/
kSimSystemClock, /**/
kSimPlatformClock, /**/
kSimBusClock, /**/
kSimFlexBusClock, /**/
kSimFlashClock, /**/
/* other internal clocks used by peripherals*/
/* osc clock*/
kSimOsc32kClock,
kSimOsc0ErClock,
kSimOsc1ErClock,
/* irc 48Mhz clock */
kSimIrc48mClock,
/* rtc clock*/
kSimRtc32kClock,
kSimRtc1hzClock,
/* lpo clcok*/
kSimLpoClock,
/* mcg clocks*/
kSimMcgFllClock,
kSimMcgPll0Clock,
kSimMcgPll1Clock,
kSimMcgOutClock,
kSimMcgIrClock,
/* constant clocks (provided in other header files?)*/
kSimSDHC0_CLKIN,
kSimENET_1588_CLKIN,
kSimEXTAL_Clock,
kSimEXTAL1_Clock,
kSimUSB_CLKIN,
/* reserved value*/
kSimReserved
};
/*! @brief Clock manager clock source names mapping into the SIM clock source name*/
sim_clock_source_names_t kClockSourceNameSimMap[kClockSourceMax] = {
kSimClockNfcSrc, /* NFCSRC*/
kSimClockEsdhcSrc, /* ESDHCSRC K70*/
kSimClockSdhcSrc, /* SDHCSRC K64*/
kSimClockLcdcSrc, /* LCDCSRC*/
kSimClockTimeSrc, /* TIMESRC*/
kSimClockRmiiSrc, /* RMIISRC*/
kSimClockUsbfSrc, /* USBFSRC K70*/
kSimClockUsbSrc, /* USBSRC K64, KL25, KV31, and K22*/
kSimClockUsbhSrc, /* USBHSRC*/
kSimClockUart0Src, /* UART0SRC*/
kSimClockTpmSrc, /* TPMSRC*/
kSimClockOsc32kSel, /* OSC32KSEL*/
kSimClockUsbfSel, /* USBF_CLKSEL*/
kSimClockPllfllSel, /* PLLFLLSEL*/
kSimClockNfcSel, /* NFC_CLKSEL*/
kSimClockLcdcSel, /* LCDC_CLKSEL*/
kSimClockTraceSel, /* TRACE_CLKSEL*/
kSimClockClkoutSel, /* CLKOUTSEL*/
kSimClockRtcClkoutSel /* RTCCLKOUTSEL */
};
/*! @brief Clock manager clock module names mapping into the SIM clock module name*/
sim_clock_gate_module_names_t kClockModuleNameSimMap[kClockModuleMax] = {
/* System modules*/
kSimClockModuleDMA, /**/
kSimClockModuleDMAMUX, /* instance 0, 1*/
kSimClockModulePORT, /* instance 0 - 5 (A - F)*/
kSimClockModuleMPU, /**/
kSimClockModuleLLWU, /**/
kSimClockModuleEWM, /**/
/* Clocks*/
kSimClockModuleOSC1, /**/
/* Memory and memory interfaces*/
kSimClockModuleFTF, /* Flash memory control clock*/
kSimClockModuleNFC, /* NAND flash control clock*/
kSimClockModuleFLEXBUS, /**/
kSimClockModuleDDR, /**/
/* Security*/
kSimClockModuleCRC, /**/
kSimClockModuleRNGA, /**/
kSimClockModuleREGFILE, /**/
kSimClockModuleDRYICESECREG, /**/
kSimClockModuleDRYICE, /**/
/* Analog*/
kSimClockModuleADC, /* instance 0 - 3*/
kSimClockModuleCMP, /* */
kSimClockModuleDAC, /* instance 0, 1*/
kSimClockModuleVREF, /* */
kSimClockModuleSAI, /* instance 0, 1*/
/* Timers*/
kSimClockModuleTPM, /* TPM timers 0 - 2*/
kSimClockModulePDB, /* */
kSimClockModuleFTM, /* instance 0 - 3*/
kSimClockModulePIT, /**/
kSimClockModuleLPTIMER, /**/
kSimClockModuleCMT, /**/
kSimClockModuleRTC, /**/
/* Communication Interfaces*/
kSimClockModuleENET, /**/
kSimClockModuleUSBHS, /**/
kSimClockModuleUSBFS, /**/
kSimClockModuleUSBDCD, /**/
kSimClockModuleFLEXCAN, /* instance 0, 1*/
kSimClockModuleSPI, /* instance 0 - 2*/
kSimClockModuleI2C, /* instance 0, 1*/
kSimClockModuleUART, /* instance 0 - 5*/
kSimClockModuleESDHC, /**/
kSimClockModuleLPUART, /**/
/* Human-machine Interfaces*/
kSimClockModuleTSI, /**/
kSimClockModuleLCDC /**/
};
extern const sim_clock_source_value_t *kSimClockSourceValueTable[];
/*******************************************************************************
* API
******************************************************************************/
/*! @name System out clock access API*/
/*@{*/
/*!
* @brief Gets the current out clock.
*
* @param none
*
* @return frequency Out clock frequency for the clock system
*/
extern uint32_t clock_hal_get_outclk(void);
/*!
* @brief Gets the current FLL clock.
*
* @param none
*
* @return frequency FLL clock frequency for the clock system
*/
extern uint32_t clock_hal_get_fllclk(void);
/*!
* @brief Gets the current PLL0 clock.
*
* @param none
*
* @return frequency PLL0 clock frequency for the clock system
*/
extern uint32_t clock_hal_get_pll0clk(void);
/*!
* @brief Gets the current PLL1 clock.
*
* @param none
*
* @return frequency PLL1 clock frequency for the clock system
*/
extern uint32_t clock_hal_get_pll1clk(void);
/*!
* @brief Get the current IR (internal reference) clock.
*
* @param none
*
* @return frequency IR clock frequency for the clock system
*/
extern uint32_t clock_hal_get_irclk(void);
/*@}*/
/*! @}*/
#endif /* __FSL_CLOCK_MANAGER_PRIVATE_H__*/
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__FSL_ADC_FEATURES_H__)
#define __FSL_ADC_FEATURES_H__
#if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \
defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \
defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \
defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \
defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FN1M0VDC12) || \
defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VMD12) || \
defined(CPU_MK64FX512VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || \
defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || \
defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || defined(CPU_MKV31F256VLH12) || \
defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31FN512VLH12) || defined(CPU_MKV31F512VLL12)
/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA).*/
#define FSL_FEATURE_ADC_HAS_PGA (0)
/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]).*/
#define FSL_FEATURE_ADC_HAS_DMA (1)
/* @brief Has differential mode (bitfield SC1x[DIFF]).*/
#define FSL_FEATURE_ADC_HAS_DIFF_MODE (1)
/* @brief Has FIFO (bit SC4[AFDEP]).*/
#define FSL_FEATURE_ADC_HAS_FIFO (0)
/* @brief FIFO size if available (bitfield SC4[AFDEP]).*/
#define FSL_FEATURE_ADC_FIFO_SIZE (0)
/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]).*/
#define FSL_FEATURE_ADC_HAS_MUX_SELECT (1)
/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE].*/
#define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0)
/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx).*/
#define FSL_FEATURE_ADC_HAS_CALIBRATION (1)
/* @brief Has HW averaging (bit SC3[AVGE]).*/
#define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1)
/* @brief Has offset correction (register OFS).*/
#define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1)
/* @brief Maximum ADC resolution.*/
#define FSL_FEATURE_ADC_MAX_RESOLUTION (16)
/* @brief Number of SC1x and Rx register pairs (conversion control and result registers).*/
#define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2)
#elif defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || \
defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \
defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || \
defined(CPU_MKL05Z32VLF4)
/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA).*/
#define FSL_FEATURE_ADC_HAS_PGA (0)
/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]).*/
#define FSL_FEATURE_ADC_HAS_DMA (1)
/* @brief Has differential mode (bitfield SC1x[DIFF]).*/
#define FSL_FEATURE_ADC_HAS_DIFF_MODE (0)
/* @brief Has FIFO (bit SC4[AFDEP]).*/
#define FSL_FEATURE_ADC_HAS_FIFO (0)
/* @brief FIFO size if available (bitfield SC4[AFDEP]).*/
#define FSL_FEATURE_ADC_FIFO_SIZE (0)
/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]).*/
#define FSL_FEATURE_ADC_HAS_MUX_SELECT (1)
/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE].*/
#define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0)
/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx).*/
#define FSL_FEATURE_ADC_HAS_CALIBRATION (1)
/* @brief Has HW averaging (bit SC3[AVGE]).*/
#define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1)
/* @brief Has offset correction (register OFS).*/
#define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1)
/* @brief Maximum ADC resolution.*/
#define FSL_FEATURE_ADC_MAX_RESOLUTION (16)
/* @brief Number of SC1x and Rx register pairs (conversion control and result registers).*/
#define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2)
#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA).*/
#define FSL_FEATURE_ADC_HAS_PGA (1)
/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]).*/
#define FSL_FEATURE_ADC_HAS_DMA (1)
/* @brief Has differential mode (bitfield SC1x[DIFF]).*/
#define FSL_FEATURE_ADC_HAS_DIFF_MODE (1)
/* @brief Has FIFO (bit SC4[AFDEP]).*/
#define FSL_FEATURE_ADC_HAS_FIFO (0)
/* @brief FIFO size if available (bitfield SC4[AFDEP]).*/
#define FSL_FEATURE_ADC_FIFO_SIZE (0)
/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]).*/
#define FSL_FEATURE_ADC_HAS_MUX_SELECT (1)
/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE].*/
#define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0)
/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx).*/
#define FSL_FEATURE_ADC_HAS_CALIBRATION (1)
/* @brief Has HW averaging (bit SC3[AVGE]).*/
#define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1)
/* @brief Has offset correction (register OFS).*/
#define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1)
/* @brief Maximum ADC resolution.*/
#define FSL_FEATURE_ADC_MAX_RESOLUTION (16)
/* @brief Number of SC1x and Rx register pairs (conversion control and result registers).*/
#define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2)
#else
#error "No valid CPU defined!"
#endif
#endif /* __FSL_ADC_FEATURES_H__*/
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_adc_hal.h"
#include "fsl_device_registers.h"
#include <assert.h>
/*******************************************************************************
* Code
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : adc_hal_start_calibration
* Description : This function is to clear the calibrate flag bit and then set
* the enable bit to start the calibration.
*
*END**************************************************************************/
adc_status_t adc_hal_start_calibration(uint32_t instance)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
/* Execute the calibration */
HW_ADC_SC3_SET(instance, BM_ADC_SC3_CALF); /* Clear the calibration's flag */
BW_ADC_SC3_CAL(instance, 1U); /* Enable the calibration */
while (!adc_hal_is_conversion_completed(instance, 0U))
{} /* Wait conversion is competed */
if (adc_hal_is_calibration_fail(instance))
{
return kStatus_ADC_Failed; /* Check for calibration fail error and return */
}
return kStatus_ADC_Success;
}
/*FUNCTION**********************************************************************
*
* Function Name : adc_hal_get_calibration_PG
* Description : This function is to get the CLP0 - CLP4 and CLPS and
* accumulate them, and then return the value that can be set to PG directly.
*
*END**************************************************************************/
uint32_t adc_hal_get_calibration_PG(uint32_t instance)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
uint32_t cal_var;
/* Calculate plus-side calibration */
cal_var = 0U;
cal_var += BR_ADC_CLP0_CLP0(instance);
cal_var += BR_ADC_CLP1_CLP1(instance);
cal_var += BR_ADC_CLP2_CLP2(instance);
cal_var += BR_ADC_CLP3_CLP3(instance);
cal_var += BR_ADC_CLP4_CLP4(instance);
cal_var += BR_ADC_CLPS_CLPS(instance);
cal_var = 0x8000U | (cal_var>>1U);
return cal_var;
}
/*FUNCTION**********************************************************************
*
* Function Name : adc_hal_get_calibration_MG
* Description : This function is to get the CLM0 - CLM4 and CLMS and
* accumulate them, and then return the value that can be set to MG directly.
*
*END**************************************************************************/
uint32_t adc_hal_get_calibration_MG(uint32_t instance)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
uint32_t cal_var;
/* Calculate minus-side calibration */
cal_var = 0U;
cal_var += BR_ADC_CLM0_CLM0(instance);
cal_var += BR_ADC_CLM1_CLM1(instance);
cal_var += BR_ADC_CLM2_CLM2(instance);
cal_var += BR_ADC_CLM3_CLM3(instance);
cal_var += BR_ADC_CLM4_CLM4(instance);
cal_var += BR_ADC_CLMS_CLMS(instance);
cal_var = 0x8000U | (cal_var>>1U);
return cal_var;
}
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __FSL_ADC_HAL_H__
#define __FSL_ADC_HAL_H__
#include <assert.h>
#include <stdint.h>
#include <stdbool.h>
#include "fsl_adc_features.h"
#include "fsl_device_registers.h"
/*!
* @addtogroup adc_hal
* @{
*/
/*! @file*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Defines the selection of the clock source that ADC module uses.*/
typedef enum _adc_clock_source_mode
{
kAdcClockSourceBusClk = 0U, /*!< Use bus clock.*/
kAdcClockSourceBusClk2 = 1U, /*!< Use bus clock / 2.*/
kAdcClockSourceAlternate = 2U, /*!< Use the optional external clock.*/
kAdcClockSourceAsynchrounous = 3U, /*!< Use ADC's internal asynchronous clock. */
} adc_clock_source_mode_t;
/*! @brief Defines the selection of the clock divider.*/
typedef enum _adc_clock_divider_mode
{
kAdcClockDivider1 = 0U, /*!< Divide 1.*/
kAdcClockDivider2 = 1U, /*!< Divide 2.*/
kAdcClockDivider4 = 2U, /*!< Divide 4.*/
kAdcClockDivider8 = 3U, /*!< Divide 8.*/
} adc_clock_divider_mode_t;
/*! @brief Defines the selection of the voltage source that ADC module uses.*/
typedef enum _adc_reference_voltage_mode
{
kAdcVoltageVref = 0U, /*!< Use V_REFH & V_REFL as ref source pin.*/
kAdcVoltageValt = 1U, /*!< Use V_ALTH & V_REFL as ref source pin.*/
} adc_reference_voltage_mode_t;
/*! @brief Defines the selection of the long sample extra cycle configuration.*/
typedef enum _adc_long_sample_mode
{
kAdcLongSampleExtra20 = 0U, /*!< Extra 20 cycles, total 24 cycles, default.*/
kAdcLongSampleExtra12 = 1U, /*!< Extra 12 cycles.*/
kAdcLongSampleExtra6 = 2U, /*!< Extra 6 cycles.*/
kAdcLongSampleExtra2 = 3U, /*!< Extra 2 cycles.*/
} adc_long_sample_mode_t;
/*! @brief Defines the selection of the sample resolution.*/
typedef enum _adc_resolution_mode
{
kAdcSingleDiff8or9 = 0U, /*!< 8-bits in single-end or 9-bits in differential.*/
kAdcSingleDiff12or13 = 1U, /*!< 12-bits in single-end or 13-bits in differential.*/
kAdcSingleDiff10or11 = 2U, /*!< 10-bits in single-end or 11-bits in differential.*/
kAdcSingleDiff16 = 3U, /*!< 16-bits both in single-end and differential.*/
} adc_resolution_mode_t;
/*! @brief Defines the selection of the A/B group mux.*/
typedef enum _adc_group_mux_mode
{
kAdcChannelMuxA = 0U, /*!< Mux A group is active.*/
kAdcChannelMuxB = 1U, /*!< Mux B group is active.*/
} adc_group_mux_mode_t;
/*! @brief Defines the selection of the time in a hard average mode.*/
typedef enum _adc_hw_average_mode
{
kAdcHwAverageCount4 = 0U, /*!< Average the result after accumulating 4 conversion.*/
kAdcHwAverageCount8 = 1U, /*!< Average the result after accumulating 8 conversion.*/
kAdcHwAverageCount16 = 2U, /*!< Average the result after accumulating 16 conversion.*/
kAdcHwAverageCount32 = 3U, /*!< Average the result after accumulating 32 conversion.*/
} adc_hw_average_mode_t;
/*! @brief Defines the selection of the channel inside the ADC module.*/
typedef enum _adc_channel_mode
{
kAdcChannel0 = 0U, /*!< ADC channel 0.*/
kAdcChannell = 1U, /*!< ADC channel 1.*/
kAdcChannel2 = 2U, /*!< ADC channel 2.*/
kAdcChannel3 = 3U, /*!< ADC channel 3.*/
kAdcChannel4 = 4U, /*!< ADC channel 4.*/
kAdcChannel5 = 5U, /*!< ADC channel 5.*/
kAdcChannel6 = 6U, /*!< ADC channel 6.*/
kAdcChannel7 = 7U, /*!< ADC channel 7.*/
kAdcChannel8 = 8U, /*!< ADC channel 8.*/
kAdcChannel9 = 9U, /*!< ADC channel 9.*/
kAdcChannel10 = 10U, /*!< ADC channel 10.*/
kAdcChannel11 = 11U, /*!< ADC channel 11.*/
kAdcChannel12 = 12U, /*!< ADC channel 12.*/
kAdcChannel13 = 13U, /*!< ADC channel 13.*/
kAdcChannel14 = 14U, /*!< ADC channel 14.*/
kAdcChannel15 = 15U, /*!< ADC channel 15.*/
kAdcChannel16 = 16U, /*!< ADC channel 16.*/
kAdcChannel17 = 17U, /*!< ADC channel 17.*/
kAdcChannel18 = 18U, /*!< ADC channel 18.*/
kAdcChannel19 = 19U, /*!< ADC channel 19.*/
kAdcChannel20 = 20U, /*!< ADC channel 20.*/
kAdcChannel21 = 21U, /*!< ADC channel 21.*/
kAdcChannel22 = 22U, /*!< ADC channel 22.*/
kAdcChannel23 = 23U, /*!< ADC channel 23.*/
kAdcChannelTemperature = 26U, /*!< Internal temperature sensor.*/
kAdcChannelBandgap = 27U, /*!< Internal band gap.*/
kAdcChannelReferenceVoltageHigh = 29U, /*!< Internal ref voltage High.*/
kAdcChannelReferenceVoltageLow = 30U, /*!< Internal ref voltage L.*/
kAdcChannelDisable = 31U /*!< Disable the sample process.*/
} adc_channel_mode_t;
/*! @brief Defines the status returned from the ADC API.*/
typedef enum _adc_status
{
kStatus_ADC_Success = 0U,
kStatus_ADC_InvalidArgument = 1U,/*!< Parameter is not available for the current configuration.*/
kStatus_ADC_Failed = 2U /*!< Function operation failed. */
} adc_status_t;
#if FSL_FEATURE_ADC_HAS_PGA
/*! @brief Defines the selection of the Programmable Gain Amplifier mode.*/
typedef enum _adc_pga_mode
{
kAdcPga1 = 0U, /*!< Gain is 1*/
kAdcPga2 = 1U, /*!< Gain is 2*/
kAdcPga4 = 2U, /*!< Gain is 4*/
kAdcPga8 = 3U, /*!< Gain is 8*/
kAdcPga16 = 4U, /*!< Gain is 16*/
kAdcPga32 = 5U, /*!< Gain is 32*/
kAdcPga64 = 6U /*!< Gain is 64*/
} adc_pga_mode_t;
#endif /* FSL_FEATURE_ADC_HAS_PGA */
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Starts the calibration process.
*
* This function clears the calibration flag bit and sets the enable bit
* to start the calibration.
*
* @param instance ADC instance ID.
*/
adc_status_t adc_hal_start_calibration(uint32_t instance);
/*!
* @brief Ends the calibration process.
*
* This function clears the calibration enable bit to end the calibration.
*
* @param instance ADC instance ID.
*/
static inline void adc_hal_end_calibration(uint32_t instance)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_SC3_CAL(instance, 0U);
}
/*!
* @brief Gets and calculates the plus-side calibration parameter.
*
* This function gets the CLP0 - CLP4 and CLPS, accumulates them, and
* returns the value that can be set to the PG directly.
*
* @param instance ADC instance ID.
* @return the value that can be set to PG directly.
*/
uint32_t adc_hal_get_calibration_PG(uint32_t instance);
/*!
* @brief Sets the plus-side calibration parameter to the ADC instance.
*
* This function sets the PG register directly.
*
* @param instance ADC instance ID.
* @param val the value that can be set to PG directly.
*/
static inline void adc_hal_set_calibration_PG(uint32_t instance, uint32_t val)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
HW_ADC_PG_WR(instance, val);
}
/*!
* @brief Gets and calculates the minus-side calibration parameter.
*
* This function gets the CLM0 - CLM4 and CLMS, accumulates them, and
* returns the value that can be set to the MG directly.
*
* @param instance ADC instance ID.
* @return the value that can be set to MG directly.
*/
uint32_t adc_hal_get_calibration_MG(uint32_t instance);
/*!
* @brief Sets the minus-side calibration parameter to the ADC instance.
*
* This function sets the MG register directly.
*
* @param instance ADC instance ID.
* @param val the value that can be set to MG directly.
*/
static inline void adc_hal_set_calibration_MG(uint32_t instance, uint32_t val)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
HW_ADC_MG_WR(instance, val);
}
/*!
* @brief Gets the offset value after the auto-calibration.
*
* If the user wants to adjust the offset value according to the application,
* the origin offset value will be a reference.
*
* @param instance ADC instance ID.
* @return The offset value created by auto-calibration.
*/
static inline uint32_t adc_hal_get_calibration_offset(uint32_t instance)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
return BR_ADC_OFS_OFS(instance);
}
/*!
* @brief Sets the offset value for manual calibration.
*
* This function is to set the user selected or calibration generated offset
* error correction value. The value set here is subtracted from the conversion
* and the result is transferred into the result registers (Rn). If the result
* is above the maximum or below the minimum result value, it is forced to the
* appropriate limit for the current mode of operation.
*
* @param instance ADC instance ID.
* @param value The manual offset value.
*/
static inline void adc_hal_set_calibration_offset(uint32_t instance,
uint32_t value)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_OFS_OFS(instance, value);
}
/*!
* @brief Sets the selection of the clock source.
*
* The selection of ADC clock source can see to the type definition of
* adc_clock_source_mode_t.
* This function selects the input clock source to generate the internal
* clock, ADCK. Note that when the ADACK clock source is selected, it does not
* have to be activated prior to the start of the conversion. When it is
* selected and it is not activated prior to start a conversion , the
* asynchronous clock will be activated at the start of a conversion and shuts
* off when conversions are terminated. In this case, there is an associated
* clock startup delay each time the clock source is re-activated.
*
* @param instance ADC instance ID.
* @param mode The indicated clock source mode.
*/
static inline void adc_hal_set_clock_source_mode(uint32_t instance,
adc_clock_source_mode_t mode)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_CFG1_ADICLK(instance, (uint32_t)(mode));
}
/*!
* @brief Switches the asynchronous clock on/off.
*
* When enables the ADC's asynchronous clock source and the clock source output
* regardless of the conversion and input clock select status of the ADC. Based
* on MCU configuration, the asynchronous clock may be used by other modules.
* Setting this mode allows the clock to be used even while the ADC is idle or
* operating from a different clock source. Also, latency of initiating a single
* or first-continuous conversion with the asynchronous clock selected is
* reduced since the ADACK clock is already operational.
*
* @param instance ADC instance ID.
* @param isEnabled The switcher.
*/
static inline void adc_hal_configure_asynchronous_clock(uint32_t instance,
bool isEnabled)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_CFG2_ADACKEN(instance, (isEnabled ? 1U : 0U));
}
/*!
* @brief Sets the selection of the clock divider.
*
* The selection of ADC's clock divider can see to the type definition of the
* adc_clock_divider_mode_t.
* This function selects the divide ratio used by the ADC to generate the
* internal clock ADCK.
*
* @param instance ADC instance ID.
* @param mode The selection of the divider.
*/
static inline void adc_hal_set_clock_divider_mode(uint32_t instance,
adc_clock_divider_mode_t mode)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_CFG1_ADIV(instance, (uint32_t)(mode));
}
/*!
* @brief Sets the selection of the reference voltage source.
*
* The selection of ADC's reference voltage can see to the type definition of
* adc_reference_voltage_mode_t.
* This function selects the voltage reference source used for conversions.
*
* @param instance ADC instance ID.
* @param mode The selection of the reference voltage source.
*/
static inline void adc_hal_set_reference_voltage_mode(uint32_t instance,
adc_reference_voltage_mode_t mode)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_SC2_REFSEL(instance, (uint32_t)(mode));
}
/*!
* @brief Switches the high speed mode on/off .
*
* This function configures the ADC for high speed operations. The
* conversion sequence is altered (2 ADCK cycles added to the conversion time)
* to allow higher speed conversion clocks.
*
* @param instance ADC instance ID.
* @param isEnabled The switcher.
*/
static inline void adc_hal_configure_high_speed(uint32_t instance,
bool isEnabled)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_CFG2_ADHSC(instance, (isEnabled ? 1U : 0U));
}
/*!
* @brief Switch the long sample mode on/off.
*
* This function selects between the different sample times based on the
* conversion mode selected. It adjusts the sample period to allow
* higher impedance inputs to be accurately sampled or to maximize conversion
* speed for lower impedance inputs. Longer sample times can also be used to
* lower overall power consumption if the continuous conversions are enabled and the
* high conversion rates are not required. In fact this will be able to charge
* the SAR in a timely manner way without affecting the SAR configuration.
*
* @param instance ADC instance ID.
* @param isEnabled The switcher.
*/
static inline void adc_hal_configure_long_sample(uint32_t instance,
bool isEnabled)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_CFG1_ADLSMP(instance, (isEnabled ? 1U : 0U));
}
/*!
* @brief Sets the selection of the long sample mode.
*
* The selection of ADC long sample mode can see to the type definition of the
* adc_long_sample_mode_t.
* This function selects the long sample mode that indicating the different
* count of extra ADCK cycles are needed.
*
* @param instance ADC instance ID.
* @param mode The selection of long sample mode.
*/
static inline void adc_hal_set_long_sample_mode(uint32_t instance,
adc_long_sample_mode_t mode)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_CFG2_ADLSTS(instance, (uint32_t)(mode));
}
/*!
* @brief Switches the low power mode on/off.
*
* This function controls the power configuration of the successive approximation
* converter. This optimizes power consumption when higher sample rates are not
* required.
*
* @param instance ADC instance ID.
* @param isEnabled The switcher.
*/
static inline void adc_hal_configure_low_power(uint32_t instance, bool isEnabled)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_CFG1_ADLPC(instance, (isEnabled ? 1U : 0U));
}
/*!
* @brief Sets the selection of the resolution mode.
*
* The selection of ADC resolution mode can see to the type definition of the
* adc_resolution_mode_t.
* This function selects the ADC resolution mode. Note that the
* differential conversion is different to single-end conversion.
*
* @param instance ADC instance ID.
* @param mode The selection of resolution mode.
*/
static inline void adc_hal_set_resolution_mode(uint32_t instance,
adc_resolution_mode_t mode)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_CFG1_MODE(instance, (uint32_t)(mode));
}
/*!
* @brief Switches the continuous conversion mode on/off.
*
* This function configures the continuous conversions or sets of conversions if
* the hardware average function is enabled after initiating a conversion.
*
* @param instance ADC instance ID.
* @param isEnabled The switcher.
*/
static inline void adc_hal_configure_continuous_conversion(uint32_t instance,
bool isEnabled)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_SC3_ADCO(instance, (isEnabled ? 1U : 0U));
}
/*!
* @brief Switches the hardware trigger mode on/off .
*
* This function selects the type of trigger used for initiating a conversion.
* Two types of triggers can be selected: software trigger and hardware trigger.
* When software trigger is selected, a conversion is initiated following a
* write to SC1A. When hardware trigger is selected, a conversion is initiated
* following the assertion of the external events. The event will come through
* the signal on the line of ADHWT input after a pulse of ADHWTSn input inside SOC.
*
* @param instance ADC instance ID.
* @param isEnabled The switcher.
*/
static inline void adc_hal_configure_hw_trigger(uint32_t instance, bool isEnabled)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_SC2_ADTRG(instance, (isEnabled ? 1U : 0U));
}
/*!
* @brief Switches the hardware average mode on/off.
*
* This function enables the hardware average function of the ADC.
*
* @param instance ADC instance ID.
* @param isEnabled The switcher.
*/
static inline void adc_hal_configure_hw_average(uint32_t instance, bool isEnabled)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_SC3_AVGE(instance, (isEnabled ? 1U : 0U));
}
/*!
* @brief Sets the selection of the hardware average mode.
*
* The selection of ADC hardware average mode can see to the type definition
* of the adc_hw_average_mode_t.
* This function determines how many ADC conversions are averaged to create
* the ADC average result.
*
* @param instance ADC instance ID.
* @param mode The selection of hardware average mode.
*/
static inline void adc_hal_set_hw_average_mode(uint32_t instance,
adc_hw_average_mode_t mode)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_SC3_AVGS(instance, (uint32_t)(mode));
}
/*!
* @brief Switches the hardware compare mode on/off.
*
* This function enables the compare function.
*
* @param instance ADC instance ID.
* @param isEnabled The switcher.
*/
static inline void adc_hal_configure_hw_compare(uint32_t instance, bool isEnabled)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_SC2_ACFE(instance, (isEnabled ? 1U : 0U));
}
/*!
* @brief Switches the hardware compare greater configuration on/off .
*
* This function configures the compare function to check the conversion
* result relative to the compare value register(s) (CV1 and CV2). To enable
* will configure greater than or equal to threshold, outside range inclusive
* and inside range inclusive functionality based on the values placed in the
* CV1 and CV2 registers. Otherwise, it will configure less than threshold,
* outside range not inclusive and inside range not inclusive functionality
* based on the values placed in the CV1 and CV2 registers.
*
*
* @param instance ADC instance ID.
* @param isEnabled The switcher.
*/
static inline void adc_hal_configure_hw_compare_greater(uint32_t instance,
bool isEnabled)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_SC2_ACFGT(instance, (isEnabled ? 1U : 0U));
}
/*!
* @brief Switches the hardware compare range configuration on/off .
*
* This function configures the compare function to check if the conversion
* result of the input being monitored is either inside or outside the range
* formed by the compare value registers (CV1 and CV2). However, the actual
* compare range should be determined alone with the function of
* adc_hal_configure_hw_compare_greater() as well.
*
* @param instance ADC instance ID.
* @param isEnabled The switcher.
*/
static inline void adc_hal_configure_hw_compare_in_range(uint32_t instance,
bool isEnabled)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_SC2_ACREN(instance, (isEnabled ? 1U : 0U));
}
/*!
* @brief Sets the value1 in the hardware compare.
*
* This function sets the value of the CV1 register.
*
* @param instance ADC instance ID.
* @param value The setting value.
*/
static inline void adc_hal_set_hw_compare_value1(uint32_t instance, uint32_t value)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_CV1_CV(instance, value);
}
/*!
* @brief Sets the value2 in the hardware compare.
*
* This function sets the value of the CV2 register.
*
* @param instance ADC instance ID.
* @param value The setting value.
*/
static inline void adc_hal_set_hw_compare_value2(uint32_t instance, uint32_t value)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_CV2_CV(instance, value);
}
/*!
* @brief Switches the ADC DMA trigger on/off.
*
* When DMA is enabled, it asserts the ADC DMA request during the ADC
* conversion complete event noted by the assertion of any of the ADC COCO flags.
*
* @param instance ADC instance ID.
* @param isEnabled The switcher.
*/
static inline void adc_hal_configure_dma(uint32_t instance, bool isEnabled)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_SC2_DMAEN(instance, (isEnabled ? 1U : 0U));
}
/*!
* @brief Switches off the ADC channel conversion.
*
* Here the "NUll" channel is set to the conversion channel.
*
* @param instance ADC instance ID.
* @param group The group mux index.
*/
static inline void adc_hal_disable(uint32_t instance, uint32_t group)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
assert(group < HW_ADC_SC1n_COUNT);
BW_ADC_SC1n_ADCH(instance, group, (uint32_t)(kAdcChannelDisable));
}
/*!
* @brief Sets the channel number and switches on the conversion.
*
* When the available channel is set, the conversion begins to execute.
*
* @param instance ADC instance ID.
* @param group The group mux index.
* @param mode The selection of channel number.
* @param isDifferential the selection of differential input.
*/
static inline void adc_hal_enable(uint32_t instance, uint32_t group,
adc_channel_mode_t mode, bool isDifferential)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
assert(group < HW_ADC_SC1n_COUNT);
BW_ADC_SC1n_DIFF(instance, group, (isDifferential ? 1U : 0U));
/* Set new channel will restart the conversion. */
BW_ADC_SC1n_ADCH(instance, group, (uint32_t)(mode));
}
/*!
* @brief Switches the ADC interrupt trigger on/off .
*
* This function enables conversion complete interrupts. When COCO is
* set while the respective AIEN is high, an interrupt is asserted.
*
* @param instance ADC instance ID.
* @param group The group mux index.
* @param inEnable The switcher.
*/
static inline void adc_hal_configure_interrupt(uint32_t instance, uint32_t group,
bool isEnabled)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
assert(group < HW_ADC_SC1n_COUNT);
BW_ADC_SC1n_AIEN(instance, group, (isEnabled ? 1U : 0U));
}
/*!
* @brief Checks whether the ADC is in process.
*
* This function indicates that a conversion or hardware averaging is in
* progress. ADACT is set when a conversion is initiated and cleared when a
* conversion is completed or aborted. Note that if the continuous conversion
* is been use, this function will always return true.
*
* @param instance ADC instance ID.
* @return true if it is.
*/
static inline bool adc_hal_is_in_process(uint32_t instance)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
return BR_ADC_SC2_ADACT(instance);
}
/*!
* @brief Checks whether the channel conversion is complete.
*
* This function indicates whether each conversion is completed.
*
* @param instance ADC instance ID.
* @param group The grout mux index.
* @return true if it is.
*/
static inline bool adc_hal_is_conversion_completed(uint32_t instance, uint32_t group)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
assert(group < HW_ADC_SC1n_COUNT);
return BR_ADC_SC1n_COCO(instance, group);
}
/*!
* @brief Checks whether the calibration failed.
*
* This function displays the result of the calibration sequence.
*
* @param instance ADC instance ID.
* @return true if it is.
*/
static inline bool adc_hal_is_calibration_fail(uint32_t instance)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
return BR_ADC_SC3_CALF(instance);
}
/*!
* @brief Gets the conversion value.
*
* This function returns the conversion value kept in the Rn Register. Unused bits
* in the Rn register are cleared in unsigned right justified modes and carry
* the sign bit (MSB) in sign extended 2's complement modes.
*
* @param instance ADC instance ID.
* @param group The group mux index.
*/
static inline uint32_t adc_hal_get_conversion_value(uint32_t instance,
uint32_t group)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
assert(group < HW_ADC_SC1n_COUNT);
return BR_ADC_Rn_D(instance, group);
}
/*!
* @brief Sets the current group mux that executes the conversion.
*
* ADC Mux select bit changes the ADC group setting to select between
* alternate sets of ADC channels. It will activate group A or group B.
*
* @param instance ADC instance ID.
* @param group The group mux index.
*/
static inline void adc_hal_set_group_mux(uint32_t instance, adc_group_mux_mode_t group)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
assert(group < HW_ADC_SC1n_COUNT);
BW_ADC_CFG2_MUXSEL(instance, (uint32_t)group);
}
#if FSL_FEATURE_ADC_HAS_PGA
/*!
* @brief Switches on/off to enable the ADC Programmable Gain Amplifier.
*
* The Programmable Gain Amplifier (PGA) is designed to increase the dynamic
* range by amplifying low-amplitude signals before they are fed to the 16-bit
* SAR ADC. The gain of this amplifier ranges between 1 to 64 in (2^N) steps.
*
* @param instance ADC instance ID.
* @param isEnabled The switcher.
*/
static inline void adc_hal_configure_pga(uint32_t instance, bool isEnabled)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_PGA_PGAEN(instance, (isEnabled ? 1U : 0U));
}
/*!
* @brief Switches on/off to enable the PGA chopping mode.
*
* The PGA employs chopping to remove/reduce offset and 1/f noise and offers an
* offset measurement configuration that aids the offset calibration.
*
* @param instance ADC instance ID.
* @param isEnabled The switcher.
*/
static inline void adc_hal_configure_pga_chopping(uint32_t instance,
bool isEnabled)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_PGA_PGACHPb(instance, (isEnabled ? 0U : 1U));
}
/*!
* @brief Switches on/off to enable the PGA in a low power mode.
*
* This function configures the PGA running in low power mode.
*
* @param instance ADC instance ID.
* @param isEnabled The switcher.
*/
static inline void adc_hal_configure_pga_in_low_power(uint32_t instance,
bool isEnabled)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_PGA_PGALPb(instance, (isEnabled ? 0U : 1U));
}
/*!
* @brief Switches on/off to enable the offset measurement mode.
*
* When this function is asserted, the PGA disconnects from the external
* inputs and auto-configures into offset measurement mode. With this function is
* asserted, run the ADC in recommended settings and enable maximum
* hardware averaging to get the PGA offset number. The output is
* (PGA offset * (64+1)) for a given PGA setting.
*
* @param instance ADC instance ID.
* @param isEnabled The switcher.
*/
static inline void adc_hal_configure_pga_offset_measurement(uint32_t instance,
bool isEnabled)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_PGA_PGAOFSM(instance, (isEnabled ? 0U : 1U));
}
/*!
* @brief Sets the selection of the PGA gain mode.
*
* The selection of the PGA gain mode can see to the type definition of the adc_pga_mode_t.
*
* @param instance ADC instance ID.
* @param mode The selection of gain.
*/
static inline void adc_hal_set_pga_gain_mode(uint32_t instance,
adc_pga_mode_t mode)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
BW_ADC_PGA_PGAG(instance, (uint32_t)(mode));
}
/*!
* @brief Gets the selection of the current PGA gain mode.
*
* This function returns the selection of the current PGA gain mode status.
*
* @param instance ADC instance ID.
* @return Current selection of gain mode.
*/
static inline adc_pga_mode_t adc_hal_get_pga_gain_mode(uint32_t instance)
{
assert(instance < HW_ADC_INSTANCE_COUNT);
return (adc_pga_mode_t)(BR_ADC_PGA_PGAG(instance));
}
#endif /* FSL_FEATURE_ADC_HAS_PGA */
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* __FSL_ADC_HAL_H__ */
/*******************************************************************************
* EOF
*******************************************************************************/

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__FSL_CAN_FEATURES_H__)
#define __FSL_CAN_FEATURES_H__
#if defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || \
defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VLQ12) || \
defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || \
defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || \
defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18)
/* @brief Message buffer size*/
#define FSL_FEATURE_CAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16)
/* @brief Has doze mode support (register bit field MCR[DOZE]).*/
#define FSL_FEATURE_CAN_HAS_DOZE_MODE_SUPPORT (0)
/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]).*/
#define FSL_FEATURE_CAN_HAS_GLITCH_FILTER (1)
/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2).*/
#define FSL_FEATURE_CAN_HAS_EXTENDED_FLAG_REGISTER (0)
/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]).*/
#define FSL_FEATURE_CAN_HAS_SEPARATE_BUFFER_0_FLAG (1)
#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
/* @brief Message buffer size*/
#define FSL_FEATURE_CAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16)
/* @brief Has doze mode support (register bit field MCR[DOZE]).*/
#define FSL_FEATURE_CAN_HAS_DOZE_MODE_SUPPORT (0)
/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]).*/
#define FSL_FEATURE_CAN_HAS_GLITCH_FILTER (0)
/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2).*/
#define FSL_FEATURE_CAN_HAS_EXTENDED_FLAG_REGISTER (1)
/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]).*/
#define FSL_FEATURE_CAN_HAS_SEPARATE_BUFFER_0_FLAG (0)
#else
#error "No valid CPU defined!"
#endif
#endif /* __FSL_CAN_FEATURES_H__*/
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __FSL_FLEXCAN_HAL_H__
#define __FSL_FLEXCAN_HAL_H__
#include <assert.h>
#include <stdint.h>
#include <stdbool.h>
#include "fsl_flexcan_features.h"
#include "fsl_device_registers.h"
/*!
* @addtogroup flexcan_hal
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief FlexCAN constants*/
enum _flexcan_constants
{
kFlexCanMessageSize = 8, /*!< FlexCAN message buffer data size in bytes*/
};
/*! @brief The Status enum is used to report current status of the FlexCAN interface.*/
enum _flexcan_err_status
{
kFlexCan_RxWrn = 0x0080, /*!< Reached warning level for RX errors*/
kFlexCan_TxWrn = 0x0100, /*!< Reached warning level for TX errors*/
kFlexCan_StfErr = 0x0200, /*!< Stuffing Error*/
kFlexCan_FrmErr = 0x0400, /*!< Form Error*/
kFlexCan_CrcErr = 0x0800, /*!< Cyclic Redundancy Check Error*/
kFlexCan_AckErr = 0x1000, /*!< Received no ACK on transmission*/
kFlexCan_Bit0Err = 0x2000, /*!< Unable to send dominant bit*/
kFlexCan_Bit1Err = 0x4000, /*!< Unable to send recessive bit*/
};
/*! @brief FlexCAN status return codes*/
typedef enum _flexcan_status
{
kStatus_FLEXCAN_Success = 0,
kStatus_FLEXCAN_OutOfRange,
kStatus_FLEXCAN_UnknownProperty,
kStatus_FLEXCAN_InvalidArgument,
kStatus_FLEXCAN_Fail,
kStatus_FLEXCAN_TimeOut,
} flexcan_status_t;
/*! @brief FlexCAN operation modes*/
typedef enum _flexcan_operation_modes {
kFlexCanNormalMode, /*!< Normal mode or user mode*/
kFlexCanListenOnlyMode, /*!< Listen-only mode*/
kFlexCanLoopBackMode, /*!< Loop-back mode*/
kFlexCanFreezeMode, /*!< Freeze mode*/
kFlexCanDisableMode, /*!< Module disable mode*/
} flexcan_operation_modes_t;
/*! @brief FlexCAN message buffer CODE for Rx buffers*/
typedef enum _flexcan_mb_code_rx {
kFlexCanRX_Inactive = 0x0, /*!< MB is not active.*/
kFlexCanRX_Full = 0x2, /*!< MB is full.*/
kFlexCanRX_Empty = 0x4, /*!< MB is active and empty.*/
kFlexCanRX_Overrun = 0x6, /*!< MB is overwritten into a full buffer.*/
kFlexCanRX_Busy = 0x8, /*!< FlexCAN is updating the contents of the MB.*/
/*! The CPU must not access the MB.*/
kFlexCanRX_Ranswer = 0xA, /*!< A frame was configured to recognize a Remote Request Frame*/
/*! and transmit a Response Frame in return.*/
kFlexCanRX_NotUsed = 0xF, /*!< Not used*/
} flexcan_mb_code_rx_t;
/*! @brief FlexCAN message buffer CODE FOR Tx buffers*/
typedef enum _flexcan_mb_code_tx {
kFlexCanTX_Inactive = 0x08, /*!< MB is not active.*/
kFlexCanTX_Abort = 0x09, /*!< MB is aborted.*/
kFlexCanTX_Data = 0x0C, /*!< MB is a TX Data Frame(MB RTR must be 0).*/
kFlexCanTX_Remote = 0x1C, /*!< MB is a TX Remote Request Frame (MB RTR must be 1).*/
kFlexCanTX_Tanswer = 0x0E, /*!< MB is a TX Response Request Frame from.*/
/*! an incoming Remote Request Frame.*/
kFlexCanTX_NotUsed = 0xF, /*!< Not used*/
} flexcan_mb_code_tx_t;
/*! @brief FlexCAN message buffer transmission types*/
typedef enum _flexcan_mb_transmission_type {
kFlexCanMBStatusType_TX, /*!< Transmit MB*/
kFlexCanMBStatusType_TXRemote, /*!< Transmit remote request MB*/
kFlexCanMBStatusType_RX, /*!< Receive MB*/
kFlexCanMBStatusType_RXRemote, /*!< Receive remote request MB*/
kFlexCanMBStatusType_RXTXRemote, /*!< FlexCAN remote frame receives remote request and*/
/*! transmits MB.*/
} flexcan_mb_transmission_type_t;
typedef enum _flexcan_rx_fifo_id_element_format {
kFlexCanRxFifoIdElementFormat_A, /*!< One full ID (standard and extended) per ID Filter Table*/
/*! element.*/
kFlexCanRxFifoIdElementFormat_B, /*!< Two full standard IDs or two partial 14-bit (standard and*/
/*! extended) IDs per ID Filter Table element.*/
kFlexCanRxFifoIdElementFormat_C, /*!< Four partial 8-bit Standard IDs per ID Filter Table*/
/*! element.*/
kFlexCanRxFifoIdElementFormat_D, /*!< All frames rejected.*/
} flexcan_rx_fifo_id_element_format_t;
/*! @brief FlexCAN Rx FIFO filters number*/
typedef enum _flexcan_rx_fifo_id_filter_number {
kFlexCanRxFifoIDFilters_8 = 0x0, /*!< 8 Rx FIFO Filters*/
kFlexCanRxFifoIDFilters_16 = 0x1, /*!< 16 Rx FIFO Filters*/
kFlexCanRxFifoIDFilters_24 = 0x2, /*!< 24 Rx FIFO Filters*/
kFlexCanRxFifoIDFilters_32 = 0x3, /*!< 32 Rx FIFO Filters*/
kFlexCanRxFifoIDFilters_40 = 0x4, /*!< 40 Rx FIFO Filters*/
kFlexCanRxFifoIDFilters_48 = 0x5, /*!< 48 Rx FIFO Filters*/
kFlexCanRxFifoIDFilters_56 = 0x6, /*!< 56 Rx FIFO Filters*/
kFlexCanRxFifoIDFilters_64 = 0x7, /*!< 64 Rx FIFO Filters*/
kFlexCanRxFifoIDFilters_72 = 0x8, /*!< 72 Rx FIFO Filters*/
kFlexCanRxFifoIDFilters_80 = 0x9, /*!< 80 Rx FIFO Filters*/
kFlexCanRxFifoIDFilters_88 = 0xA, /*!< 88 Rx FIFO Filters*/
kFlexCanRxFifoIDFilters_96 = 0xB, /*!< 96 Rx FIFO Filters*/
kFlexCanRxFifoIDFilters_104 = 0xC, /*!< 104 Rx FIFO Filters*/
kFlexCanRxFifoIDFilters_112 = 0xD, /*!< 112 Rx FIFO Filters*/
kFlexCanRxFifoIDFilters_120 = 0xE, /*!< 120 Rx FIFO Filters*/
kFlexCanRxFifoIDFilters_128 = 0xF /*!< 128 Rx FIFO Filters*/
} flexcan_rx_fifo_id_filter_num_t;
/*! @brief FlexCAN RX FIFO ID filter table structure*/
typedef struct FLEXCANIdTable {
bool is_remote_mb; /*!< Remote frame*/
bool is_extended_mb; /*!< Extended frame*/
uint32_t *id_filter; /*!< Rx FIFO ID filter elements*/
} flexcan_id_table_t;
/*! @brief FlexCAN RX mask type.*/
typedef enum _flexcan_rx_mask_type {
kFlexCanRxMask_Global, /*!< Rx global mask*/
kFlexCanRxMask_Individual, /*!< Rx individual mask*/
} flexcan_rx_mask_type_t;
/*! @brief FlexCAN MB ID type*/
typedef enum _flexcan_mb_id_type {
kFlexCanMbId_Std, /*!< Standard ID*/
kFlexCanMbId_Ext, /*!< Extended ID*/
} flexcan_mb_id_type_t;
/*! @brief FlexCAN clock source*/
typedef enum _flexcan_clk_source {
kFlexCanClkSource_Osc, /*!< Oscillator clock*/
kFlexCanClkSource_Ipbus, /*!< Peripheral clock*/
} flexcan_clk_source_t;
/*! @brief FlexCAN error interrupt types*/
typedef enum _flexcan_int_type {
kFlexCanInt_Buf, /*!< OR'd message buffers interrupt*/
kFlexCanInt_Err, /*!< Error interrupt*/
kFlexCanInt_Boff, /*!< Bus off interrupt*/
kFlexCanInt_Wakeup, /*!< Wakeup interrupt*/
kFlexCanInt_Txwarning, /*!< TX warning interrupt*/
kFlexCanInt_Rxwarning, /*!< RX warning interrupt*/
} flexcan_int_type_t;
/*! @brief FlexCAN bus error counters*/
typedef struct FLEXCANBerrCounter {
uint16_t txerr; /*!< Transmit error counter*/
uint16_t rxerr; /*!< Receive error counter*/
} flexcan_berr_counter_t;
/*! @brief FlexCAN MB code and status for transmitting*/
typedef struct FLEXCANMbCodeStatusTx {
flexcan_mb_code_tx_t code; /*!< MB code for Tx buffers*/
flexcan_mb_id_type_t msg_id_type; /*!< Type of message ID (standard or extended)*/
uint32_t data_length; /*!< Length of Data in Bytes*/
uint32_t substitute_remote; /*!< Substitute remote request (used only in*/
/*! extended format)*/
uint32_t remote_transmission; /*!< Remote transmission request*/
bool local_priority_enable; /*!< 1 if enable it; 0 if disable it*/
uint32_t local_priority_val; /*!< Local priority value [0..2]*/
} flexcan_mb_code_status_tx_t;
/*! @brief FlexCAN MB code and status for receiving*/
typedef struct FLEXCANMbCodeStatusRx {
flexcan_mb_code_rx_t code; /*!< MB code for Rx buffers*/
flexcan_mb_id_type_t msg_id_type; /*!< Type of message ID (standard or extended)*/
uint32_t data_length; /*!< Length of Data in Bytes*/
uint32_t substitute_remote; /*!< Substitute remote request (used only in*/
/*! extended format)*/
uint32_t remote_transmission; /*!< Remote transmission request*/
bool local_priority_enable; /*!< 1 if enable it; 0 if disable it*/
uint32_t local_priority_val; /*!< Local priority value [0..2]*/
} flexcan_mb_code_status_rx_t;
/*! @brief FlexCAN Rx FIFO configuration*/
typedef struct FLEXCANRxFifoConfig {
flexcan_mb_id_type_t msg_id_type; /*!< Type of message ID*/
/*! (standard or extended)*/
uint32_t data_length; /*!< Length of Data in Bytes*/
uint32_t substitute_remote; /*!< Substitute remote request (used*/
/*! only in extended format)*/
uint32_t remote_transmission; /*!< Remote transmission request*/
flexcan_rx_fifo_id_element_format_t id_filter_number; /*!< The number of Rx FIFO ID filters*/
} flexcan_rx_fifo_config_t;
/*! @brief FlexCAN message buffer structure*/
typedef struct FLEXCANMb {
uint32_t cs; /*!< Code and Status*/
uint32_t msg_id; /*!< Message Buffer ID*/
uint8_t data[kFlexCanMessageSize]; /*!< Bytes of the FlexCAN message*/
} flexcan_mb_t;
/*! @brief FlexCAN configuration*/
typedef struct FLEXCANUserConfig {
uint32_t num_mb; /*!< The number of Message Buffers needed*/
uint32_t max_num_mb; /*!< The maximum number of Message Buffers*/
flexcan_rx_fifo_id_filter_num_t num_id_filters; /*!< The number of Rx FIFO ID filters needed*/
bool is_rx_fifo_needed; /*!< 1 if needed; 0 if not*/
bool is_rx_mb_needed; /*!< 1 if needed; 0 if not*/
} flexcan_user_config_t;
/*! @brief FlexCAN timing related structures*/
typedef struct FLEXCANTimeSegment {
uint32_t propseg; /*!< Propagation segment*/
uint32_t pseg1; /*!< Phase segment 1*/
uint32_t pseg2; /*!< Phase segment 2*/
uint32_t pre_divider; /*!< Clock pre divider*/
uint32_t rjw; /*!< Resync jump width*/
} flexcan_time_segment_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name Configuration
* @{
*/
/*!
* @brief Enables FlexCAN controller.
*
* @param instance The FlexCAN instance number
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_enable(uint8_t instance);
/*!
* @brief Disables FlexCAN controller.
*
* @param instance The FlexCAN instance number
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_disable(uint8_t instance);
/*!
* @brief Checks whether the FlexCAN is enabled or disabled.
*
* @param instance The FlexCAN instance number
* @return State of FlexCAN enable(0)/disable(1)
*/
static inline bool flexcan_hal_is_enabled(uint8_t instance)
{
assert(instance < HW_CAN_INSTANCE_COUNT);
return BR_CAN_MCR_MDIS(instance);
}
/*!
* @brief Resets the FlexCAN controller.
*
* @param instance The FlexCAN instance number
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_sw_reset(uint8_t instance);
/*!
* @brief Selects the clock source for FlexCAN.
*
* @param instance The FlexCAN instance number
* @param clk The FlexCAN clock source
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_select_clk(uint8_t instance, flexcan_clk_source_t clk);
/*!
* @brief Initializes the FlexCAN controller.
*
* @param instance The FlexCAN instance number
* @param data The FlexCAN platform data.
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_init(uint8_t instance, const flexcan_user_config_t *data);
/*!
* @brief Sets the FlexCAN time segments for setting up bit rate.
*
* @param instance The FlexCAN instance number
* @param time_seg FlexCAN time segments, which need to be set for the bit rate.
* @return 0 if successful; non-zero failed
*/
void flexcan_hal_set_time_segments(uint8_t instance, flexcan_time_segment_t *time_seg);
/*!
* @brief Gets the FlexCAN time segments to calculate the bit rate.
*
* @param instance The FlexCAN instance number
* @param time_seg FlexCAN time segments read for bit rate
* @return 0 if successful; non-zero failed
*/
void flexcan_hal_get_time_segments(uint8_t instance, flexcan_time_segment_t *time_seg);
/*!
* @brief Un freezes the FlexCAN module.
*
* @param instance The FlexCAN instance number
* @return 0 if successful; non-zero failed.
*/
void flexcan_hal_exit_freeze_mode(uint8_t instance);
/*!
* @brief Freezes the FlexCAN module.
*
* @param instance The FlexCAN instance number
*/
void flexcan_hal_enter_freeze_mode(uint8_t instance);
/*!
* @brief Enables operation mode.
*
* @param instance The FlexCAN instance number
* @param mode An operation mode to be enabled
* @return 0 if successful; non-zero failed.
*/
flexcan_status_t flexcan_hal_enable_operation_mode(
uint8_t instance,
flexcan_operation_modes_t mode);
/*!
* @brief Disables operation mode.
*
* @param instance The FlexCAN instance number
* @param mode An operation mode to be disabled
* @return 0 if successful; non-zero failed.
*/
flexcan_status_t flexcan_hal_disable_operation_mode(
uint8_t instance,
flexcan_operation_modes_t mode);
/*@}*/
/*!
* @name Data transfer
* @{
*/
/*!
* @brief Sets the FlexCAN message buffer fields for transmitting.
*
* @param instance The FlexCAN instance number
* @param data The FlexCAN platform data
* @param mb_idx Index of the message buffer
* @param cs CODE/status values (TX)
* @param msg_id ID of the message to transmit
* @param mb_data Bytes of the FlexCAN message
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_set_mb_tx(
uint8_t instance,
const flexcan_user_config_t *data,
uint32_t mb_idx,
flexcan_mb_code_status_tx_t *cs,
uint32_t msg_id,
uint8_t *mb_data);
/*!
* @brief Set the FlexCAN message buffer fields for receiving.
*
* @param instance The FlexCAN instance number
* @param data The FlexCAN platform data
* @param mb_idx Index of the message buffer
* @param cs CODE/status values (RX)
* @param msg_id ID of the message to receive
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_set_mb_rx(
uint8_t instance,
const flexcan_user_config_t *data,
uint32_t mb_idx,
flexcan_mb_code_status_rx_t *cs,
uint32_t msg_id);
/*!
* @brief Gets the FlexCAN message buffer fields.
*
* @param instance The FlexCAN instance number
* @param data The FlexCAN platform data
* @param mb_idx Index of the message buffer
* @param mb The fields of the message buffer
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_get_mb(
uint8_t instance,
const flexcan_user_config_t *data,
uint32_t mb_idx,
flexcan_mb_t *mb);
/*!
* @brief Locks the FlexCAN Rx message buffer.
*
* @param instance The FlexCAN instance number
* @param data The FlexCAN platform data
* @param mb_idx Index of the message buffer
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_lock_rx_mb(
uint8_t instance,
const flexcan_user_config_t *data,
uint32_t mb_idx);
/*!
* @brief Unlocks the FlexCAN Rx message buffer.
*
* @param instance The FlexCAN instance number
* @return 0 if successful; non-zero failed
*/
static inline void flexcan_hal_unlock_rx_mb(uint8_t instance)
{
assert(instance < HW_CAN_INSTANCE_COUNT);
/* Unlock the mailbox */
HW_CAN_TIMER_RD(instance);
}
/*!
* @brief Enables the Rx FIFO.
*
* @param instance The FlexCAN instance number
*/
void flexcan_hal_enable_rx_fifo(uint8_t instance);
/*!
* @brief Disables the Rx FIFO.
*
* @param instance The FlexCAN instance number
*/
void flexcan_hal_disable_rx_fifo(uint8_t instance);
/*!
* @brief Sets the number of the Rx FIFO filters.
*
* @param instance The FlexCAN instance number
* @param number The number of Rx FIFO filters
*/
void flexcan_hal_set_rx_fifo_filters_number(uint8_t instance, uint32_t number);
/*!
* @brief Sets the maximum number of Message Buffers.
*
* @param instance The FlexCAN instance number
* @param data The FlexCAN platform data
*/
void flexcan_hal_set_max_mb_number(
uint8_t instance,
const flexcan_user_config_t *data);
/*!
* @brief Sets the Rx FIFO ID filter table elements.
*
* @param instance The FlexCAN instance number
* @param data The FlexCAN platform data
* @param id_format The format of the Rx FIFO ID Filter Table Elements
* @param id_filter_table The ID filter table elements which contain if RTR bit,
* IDE bit and RX message ID need to be set.
* @return 0 if successful; non-zero failed.
*/
flexcan_status_t flexcan_hal_set_id_filter_table_elements(
uint8_t instance,
const flexcan_user_config_t *data,
flexcan_rx_fifo_id_element_format_t id_format,
flexcan_id_table_t *id_filter_table);
/*!
* @brief Sets the FlexCAN Rx FIFO fields.
*
* @param instance The FlexCAN instance number
* @param data The FlexCAN platform data
* @param id_format The format of the Rx FIFO ID Filter Table Elements
* @param id_filter_table The ID filter table elements which contain RTR bit, IDE bit,
* and RX message ID.
* @return 0 if successful; non-zero failed.
*/
flexcan_status_t flexcan_hal_set_rx_fifo(
uint8_t instance,
const flexcan_user_config_t *data,
flexcan_rx_fifo_id_element_format_t id_format,
flexcan_id_table_t *id_filter_table);
/*!
* @brief Gets the FlexCAN Rx FIFO data.
*
* @param instance The FlexCAN instance number
* @param rx_fifo The FlexCAN receive FIFO data
* @return 0 if successful; non-zero failed.
*/
flexcan_status_t flexcan_hal_read_fifo(
uint8_t instance,
flexcan_mb_t *rx_fifo);
/*@}*/
/*!
* @name Interrupts
* @{
*/
/*!
* @brief Enables the FlexCAN Message Buffer interrupt.
*
* @param instance The FlexCAN instance number
* @param data The FlexCAN platform data
* @param mb_idx Index of the message buffer
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_enable_mb_interrupt(
uint8_t instance,
const flexcan_user_config_t *data,
uint32_t mb_idx);
/*!
* @brief Disables the FlexCAN Message Buffer interrupt.
*
* @param instance The FlexCAN instance number
* @param data The FlexCAN platform data
* @param mb_idx Index of the message buffer
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_disable_mb_interrupt(
uint8_t instance,
const flexcan_user_config_t *data,
uint32_t mb_idx);
/*!
* @brief Enables error interrupt of the FlexCAN module.
* @param instance The FlexCAN instance number
*/
void flexcan_hal_enable_error_interrupt(uint8_t instance);
/*!
* @brief Disables error interrupt of the FlexCAN module.
*
* @param instance The FlexCAN instance number
*/
void flexcan_hal_disable_error_interrupt(uint8_t instance);
/*!
* @brief Enables Bus off interrupt of the FlexCAN module.
*
* @param instance The FlexCAN instance number
*/
void flexcan_hal_enable_bus_off_interrupt(uint8_t instance);
/*!
* @brief Disables Bus off interrupt of the FlexCAN module.
*
* @param instance The FlexCAN instance number
*/
void flexcan_hal_disable_bus_off_interrupt(uint8_t instance);
/*!
* @brief Enables Wakeup interrupt of the FlexCAN module.
*
* @param instance The FlexCAN instance number
*/
void flexcan_hal_enable_wakeup_interrupt(uint8_t instance);
/*!
* @brief Disables Wakeup interrupt of the FlexCAN module.
*
* @param instance The FlexCAN instance number
*/
void flexcan_hal_disable_wakeup_interrupt(uint8_t instance);
/*!
* @brief Enables TX warning interrupt of the FlexCAN module
*
* @param instance The FlexCAN instance number
*/
void flexcan_hal_enable_tx_warning_interrupt(uint8_t instance);
/*!
* @brief Disables TX warning interrupt of the FlexCAN module.
*
* @param instance The FlexCAN instance number
*/
void flexcan_hal_disable_tx_warning_interrupt(uint8_t instance);
/*!
* @brief Enables RX warning interrupt of the FlexCAN module.
*
* @param instance The FlexCAN instance number
*/
void flexcan_hal_enable_rx_warning_interrupt(uint8_t instance);
/*!
* @brief Disables RX warning interrupt of the FlexCAN module.
*
* @param instance The FlexCAN instance number
*/
void flexcan_hal_disable_rx_warning_interrupt(uint8_t instance);
/*@}*/
/*!
* @name Status
* @{
*/
/*!
* @brief Gets the value of FlexCAN freeze ACK.
*
* @param instance The FlexCAN instance number
* @return freeze ACK state (1-freeze mode, 0-not in freeze mode).
*/
static inline uint32_t flexcan_hal_get_freeze_ack(uint8_t instance)
{
assert(instance < HW_CAN_INSTANCE_COUNT);
return HW_CAN_MCR(instance).B.FRZACK;
}
/*!
* @brief Gets the individual FlexCAN MB interrupt flag.
*
* @param instance The FlexCAN instance number
* @param data The FlexCAN platform data
* @param mb_idx Index of the message buffer
* @return the individual MB interrupt flag (0 and 1 are the flag value)
*/
uint8_t flexcan_hal_get_mb_int_flag(
uint8_t instance,
const flexcan_user_config_t *data,
uint32_t mb_idx);
/*!
* @brief Gets all FlexCAN MB interrupt flags.
*
* @param instance The FlexCAN instance number
* @return all MB interrupt flags
*/
static inline uint32_t flexcan_hal_get_all_mb_int_flags(uint8_t instance)
{
assert(instance < HW_CAN_INSTANCE_COUNT);
return HW_CAN_IFLAG1_RD(instance);
}
/*!
* @brief Clears the interrupt flag of the message buffers.
*
* @param instance The FlexCAN instance number
* @param reg_val The value to be written to the interrupt flag1 register.
*/
/* See fsl_flexcan_hal.h for documentation of this function.*/
static inline void flexcan_hal_clear_mb_int_flag(
uint8_t instance,
uint32_t reg_val)
{
assert(instance < HW_CAN_INSTANCE_COUNT);
/* Clear the corresponding message buffer interrupt flag*/
HW_CAN_IFLAG1_SET(instance, reg_val);
}
/*!
* @brief Gets the transmit error counter and receives the error counter.
*
* @param instance The FlexCAN instance number
* @param err_cnt Transmit error counter and receive error counter
*/
void flexcan_hal_get_err_counter(
uint8_t instance,
flexcan_berr_counter_t *err_cnt);
/*!
* @brief Gets error and status.
*
* @param instance The FlexCAN instance number
* @return The current error and status
*/
static inline uint32_t flexcan_hal_get_err_status(uint8_t instance)
{
assert(instance < HW_CAN_INSTANCE_COUNT);
return HW_CAN_ESR1_RD(instance);
}
/*!
* @brief Clears all other interrupts in ERRSTAT register (Error, Busoff, Wakeup).
*
* @param instance The FlexCAN instance number
*/
void flexcan_hal_clear_err_interrupt_status(uint8_t instance);
/*@}*/
/*!
* @name Mask
* @{
*/
/*!
* @brief Sets the Rx masking type.
*
* @param instance The FlexCAN instance number
* @param type The FlexCAN Rx mask type
*/
void flexcan_hal_set_mask_type(uint8_t instance, flexcan_rx_mask_type_t type);
/*!
* @brief Sets the FlexCAN RX FIFO global standard mask.
*
* @param instance The FlexCAN instance number
* @param std_mask Standard mask
*/
void flexcan_hal_set_rx_fifo_global_std_mask(
uint8_t instance,
uint32_t std_mask);
/*!
* @brief Sets the FlexCAN Rx FIFO global extended mask.
*
* @param instance The FlexCAN instance number
* @param ext_mask Extended mask
*/
void flexcan_hal_set_rx_fifo_global_ext_mask(
uint8_t instance,
uint32_t ext_mask);
/*!
* @brief Sets the FlexCAN Rx individual standard mask for ID filtering in the Rx MBs and the Rx FIFO.
*
* @param instance The FlexCAN instance number
* @param data The FlexCAN platform data
* @param mb_idx Index of the message buffer
* @param std_mask Individual standard mask
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_set_rx_individual_std_mask(
uint8_t instance,
const flexcan_user_config_t * data,
uint32_t mb_idx,
uint32_t std_mask);
/*!
* @brief Sets the FlexCAN Rx individual extended mask for ID filtering in the Rx MBs and the Rx FIFO.
*
* @param instance The FlexCAN instance number
* @param data The FlexCAN platform data
* @param mb_idx Index of the message buffer
* @param ext_mask Individual extended mask
* @return 0 if successful; non-zero failed
*/
flexcan_status_t flexcan_hal_set_rx_individual_ext_mask(
uint8_t instance,
const flexcan_user_config_t * data,
uint32_t mb_idx,
uint32_t ext_mask);
/*!
* @brief Sets the FlexCAN Rx MB global standard mask.
*
* @param instance The FlexCAN instance number
* @param std_mask Standard mask
*/
void flexcan_hal_set_rx_mb_global_std_mask(
uint8_t instance,
uint32_t std_mask);
/*!
* @brief Sets the FlexCAN RX MB BUF14 standard mask.
*
* @param instance The FlexCAN instance number
* @param std_mask Standard mask
*/
void flexcan_hal_set_rx_mb_buf14_std_mask(
uint8_t instance,
uint32_t std_mask);
/*!
* @brief Sets the FlexCAN Rx MB BUF15 standard mask.
*
* @param instance The FlexCAN instance number
* @param std_mask Standard mask
* @return 0 if successful; non-zero failed
*/
void flexcan_hal_set_rx_mb_buf15_std_mask(
uint8_t instance,
uint32_t std_mask);
/*!
* @brief Sets the FlexCAN RX MB global extended mask.
*
* @param instance The FlexCAN instance number
* @param ext_mask Extended mask
*/
void flexcan_hal_set_rx_mb_global_ext_mask(
uint8_t instance,
uint32_t ext_mask);
/*!
* @brief Sets the FlexCAN RX MB BUF14 extended mask.
*
* @param instance The FlexCAN instance number
* @param ext_mask Extended mask
*/
void flexcan_hal_set_rx_mb_buf14_ext_mask(
uint8_t instance,
uint32_t ext_mask);
/*!
* @brief Sets the FlexCAN RX MB BUF15 extended mask.
*
* @param instance The FlexCAN instance number
* @param ext_mask Extended mask
*/
void flexcan_hal_set_rx_mb_buf15_ext_mask(
uint8_t instance,
uint32_t ext_mask);
/*!
* @brief Gets the FlexCAN ID acceptance filter hit indicator on Rx FIFO.
*
* @param instance The FlexCAN instance number
* @return RX FIFO information
*/
static inline uint32_t flexcan_hal_get_rx_fifo_id_acceptance_filter(uint8_t instance)
{
assert(instance < HW_CAN_INSTANCE_COUNT);
return BR_CAN_RXFIR_IDHIT(instance);
}
/*@}*/
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* __FSL_FLEXCAN_HAL_H__*/
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__FSL_DMAMUX_FEATURES_H__)
#define __FSL_DMAMUX_FEATURES_H__
#if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \
defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || \
defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \
defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || \
defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || \
defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || \
defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
/* @brief Number of DMA channels (related to number of register CHCFGn).*/
#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4)
/* @brief Total number of DMA channels on all modules.*/
#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (HW_DMAMUX_INSTANCE_COUNT * 4)
#elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \
defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FN1M0VDC12) || \
defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VMD12) || \
defined(CPU_MK64FX512VMD12) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31FN512VLH12) || \
defined(CPU_MKV31F512VLL12) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \
defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || \
defined(CPU_MK70FX512VMJ15) || defined(CPU_MK70FN1M0VMJ12WS) || defined(CPU_MK70FX512VMJ12WS) || defined(CPU_MK70FN1M0VMJ15WS)
/* @brief Number of DMA channels (related to number of register CHCFGn).*/
#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16)
/* @brief Total number of DMA channels on all modules.*/
#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (HW_DMAMUX_INSTANCE_COUNT * 16)
#elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \
defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18)
/* @brief Number of DMA channels (related to number of register CHCFGn).*/
#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32)
/* @brief Total number of DMA channels on all modules.*/
#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (HW_DMAMUX_INSTANCE_COUNT * 32)
#else
#error "No valid CPU defined!"
#endif
#endif /* __FSL_DMAMUX_FEATURES_H__*/
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_dmamux_hal.h"
/*******************************************************************************
* Code
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : dmamux_hal_init
* Description : Initialize the dmamux module to the reset state.
*
*END**************************************************************************/
void dmamux_hal_init(uint8_t module)
{
assert(module < HW_DMAMUX_INSTANCE_COUNT);
int i;
for (i = 0; i < FSL_FEATURE_DMAMUX_MODULE_CHANNEL; i++)
{
BW_DMAMUX_CHCFGn_ENBL(module, i, 0U);
BW_DMAMUX_CHCFGn_SOURCE(module, i, 0U);
}
}
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __FSL_DMAMUX_HAL_H__
#define __FSL_DMAMUX_HAL_H__
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include "fsl_dmamux_features.h"
#include "fsl_device_registers.h"
/*!
* @addtogroup dmamux_hal
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*!
* @brief A constant for the length of the DMA hardware source. This structure is used inside
* the DMA driver.
*/
typedef enum _dmamux_source {
kDmamuxDmaRequestSource = 64U /*!< Maximum number of the DMA requests allowed for the DMA mux. */
} dmamux_dma_request_source;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name DMAMUX HAL function
* @{
*/
/*!
* @brief Initializes the DMAMUX module to the reset state.
*
* Initializes the DMAMUX module to the reset state.
*
* @param module DMAMUX module index
*/
void dmamux_hal_init(uint8_t module);
/*!
* @brief Enables the DMAMUX channel.
*
* Enables the hardware request. If enabled, the hardware request is sent to
* the corresponding DMA channel.
*
* @param module DMAMUX module.
* @param channel DMAMUX channel.
*/
static inline void dmamux_hal_enable_channel(uint8_t module, uint8_t channel)
{
assert(module < HW_DMAMUX_INSTANCE_COUNT);
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
BW_DMAMUX_CHCFGn_ENBL(module, channel, 1U);
}
/*!
* @brief Disables the DMAMUX channel.
*
* Disable hardware request. If disabled, the hardware request is not sent to
* the corresponding DMA channel.
*
* @param module DMAMUX module.
* @param channel DMAMUX channel.
*/
static inline void dmamux_hal_disable_channel(uint8_t module, uint8_t channel)
{
assert(module < HW_DMAMUX_INSTANCE_COUNT);
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
BW_DMAMUX_CHCFGn_ENBL(module, channel, 0U);
}
/*!
* @brief Enables the period trigger.
*
* @param module DMAMUX module.
* @param channel DMAMUX channel.
*/
static inline void dmamux_hal_enable_period_trigger(uint8_t module, uint8_t channel)
{
assert(module < HW_DMAMUX_INSTANCE_COUNT);
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
BW_DMAMUX_CHCFGn_TRIG(module, channel, 1U);
}
/*!
* @brief Disables the period trigger.
*
* @param module DMAMUX module.
* @param channel DMAMUX channel.
*/
static inline void dmamux_hal_disable_period_trigger(uint8_t module, uint8_t channel)
{
assert(module < HW_DMAMUX_INSTANCE_COUNT);
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
BW_DMAMUX_CHCFGn_TRIG(module, channel, 0U);
}
/*!
* @brief Configures the DMA request for the DMAMUX channel.
*
* Sets the trigger source for the DMA channel. The trigger source is in the file
* fsl_dma_request.h.
*
* @param module DMAMUX module.
* @param channel DMAMUX channel.
* @param source DMA request source.
*/
static inline void dmamux_hal_set_trigger_source(uint8_t module, uint8_t channel, uint8_t source)
{
assert(module < HW_DMAMUX_INSTANCE_COUNT);
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
BW_DMAMUX_CHCFGn_SOURCE(module, channel, source);
}
/* @} */
#if defined(__cplusplus)
}
#endif
/*! @} */
#endif /* __FSL_DMAMUX_HAL_H__ */
/*******************************************************************************
* EOF
******************************************************************************/

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@ -0,0 +1,365 @@
/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__FSL_DSPI_FEATURES_H__)
#define __FSL_DSPI_FEATURES_H__
#if defined(CPU_MK10DN512VLK10) || defined(CPU_MK10DN512VMB10) || defined(CPU_MK10DX128VMP5) || defined(CPU_MK10DN128VMP5) || \
defined(CPU_MK10DX64VMP5) || defined(CPU_MK10DN64VMP5) || defined(CPU_MK10DX32VMP5) || defined(CPU_MK10DN32VMP5) || \
defined(CPU_MK10DX128VLH5) || defined(CPU_MK10DN128VLH5) || defined(CPU_MK10DX64VLH5) || defined(CPU_MK10DN64VLH5) || \
defined(CPU_MK10DX32VLH5) || defined(CPU_MK10DN32VLH5) || defined(CPU_MK10DX128VFT5) || defined(CPU_MK10DN128VFT5) || \
defined(CPU_MK10DX64VFT5) || defined(CPU_MK10DN64VFT5) || defined(CPU_MK10DX32VFT5) || defined(CPU_MK10DN32VFT5) || \
defined(CPU_MK10DX128VLF5) || defined(CPU_MK10DN128VLF5) || defined(CPU_MK10DX64VLF5) || defined(CPU_MK10DN64VLF5) || \
defined(CPU_MK10DX32VLF5) || defined(CPU_MK10DN32VLF5) || defined(CPU_MK10DX64VLH7) || defined(CPU_MK10DX128VLH7) || \
defined(CPU_MK10DX256VLH7) || defined(CPU_MK10DX64VLK7) || defined(CPU_MK10DX128VLK7) || defined(CPU_MK10DX256VLK7) || \
defined(CPU_MK10DX64VMB7) || defined(CPU_MK10DX128VMB7) || defined(CPU_MK10DX256VMB7) || defined(CPU_MK10DN512ZVLK10) || \
defined(CPU_MK10DN512ZVMB10) || defined(CPU_MK20DN512VLK10) || defined(CPU_MK20DN512VMB10) || defined(CPU_MK20DX128VMP5) || \
defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || \
defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || \
defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFT5) || \
defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || \
defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || \
defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK20DX64VLH7) || \
defined(CPU_MK20DX128VLH7) || defined(CPU_MK20DX256VLH7) || defined(CPU_MK20DX64VLK7) || defined(CPU_MK20DX128VLK7) || \
defined(CPU_MK20DX256VLK7) || defined(CPU_MK20DX64VMB7) || defined(CPU_MK20DX128VMB7) || defined(CPU_MK20DX256VMB7) || \
defined(CPU_MK20DN512ZVLK10) || defined(CPU_MK20DX256ZVLK10) || defined(CPU_MK20DN512ZVMB10) || defined(CPU_MK20DX256ZVMB10) || \
defined(CPU_MK22FX512VLH12) || defined(CPU_MK22FN1M0VLH12) || defined(CPU_MK22FX512VLK12) || defined(CPU_MK22FN1M0VLK12) || \
defined(CPU_MK30DN512VLK10) || defined(CPU_MK30DN512VMB10) || defined(CPU_MK30DX64VLH7) || defined(CPU_MK30DX128VLH7) || \
defined(CPU_MK30DX256VLH7) || defined(CPU_MK30DX64VLK7) || defined(CPU_MK30DX128VLK7) || defined(CPU_MK30DX256VLK7) || \
defined(CPU_MK30DX64VMB7) || defined(CPU_MK30DX128VMB7) || defined(CPU_MK30DX256VMB7) || defined(CPU_MK30DN512ZVLK10) || \
defined(CPU_MK30DN512ZVMB10) || defined(CPU_MK40DN512VLK10) || defined(CPU_MK40DN512VMB10) || defined(CPU_MK40DX64VLH7) || \
defined(CPU_MK40DX128VLH7) || defined(CPU_MK40DX256VLH7) || defined(CPU_MK40DX64VLK7) || defined(CPU_MK40DX128VLK7) || \
defined(CPU_MK40DX256VLK7) || defined(CPU_MK40DX64VMB7) || defined(CPU_MK40DX128VMB7) || defined(CPU_MK40DX256VMB7) || \
defined(CPU_MK40DN512ZVLK10) || defined(CPU_MK40DN512ZVMB10) || defined(CPU_MK50DX128CLH7) || defined(CPU_MK50DX256CLK10) || \
defined(CPU_MK50DX128CLK7) || defined(CPU_MK50DX256CLK7) || defined(CPU_MK50DX256CMB10) || defined(CPU_MK50DX128CMB7) || \
defined(CPU_MK50DX256CMB7) || defined(CPU_MK50DX256ZCLK10) || defined(CPU_MK50DX256ZCMB10) || defined(CPU_MK51DX128CLH7) || \
defined(CPU_MK51DX256CLK10) || defined(CPU_MK51DX128CLK7) || defined(CPU_MK51DX256CLK7) || defined(CPU_MK51DX256CMB10) || \
defined(CPU_MK51DX128CMB7) || defined(CPU_MK51DX256CMB7) || defined(CPU_MK51DX256ZCLK10) || defined(CPU_MK51DX256ZCMB10)
/* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
#define FSL_FEATURE_SPI_IS_DSPI (1)
/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
/* @brief Receive/transmit FIFO size in number of items.*/
#define FSL_FEATURE_SPI_FIFO_SIZE (4)
/* @brief Maximum transfer data width in bits.*/
#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
#define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (6)
/* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_CHIP_SELECT_COUNTn(x) \
((x) == 0 ? (5) : \
((x) == 1 ? (3) : (-1)))
/* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (1)
/* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0)
/* @brief Has 16-bit data transfer support.*/
#define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1)
#elif defined(CPU_MK10DN512VLL10) || defined(CPU_MK10DX128VLQ10) || defined(CPU_MK10DX256VLQ10) || defined(CPU_MK10DN512VLQ10) || \
defined(CPU_MK10DN512VMC10) || defined(CPU_MK10DX128VMD10) || defined(CPU_MK10DX256VMD10) || defined(CPU_MK10DN512VMD10) || \
defined(CPU_MK10DX128VLL7) || defined(CPU_MK10DX256VLL7) || defined(CPU_MK10DX128VML7) || defined(CPU_MK10DX256VML7) || \
defined(CPU_MK10FN1M0VLQ12) || defined(CPU_MK10FX512VLQ12) || defined(CPU_MK10FN1M0VMD12) || defined(CPU_MK10FX512VMD12) || \
defined(CPU_MK10DN512ZVLL10) || defined(CPU_MK10DN512ZVLQ10) || defined(CPU_MK10DX256ZVLQ10) || defined(CPU_MK10DX128ZVLQ10) || \
defined(CPU_MK10DN512ZVMC10) || defined(CPU_MK10DN512ZVMD10) || defined(CPU_MK10DX256ZVMD10) || defined(CPU_MK10DX128ZVMD10) || \
defined(CPU_MK20DN512VLL10) || defined(CPU_MK20DX128VLQ10) || defined(CPU_MK20DX256VLQ10) || defined(CPU_MK20DN512VLQ10) || \
defined(CPU_MK20DX256VMC10) || defined(CPU_MK20DN512VMC10) || defined(CPU_MK20DX128VMD10) || defined(CPU_MK20DX256VMD10) || \
defined(CPU_MK20DN512VMD10) || defined(CPU_MK20DX128VLL7) || defined(CPU_MK20DX256VLL7) || defined(CPU_MK20DX128VML7) || \
defined(CPU_MK20DX256VML7) || defined(CPU_MK20FN1M0VLQ12) || defined(CPU_MK20FX512VLQ12) || defined(CPU_MK20FN1M0VMD12) || \
defined(CPU_MK20FX512VMD12) || defined(CPU_MK20DN512ZVLL10) || defined(CPU_MK20DX256ZVLL10) || defined(CPU_MK20DN512ZVLQ10) || \
defined(CPU_MK20DX256ZVLQ10) || defined(CPU_MK20DX128ZVLQ10) || defined(CPU_MK20DN512ZVMC10) || defined(CPU_MK20DX256ZVMC10) || \
defined(CPU_MK20DN512ZVMD10) || defined(CPU_MK20DX256ZVMD10) || defined(CPU_MK20DX128ZVMD10) || defined(CPU_MK21FX512VLQ12) || \
defined(CPU_MK21FN1M0VLQ12) || defined(CPU_MK21FX512VLQ12WS) || defined(CPU_MK21FN1M0VLQ12WS) || defined(CPU_MK21FX512VMC12) || \
defined(CPU_MK21FN1M0VMC12) || defined(CPU_MK21FX512VMC12WS) || defined(CPU_MK21FN1M0VMC12WS) || defined(CPU_MK21FX512VMD12) || \
defined(CPU_MK21FN1M0VMD12) || defined(CPU_MK21FX512VMD12WS) || defined(CPU_MK21FN1M0VMD12WS) || defined(CPU_MK22FX512VLL12) || \
defined(CPU_MK22FN1M0VLL12) || defined(CPU_MK22FX512VLQ12) || defined(CPU_MK22FN1M0VLQ12) || defined(CPU_MK22FX512VMC12) || \
defined(CPU_MK22FN1M0VMC12) || defined(CPU_MK22FX512VMD12) || defined(CPU_MK22FN1M0VMD12) || defined(CPU_MK30DN512VLL10) || \
defined(CPU_MK30DX128VLQ10) || defined(CPU_MK30DX256VLQ10) || defined(CPU_MK30DN512VLQ10) || defined(CPU_MK30DN512VMC10) || \
defined(CPU_MK30DX128VMD10) || defined(CPU_MK30DX256VMD10) || defined(CPU_MK30DN512VMD10) || defined(CPU_MK30DX128VLL7) || \
defined(CPU_MK30DX256VLL7) || defined(CPU_MK30DX128VML7) || defined(CPU_MK30DX256VML7) || defined(CPU_MK30DN512ZVLL10) || \
defined(CPU_MK30DN512ZVLQ10) || defined(CPU_MK30DX256ZVLQ10) || defined(CPU_MK30DX128ZVLQ10) || defined(CPU_MK30DN512ZVMC10) || \
defined(CPU_MK30DN512ZVMD10) || defined(CPU_MK30DX256ZVMD10) || defined(CPU_MK30DX128ZVMD10) || defined(CPU_MK40DN512VLL10) || \
defined(CPU_MK40DX128VLQ10) || defined(CPU_MK40DX256VLQ10) || defined(CPU_MK40DN512VLQ10) || defined(CPU_MK40DN512VMC10) || \
defined(CPU_MK40DX128VMD10) || defined(CPU_MK40DX256VMD10) || defined(CPU_MK40DN512VMD10) || defined(CPU_MK40DX128VLL7) || \
defined(CPU_MK40DX256VLL7) || defined(CPU_MK40DX128VML7) || defined(CPU_MK40DX256VML7) || defined(CPU_MK40DN512ZVLL10) || \
defined(CPU_MK40DN512ZVLQ10) || defined(CPU_MK40DX256ZVLQ10) || defined(CPU_MK40DX128ZVLQ10) || defined(CPU_MK40DN512ZVMC10) || \
defined(CPU_MK40DN512ZVMD10) || defined(CPU_MK40DX256ZVMD10) || defined(CPU_MK40DX128ZVMD10) || defined(CPU_MK50DX256CLL10) || \
defined(CPU_MK50DN512CLL10) || defined(CPU_MK50DN512CLQ10) || defined(CPU_MK50DX256CMC10) || defined(CPU_MK50DN512CMC10) || \
defined(CPU_MK50DN512CMD10) || defined(CPU_MK50DX256CMD10) || defined(CPU_MK50DX256CLL7) || defined(CPU_MK50DX256CML7) || \
defined(CPU_MK50DN512ZCLL10) || defined(CPU_MK50DX256ZCLL10) || defined(CPU_MK50DN512ZCLQ10) || defined(CPU_MK50DN512ZCMC10) || \
defined(CPU_MK50DX256ZCMC10) || defined(CPU_MK50DN512ZCMD10) || defined(CPU_MK51DX256CLL10) || defined(CPU_MK51DN512CLL10) || \
defined(CPU_MK51DN256CLQ10) || defined(CPU_MK51DN512CLQ10) || defined(CPU_MK51DX256CMC10) || defined(CPU_MK51DN512CMC10) || \
defined(CPU_MK51DN256CMD10) || defined(CPU_MK51DN512CMD10) || defined(CPU_MK51DX256CLL7) || defined(CPU_MK51DX256CML7) || \
defined(CPU_MK51DN512ZCLL10) || defined(CPU_MK51DX256ZCLL10) || defined(CPU_MK51DN512ZCLQ10) || defined(CPU_MK51DN256ZCLQ10) || \
defined(CPU_MK51DN512ZCMC10) || defined(CPU_MK51DX256ZCMC10) || defined(CPU_MK51DN512ZCMD10) || defined(CPU_MK51DN256ZCMD10) || \
defined(CPU_MK52DN512CLQ10) || defined(CPU_MK52DN512CMD10) || defined(CPU_MK52DN512ZCLQ10) || defined(CPU_MK52DN512ZCMD10) || \
defined(CPU_MK53DN512CLQ10) || defined(CPU_MK53DX256CLQ10) || defined(CPU_MK53DN512CMD10) || defined(CPU_MK53DX256CMD10) || \
defined(CPU_MK53DN512ZCLQ10) || defined(CPU_MK53DX256ZCLQ10) || defined(CPU_MK53DN512ZCMD10) || defined(CPU_MK53DX256ZCMD10) || \
defined(CPU_MK60DN256VLL10) || defined(CPU_MK60DX256VLL10) || defined(CPU_MK60DN512VLL10) || defined(CPU_MK60DN256VLQ10) || \
defined(CPU_MK60DX256VLQ10) || defined(CPU_MK60DN512VLQ10) || defined(CPU_MK60DN256VMC10) || defined(CPU_MK60DX256VMC10) || \
defined(CPU_MK60DN512VMC10) || defined(CPU_MK60DN256VMD10) || defined(CPU_MK60DX256VMD10) || defined(CPU_MK60DN512VMD10) || \
defined(CPU_MK60FN1M0VLQ12) || defined(CPU_MK60FX512VLQ12) || defined(CPU_MK60FN1M0VLQ15) || defined(CPU_MK60FX512VLQ15) || \
defined(CPU_MK60FN1M0VMD12) || defined(CPU_MK60FX512VMD12) || defined(CPU_MK60FN1M0VMD15) || defined(CPU_MK60FX512VMD15) || \
defined(CPU_MK60DN512ZVLL10) || defined(CPU_MK60DX256ZVLL10) || defined(CPU_MK60DN256ZVLL10) || defined(CPU_MK60DN512ZVLQ10) || \
defined(CPU_MK60DX256ZVLQ10) || defined(CPU_MK60DN256ZVLQ10) || defined(CPU_MK60DN512ZVMC10) || defined(CPU_MK60DX256ZVMC10) || \
defined(CPU_MK60DN256ZVMC10) || defined(CPU_MK60DN512ZVMD10) || defined(CPU_MK60DX256ZVMD10) || defined(CPU_MK60DN256ZVMD10) || \
defined(CPU_MK61FN1M0VMD12) || defined(CPU_MK61FX512VMD12) || defined(CPU_MK61FN1M0VMD15) || defined(CPU_MK61FX512VMD15) || \
defined(CPU_MK61FN1M0VMD12WS) || defined(CPU_MK61FX512VMD12WS) || defined(CPU_MK61FN1M0VMD15WS) || defined(CPU_MK61FX512VMD15WS) || \
defined(CPU_MK61FN1M0VMF12) || defined(CPU_MK61FX512VMF12) || defined(CPU_MK61FN1M0VMF15) || defined(CPU_MK61FX512VMF15) || \
defined(CPU_MK61FN1M0VMJ12) || defined(CPU_MK61FX512VMJ12) || defined(CPU_MK61FN1M0VMJ15) || defined(CPU_MK61FX512VMJ15) || \
defined(CPU_MK61FN1M0VMJ12WS) || defined(CPU_MK61FX512VMJ12WS) || defined(CPU_MK61FN1M0VMJ15WS) || defined(CPU_MK61FX512VMJ15WS) || \
defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK63FN1M0VMD12WS) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12) || \
defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) || \
defined(CPU_MK70FN1M0VMJ12WS) || defined(CPU_MK70FX512VMJ12WS) || defined(CPU_MK70FN1M0VMJ15WS) || defined(CPU_MK70FX512VMJ15WS)
/* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
#define FSL_FEATURE_SPI_IS_DSPI (1)
/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
/* @brief Receive/transmit FIFO size in number of items.*/
#if defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12)
#define FSL_FEATURE_SPI_FIFO_SIZEn(x) \
((x) == 0 ? (4) : \
((x) == 1 ? (1) : \
((x) == 2 ? (1) : (-1))))
#else
#define FSL_FEATURE_SPI_FIFO_SIZEn(x) \
((x) == 0 ? (4) : \
((x) == 1 ? (4) : \
((x) == 2 ? (4) : (-1))))
#endif
/* @brief Maximum transfer data width in bits.*/
#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
#define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (6)
/* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_CHIP_SELECT_COUNTn(x) \
((x) == 0 ? (6) : \
((x) == 1 ? (4) : \
((x) == 2 ? (1) : (-1))))
/* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (1)
/* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0)
/* @brief Has 16-bit data transfer support.*/
#define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1)
#elif defined(CPU_MK10DX128VFM5) || defined(CPU_MK10DN128VFM5) || defined(CPU_MK10DX64VFM5) || defined(CPU_MK10DN64VFM5) || \
defined(CPU_MK10DX32VFM5) || defined(CPU_MK10DN32VFM5) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \
defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5)
/* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
#define FSL_FEATURE_SPI_IS_DSPI (1)
/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
/* @brief Receive/transmit FIFO size in number of items.*/
#define FSL_FEATURE_SPI_FIFO_SIZE (4)
/* @brief Maximum transfer data width in bits.*/
#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
#define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (6)
/* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_CHIP_SELECT_COUNT (4)
/* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (1)
/* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0)
/* @brief Has 16-bit data transfer support.*/
#define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1)
#elif defined(CPU_MK11DX128VLK5) || defined(CPU_MK11DX256VLK5) || defined(CPU_MK11DN512VLK5) || defined(CPU_MK11DX128VLK5WS) || \
defined(CPU_MK11DX256VLK5WS) || defined(CPU_MK11DN512VLK5WS) || defined(CPU_MK11DX128VMC5) || defined(CPU_MK11DX256VMC5) || \
defined(CPU_MK11DN512VMC5) || defined(CPU_MK11DX128VMC5WS) || defined(CPU_MK11DX256VMC5WS) || defined(CPU_MK11DN512VMC5WS) || \
defined(CPU_MK12DX128VLH5) || defined(CPU_MK12DX256VLH5) || defined(CPU_MK12DN512VLH5) || defined(CPU_MK12DX128VLK5) || \
defined(CPU_MK12DX256VLK5) || defined(CPU_MK12DN512VLK5) || defined(CPU_MK12DX128VMC5) || defined(CPU_MK12DX256VMC5) || \
defined(CPU_MK12DN512VMC5) || defined(CPU_MK12DX128VLF5) || defined(CPU_MK12DX256VLF5) || defined(CPU_MK21DX128VLK5) || \
defined(CPU_MK21DX256VLK5) || defined(CPU_MK21DN512VLK5) || defined(CPU_MK21DX128VLK5WS) || defined(CPU_MK21DX256VLK5WS) || \
defined(CPU_MK21DN512VLK5WS) || defined(CPU_MK21DX128VMC5) || defined(CPU_MK21DX256VMC5) || defined(CPU_MK21DN512VMC5) || \
defined(CPU_MK21DX128VMC5WS) || defined(CPU_MK21DX256VMC5WS) || defined(CPU_MK21DN512VMC5WS) || defined(CPU_MK22DX128VLH5) || \
defined(CPU_MK22DX256VLH5) || defined(CPU_MK22DN512VLH5) || defined(CPU_MK22DX128VLK5) || defined(CPU_MK22DX256VLK5) || \
defined(CPU_MK22DN512VLK5) || defined(CPU_MK22DX128VMC5) || defined(CPU_MK22DX256VMC5) || defined(CPU_MK22DN512VMC5) || \
defined(CPU_MK22DX128VLF5) || defined(CPU_MK22DX256VLF5)
/* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
#define FSL_FEATURE_SPI_IS_DSPI (1)
/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
/* @brief Receive/transmit FIFO size in number of items.*/
#define FSL_FEATURE_SPI_FIFO_SIZE (4)
/* @brief Maximum transfer data width in bits.*/
#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
#define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (5)
/* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_CHIP_SELECT_COUNTn(x) \
((x) == 0 ? (5) : \
((x) == 1 ? (3) : (-1)))
/* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (0)
/* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0)
/* @brief Has 16-bit data transfer support.*/
#define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1)
#elif defined(CPU_MK22FN512VDC12)
/* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
#define FSL_FEATURE_SPI_IS_DSPI (1)
/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
/* @brief Receive/transmit FIFO size in number of items.*/
#define FSL_FEATURE_SPI_FIFO_SIZEn(x) \
((x) == 0 ? (4) : \
((x) == 1 ? (1) : (-1)))
/* @brief Maximum transfer data width in bits.*/
#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
#define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (6)
/* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_CHIP_SELECT_COUNT (0)
/* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (1)
/* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0)
/* @brief Has 16-bit data transfer support.*/
#define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1)
#elif defined(CPU_MK22FN512VDC12)
/* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
#define FSL_FEATURE_SPI_IS_DSPI (1)
/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
/* @brief Receive/transmit FIFO size in number of items.*/
#define FSL_FEATURE_SPI_FIFO_SIZEn(x) \
((x) == 0 ? (4) : \
((x) == 1 ? (1) : (-1)))
/* @brief Maximum transfer data width in bits.*/
#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
#define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (6)
/* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_CHIP_SELECT_COUNTn(x) \
((x) == 0 ? (5) : \
((x) == 1 ? (3) : (-1)))
/* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (1)
/* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0)
/* @brief Has 16-bit data transfer support.*/
#define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1)
#elif defined(CPU_MKE02Z64VLC2) || defined(CPU_MKE02Z32VLC2) || defined(CPU_MKE02Z16VLC2) || defined(CPU_MKE02Z64VLD2) || \
defined(CPU_MKE02Z32VLD2) || defined(CPU_MKE02Z16VLD2) || defined(CPU_MKE02Z64VLH2) || defined(CPU_MKE02Z64VQH2) || \
defined(CPU_MKE02Z32VLH2) || defined(CPU_MKE02Z32VQH2) || defined(CPU_MKE04Z8VFK4) || defined(CPU_MKE04Z8VTG4) || \
defined(CPU_MKE04Z8VWJ4) || defined(CPU_MKL02Z32CAF4) || defined(CPU_MKL02Z8VFG4) || defined(CPU_MKL02Z16VFG4) || \
defined(CPU_MKL02Z32VFG4) || defined(CPU_MKL02Z16VFK4) || defined(CPU_MKL02Z32VFK4) || defined(CPU_MKL02Z16VFM4) || \
defined(CPU_MKL02Z32VFM4)
/* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
#define FSL_FEATURE_SPI_IS_DSPI (0)
/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (0)
/* @brief Receive/transmit FIFO size in number of items.*/
#define FSL_FEATURE_SPI_FIFO_SIZE (1)
/* @brief Maximum transfer data width in bits.*/
#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (8)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
#define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (1)
/* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_CHIP_SELECT_COUNT (0)
/* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (0)
/* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1)
/* @brief Has 16-bit data transfer support.*/
#define FSL_FEATURE_SPI_16BIT_TRANSFERS (0)
#elif defined(CPU_MKL04Z8VFK4) || defined(CPU_MKL04Z16VFK4) || defined(CPU_MKL04Z32VFK4) || defined(CPU_MKL04Z8VLC4) || \
defined(CPU_MKL04Z16VLC4) || defined(CPU_MKL04Z32VLC4) || defined(CPU_MKL04Z8VFM4) || defined(CPU_MKL04Z16VFM4) || \
defined(CPU_MKL04Z32VFM4) || defined(CPU_MKL04Z16VLF4) || defined(CPU_MKL04Z32VLF4) || defined(CPU_MKL05Z8VFK4) || \
defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || \
defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \
defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL14Z32VFM4) || defined(CPU_MKL14Z64VFM4) || \
defined(CPU_MKL14Z32VFT4) || defined(CPU_MKL14Z64VFT4) || defined(CPU_MKL14Z32VLH4) || defined(CPU_MKL14Z64VLH4) || \
defined(CPU_MKL14Z32VLK4) || defined(CPU_MKL14Z64VLK4) || defined(CPU_MKL15Z32VFM4) || defined(CPU_MKL15Z64VFM4) || \
defined(CPU_MKL15Z128VFM4) || defined(CPU_MKL15Z32VFT4) || defined(CPU_MKL15Z64VFT4) || defined(CPU_MKL15Z128VFT4) || \
defined(CPU_MKL15Z32VLH4) || defined(CPU_MKL15Z64VLH4) || defined(CPU_MKL15Z128VLH4) || defined(CPU_MKL15Z32VLK4) || \
defined(CPU_MKL15Z64VLK4) || defined(CPU_MKL15Z128VLK4) || defined(CPU_MKL24Z32VFM4) || defined(CPU_MKL24Z64VFM4) || \
defined(CPU_MKL24Z32VFT4) || defined(CPU_MKL24Z64VFT4) || defined(CPU_MKL24Z32VLH4) || defined(CPU_MKL24Z64VLH4) || \
defined(CPU_MKL24Z32VLK4) || defined(CPU_MKL24Z64VLK4) || defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || \
defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \
defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || \
defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4)
/* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
#define FSL_FEATURE_SPI_IS_DSPI (0)
/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
/* @brief Receive/transmit FIFO size in number of items.*/
#define FSL_FEATURE_SPI_FIFO_SIZE (1)
/* @brief Maximum transfer data width in bits.*/
#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (8)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
#define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (1)
/* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_CHIP_SELECT_COUNT (0)
/* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (0)
/* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1)
/* @brief Has 16-bit data transfer support.*/
#define FSL_FEATURE_SPI_16BIT_TRANSFERS (0)
#elif defined(CPU_MKL16Z32VFM4) || defined(CPU_MKL16Z64VFM4) || defined(CPU_MKL16Z128VFM4) || defined(CPU_MKL16Z32VFT4) || \
defined(CPU_MKL16Z64VFT4) || defined(CPU_MKL16Z128VFT4) || defined(CPU_MKL16Z32VLH4) || defined(CPU_MKL16Z64VLH4) || \
defined(CPU_MKL16Z128VLH4) || defined(CPU_MKL16Z256VLH4) || defined(CPU_MKL16Z256VLK4) || defined(CPU_MKL26Z32VFM4) || \
defined(CPU_MKL26Z64VFM4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || \
defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || defined(CPU_MKL26Z128VLH4) || \
defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || \
defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL34Z64VLH4) || defined(CPU_MKL34Z64VLL4) || \
defined(CPU_MKL36Z64VLH4) || defined(CPU_MKL36Z128VLH4) || defined(CPU_MKL36Z256VLH4) || defined(CPU_MKL36Z64VLL4) || \
defined(CPU_MKL36Z128VLL4) || defined(CPU_MKL36Z256VLL4) || defined(CPU_MKL36Z128VMC4) || defined(CPU_MKL36Z256VMC4) || \
defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || \
defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
/* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
#define FSL_FEATURE_SPI_IS_DSPI (0)
/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
/* @brief Receive/transmit FIFO size in number of items.*/
#define FSL_FEATURE_SPI_FIFO_SIZEn(x) \
((x) == 0 ? (1) : \
((x) == 1 ? (8) : (-1)))
/* @brief Maximum transfer data width in bits.*/
#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
#define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (1)
/* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_CHIP_SELECT_COUNT (0)
/* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
#define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (0)
/* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1)
/* @brief Has 16-bit data transfer support.*/
#define FSL_FEATURE_SPI_16BIT_TRANSFERS (1)
#else
#error "No valid CPU defined!"
#endif
#endif /* __FSL_DSPI_FEATURES_H__*/
/*******************************************************************************
* EOF
******************************************************************************/

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libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.c Normal file
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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_dspi_hal.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_master_init
* Description : Configure the DSPI peripheral in master mode.
* This function will initialize the module to user defined settings and default settings in master
* mode. Here is an example demonstrating how to define the dspi_master_config_t structure and call
* the dspi_hal_master_init function:
* dspi_master_config_t dspiConfig;
* dspiConfig.isEnabled = false;
* dspiConfig.whichCtar = kDspiCtar0;
* dspiConfig.bitsPerSec = 0;
* dspiConfig.sourceClockInHz = dspiSourceClock;
* dspiConfig.isSckContinuous = false;
* dspiConfig.whichPcs = kDspiPcs0;
* dspiConfig.pcsPolarity = kDspiPcs_ActiveLow;
* dspiConfig.masterInSample = kDspiSckToSin_0Clock;
* dspiConfig.isModifiedTimingFormatEnabled = false;
* dspiConfig.isTxFifoDisabled = false;
* dspiConfig.isRxFifoDisabled = false;
* dspiConfig.dataConfig.bitsPerFrame = 16;
* dspiConfig.dataConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
* dspiConfig.dataConfig.clkPhase = kDspiClockPhase_FirstEdge;
* dspiConfig.dataConfig.direction = kDspiMsbFirst;
* dspi_hal_master_init(instance, &dspiConfig, calculatedBaudRate);
*
*END**************************************************************************/
dspi_status_t dspi_hal_master_init(uint32_t instance, const dspi_master_config_t * config,
uint32_t * calculatedBaudRate)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
/* Enable or disable the module. */
/* Note, to enable the module, MDIS must be cleared. However, the member isEnabled*/
/* must be true (1) to enable module, hence we negate the value of isEnabled to properly*/
/* configure the MDIS bit*/
BW_SPI_MCR_MDIS(instance, ~(config->isEnabled == true));
/* Configure baud rate if a value is provided.*/
if (config->bitsPerSec != 0U)
{
*calculatedBaudRate = dspi_hal_set_baud(instance, config->whichCtar, config->bitsPerSec,
config->sourceClockInHz);
}
else
{
*calculatedBaudRate = 0;
}
/* Set master or slave mode.*/
dspi_hal_set_master_slave(instance, kDspiMaster);
/* Configure data format.*/
if (dspi_hal_configure_data_format(instance, config->whichCtar, &config->dataConfig)
!= kStatus_DSPI_Success)
{
return kStatus_DSPI_InvalidBitCount;
}
/* Configure for continuous SCK operation*/
dspi_hal_configure_continuous_sck(instance, config->isSckContinuous);
/* Configure for peripheral chip select polarity*/
dspi_hal_configure_pcs_polarity(instance, config->whichPcs,config->pcsPolarity);
/* Configure sample point for data in, master mode*/
dspi_hal_set_datain_samplepoint(instance, config->masterInSample);
/* Configure for modified timing format*/
dspi_hal_configure_modified_timing_format(instance, config->isModifiedTimingFormatEnabled);
/* Configure for fifo operation*/
dspi_hal_configure_fifos(instance, config->isTxFifoDisabled, config->isRxFifoDisabled);
/* finally, clear the DSPI CONFIGURATION (DCONF), even though this is cleared in some IPs*/
/* by default and other bit settings are reserved*/
HW_SPI_MCR_CLR(instance, BM_SPI_MCR_DCONF);
return kStatus_DSPI_Success;
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_slave_init
* Description : Configure the DSPI peripheral in slave mode.
* This function initializes the DSPI module for slave mode. Here is an example demonstrating how
* to define the dspi_slave_config_t structure and call the dspi_hal_slave_init function:
* dspi_slave_config_t dspiConfig;
* dspiConfig.isEnabled = false;
* dspiConfig.isTxFifoDisabled = false;
* dspiConfig.isRxFifoDisabled = false;
* dspiConfig.dataConfig.bitsPerFrame = 16;
* dspiConfig.dataConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
* dspiConfig.dataConfig.clkPhase = kDspiClockPhase_FirstEdge;
* dspi_hal_slave_init(instance, &dspiConfig);
*
*END**************************************************************************/
dspi_status_t dspi_hal_slave_init(uint32_t instance, const dspi_slave_config_t * config)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
/* Enable or disable the module.
* Note, to enable the module, MDIS must be cleared. However, the member isEnabled
* must be true (1) to enable module, hence we negate the value of isEnabled to properly
* configure the MDIS bit
*/
BW_SPI_MCR_MDIS(instance, ~(config->isEnabled == true));
/* Set master or slave moe. */
dspi_hal_set_master_slave(instance, kDspiSlave);
/* Configure data format. For slave mode, only CTAR0 is available for use */
if (dspi_hal_configure_data_format(instance, kDspiCtar0, &config->dataConfig)
!= kStatus_DSPI_Success)
{
return kStatus_DSPI_InvalidBitCount;
}
/* Configure for fifo operation */
dspi_hal_configure_fifos(instance, config->isTxFifoDisabled, config->isRxFifoDisabled);
/* finally, clear the DSPI CONFIGURATION (DCONF), even though this is cleared in some IPs
* by default and other bit settings are reserved
*/
HW_SPI_MCR_CLR(instance, BM_SPI_MCR_DCONF);
return kStatus_DSPI_Success;
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_reset
* Description : Restore DSPI to reset configuration.
* This function basically resets all of the DSPI registers to their default setting including
* disabling the module.
*
*END**************************************************************************/
void dspi_hal_reset(uint32_t instance)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
/* first, make sure the module is enabled to allow writes to certain registers*/
dspi_hal_enable(instance);
/* Halt all transfers*/
HW_SPI_MCR_WR(instance, BM_SPI_MCR_HALT);
/* flush the fifos*/
dspi_hal_flush_fifos(instance, true, true);
/* set the registers to their default states*/
/* clear the status bits (write-1-to-clear)*/
HW_SPI_SR_WR(instance, BM_SPI_SR_TCF | BM_SPI_SR_EOQF | BM_SPI_SR_TFUF | BM_SPI_SR_TFFF |
BM_SPI_SR_RFOF | BM_SPI_SR_RFDF);
HW_SPI_TCR_WR(instance, 0);
HW_SPI_CTARn_WR(instance, 0, 0); /* CTAR0*/
HW_SPI_CTARn_WR(instance, 1, 0); /* CTAR1*/
HW_SPI_RSER_WR(instance, 0);
/* disable the module*/
HW_SPI_MCR_WR(instance, BM_SPI_MCR_MDIS | BM_SPI_MCR_HALT);
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_set_baud
* Description : Set the DSPI baud rate in bits per second.
* This function will take in the desired bitsPerSec (baud rate) and will calculate the nearest
* possible baud rate without exceeding the desired baud rate, and will return the calculated
* baud rate in bits-per-second. It requires that the caller also provide the frequency of the
* module source clock (in Hz).
*
*END**************************************************************************/
uint32_t dspi_hal_set_baud(uint32_t instance, dspi_ctar_selection_t whichCtar, uint32_t bitsPerSec,
uint32_t sourceClockInHz)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
/* for master mode configuration, if slave mode detected, return 0*/
if (HW_SPI_MCR(instance).B.MSTR != 1)
{
return 0;
}
uint32_t prescaler, bestPrescaler;
uint32_t scaler, bestScaler;
uint32_t dbr, bestDbr;
uint32_t realBaudrate, bestBaudrate;
uint32_t diff, min_diff;
uint32_t baudrate = bitsPerSec;
/* find combination of prescaler and scaler resulting in baudrate closest to the */
/* requested value */
min_diff = 0xFFFFFFFFU;
bestPrescaler = 0;
bestScaler = 0;
bestDbr = 1;
bestBaudrate = 0; /* required to avoid compilation warning */
/* In all for loops, if min_diff = 0, the exit for loop*/
for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++)
{
for (scaler = 0; (scaler < 16) && min_diff; scaler++)
{
for (dbr = 1; (dbr < 3) && min_diff; dbr++)
{
realBaudrate = ((sourceClockInHz * dbr) /
(s_baudratePrescaler[prescaler] * (s_baudrateScaler[scaler])));
/* calculate the baud rate difference based on the conditional statement*/
/* that states that the calculated baud rate must not exceed the desired baud rate*/
if (baudrate >= realBaudrate)
{
diff = baudrate-realBaudrate;
if (min_diff > diff)
{
/* a better match found */
min_diff = diff;
bestPrescaler = prescaler;
bestScaler = scaler;
bestBaudrate = realBaudrate;
bestDbr = dbr;
}
}
}
}
}
uint32_t temp;
/* write the best dbr, prescalar, and baud rate scalar to the CTAR*/
temp = HW_SPI_CTARn_RD(instance, whichCtar); /* save register contents*/
temp &= ~(BM_SPI_CTARn_DBR| BM_SPI_CTARn_PBR | BM_SPI_CTARn_BR);
temp |= BF_SPI_CTARn_DBR(bestDbr - 1) |
BF_SPI_CTARn_PBR(bestPrescaler) |
BF_SPI_CTARn_BR(bestScaler);
HW_SPI_CTARn_WR(instance, whichCtar, temp);
/* return the actual calculated baud rate*/
return bestBaudrate;
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_set_baud_divisors
* Description : Configure the baud rate divisors manually.
* This function allows the caller to manually set the baud rate divisors in the event that
* these dividers are known and the caller does not wish to call the dspi_hal_set_baud function.
*
*END**************************************************************************/
void dspi_hal_set_baud_divisors(uint32_t instance,
dspi_ctar_selection_t whichCtar,
const dspi_baud_rate_divisors_t * divisors)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
uint32_t temp;
/* these settings are only relevant in master mode*/
if (HW_SPI_MCR(instance).B.MSTR == 1)
{
temp = HW_SPI_CTARn_RD(instance, whichCtar); /* save register contents*/
temp &= ~(BM_SPI_CTARn_DBR | BM_SPI_CTARn_PBR | BM_SPI_CTARn_BR); /* clear dividers*/
temp |= BF_SPI_CTARn_DBR(divisors->doubleBaudRate) |
BF_SPI_CTARn_PBR(divisors->prescaleDivisor) |
BF_SPI_CTARn_BR(divisors->baudRateDivisor);
HW_SPI_CTARn_WR(instance, whichCtar, temp);
}
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_configure_pcs_polarity
* Description : Configure DSPI peripheral chip select polarity.
* This function will take in the desired peripheral chip select (PCS) and it's
* corresponding desired polarity and will configure the PCS signal to operate with the
* desired characteristic.
*
*END**************************************************************************/
void dspi_hal_configure_pcs_polarity(uint32_t instance, dspi_which_pcs_config_t pcs,
dspi_pcs_polarity_config_t activeLowOrHigh)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
uint32_t temp;
temp = BR_SPI_MCR_PCSIS(instance);
if (activeLowOrHigh == kDspiPcs_ActiveLow)
{
temp |= pcs;
}
else /* kDspiPcsPolarity_ActiveHigh*/
{
temp &= ~(unsigned)pcs;
}
BW_SPI_MCR_PCSIS(instance, temp);
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_configure_fifos
* Description : Configure DSPI fifos.
* This function with allow the caller to disable/enable the TX and RX FIFOs (independently).
* Note that to disable, the caller must pass in a logic 1 (true) for the particular FIFO
* configuration. To enable, the caller must pass in a logic 0 (false). For example, to enable
* both the TX and RX FIFOs, the caller will make this function call (where instance is the
*
*END**************************************************************************/
void dspi_hal_configure_fifos(uint32_t instance, bool disableTxFifo, bool disableRxFifo)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
/* first see if MDIS is set or cleared */
uint32_t isMdisSet = HW_SPI_MCR(instance).B.MDIS;
if (isMdisSet)
{
/* clear the MDIS bit to allow us to write to the fifo disables */
HW_SPI_MCR_CLR(instance, BM_SPI_MCR_MDIS);
}
BW_SPI_MCR_DIS_TXF(instance, (disableTxFifo == true));
BW_SPI_MCR_DIS_RXF(instance, (disableRxFifo == true));
/* set MDIS if it was set to begin with */
if (isMdisSet)
{
HW_SPI_MCR_SET(instance, BM_SPI_MCR_MDIS);
}
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_flush_fifos
* Description : Flush DSPI fifos.
*
*END**************************************************************************/
void dspi_hal_flush_fifos(uint32_t instance, bool enableFlushTxFifo, bool enableFlushRxFifo)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_MCR_CLR_TXF(instance, (enableFlushTxFifo == true));
BW_SPI_MCR_CLR_RXF(instance, (enableFlushRxFifo == true));
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_configure_data_format
* Description : Configure the data format for a particular CTAR.
* This function configures the bits-per-frame, polarity, phase, and shift direction for a
* particular CTAR. An example use case is as follows:
* dspi_data_format_config_t dataFormat;
* dataFormat.bitsPerFrame = 16;
* dataFormat.clkPolarity = kDspiClockPolarity_ActiveLow;
* dataFormat.clkPhase = kDspiClockPhase_FirstEdge;
* dataFormat.direction = kDspiMsbFirst;
* dspi_hal_configure_data_format(instance, kDspiCtar0, &dataFormat);
*
*END**************************************************************************/
dspi_status_t dspi_hal_configure_data_format(uint32_t instance,
dspi_ctar_selection_t whichCtar,
const dspi_data_format_config_t * config)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
/* check bits-per-frame value to make sure it it within the proper range*/
/* in either master or slave mode*/
if ((config->bitsPerFrame < 4) ||
((config->bitsPerFrame > 16) && (HW_SPI_MCR(instance).B.MSTR == 1)) ||
((config->bitsPerFrame > 32) && (HW_SPI_MCR(instance).B.MSTR == 0)))
{
return kStatus_DSPI_InvalidBitCount;
}
uint32_t temp;
/* for master mode configuration*/
if (HW_SPI_MCR(instance).B.MSTR == 1)
{
temp = HW_SPI_CTARn_RD(instance, whichCtar); /* save register contents*/
temp &= ~(BM_SPI_CTARn_FMSZ| BM_SPI_CTARn_CPOL | BM_SPI_CTARn_CPHA | BM_SPI_CTARn_LSBFE);
temp |= BF_SPI_CTARn_FMSZ(config->bitsPerFrame - 1) |
BF_SPI_CTARn_CPOL(config->clkPolarity) |
BF_SPI_CTARn_CPHA(config->clkPhase) |
BF_SPI_CTARn_LSBFE(config->direction);
HW_SPI_CTARn_WR(instance, whichCtar, temp);
}
else /* for slave mode configuration*/
{
temp = HW_SPI_CTARn_SLAVE_RD(instance, whichCtar); /* save register contents*/
temp &= ~(BM_SPI_CTARn_SLAVE_FMSZ| BM_SPI_CTARn_SLAVE_CPOL | BM_SPI_CTARn_SLAVE_CPHA);
temp |= BF_SPI_CTARn_SLAVE_FMSZ(config->bitsPerFrame - 1) |
BF_SPI_CTARn_SLAVE_CPOL(config->clkPolarity) |
BF_SPI_CTARn_SLAVE_CPHA(config->clkPhase);
HW_SPI_CTARn_SLAVE_WR(instance, whichCtar, temp);
}
return kStatus_DSPI_Success;
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_configure_delays
* Description : Configure the delays for a particular CTAR, master mode only.
* This function configures the PCS to SCK delay prescalar (PCSSCK),
* the PCS to SCK Delay scalar (CSSCK),
* the After SCK delay prescalar (PASC),
* the After SCK delay scalar (ASC),
* the Delay after transfer prescalar (PDT),
* and the Delay after transfer scalar (DT).
* The following is an example use case of this function:
* dspi_delay_settings_config_t delayConfig;
* delayConfig.pcsToSckPre = 0x3;
* delayConfig.pcsToSck = 0xF;
* delayConfig.afterSckPre = 0x2;
* delayConfig.afterSck = 0xA;
* delayConfig.afterTransferPre = 0x1;
* delayConfig.afterTransfer = 0x5;
* dspi_hal_configure_delays(instance, kDspiCtar0, &delayConfig);
*
*END**************************************************************************/
void dspi_hal_configure_delays(uint32_t instance,
dspi_ctar_selection_t whichCtar,
const dspi_delay_settings_config_t * config)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
uint32_t temp;
/* these settings are only relevant in master mode*/
if (HW_SPI_MCR(instance).B.MSTR == 1)
{
temp = HW_SPI_CTARn_RD(instance, whichCtar); /* save register contents*/
temp &= ~(BM_SPI_CTARn_PCSSCK | BM_SPI_CTARn_PASC | BM_SPI_CTARn_PDT |
BM_SPI_CTARn_CSSCK| BM_SPI_CTARn_ASC | BM_SPI_CTARn_DT);
temp |= BF_SPI_CTARn_PCSSCK(config->pcsToSckPre) |
BF_SPI_CTARn_PASC(config->afterSckPre) |
BF_SPI_CTARn_PDT(config->afterTransferPre) |
BF_SPI_CTARn_CSSCK(config->pcsToSck) |
BF_SPI_CTARn_ASC(config->afterSck) |
BF_SPI_CTARn_DT(config->afterTransfer);
HW_SPI_CTARn_WR(instance, whichCtar, temp);
}
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_configure_dma
* Description : Configure transmit and receive DMA requests.
* This function configures the FIFOs to generate a DMA or interrupt request. Note that the
* corresponding request enable must also be set. For the Transmit FIFO Fill, in order
* to generate a DMA request, the Transmit FIFO Fill Request Enable (TFFF_RE) must also be set.
* Similarly for the Receive FIFO Drain Request, to generate a DMA request, the Receive FIFO Drain
* Request Enable (RFDF_RE) must also be set. These request enables can be configured via
* the function dspi_hal_configure_interrupt(). So basically to enable DMA operation, first enable
* the desired request enable using the dspi_hal_configure_interrupt() function and then use
* the dspi_hal_configure_dma() to configure the request to generate a DMA reuqest.
*
*END**************************************************************************/
void dspi_hal_configure_dma(uint32_t instance, bool enableTransmit, bool enableReceive)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_RSER_TFFF_DIRS(instance, enableTransmit);
BW_SPI_RSER_RFDF_DIRS(instance, enableReceive);
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_configure_interrupt
* Description : Configure DSPI interrupts.
* This function will configure the various interrupt sources of the DSPI. The parameters to pass
* in are instance, interrupt source, and enable/disable setting.
* The interrupt source will be of a typedef enum whose value will be the bit position of the
* interrupt source setting within the RSER register. In the DSPI, all of the interrupt
* configuration settings reside within the one register. The typedef enum will equate each
* interrupt source to the bit position defined in the device header file.
* The function will use these bit positions in its algorithm to enable/disable the
* interrupt source, where interrupt source is of type dspi_status_and_interrupt_request_t.
* temp = (HW_SPI_RSER_RD(instance) & ~interruptSrc) | (enable << interruptSrc);
* HW_SPI_RSER_WR(instance, temp);
*
* dspi_hal_configure_interrupt(instance, kDspiTxComplete, true); <- example use-case
*
*END**************************************************************************/
void dspi_hal_configure_interrupt(uint32_t instance,
dspi_status_and_interrupt_request_t interruptSrc,
bool enable)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
uint32_t temp;
temp = (HW_SPI_RSER_RD(instance) & ~(0x1U << interruptSrc)) | ((uint32_t)enable << interruptSrc);
HW_SPI_RSER_WR(instance, temp);
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_get_fifo_data
* Description : Read fifo registers for debug purposes.
*
*END**************************************************************************/
uint32_t dspi_hal_get_fifo_data(uint32_t instance, dspi_fifo_t whichFifo, uint32_t whichFifoEntry)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
if (whichFifo == kDspiTxFifo)
{
return HW_SPI_TXFRn_RD(instance, whichFifoEntry);
}
else
{
return HW_SPI_RXFRn_RD(instance, whichFifoEntry);
}
}
/*FUNCTION**********************************************************************
*
* Function Name : dspi_hal_write_data_master_mode
* Description : Write data into the data buffer, master mode.
* In master mode, the 16-bit data is appended with the 16-bit command info. The command portion
* provides characteristics of the data being sent such as: optional continuous chip select
* operation between transfers, the desired Clock and Transfer Attributes register to use for the
* associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
* transfer is the last in the queue, and whether to clear the transfer count (normally needed when
* sending the first frame of a data packet). An example use case is as follows:
* dspi_command_config_t commandConfig;
* commandConfig.isChipSelectContinuous = true;
* commandConfig.whichCtar = kDspiCtar0;
* commandConfig.whichPcs = kDspiPcs1;
* commandConfig.clearTransferCount = false;
* commandConfig.isEndOfQueue = false;
* dspi_hal_write_data_master_mode(instance, &commandConfig, dataWord);
*
*END**************************************************************************/
void dspi_hal_write_data_master_mode(uint32_t instance,
dspi_command_config_t * command,
uint16_t data)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
uint32_t temp;
temp = BF_SPI_PUSHR_CONT(command->isChipSelectContinuous) |
BF_SPI_PUSHR_CTAS(command->whichCtar) |
BF_SPI_PUSHR_PCS(command->whichPcs) |
BF_SPI_PUSHR_EOQ(command->isEndOfQueue) |
BF_SPI_PUSHR_CTCNT(command->clearTransferCount) |
BF_SPI_PUSHR_TXDATA(data);
HW_SPI_PUSHR_WR(instance, temp);
}
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__FSL_DSPI_HAL_H__)
#define __FSL_DSPI_HAL_H__
#include <assert.h>
#include <stdint.h>
#include <stdbool.h>
#include "fsl_dspi_features.h"
#include "fsl_device_registers.h"
/*!
* @addtogroup dspi_hal
* @{
*/
/*! @file*/
/*******************************************************************************
* Definitions
******************************************************************************/
/* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/
static const uint32_t s_baudratePrescaler[] = { 2, 3, 5, 7 };
static const uint32_t s_baudrateScaler[] = { 2, 4, 6, 8, 16, 32, 64, 128, 256, 512, 1024, 2048,
4096, 8192, 16384, 32768 };
/*! @brief Error codes for the DSPI driver.*/
typedef enum _dspi_status
{
kStatus_DSPI_Success = 0,
kStatus_DSPI_SlaveTxUnderrun, /*!< DSPI Slave Tx Under run error*/
kStatus_DSPI_SlaveRxOverrun, /*!< DSPI Slave Rx Overrun error*/
kStatus_DSPI_Timeout, /*!< DSPI transfer timed out*/
kStatus_DSPI_Busy, /*!< DSPI instance is already busy performing a
transfer.*/
kStatus_DSPI_NoTransferInProgress, /*!< Attempt to abort a transfer when no transfer
was in progress*/
kStatus_DSPI_InvalidBitCount, /*!< bits-per-frame value not valid*/
kStatus_DSPI_InvalidInstanceNumber, /*!< DSPI instance number does not match current count*/
kStatus_DSPI_OutOfRange /*< DSPI out-of-range error used in slave callback */
} dspi_status_t;
/*! @brief DSPI master or slave configuration*/
typedef enum _dspi_master_slave_mode {
kDspiMaster = 1, /*!< DSPI peripheral operates in master mode*/
kDspiSlave = 0 /*!< DSPI peripheral operates in slave mode*/
} dspi_master_slave_mode_t;
/*! @brief DSPI clock polarity configuration for a given CTAR*/
typedef enum _dspi_clock_polarity {
kDspiClockPolarity_ActiveHigh = 0, /*!< Active-high DSPI clock (idles low)*/
kDspiClockPolarity_ActiveLow = 1 /*!< Active-low DSPI clock (idles high)*/
} dspi_clock_polarity_t;
/*! @brief DSPI clock phase configuration for a given CTAR*/
typedef enum _dspi_clock_phase {
kDspiClockPhase_FirstEdge = 0, /*!< Data is captured on the leading edge of the SCK and
changed on the following edge.*/
kDspiClockPhase_SecondEdge = 1 /*!< Data is changed on the leading edge of the SCK and
captured on the following edge.*/
} dspi_clock_phase_t;
/*! @brief DSPI data shifter direction options for a given CTAR*/
typedef enum _dspi_shift_direction {
kDspiMsbFirst = 0, /*!< Data transfers start with most significant bit.*/
kDspiLsbFirst = 1 /*!< Data transfers start with least significant bit.*/
} dspi_shift_direction_t;
/*! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection*/
typedef enum _dspi_ctar_selection {
kDspiCtar0 = 0, /*!< CTAR0 selection option for master or slave mode*/
kDspiCtar1 = 1 /*!< CTAR1 selection option for master mode only*/
} dspi_ctar_selection_t;
/*! @brief DSPI Peripheral Chip Select (PCS) Polarity configuration.*/
typedef enum _dspi_pcs_polarity_config {
kDspiPcs_ActiveHigh = 0, /*!< PCS Active High (idles low)*/
kDspiPcs_ActiveLow = 1 /*!< PCS Active Low (idles high)*/
} dspi_pcs_polarity_config_t;
/*! @brief DSPI Peripheral Chip Select (PCS) configuration (which PCS to configure)*/
typedef enum _dspi_which_pcs_config {
kDspiPcs0 = 1 << 0, /*!< PCS[0] */
kDspiPcs1 = 1 << 1, /*!< PCS[1] */
kDspiPcs2 = 1 << 2, /*!< PCS[2] */
kDspiPcs3 = 1 << 3, /*!< PCS[3] */
kDspiPcs4 = 1 << 4, /*!< PCS[4] */
kDspiPcs5 = 1 << 5 /*!< PCS[5] */
} dspi_which_pcs_config_t;
/*!
* @brief DSPI Sample Point: Controls when the DSPI master samples SIN in Modified Transfer
* Format. This field is valid only when CPHA bit in CTAR register is 0.
*/
typedef enum _dspi_master_sample_point {
kDspiSckToSin_0Clock = 0, /*!< 0 system clocks between SCK edge and SIN sample*/
kDspiSckToSin_1Clock = 1, /*!< 1 system clock between SCK edge and SIN sample*/
kDspiSckToSin_2Clock = 2 /*!< 2 system clocks between SCK edge and SIN sample*/
} dspi_master_sample_point_t;
/*! @brief DSPI FIFO selects*/
typedef enum _dspi_fifo {
kDspiTxFifo = 0, /*!< DSPI Tx FIFO*/
kDspiRxFifo = 1 /*!< DSPI Rx FIFO.*/
} dspi_fifo_t;
/*! @brief DSPI status flags and interrupt request enable*/
typedef enum _dspi_status_and_interrupt_request {
kDspiTxComplete = BP_SPI_RSER_TCF_RE, /*!< TCF status/interrupt enable */
kDspiTxAndRxStatus = BP_SPI_SR_TXRXS, /*!< TXRXS status only, no interrupt*/
kDspiEndOfQueue = BP_SPI_RSER_EOQF_RE, /*!< EOQF status/interrupt enable*/
kDspiTxFifoUnderflow = BP_SPI_RSER_TFUF_RE, /*!< TFUF status/interrupt enable*/
kDspiTxFifoFillRequest = BP_SPI_RSER_TFFF_RE, /*!< TFFF status/interrupt enable*/
kDspiRxFifoOverflow = BP_SPI_RSER_RFOF_RE, /*!< RFOF status/interrupt enable*/
kDspiRxFifoDrainRequest = BP_SPI_RSER_RFDF_RE /*!< RFDF status/interrupt enable*/
} dspi_status_and_interrupt_request_t;
/*! @brief DSPI FIFO counter or pointer defines based on bit positions*/
typedef enum _dspi_fifo_counter_pointer {
kDspiRxFifoPointer = BP_SPI_SR_POPNXTPTR, /*!< Rx FIFO pointer*/
kDspiRxFifoCounter = BP_SPI_SR_RXCTR, /*!< Rx FIFO counter*/
kDspiTxFifoPointer = BP_SPI_SR_TXNXTPTR, /*!< Tx FIFO pointer*/
kDspiTxFifoCounter = BP_SPI_SR_TXCTR /*!< Tx FIFO counter*/
} dspi_fifo_counter_pointer_t;
/*!
* @brief DSPI data format settings configuration structure
*
* This structure contains the data format settings. These settings apply to a specific
* CTARn register, which the user must provide in this structure.
*/
typedef struct DspiDataFormatConfig {
uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16 (master), 32 (slave) */
dspi_clock_polarity_t clkPolarity; /*!< Active high or low clock polarity*/
dspi_clock_phase_t clkPhase; /*!< Clock phase setting to change and capture data*/
dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction
This setting relevant only in master mode and
can be ignored in slave mode */
} dspi_data_format_config_t;
/*!
* @brief DSPI hardware configuration settings for master mode
*
* Use an instance of this structure with the dspi_hal_master_init() to configure the
* most common settings of the DSPI peripheral in master mode with a single function call.
*
* The @c bitsPerSec member is handled in a special way. If this value is set to 0, then the baud is
* not set by the dspi_hal_master_init(), and must be set with a separate call to either the
* dspi_hal_set_baud() or the dspi_hal_set_baud_divisors(). This can be useful when you know the
* divisors in advance and don't want to spend the time to compute them for the provided rate
* in bits/sec.
*
* This structure also contains another structure template as a member:
* @c dspi_data_format_config_t @c dataConfig.
* An example usage for this is assuming declaration @c dspi_master_config_t
* @c dspiConfig:
@code
dspiConfig.dataConfig.bitsPerFrame = 16;
dspiConfig.dataConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
dspiConfig.dataConfig.clkPhase = kDspiClockPhase_FirstEdge;
dspiConfig.dataConfig.direction = kDspiMsbFirst;
@endcode
*/
typedef struct DspiMasterConfig {
bool isEnabled; /*!< Set to true to enable the DSPI peripheral.*/
dspi_ctar_selection_t whichCtar; /*!< Desired Clock and Transfer Attributes Register (CTAR)*/
uint32_t bitsPerSec; /*!< Baud rate in bits per second*/
uint32_t sourceClockInHz; /*!< Module source clock */
dspi_data_format_config_t dataConfig; /*!< Data format configuration structure*/
bool isSckContinuous; /*!< Disable(0) or Enable(1) continuous SCK operation*/
dspi_which_pcs_config_t whichPcs; /*!< Desired Peripheral Chip Select (PCS) */
dspi_pcs_polarity_config_t pcsPolarity; /*!< Peripheral Chip Select (PCS) polarity setting.*/
dspi_master_sample_point_t masterInSample; /*!< Master data-in (SIN) sample point setting.*/
bool isModifiedTimingFormatEnabled; /*!< Disable(0) or Enable(1) modified timing format.*/
bool isTxFifoDisabled; /*!< Disable(1) or Enable(0) Tx FIFO */
bool isRxFifoDisabled; /*!< Disable(1) or Enable(0) Rx FIFO */
} dspi_master_config_t;
/*!
* @brief DSPI hardware configuration settings for slave mode.
*
* Use an instance of this structure with the dspi_hal_slave_init() to configure the
* most common settings of the DSPI peripheral in slave mode with a single function call.
*/
typedef struct DspiSlaveConfig {
bool isEnabled; /*!< Set to true to enable the DSPI peripheral. */
dspi_data_format_config_t dataConfig; /*!< Data format configuration structure */
bool isTxFifoDisabled; /*!< Disable(1) or Enable(0) Tx FIFO */
bool isRxFifoDisabled; /*!< Disable(1) or Enable(0) Rx FIFO */
} dspi_slave_config_t;
/*!
* @brief DSPI baud rate divisors settings configuration structure.
*
* Note: These settings are relevant only in master mode.
* This structure contains the baud rate divisor settings, which provides the user with the option to
* explicitly set these baud rate divisors. In addition, the user must also set the
* CTARn register with the divisor settings.
*/
typedef struct DspiBaudRateDivisors {
bool doubleBaudRate; /*!< Double Baud rate parameter setting */
uint32_t prescaleDivisor; /*!< Baud Rate Pre-scalar parameter setting*/
uint32_t baudRateDivisor; /*!< Baud Rate scaler parameter setting */
} dspi_baud_rate_divisors_t;
/*!
* @brief DSPI delay settings configuration structure
*
* Note: These settings are relevant only in master mode.
* This structure contains the various delay settings. These settings apply to a specific
* CTARn register, which the user must provide in this structure.
*/
typedef struct DspiDelaySettingsConfig {
uint32_t pcsToSckPre; /*!< PCS to SCK delay pre-scalar (PCSSCK) */
uint32_t pcsToSck; /*!< PCS to SCK Delay scalar (CSSCK) */
uint32_t afterSckPre; /*!< After SCK delay pre-scalar (PASC)*/
uint32_t afterSck; /*!< After SCK delay scalar (ASC)*/
uint32_t afterTransferPre; /*!< Delay after transfer pre-scalar (PDT)*/
uint32_t afterTransfer; /*!< Delay after transfer scalar (DT) */
} dspi_delay_settings_config_t;
/*!
* @brief DSPI command and data configuration structure
*
* Note: This structure is used with the PUSHR register, which
* provides the means to write to the Tx FIFO. Data written to this register is
* transferred to the Tx FIFO. Eight or sixteen-bit write accesses to the PUSHR transfer all
* 32 register bits to the Tx FIFO. The register structure is different in master and slave
* modes. In master mode, the register provides 16-bit command and 16-bit data to the Tx
* FIFO. In slave mode all 32 register bits can be used as data, supporting up to 32-bit SPI
* frame operation.
*/
typedef struct DspiCommandDataConfig {
bool isChipSelectContinuous; /*!< Option to enable the continuous assertion of chip select
between transfers*/
dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes
Register (CTAR) to use for CTAS*/
dspi_which_pcs_config_t whichPcs; /*!< The desired PCS signal to use for the data transfer*/
bool isEndOfQueue; /*!< Signals that the current transfer is the last in the queue*/
bool clearTransferCount; /*!< Clears SPI_TCNT field; cleared before transmission starts*/
} dspi_command_config_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name Configuration
* @{
*/
/*!
* @brief Configure the DSPI peripheral in master mode
*
* This function initializes the module to the user defined settings and default settings in master
* mode. This is an example demonstrating how to define the dspi_master_config_t structure and call
* the dspi_hal_master_init function:
@code
dspi_master_config_t dspiConfig;
dspiConfig.isEnabled = false;
dspiConfig.whichCtar = kDspiCtar0;
dspiConfig.bitsPerSec = 0;
dspiConfig.sourceClockInHz = dspiSourceClock;
dspiConfig.isSckContinuous = false;
dspiConfig.whichPcs = kDspiPcs0;
dspiConfig.pcsPolarity = kDspiPcs_ActiveLow;
dspiConfig.masterInSample = kDspiSckToSin_0Clock;
dspiConfig.isModifiedTimingFormatEnabled = false;
dspiConfig.isTxFifoDisabled = false;
dspiConfig.isRxFifoDisabled = false;
dspiConfig.dataConfig.bitsPerFrame = 16;
dspiConfig.dataConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
dspiConfig.dataConfig.clkPhase = kDspiClockPhase_FirstEdge;
dspiConfig.dataConfig.direction = kDspiMsbFirst;
dspi_hal_master_init(instance, &dspiConfig, calculatedBaudRate);
@endcode
*
* @param instance Module instance number
* @param config Pointer to the master mode configuration data structure
* @param calculatedBaudRate The calculated baud rate passed back to the user for them to determine
* if the calculated baud rate is close enough to meet their needs.
* @return An error code or kStatus_DSPI_Success.
*/
dspi_status_t dspi_hal_master_init(uint32_t instance, const dspi_master_config_t * config,
uint32_t * calculatedBaudRate);
/*!
* @brief Configures the DSPI peripheral in slave mode.
*
* This function initializes the DSPI module for slave mode. This is an example demonstrating how
* to define the dspi_slave_config_t structure and call the dspi_hal_slave_init function:
@code
dspi_slave_config_t dspiConfig;
dspiConfig.isEnabled = false;
dspiConfig.isTxFifoDisabled = false;
dspiConfig.isRxFifoDisabled = false;
dspiConfig.dataConfig.bitsPerFrame = 16;
dspiConfig.dataConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
dspiConfig.dataConfig.clkPhase = kDspiClockPhase_FirstEdge;
dspi_hal_slave_init(instance, &dspiConfig);
@endcode
*
* @param instance Module instance number
* @param config Pointer to the slave mode configuration data structure
* @return An error code or kStatus_DSPI_Success.
*/
dspi_status_t dspi_hal_slave_init(uint32_t instance, const dspi_slave_config_t * config);
/*!
* @brief Restores the DSPI to reset the configuration.
*
* This function basically resets all of the DSPI registers to their default setting including
* disabling the module.
*
* @param instance Module instance number
*/
void dspi_hal_reset(uint32_t instance);
/*!
* @brief Enable the DSPI peripheral, set MCR MDIS to 0.
*
* @param instance Module instance number
*/
static inline void dspi_hal_enable(uint32_t instance)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
HW_SPI_MCR_CLR(instance, BM_SPI_MCR_MDIS);
}
/*!
* @brief Disables the DSPI peripheral, sets MCR MDIS to 1.
*
* @param instance Module instance number
*/
static inline void dspi_hal_disable(uint32_t instance)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
HW_SPI_MCR_SET(instance, BM_SPI_MCR_MDIS);
}
/*!
* @brief Sets the DSPI baud rate in bits per second.
*
* This function takes in the desired bitsPerSec (baud rate) and calculates the nearest
* possible baud rate without exceeding the desired baud rate, and returns the calculated
* baud rate in bits-per-second. It requires that the caller also provide the frequency of the
* module source clock (in Hertz).
*
* @param instance Module instance number
* @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type
* dspi_ctar_selection_t
* @param bitsPerSec The desired baud rate in bits per second
* @param sourceClockInHz Module source input clock in Hertz
* @return The actual calculated baud rate
*/
uint32_t dspi_hal_set_baud(uint32_t instance, dspi_ctar_selection_t whichCtar, uint32_t bitsPerSec,
uint32_t sourceClockInHz);
/*!
* @brief Configures the baud rate divisors manually.
*
* This function allows the caller to manually set the baud rate divisors in the event that
* these dividers are known and the caller does not wish to call the dspi_hal_set_baud function.
*
* @param instance Module instance number
* @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
* dspi_ctar_selection_t
* @param divisors Pointer to a structure containing the user defined baud rate divisor settings
*/
void dspi_hal_set_baud_divisors(uint32_t instance,
dspi_ctar_selection_t whichCtar,
const dspi_baud_rate_divisors_t * divisors);
/*!
* @brief Configures the DSPI for master or slave.
*
* @param instance Module instance number
* @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t
*/
static inline void dspi_hal_set_master_slave(uint32_t instance, dspi_master_slave_mode_t mode)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_MCR_MSTR(instance, (uint32_t)mode);
}
/*!
* @brief Configures the DSPI for the continuous SCK operation.
*
* @param instance Module instance number
* @param enable Enables (true) or disables(false) continuous SCK operation.
*/
static inline void dspi_hal_configure_continuous_sck(uint32_t instance, bool enable)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_MCR_CONT_SCKE(instance, (enable == true));
}
/*!
* @brief Configures the DSPI to enable modified timing format.
*
* @param instance Module instance number
* @param enable Enables (true) or disables(false) modified timing format.
*/
static inline void dspi_hal_configure_modified_timing_format(uint32_t instance, bool enable)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_MCR_MTFE(instance, (enable == true));
}
/*!
* @brief Configures the DSPI peripheral chip select strobe enable. Configures the PCS[5] to be the
* active-low PCS Strobe output.
*
* PCS[5] is a special case that can be configured as an active low PCS strobe or as a Peripheral
* Chip Select in master mode. When configured as a strobe, it provides a signal to an external
* demultiplexer to decode PCS[0] to PCS[4] signals into as many as 128 glitch-free PCS signals.
*
* @param instance Module instance number
* @param enable Enable (true) PCS[5] to operate as the peripheral chip select (PCS) strobe
* If disable (false), PCS[5] operates as a peripheral chip select
*/
static inline void dspi_hal_configure_pcs_strobe(uint32_t instance, bool enable)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_MCR_PCSSE(instance, (enable == true));
}
/*!
* @brief Configures the DSPI received FIFO overflow overwrite enable.
*
* When enabled, this function allows incoming receive data to overwrite the existing data in the
* receive shift register when the Rx FIFO is full. Otherwise when disabled, the incoming data
* is ignored when the RX FIFO is full.
*
* @param instance Module instance number.
* @param enable If enabled (true), allows incoming data to overwrite Rx FIFO contents when full,
* else incoming data is ignored.
*/
static inline void dspi_hal_configure_rx_fifo_overwrite(uint32_t instance, bool enable)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_MCR_ROOE(instance, (enable == true));
}
/*!
* @brief Configures the DSPI peripheral chip select polarity.
*
* This function takes in the desired peripheral chip select (PCS) and it's
* corresponding desired polarity and configures the PCS signal to operate with the
* desired characteristic.
*
* @param instance Module instance number
* @param pcs The particular peripheral chip select (parameter value is of type
* dspi_which_pcs_config_t) for which we wish to apply the active high or active
* low characteristic.
* @param activeLowOrHigh The setting for either "active high, inactive low (0)" or
* "active low, inactive high(1)" of type dspi_pcs_polarity_config_t.
*/
void dspi_hal_configure_pcs_polarity(uint32_t instance, dspi_which_pcs_config_t pcs,
dspi_pcs_polarity_config_t activeLowOrHigh);
/*!
* @brief Configures the DSPI FIFOs.
*
* This function allows the caller to disable/enable the Tx and Rx FIFOs (independently).
* Note that to disable, the caller must pass in a logic 1 (true) for the particular FIFO
* configuration. To enable, the caller must pass in a logic 0 (false). For example, to enable
* both the Tx and Rx FIFOs, the caller makes this function call (where instance is the
* desired module instance number):
@code
dspi_hal_configure_fifos(instance, false, false);
@endcode
*
* @param instance Module instance number
* @param disableTxFifo Disables (false) the TX FIFO, else enables (true) the TX FIFO
* @param disableRxFifo Disables (false) the RX FIFO, else enables (true) the RX FIFO
*/
void dspi_hal_configure_fifos(uint32_t instance, bool disableTxFifo, bool disableRxFifo);
/*!
* @brief Flushes the DSPI FIFOs.
*
* @param instance Module instance number
* @param enableFlushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO
* @param enableFlushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO
*/
void dspi_hal_flush_fifos(uint32_t instance, bool enableFlushTxFifo, bool enableFlushRxFifo);
/*!
* @brief Configures when the DSPI master samples SIN in the Modified Transfer Format
*
* This function controls when the DSPI master samples SIN (data in) in the Modified Transfer
* Format. Note that this is valid only when the CPHA bit in the CTAR register is 0.
*
* @param instance Module instance number
* @param samplePnt selects when the data in (SIN) is sampled, of type dspi_master_sample_point_t.
* This value selects either 0, 1, or 2 system clocks between the SCK edge
* and the SIN (data in) sample.
*/
static inline void dspi_hal_set_datain_samplepoint(uint32_t instance,
dspi_master_sample_point_t samplePnt)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_MCR_SMPL_PT(instance, samplePnt);
}
/*!
* @brief Starts the DSPI transfers, clears HALT bit in MCR.
*
* This function call called whenever the module is ready to begin data transfers in either master
* or slave mode.
*
* @param instance Module instance number
*/
static inline void dspi_hal_start_transfer(uint32_t instance)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
HW_SPI_MCR_CLR(instance, BM_SPI_MCR_HALT);
}
/*!
* @brief Stops (halts) DSPI transfers, sets HALT bit in MCR.
*
* This function call stops data transfers in either master or slave mode.
*
* @param instance Module instance number
*/
static inline void dspi_hal_stop_transfer(uint32_t instance)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
HW_SPI_MCR_SET(instance, BM_SPI_MCR_HALT);
}
/*!
* @brief Configures the data format for a particular CTAR.
*
* This function configures the bits-per-frame, polarity, phase, and shift direction for a
* particular CTAR. An example use case is as follows:
@code
dspi_data_format_config_t dataFormat;
dataFormat.bitsPerFrame = 16;
dataFormat.clkPolarity = kDspiClockPolarity_ActiveLow;
dataFormat.clkPhase = kDspiClockPhase_FirstEdge;
dataFormat.direction = kDspiMsbFirst;
dspi_hal_configure_data_format(instance, kDspiCtar0, &dataFormat);
@endcode
*
* @param instance Module instance number
* @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
* dspi_ctar_selection_t.
* @param config Pointer to a structure containing the user defined data format configuration settings.
* @return An error code or kStatus_DSPI_Success
*/
dspi_status_t dspi_hal_configure_data_format(uint32_t instance,
dspi_ctar_selection_t whichCtar,
const dspi_data_format_config_t * config);
/*!
* @brief Configures the delays for a particular CTAR, master mode only.
*
* This function configures the PCS to SCK delay pre-scalar (PCSSCK),
* the PCS to SCK Delay scalar (CSSCK),
* the After SCK delay pre-scalar (PASC),
* the After SCK delay scalar (ASC),
* the Delay after transfer pre-scalar (PDT),
* and the Delay after transfer scalar (DT).
* The following is an example use case of this function:
* @code
dspi_delay_settings_config_t delayConfig;
delayConfig.pcsToSckPre = 0x3;
delayConfig.pcsToSck = 0xF;
delayConfig.afterSckPre = 0x2;
delayConfig.afterSck = 0xA;
delayConfig.afterTransferPre = 0x1;
delayConfig.afterTransfer = 0x5;
dspi_hal_configure_delays(instance, kDspiCtar0, &delayConfig);
* @endcode
*
* @param instance Module instance number
* @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
* dspi_ctar_selection_t.
* @param config Pointer to a structure containing the user defined delay configuration settings.
*/
void dspi_hal_configure_delays(uint32_t instance,
dspi_ctar_selection_t whichCtar,
const dspi_delay_settings_config_t * config);
/*@}*/
/*!
* @name DMA
* @{
*/
/*!
* @brief Configures transmit and receive DMA requests.
*
* This function configures the FIFOs to generate a DMA or an interrupt request. Note that the
* corresponding request enable must also be set. For the Transmit FIFO Fill, in order
* to generate a DMA request, the Transmit FIFO Fill Request Enable (TFFF_RE) must also be set.
* Similarly for the Receive FIFO Drain Request, to generate a DMA request, the Receive FIFO Drain
* Request Enable (RFDF_RE) must also be set. These requests can be configured with
* the function dspi_hal_configure_interrupt(). To enable DMA operation, first enable
* the desired request enable by using the dspi_hal_configure_interrupt() function and then use
* the dspi_hal_configure_dma() to configure the request and generate a DMA request.
*
* @param enableTransmit Configures Tx FIFO fill request to generate a DMA or interrupt request
* @param enableReceive Configures Rx FIFO fill request to generate a DMA or interrupt request
*/
void dspi_hal_configure_dma(uint32_t instance, bool enableTransmit, bool enableReceive);
/*@}*/
/*!
* @name Low power
* @{
*/
/*!
* @brief Configures the DSPI operation during doze mode.
*
* This function provides support for an externally controlled doze mode, power-saving, mechanism.
* When disabled, the doze mode has no effect on the DSPI, and when enabled, the Doze mode
* disables the DSPI.
*
* @param instance Module instance number
* @param enable If disabled (false), the doze mode has no effect on the DSPI, if enabled (true), the doze mode
* disables the DSPI.
*/
static inline void dspi_hal_configure_doze_mode(uint32_t instance, bool enable)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_MCR_DOZE(instance, (enable == true));
}
/*@}*/
/*!
* @name Interrupts
* @{
*/
/*!
* @brief Configures the DSPI interrupts.
*
* This function configures the various interrupt sources of the DSPI. The parameters are instance, interrupt source, and enable/disable setting.
* The interrupt source is a typedef enum whose value is the bit position of the
* interrupt source setting within the RSER register. In the DSPI, all interrupt
* configuration settings are in one register. The typedef enum equates each
* interrupt source to the bit position defined in the device header file.
* The function uses these bit positions in its algorithm to enable/disable the
* interrupt source, where interrupt source is the dspi_status_and_interrupt_request_t type.
* @code
temp = (HW_SPI_RSER_RD(instance) & ~interruptSrc) | (enable << interruptSrc);
HW_SPI_RSER_WR(instance, temp);
dspi_hal_configure_interrupt(instance, kDspiTxComplete, true); <- example use-case
* @endcode
*
* @param instance Module instance number
* @param interruptSrc The interrupt source, of type dspi_status_and_interrupt_request_t
* @param enable Enable (true) or disable (false) the interrupt source to generate requests
*/
void dspi_hal_configure_interrupt(uint32_t instance,
dspi_status_and_interrupt_request_t interruptSrc,
bool enable);
/*!
* @brief Gets the DSPI interrupt configuration, returns if interrupt request is enabled or disabled.
*
* This function returns the requested interrupt source setting (enabled or disabled, of
* type bool). The parameters to pass in are instance and interrupt source. It utilizes the
* same enum definitions for the interrupt sources as described in the "interrupt configuration"
* function. The function uses these bit positions in its algorithm to obtain the desired
* interrupt source setting.
* @code
return ((HW_SPI_RSER_RD(instance) & interruptSrc) >> interruptSrc);
getInterruptSetting = dspi_hal_get_interrupt_config(instance, kDspiTxComplete);
* @endcode
*
* @param instance Module instance number
* @param interruptSrc The interrupt source, of type dspi_status_and_interrupt_request_t
* @return Configuration of interrupt request: enable (true) or disable (false).
*/
static inline bool dspi_hal_get_interrupt_config(uint32_t instance,
dspi_status_and_interrupt_request_t interruptSrc)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
return ((HW_SPI_RSER_RD(instance) >> interruptSrc) & 0x1);
}
/*@}*/
/*!
* @name Status
* @{
*/
/*!
* @brief Gets the DSPI status flag state.
*
* The status flag is defined in the same enum as the interrupt source enable because the bit
* position of the interrupt source and corresponding status flag are the same in the RSER and
* SR registers. The function uses these bit positions in its algorithm to obtain the desired
* flag state, similar to the dspi_get_interrupt_config function.
* @code
return ((HW_SPI_SR_RD(instance) & statusFlag) >> statusFlag);
getStatus = dspi_hal_get_status_flag(instance, kDspiTxComplete);
* @endcode
*
* @param instance Module instance number
* @param statusFlag The status flag, of type dspi_status_and_interrupt_request_t
* @return State of the status flag: asserted (true) or not-asserted (false)
*/
static inline bool dspi_hal_get_status_flag(uint32_t instance,
dspi_status_and_interrupt_request_t statusFlag)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
return ((HW_SPI_SR_RD(instance) >> statusFlag) & 0x1);
}
/*!
* @brief Clears the DSPI status flag.
*
* This function clears the desired status bit by using a write-1-to-clear. The user passes in
* the instance and the desired status bit to clear. The list of status bits is defined in the
* dspi_status_and_interrupt_request_t. The function uses these bit positions in its algorithm
* to clear the desired flag state. It uses this macro:
* @code
HW_SPI_SR_WR(instance, statusFlag);
dspi_hal_clear_status_flag(instance, kDspiTxComplete);
* @endcode
*
* @param instance Module instance number
* @param statusFlag The status flag, of type dspi_status_and_interrupt_request_t
*/
static inline void dspi_hal_clear_status_flag(uint32_t instance,
dspi_status_and_interrupt_request_t statusFlag)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
HW_SPI_SR_SET(instance, (0x1U << statusFlag));
}
/*!
* @brief Gets the DSPI FIFO counter or pointer.
*
* This function returns the number of entries or the next pointer in the Tx or Rx FIFO.
* The parameters to pass in are the instance and either the Tx or Rx FIFO counter or a
* pointer. The latter is an enum type defined as the bitmask of
* those particular bit fields found in the device header file. For example:
* @code
return ((HW_SPI_SR_RD(instance) >> desiredParamter) & 0xF);
dspi_hal_get_fifo_counter_or_pointer(instance, kDspiRxFifoCounter);
* @endcode
*
* @param instance Module instance number
* @param desiredParameter Desired parameter to obtain, of type dspi_fifo_counter_pointer_t
*/
static inline uint32_t dspi_hal_get_fifo_counter_or_pointer(uint32_t instance,
dspi_fifo_counter_pointer_t desiredParameter)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
return ((HW_SPI_SR_RD(instance) >> desiredParameter) & 0xFU);
}
/*@}*/
/*!
* @name Data transfer
* @{
*/
/*!
* @brief Reads data from the data buffer.
*
* @param instance Module instance number
*/
static inline uint32_t dspi_hal_read_data(uint32_t instance)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
return HW_SPI_POPR_RD(instance);
}
/*!
* @brief Writes data into the data buffer, slave mode.
*
* In slave mode, up to 32-bit words may be written.
*
* @param instance Module instance number
* @param data The data to send
*/
static inline void dspi_hal_write_data_slave_mode(uint32_t instance, uint32_t data)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
HW_SPI_PUSHR_SLAVE_WR(instance, data);
}
/*!
* @brief Writes data into the data buffer, master mode.
*
* In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
* provides characteristics of the data such as: optional continuous chip select
* operation between transfers, the desired Clock and Transfer Attributes register to use for the
* associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
* transfer is the last in the queue, and whether to clear the transfer count (normally needed when
* sending the first frame of a data packet). This is an example:
* @code
dspi_command_config_t commandConfig;
commandConfig.isChipSelectContinuous = true;
commandConfig.whichCtar = kDspiCtar0;
commandConfig.whichPcs = kDspiPcs1;
commandConfig.clearTransferCount = false;
commandConfig.isEndOfQueue = false;
dspi_hal_write_data_master_mode(instance, &commandConfig, dataWord);
* endcode
*
* @param instance Module instance number
* @param command Pointer to command structure
* @param data The data word to be sent
*/
void dspi_hal_write_data_master_mode(uint32_t instance,
dspi_command_config_t * command,
uint16_t data);
/*!
* @brief Gets the transfer count.
*
* This function returns the current value of the DSPI Transfer Count Register.
*
* @param instance Module instance number
* @return The current transfer count
*/
static inline uint32_t dspi_hal_get_transfer_count(uint32_t instance)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
return BR_SPI_TCR_SPI_TCNT(instance);
}
/*!
* @brief Pre-sets the transfer count.
*
* This function allows the caller to pre-set the DSI Transfer Count Register to a desired value up
* to 65535; Incrementing past this resets the counter back to 0.
*
* @param instance Module instance number
* @param presetValue The desired pre-set value for the transfer counter
*/
static inline void dspi_hal_preset_transfer_count(uint32_t instance, uint16_t presetValue)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_TCR_SPI_TCNT(instance, presetValue);
}
/*@}*/
/*!
* @name Debug
* @{
*/
/*!
* @brief Read FIFO registers for debug purposes.
*
* @param instance Module instance number
* @param whichFifo Selects Tx or Rx FIFO, of type dspi_fifo_t.
* @param whichFifoEntry Selects which FIFO entry to read: 0, 1, 2, or 3.
* @retrun The desired FIFO register contents
*/
uint32_t dspi_hal_get_fifo_data(uint32_t instance, dspi_fifo_t whichFifo, uint32_t whichFifoEntry);
/*!
* @brief Configures the DSPI to halt during debug mode.
*
* @param instance Module instance number
* @param enable Enables (true) debug mode to halt transfers, else disable to not halt transfer
* in debug mode.
*/
static inline void dspi_hal_configure_halt_in_debug_mode(uint32_t instance, bool enable)
{
assert(instance < HW_SPI_INSTANCE_COUNT);
BW_SPI_MCR_FRZ(instance, (enable == true));
}
/* @}*/
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* __FSL_DSPI_HAL_H__*/
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__FSL_DMA_FEATURES_H__)
#define __FSL_DMA_FEATURES_H__
#if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \
defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5)
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_MODULE_CHANNEL (4)
/* @brief Total number of DMA channels on all modules.*/
#define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 4)
/* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/
#define FSL_FEATURE_DMA_IS_EDMA (1)
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (1)
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
#elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MKV31F256VLH12) || \
defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31FN512VLH12) || defined(CPU_MKV31F512VLL12)
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_MODULE_CHANNEL (16)
/* @brief Total number of DMA channels on all modules.*/
#define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 16)
/* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/
#define FSL_FEATURE_DMA_IS_EDMA (1)
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (1)
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4)
#elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || \
defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VLQ12) || \
defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12)
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_MODULE_CHANNEL (16)
/* @brief Total number of DMA channels on all modules.*/
#define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 16)
/* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/
#define FSL_FEATURE_DMA_IS_EDMA (1)
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (1)
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
#elif defined(CPU_MK65FN2M0VMF18) || defined(CPU_MK65FX1M0VMF18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18)
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_MODULE_CHANNEL (32)
/* @brief Total number of DMA channels on all modules.*/
#define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 32)
/* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/
#define FSL_FEATURE_DMA_IS_EDMA (1)
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (2)
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
#elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_MODULE_CHANNEL (32)
/* @brief Total number of DMA channels on all modules.*/
#define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 32)
/* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/
#define FSL_FEATURE_DMA_IS_EDMA (1)
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (2)
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
#elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL25Z32VFM4) || \
defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \
defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL46Z128VLH4) || \
defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || \
defined(CPU_MKL46Z256VMC4)
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_MODULE_CHANNEL (4)
/* @brief Total number of DMA channels on all modules.*/
#define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 4)
/* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/
#define FSL_FEATURE_DMA_IS_EDMA (0)
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (0)
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/
#define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4)
#else
#error "No valid CPU defined!"
#endif
#endif /* __FSL_DMA_FEATURES_H__*/
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_edma_hal.h"
/*******************************************************************************
* Code
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : edma_hal_init
* Description : Init edma module.
*
*END**************************************************************************/
void edma_hal_init(uint32_t instance, const edma_config_t *init)
{
assert(instance < HW_DMA_INSTANCE_COUNT);
assert(init);
edma_hal_set_minor_loop_mapping(instance, init->isEnableMinorLoopping);
edma_hal_set_continuous_mode(instance, init->isEnableContinuousMode);
edma_hal_set_halt_on_error(instance, init->isHaltOnError);
if (init->isEnableRoundrobinArbitration)
{
edma_hal_set_roundrobin_channel_arbitration(instance);
}
else
{
edma_hal_set_fixed_priority_channel_arbitration(instance);
}
edma_hal_set_debug_mode(instance, init->isEnableDebug);
#if (FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT > 0x1U)
edma_hal_set_group_priority(instance, init->groupPriority);
if (init->isEnableGroupRoundrobinArbitration)
{
edma_hal_set_roundrobin_group_arbitration(instance);
}
else
{
edma_hal_set_fixed_priority_group_arbitration(instance);
}
#endif
}
/*FUNCTION**********************************************************************
*
* Function Name : edma_hal_stcd_push_to_htcd
* Description : Copy the configuration data from the software TCD to hardware TCD.
*
*END**************************************************************************/
void edma_hal_stcd_push_to_htcd(uint32_t instance, uint32_t channel, edma_software_tcd_t *stcd)
{
assert(instance < HW_DMA_INSTANCE_COUNT);
assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
assert(stcd);
HW_DMA_TCDn_SADDR_WR(instance, channel, stcd->SADDR);
HW_DMA_TCDn_SOFF_WR(instance, channel, stcd->SOFF);
HW_DMA_TCDn_ATTR_WR(instance, channel, stcd->ATTR);
HW_DMA_TCDn_NBYTES_MLNO_WR(instance, channel, stcd->NBYTES_MLNO);
HW_DMA_TCDn_SLAST_WR(instance, channel, stcd->SLAST);
HW_DMA_TCDn_DADDR_WR(instance, channel, stcd->DADDR);
HW_DMA_TCDn_DOFF_WR(instance, channel, stcd->DOFF);
HW_DMA_TCDn_CITER_ELINKYES_WR(instance, channel, stcd->CITER_ELINKYES);
HW_DMA_TCDn_DLASTSGA_WR(instance, channel, stcd->DLAST_SGA);
HW_DMA_TCDn_CSR_WR(instance, channel, stcd->CSR);
HW_DMA_TCDn_BITER_ELINKYES_WR(instance, channel, stcd->BITER_ELINKYES);
}
/*FUNCTION**********************************************************************
*
* Function Name : edma_hal_htcd_get_nbytes_configuration.
* Description : Get nbytes configuration data.
*
*END**************************************************************************/
uint32_t edma_hal_htcd_get_nbytes_configuration(uint32_t instance, uint32_t channel)
{
assert(instance < HW_DMA_INSTANCE_COUNT);
assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
if (BR_DMA_CR_EMLM(instance))
{
if (BR_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(instance, channel) ||
BR_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(instance, channel))
{
return BR_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(instance, channel);
}
else
{
return BR_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(instance, channel);
}
}
else
{
return BR_DMA_TCDn_NBYTES_MLNO_NBYTES(instance, channel);
}
}
/*FUNCTION**********************************************************************
*
* Function Name : edma_hal_htcd_get_current_major_count
* Description : Get current major loop count.
*
*END**************************************************************************/
uint32_t edma_hal_htcd_get_current_major_count(uint32_t instance, uint32_t channel)
{
assert(instance < HW_DMA_INSTANCE_COUNT);
assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
if (BR_DMA_TCDn_CITER_ELINKYES_ELINK(instance, channel))
{
return BR_DMA_TCDn_CITER_ELINKYES_CITER(instance, channel);
}
else
{
return BR_DMA_TCDn_CITER_ELINKNO_CITER(instance, channel);
}
}
/*FUNCTION**********************************************************************
*
* Function Name : edma_hal_htcd_get_begin_major_count
* Description : Get begin major loop count.
*
*END**************************************************************************/
uint32_t edma_hal_htcd_get_begin_major_count(uint32_t instance, uint32_t channel)
{
assert(instance < HW_DMA_INSTANCE_COUNT);
assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
if (BR_DMA_TCDn_BITER_ELINKYES_ELINK(instance, channel))
{
return BR_DMA_TCDn_BITER_ELINKYES_BITER(instance, channel);
}
else
{
return BR_DMA_TCDn_BITER_ELINKNO_BITER(instance, channel);
}
}
/*FUNCTION**********************************************************************
*
* Function Name : edma_hal_htcd_get_unfinished_bytes
* Description : Get the bytes number not be transferred for this hardware TCD.
*
*END**************************************************************************/
uint32_t edma_hal_htcd_get_unfinished_bytes(uint32_t instance, uint32_t channel)
{
assert(instance < HW_DMA_INSTANCE_COUNT);
assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
return edma_hal_htcd_get_current_major_count(instance, channel) *
edma_hal_htcd_get_nbytes_configuration(instance, channel);
}
/*FUNCTION**********************************************************************
*
* Function Name : edma_hal_htcd_get_finished_bytes
* Description : Get the bytes number already be transferred for this hardware TCD.
*
*END**************************************************************************/
uint32_t edma_hal_htcd_get_finished_bytes(uint32_t instance, uint32_t channel)
{
assert(instance < HW_DMA_INSTANCE_COUNT);
assert(channel < FSL_FEATURE_DMA_MODULE_CHANNEL);
return (edma_hal_htcd_get_begin_major_count(instance, channel) -
edma_hal_htcd_get_current_major_count(instance, channel)) *
edma_hal_htcd_get_nbytes_configuration(instance, channel);
}
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if !defined(__FSL_ENET_FEATURES_H__)
#define __FSL_ENET_FEATURES_H__
#if defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK63FN1M0VMD12WS) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12)
#define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (1)
#define FSL_FEATURE_ENET_SUPPORT_PTP (0)
#define FSL_FEATURE_ENET_INTERRUPT_COUNT (4)
#define FSL_FEATURE_ENET_PTP_TIMER_CHANNEL_INTERRUPT (0)
#elif defined(CPU_MK70FN1M0VMJ12)
#define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (1)
#define FSL_FEATURE_ENET_SUPPORT_PTP (0)
#define FSL_FEATURE_ENET_INTERRUPT_COUNT (4)
#else
#error "No valid CPU defined"
#endif
#endif /* __FSL_ENET_FEATURES_H__*/
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_enet_hal.h"
/*******************************************************************************
* Code
******************************************************************************/
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_set_mac_address
* Description: Set ENET mac physical address.
*
*END*********************************************************************/
void enet_hal_set_mac_address(uint32_t instance, enetMacAddr hwAddr)
{
assert(instance < HW_ENET_INSTANCE_COUNT);
uint32_t address, data;
address = (uint32_t)(((uint32_t)hwAddr[0] << 24U)|((uint32_t)hwAddr[1] << 16U)|((uint32_t)hwAddr[2] << 8U)| (uint32_t)hwAddr[3]) ;
HW_ENET_PALR_WR(instance,address); /* Set low physical address */
address = (uint32_t)(((uint32_t)hwAddr[4] << 24U)|((uint32_t)hwAddr[5] << 16U)) ;
data = HW_ENET_PAUR_RD(instance) & BM_ENET_PAUR_TYPE;
HW_ENET_PAUR_WR(instance, (data | address)); /* Set high physical address */
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_set_group_hashtable
* Description: Set multicast group address hash value to the mac register
* To join the multicast group address.
*END*********************************************************************/
void enet_hal_set_group_hashtable(uint32_t instance, uint32_t crcValue, enet_special_address_filter_t mode)
{
assert(instance < HW_ENET_INSTANCE_COUNT);
switch (mode)
{
case kEnetSpecialAddressInit: /* Clear group address register on ENET initialize */
HW_ENET_GALR_WR(instance,0);
HW_ENET_GAUR_WR(instance,0);
break;
case kEnetSpecialAddressEnable: /* Enable a multicast group address*/
if (!((crcValue >> 31) & 1U))
{
HW_ENET_GALR_SET(instance,(1U << ((crcValue >> 26) & kEnetHashValMask)));
}
else
{
HW_ENET_GAUR_SET(instance,(1U << ((crcValue >> 26) & kEnetHashValMask)));
}
break;
case kEnetSpecialAddressDisable: /* Disable a multicast group address*/
if (!((crcValue >> 31) & 1U))
{
HW_ENET_GALR_CLR(instance,(1U << ((crcValue >> 26) & kEnetHashValMask)));
}
else
{
HW_ENET_GAUR_CLR(instance,(1U << ((crcValue>>26) & kEnetHashValMask)));
}
break;
default:
break;
}
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_set_individual_hashtable
* Description: Set a specific unicast address hash value to the mac register
* To receive frames with the individual destination address.
*END*********************************************************************/
void enet_hal_set_individual_hashtable(uint32_t instance, uint32_t crcValue, enet_special_address_filter_t mode)
{
assert(instance < HW_ENET_INSTANCE_COUNT);
switch (mode)
{
case kEnetSpecialAddressInit: /* Clear individual address register on ENET initialize */
HW_ENET_IALR_WR(instance,0);
HW_ENET_IAUR_WR(instance,0);
break;
case kEnetSpecialAddressEnable: /* Enable a special address*/
if (((crcValue >>31) & 1U) == 0)
{
HW_ENET_IALR_SET(instance,(1U << ((crcValue>>26)& kEnetHashValMask)));
}
else
{
HW_ENET_IAUR_SET(instance,(1U << ((crcValue>>26)& kEnetHashValMask)));
}
break;
case kEnetSpecialAddressDisable: /* Disable a special address*/
if (((crcValue >>31) & 1U) == 0)
{
HW_ENET_IALR_CLR(instance,(1U << ((crcValue>>26)& kEnetHashValMask)));
}
else
{
HW_ENET_IAUR_CLR(instance,(1U << ((crcValue>>26)& kEnetHashValMask)));
}
break;
default:
break;
}
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_config_tx_fifo
* Description: Configure ENET transmit FIFO.
*END*********************************************************************/
void enet_hal_config_tx_fifo(uint32_t instance, enet_config_tx_fifo_t *thresholdCfg)
{
assert(instance < HW_ENET_INSTANCE_COUNT);
assert(thresholdCfg);
assert(thresholdCfg->txFifoWrite <= BM_ENET_TFWR_TFWR);
BW_ENET_TFWR_STRFWD(instance, thresholdCfg->isStoreForwardEnabled); /* Set store and forward mode*/
if(!thresholdCfg->isStoreForwardEnabled)
{
BW_ENET_TFWR_TFWR(instance, thresholdCfg->txFifoWrite); /* Set transmit FIFO write bytes*/
}
BW_ENET_TSEM_TX_SECTION_EMPTY(instance,thresholdCfg->txEmpty); /* Set transmit FIFO empty threshold*/
BW_ENET_TAEM_TX_ALMOST_EMPTY(instance,thresholdCfg->txAlmostEmpty); /* Set transmit FIFO almost empty threshold*/
BW_ENET_TAFL_TX_ALMOST_FULL(instance,thresholdCfg->txAlmostFull); /* Set transmit FIFO almost full threshold*/
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_config_rx_fifo
* Description: Configure ENET receive FIFO.
*END*********************************************************************/
void enet_hal_config_rx_fifo(uint32_t instance,enet_config_rx_fifo_t *thresholdCfg )
{
assert(instance < HW_ENET_INSTANCE_COUNT);
assert(thresholdCfg);
if(thresholdCfg->rxFull > 0)
{
assert(thresholdCfg->rxFull > thresholdCfg->rxAlmostEmpty);
}
BW_ENET_RSFL_RX_SECTION_FULL(instance,thresholdCfg->rxFull); /* Set receive FIFO full threshold*/
BW_ENET_RSEM_RX_SECTION_EMPTY(instance,thresholdCfg->rxEmpty); /* Set receive FIFO empty threshold*/
BW_ENET_RAEM_RX_ALMOST_EMPTY(instance,thresholdCfg->rxAlmostEmpty); /* Set receive FIFO almost empty threshold*/
BW_ENET_RAFL_RX_ALMOST_FULL(instance,thresholdCfg->rxAlmostFull); /* Set receive FIFO almost full threshold*/
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_init_rxbds
* Description: Initialize ENET receive buffer descriptors.
*END*********************************************************************/
void enet_hal_init_rxbds(void *rxBds, uint8_t *buffer, bool isLastBd)
{
assert(rxBds);
assert(buffer);
volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)rxBds;
bdPtr->buffer = (uint8_t *)NTOHL((uint32_t)buffer); /* Set data buffer address */
bdPtr->length = 0; /* Initialize data length*/
/*The last buffer descriptor should be set with the wrap flag*/
if (isLastBd)
{
bdPtr->control |= kEnetRxBdWrap;
}
bdPtr->control |= kEnetRxBdEmpty; /* Initialize bd with empty bit*/
bdPtr->controlExtend1 |= kEnetRxBdIntrrupt;/* Enable receive interrupt*/
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_init_txbds
* Description: Initialize ENET transmit buffer descriptors.
*END*********************************************************************/
void enet_hal_init_txbds(void *txBds, bool isLastBd)
{
assert(txBds);
volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)txBds;
bdPtr->length = 0; /* Initialize data length*/
/*The last buffer descriptor should be set with the wrap flag*/
if (isLastBd)
{
bdPtr->control |= kEnetTxBdWrap;
}
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_update_rxbds
* Description: Update ENET receive buffer descriptors.
*END*********************************************************************/
void enet_hal_update_rxbds(void *rxBds, uint8_t *data, bool isbufferUpdate)
{
assert(rxBds);
volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)rxBds;
if (isbufferUpdate)
{
bdPtr->buffer = (uint8_t *)HTONL((uint32_t)data);
}
bdPtr->control &= kEnetRxBdWrap; /* Clear status*/
bdPtr->control |= kEnetRxBdEmpty; /* Set rx bd empty*/
bdPtr->controlExtend1 |= kEnetRxBdIntrrupt;/* Enable interrupt*/
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_update_txbds
* Description: Update ENET transmit buffer descriptors.
*END*********************************************************************/
void enet_hal_update_txbds(void *txBds,uint8_t *buffer, uint16_t length, bool isTxtsCfged)
{
assert(txBds);
assert(buffer);
volatile enet_bd_struct_t * bdPtr = (enet_bd_struct_t *)txBds;
bdPtr->length = HTONS(length); /* Set data length*/
bdPtr->buffer = (uint8_t *)HTONL((uint32_t)buffer); /* Set data buffer*/
bdPtr->control |= kEnetTxBdLast | kEnetTxBdTransmitCrc | kEnetTxBdReady;/* set control */
if (isTxtsCfged)
{
/* Set receive and timestamp interrupt*/
bdPtr->controlExtend1 |= (kEnetTxBdTxInterrupt | kEnetTxBdTimeStamp);
}
else
{
/* Set receive interrupt*/
bdPtr->controlExtend1 |= kEnetTxBdTxInterrupt;
}
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_get_rxbd_control
* Description: Get receive buffer descriptor control and status region.
*END*********************************************************************/
uint16_t enet_hal_get_rxbd_control(void *curBd)
{
assert(curBd);
volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd;
return bdPtr->control;
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_get_txbd_control
* Description: Get ENET transmit buffer descriptor control and status data.
*END*********************************************************************/
uint16_t enet_hal_get_txbd_control(void *curBd)
{
assert(curBd);
volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd;
return bdPtr->control;
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_get_bd_length
* Description: Get ENET data length of buffer descriptors.
*END*********************************************************************/
uint16_t enet_hal_get_bd_length(void *curBd)
{
assert(curBd);
uint16_t length;
volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd;
length = bdPtr->length;
return NTOHS(length);
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_get_bd_buffer
* Description: Get the buffer address of buffer descriptors.
*END*********************************************************************/
uint8_t* enet_hal_get_bd_buffer(void *curBd)
{
assert(curBd);
volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd;
uint32_t buffer = (uint32_t)(bdPtr->buffer);
return (uint8_t *)NTOHL(buffer);
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_get_bd_timestamp
* Description: Get the timestamp of buffer descriptors.
*END*********************************************************************/
uint32_t enet_hal_get_bd_timestamp(void *curBd)
{
assert(curBd);
volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd;
uint32_t timestamp = bdPtr->timestamp;
return NTOHL(timestamp);
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_get_rxbd_control_extend
* Description: Get ENET receive buffer descriptor extended control region.
*END*********************************************************************/
bool enet_hal_get_rxbd_control_extend(void *curBd,enet_rx_bd_control_extend_t controlRegion)
{
assert(curBd);
volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd;
#if SYSTEM_LITTLE_ENDIAN && FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY
if (((uint16_t)controlRegion > kEnetRxBdCtlJudge1) && ((uint16_t)controlRegion < kEnetRxBdCtlJudge2))
{
return ((bdPtr->controlExtend0 & controlRegion) != 0); /* Control extended0 region*/
}
else
{
return ((bdPtr->controlExtend1 & controlRegion) != 0); /* Control extended1 region*/
}
#else
if( (uint16_t)controlRegion < kEnetRxBdCtlJudge1)
{
return ((bdPtr->controlExtend0 & controlRegion) != 0); /* Control extended0 region*/
}
else
{
return ((bdPtr->controlExtend1 & controlRegion) != 0);/* Control extended1 region*/
}
#endif
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_get_txbd_control_extend
* Description: Get ENET transmit buffer descriptor extended control region.
*END*********************************************************************/
uint16_t enet_hal_get_txbd_control_extend(void *curBd)
{
assert(curBd);
volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd;
return bdPtr->controlExtend0;
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_get_txbd_timestamp_flag
* Description: Get ENET transmit buffer descriptor timestamp region.
*END*********************************************************************/
bool enet_hal_get_txbd_timestamp_flag(void *curBd)
{
assert(curBd);
volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd;
return ((bdPtr->controlExtend1 & kEnetTxBdTimeStamp) != 0);
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_config_rmii
* Description: Configure (R)MII mode.
*END*********************************************************************/
void enet_hal_config_rmii(uint32_t instance, enet_config_rmii_t mode, enet_config_speed_t speed, enet_config_duplex_t duplex, bool isRxOnTxDisabled, bool isLoopEnabled)
{
assert(instance < HW_ENET_INSTANCE_COUNT);
BW_ENET_RCR_MII_MODE(instance,1); /* Set mii mode */
BW_ENET_RCR_RMII_MODE(instance,mode);
BW_ENET_RCR_RMII_10T(instance,speed); /* Set speed mode */
BW_ENET_TCR_FDEN(instance,duplex); /* Set duplex mode*/
if ((!duplex) && isRxOnTxDisabled)
{
BW_ENET_RCR_DRT(instance,1); /* Disable receive on transmit*/
}
if (mode == kEnetCfgMii) /* Set internal loop only for mii mode*/
{
BW_ENET_RCR_LOOP(instance,isLoopEnabled);
}
else
{
BW_ENET_RCR_LOOP(instance, 0); /* Clear internal loop for rmii mode*/
}
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_set_mii_command
* Description: Set MII command.
*END*********************************************************************/
void enet_hal_set_mii_command(uint32_t instance, uint32_t phyAddr, uint32_t phyReg, enet_mii_operation_t operation, uint32_t data)
{
assert(instance < HW_ENET_INSTANCE_COUNT);
uint32_t mmfrValue = 0 ;
mmfrValue = BF_ENET_MMFR_ST(1)| BF_ENET_MMFR_OP(operation)| BF_ENET_MMFR_PA(phyAddr) | BF_ENET_MMFR_RA(phyReg)| BF_ENET_MMFR_TA(2) | (data&0xFFFF); /* mii command*/
HW_ENET_MMFR_WR(instance,mmfrValue);
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_config_ethernet
* Description: Enable or disable normal Ethernet mode and enhanced mode.
*END*********************************************************************/
void enet_hal_config_ethernet(uint32_t instance, bool isEnhanced, bool isEnabled)
{
assert(instance < HW_ENET_INSTANCE_COUNT);
BW_ENET_ECR_ETHEREN(instance,isEnabled); /* Enable/Disable Ethernet module*/
if (isEnhanced)
{
BW_ENET_ECR_EN1588(instance,isEnabled); /* Enable/Disable enhanced frame feature*/
}
#if SYSTEM_LITTLE_ENDIAN && !FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY
BW_ENET_ECR_DBSWP(instance,1); /* buffer descriptor byte swapping for little-endian system and endianness configurable IP*/
#endif
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_config_interrupt
* Description: Enable or disable different Ethernet interrupts.
* the parameter source is the interrupt source and enet_interrupt_request_t
* enum types is recommended to be used as the interrupt sources.
*END*********************************************************************/
void enet_hal_config_interrupt(uint32_t instance, uint32_t source, bool isEnabled)
{
assert(instance < HW_ENET_INSTANCE_COUNT);
if (isEnabled)
{
HW_ENET_EIMR_SET(instance,source); /* Enable interrupt */
}
else
{
HW_ENET_EIMR_CLR(instance,source); /* Disable interrupt*/
}
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_config_tx_accelerator
* Description: Configure Ethernet transmit accelerator features.
*END*********************************************************************/
void enet_hal_config_tx_accelerator(uint32_t instance, enet_config_tx_accelerator_t *txCfgPtr)
{
assert(instance < HW_ENET_INSTANCE_COUNT);
assert(txCfgPtr);
HW_ENET_TACC_WR(instance,0); /* Clear all*/
BW_ENET_TACC_IPCHK(instance,txCfgPtr->isIpCheckEnabled); /* Insert ipheader checksum */
BW_ENET_TACC_PROCHK(instance,txCfgPtr->isProtocolCheckEnabled); /* Insert protocol checksum*/
BW_ENET_TACC_SHIFT16(instance,txCfgPtr->isShift16Enabled); /* Set tx fifo shift-16*/
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_config_rx_accelerator
* Description: Configure Ethernet receive accelerator features.
*END*********************************************************************/
void enet_hal_config_rx_accelerator(uint32_t instance, enet_config_rx_accelerator_t *rxCfgPtr)
{
assert(instance < HW_ENET_INSTANCE_COUNT);
assert(rxCfgPtr);
HW_ENET_RACC_WR(instance,0); /* Clear all*/
BW_ENET_RACC_IPDIS(instance,rxCfgPtr->isIpcheckEnabled); /* Set ipchecksum field*/
BW_ENET_RACC_PRODIS(instance,rxCfgPtr->isProtocolCheckEnabled); /* Set protocol field*/
BW_ENET_RACC_LINEDIS(instance,rxCfgPtr->isMacCheckEnabled); /* Set maccheck field*/
BW_ENET_RACC_SHIFT16(instance,rxCfgPtr->isShift16Enabled); /* Set rx fifo shift field*/
BW_ENET_RACC_PADREM(instance,rxCfgPtr->isPadRemoveEnabled); /* Set rx padding remove field*/
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_set_txpause
* Return Value: The execution status.
* Description: Set the ENET transmit controller with pause duration and
* Set enet transmit PAUSE frame transmission.
* This should be called when a PAUSE frame is dynamically wanted.
*END*********************************************************************/
void enet_hal_set_txpause(uint32_t instance, uint32_t pauseDuration)
{
assert(instance < HW_ENET_INSTANCE_COUNT);
assert(pauseDuration <= BM_ENET_OPD_PAUSE_DUR);
BW_ENET_OPD_PAUSE_DUR(instance, pauseDuration);
BW_ENET_TCR_TFC_PAUSE(instance, 1);
}
/*FUNCTION****************************************************************
*
* Function Name: enet_hal_init_ptp_timer
* Description: Initialize Ethernet ptp timer.
*END*********************************************************************/
void enet_hal_init_ptp_timer(uint32_t instance,enet_config_ptp_timer_t *ptpCfgPtr)
{
assert(instance < HW_ENET_INSTANCE_COUNT);
assert(ptpCfgPtr);
BW_ENET_ATINC_INC(instance, ptpCfgPtr->clockIncease); /* Set increase value for ptp timer*/
HW_ENET_ATPER_WR(instance, ptpCfgPtr->period); /* Set wrap time for ptp timer*/
/* set periodical event and the event signal output assertion*/
BW_ENET_ATCR_PEREN(instance, 1);
BW_ENET_ATCR_PINPER(instance, 1);
/* Set ptp timer slave/master mode*/
BW_ENET_ATCR_SLAVE(instance, ptpCfgPtr->isSlaveEnabled);
}
/*******************************************************************************
* EOF
******************************************************************************/

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