mirror of https://github.com/ARMmbed/mbed-os.git
Modify and add a file to support GCC. (mbed common codes)
Masao Hamanaka
parent
f6f45026f6
commit
0365977217
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@ -459,6 +459,10 @@ extern "C" void __iar_argc_argv() {
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// Linker defined symbol used by _sbrk to indicate where heap should start.
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extern "C" int __end__;
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#if (TARGET_CORTEX_A)
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extern "C" uint32_t __HeapLimit;
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#endif
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// Turn off the errno macro and use actual global variable instead.
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#undef errno
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extern "C" int errno;
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@ -474,6 +478,8 @@ extern "C" caddr_t _sbrk(int incr) {
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#if defined(TARGET_ARM7)
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if (new_heap >= stack_ptr) {
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#elif (TARGET_CORTEX_A)
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if (new_heap >= (unsigned char*)&__HeapLimit) { /* __HeapLimit is end of heap section */
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#else
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if (new_heap >= (unsigned char*)__get_MSP()) {
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#endif
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@ -0,0 +1,94 @@
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/* Copyright (c) 2009 - 2012 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------
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* Functions
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*---------------------------------------------------------------------------*/
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.text
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.global __v7_all_cache
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/*
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* __STATIC_ASM void __v7_all_cache(uint32_t op) {
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*/
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__v7_all_cache:
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.arm
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PUSH {R4-R11}
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MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
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ANDS R3, R6, #0x07000000 // Extract coherency level
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MOV R3, R3, LSR #23 // Total cache levels << 1
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BEQ Finished // If 0, no need to clean
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MOV R10, #0 // R10 holds current cache level << 1
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Loop1: ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
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MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
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AND R1, R1, #7 // Isolate those lower 3 bits
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CMP R1, #2
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BLT Skip // No cache or only instruction cache at this level
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MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
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ISB // ISB to sync the change to the CacheSizeID reg
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MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
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AND R2, R1, #7 // Extract the line length field
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ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
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LDR R4, =0x3FF
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ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
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CLZ R5, R4 // R5 is the bit position of the way size increment
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LDR R7, =0x7FFF
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ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
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Loop2: MOV R9, R4 // R9 working copy of the max way size (right aligned)
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Loop3: ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
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ORR R11, R11, R7, LSL R2 // Factor in the Set number
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CMP R0, #0
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BNE Dccsw
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MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
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B cont
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Dccsw: CMP R0, #1
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BNE Dccisw
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MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
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B cont
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Dccisw: MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way
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cont: SUBS R9, R9, #1 // Decrement the Way number
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BGE Loop3
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SUBS R7, R7, #1 // Decrement the Set number
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BGE Loop2
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Skip: ADD R10, R10, #2 // increment the cache number
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CMP R3, R10
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BGT Loop1
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Finished:
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DSB
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POP {R4-R11}
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BX lr
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.END
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/*----------------------------------------------------------------------------
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* end of file
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*---------------------------------------------------------------------------*/
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@ -578,7 +578,576 @@ __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
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#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
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//#error GNU Compiler support not implemented for Cortex-A
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/* GNU gcc specific functions */
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#define MODE_USR 0x10
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#define MODE_FIQ 0x11
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#define MODE_IRQ 0x12
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#define MODE_SVC 0x13
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#define MODE_MON 0x16
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#define MODE_ABT 0x17
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#define MODE_HYP 0x1A
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#define MODE_UND 0x1B
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#define MODE_SYS 0x1F
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
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{
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__ASM volatile ("cpsie i");
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}
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/** \brief Disable IRQ Interrupts
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This function disables IRQ interrupts by setting the I-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
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{
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uint32_t result;
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__ASM volatile ("mrs %0, cpsr" : "=r" (result));
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__ASM volatile ("cpsid i");
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return(result & 0x80);
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}
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/** \brief Get APSR Register
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This function returns the content of the APSR Register.
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\return APSR Register value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
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{
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#if 1
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uint32_t result;
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__ASM volatile ("mrs %0, apsr" : "=r" (result) );
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return (result);
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#else
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register uint32_t __regAPSR __ASM("apsr");
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return(__regAPSR);
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#endif
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}
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/** \brief Get CPSR Register
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This function returns the content of the CPSR Register.
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\return CPSR Register value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
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{
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#if 1
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register uint32_t __regCPSR;
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__ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
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#else
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register uint32_t __regCPSR __ASM("cpsr");
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#endif
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return(__regCPSR);
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}
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#if 0
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/** \brief Set Stack Pointer
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This function assigns the given value to the current stack pointer.
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\param [in] topOfStack Stack Pointer value to set
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
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{
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register uint32_t __regSP __ASM("sp");
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__regSP = topOfStack;
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}
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#endif
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/** \brief Get link register
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This function returns the value of the link register
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\return Value of link register
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
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{
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register uint32_t __reglr __ASM("lr");
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return(__reglr);
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}
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#if 0
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/** \brief Set link register
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This function sets the value of the link register
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\param [in] lr LR value to set
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
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{
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register uint32_t __reglr __ASM("lr");
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__reglr = lr;
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}
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#endif
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/** \brief Set Process Stack Pointer
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This function assigns the given value to the USR/SYS Stack Pointer (PSP).
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\param [in] topOfProcStack USR/SYS Stack Pointer value to set
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*/
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extern void __set_PSP(uint32_t topOfProcStack);
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/** \brief Set User Mode
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This function changes the processor state to User Mode
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\param [in] topOfProcStack USR/SYS Stack Pointer value to set
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*/
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extern void __set_CPS_USR(void);
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/** \brief Enable FIQ
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This function enables FIQ interrupts by clearing the F-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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#define __enable_fault_irq __enable_fiq
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/** \brief Disable FIQ
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This function disables FIQ interrupts by setting the F-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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#define __disable_fault_irq __disable_fiq
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/** \brief Get FPSCR
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This function returns the current value of the Floating Point Status/Control register.
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\return Floating Point Status/Control register value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
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{
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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#if 1
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uint32_t result;
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__ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
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return (result);
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#else
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register uint32_t __regfpscr __ASM("fpscr");
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return(__regfpscr);
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#endif
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#else
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return(0);
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#endif
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}
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/** \brief Set FPSCR
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This function assigns the given value to the Floating Point Status/Control register.
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\param [in] fpscr Floating Point Status/Control value to set
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
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{
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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#if 1
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__ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
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#else
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register uint32_t __regfpscr __ASM("fpscr");
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__regfpscr = (fpscr);
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#endif
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#endif
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}
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/** \brief Get FPEXC
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This function returns the current value of the Floating Point Exception Control register.
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\return Floating Point Exception Control register value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
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{
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#if (__FPU_PRESENT == 1)
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#if 1
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uint32_t result;
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__ASM volatile ("vmrs %0, fpexc" : "=r" (result));
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return (result);
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#else
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register uint32_t __regfpexc __ASM("fpexc");
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return(__regfpexc);
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#endif
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#else
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return(0);
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#endif
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}
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/** \brief Set FPEXC
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This function assigns the given value to the Floating Point Exception Control register.
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\param [in] fpscr Floating Point Exception Control value to set
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
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{
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#if (__FPU_PRESENT == 1)
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#if 1
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__ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
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#else
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register uint32_t __regfpexc __ASM("fpexc");
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__regfpexc = (fpexc);
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#endif
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#endif
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}
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/** \brief Get CPACR
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This function returns the current value of the Coprocessor Access Control register.
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\return Coprocessor Access Control register value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
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{
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#if 1
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register uint32_t __regCPACR;
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__ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
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#else
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register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
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#endif
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return __regCPACR;
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}
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/** \brief Set CPACR
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This function assigns the given value to the Coprocessor Access Control register.
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\param [in] cpacr Coporcessor Acccess Control value to set
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
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{
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#if 1
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__ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
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#else
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register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
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__regCPACR = cpacr;
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#endif
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__ISB();
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}
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/** \brief Get CBAR
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This function returns the value of the Configuration Base Address register.
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\return Configuration Base Address register value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
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#if 1
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register uint32_t __regCBAR;
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__ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
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#else
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register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
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#endif
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return(__regCBAR);
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}
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/** \brief Get TTBR0
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This function returns the value of the Configuration Base Address register.
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\return Translation Table Base Register 0 value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
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#if 1
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register uint32_t __regTTBR0;
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__ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
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#else
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register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
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#endif
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return(__regTTBR0);
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}
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/** \brief Set TTBR0
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This function assigns the given value to the Coprocessor Access Control register.
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\param [in] ttbr0 Translation Table Base Register 0 value to set
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
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#if 1
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__ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
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#else
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register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
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__regTTBR0 = ttbr0;
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#endif
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__ISB();
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}
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/** \brief Get DACR
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This function returns the value of the Domain Access Control Register.
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\return Domain Access Control Register value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
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#if 1
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register uint32_t __regDACR;
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__ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
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#else
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register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
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#endif
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return(__regDACR);
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}
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/** \brief Set DACR
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This function assigns the given value to the Coprocessor Access Control register.
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\param [in] dacr Domain Access Control Register value to set
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
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#if 1
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__ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
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#else
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register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
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__regDACR = dacr;
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#endif
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__ISB();
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}
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/******************************** Cache and BTAC enable ****************************************************/
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/** \brief Set SCTLR
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This function assigns the given value to the System Control Register.
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\param [in] sctlr System Control Register, value to set
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
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{
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#if 1
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__ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
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#else
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register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
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__regSCTLR = sctlr;
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#endif
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}
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/** \brief Get SCTLR
|
||||
|
||||
This function returns the value of the System Control Register.
|
||||
|
||||
\return System Control Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
|
||||
#if 1
|
||||
register uint32_t __regSCTLR;
|
||||
__ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
|
||||
#else
|
||||
register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
|
||||
#endif
|
||||
return(__regSCTLR);
|
||||
}
|
||||
|
||||
/** \brief Enable Caches
|
||||
|
||||
Enable Caches
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
|
||||
// Set I bit 12 to enable I Cache
|
||||
// Set C bit 2 to enable D Cache
|
||||
__set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
|
||||
}
|
||||
|
||||
/** \brief Disable Caches
|
||||
|
||||
Disable Caches
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
|
||||
// Clear I bit 12 to disable I Cache
|
||||
// Clear C bit 2 to disable D Cache
|
||||
__set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** \brief Enable BTAC
|
||||
|
||||
Enable BTAC
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
|
||||
// Set Z bit 11 to enable branch prediction
|
||||
__set_SCTLR( __get_SCTLR() | (1 << 11));
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** \brief Disable BTAC
|
||||
|
||||
Disable BTAC
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
|
||||
// Clear Z bit 11 to disable branch prediction
|
||||
__set_SCTLR( __get_SCTLR() & ~(1 << 11));
|
||||
}
|
||||
|
||||
|
||||
/** \brief Enable MMU
|
||||
|
||||
Enable MMU
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
|
||||
// Set M bit 0 to enable the MMU
|
||||
// Set AFE bit to enable simplified access permissions model
|
||||
// Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
|
||||
__set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** \brief Enable MMU
|
||||
|
||||
Enable MMU
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
|
||||
// Clear M bit 0 to disable the MMU
|
||||
__set_SCTLR( __get_SCTLR() & ~1);
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/******************************** TLB maintenance operations ************************************************/
|
||||
/** \brief Invalidate the whole tlb
|
||||
|
||||
TLBIALL. Invalidate the whole tlb
|
||||
*/
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
|
||||
#if 1
|
||||
__ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
|
||||
#else
|
||||
register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
|
||||
__TLBIALL = 0;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/******************************** BTB maintenance operations ************************************************/
|
||||
/** \brief Invalidate entire branch predictor array
|
||||
|
||||
BPIALL. Branch Predictor Invalidate All.
|
||||
*/
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
|
||||
#if 1
|
||||
__ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
|
||||
#else
|
||||
register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
|
||||
__BPIALL = 0;
|
||||
#endif
|
||||
__DSB(); //ensure completion of the invalidation
|
||||
__ISB(); //ensure instruction fetch path sees new state
|
||||
}
|
||||
|
||||
|
||||
/******************************** L1 cache operations ******************************************************/
|
||||
|
||||
/** \brief Invalidate the whole I$
|
||||
|
||||
ICIALLU. Instruction Cache Invalidate All to PoU
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
|
||||
#if 1
|
||||
__ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
|
||||
#else
|
||||
register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
|
||||
__ICIALLU = 0;
|
||||
#endif
|
||||
__DSB(); //ensure completion of the invalidation
|
||||
__ISB(); //ensure instruction fetch path sees new I cache state
|
||||
}
|
||||
|
||||
/** \brief Clean D$ by MVA
|
||||
|
||||
DCCMVAC. Data cache clean by MVA to PoC
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
|
||||
#if 1
|
||||
__ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
|
||||
#else
|
||||
register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
|
||||
__DCCMVAC = (uint32_t)va;
|
||||
#endif
|
||||
__DMB(); //ensure the ordering of data cache maintenance operations and their effects
|
||||
}
|
||||
|
||||
/** \brief Invalidate D$ by MVA
|
||||
|
||||
DCIMVAC. Data cache invalidate by MVA to PoC
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
|
||||
#if 1
|
||||
__ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
|
||||
#else
|
||||
register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
|
||||
__DCIMVAC = (uint32_t)va;
|
||||
#endif
|
||||
__DMB(); //ensure the ordering of data cache maintenance operations and their effects
|
||||
}
|
||||
|
||||
/** \brief Clean and Invalidate D$ by MVA
|
||||
|
||||
DCCIMVAC. Data cache clean and invalidate by MVA to PoC
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
|
||||
#if 1
|
||||
__ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
|
||||
#else
|
||||
register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
|
||||
__DCCIMVAC = (uint32_t)va;
|
||||
#endif
|
||||
__DMB(); //ensure the ordering of data cache maintenance operations and their effects
|
||||
}
|
||||
|
||||
/** \brief
|
||||
* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
|
||||
*/
|
||||
|
||||
/** \brief __v7_all_cache - helper function
|
||||
|
||||
*/
|
||||
|
||||
extern void __v7_all_cache(uint32_t op);
|
||||
|
||||
|
||||
/** \brief Invalidate the whole D$
|
||||
|
||||
DCISW. Invalidate by Set/Way
|
||||
*/
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
|
||||
__v7_all_cache(0);
|
||||
}
|
||||
|
||||
/** \brief Clean the whole D$
|
||||
|
||||
DCCSW. Clean by Set/Way
|
||||
*/
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
|
||||
__v7_all_cache(1);
|
||||
}
|
||||
|
||||
/** \brief Clean and invalidate the whole D$
|
||||
|
||||
DCCISW. Clean and Invalidate by Set/Way
|
||||
*/
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
|
||||
__v7_all_cache(2);
|
||||
}
|
||||
|
||||
#include "core_ca_mmu.h"
|
||||
|
||||
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue