ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge remote-tracking branch 'upstream/master' 

Conflicts:
	libraries/tests/mbed/portinout/main.cpp
	libraries/tests/mbed/portout_portin/main.cpp
	libraries/tests/mbed/sd/main.cpp
	libraries/tests/mbed/spi_slave/main.cpp
	workspace_tools/targets.py
	workspace_tools/toolchains/arm.py
	workspace_tools/toolchains/gcc.py
	workspace_tools/toolchains/iar.py
pull/159/head
tkuyucu 2014-02-07 11:04:50 +01:00
parent 9b701f6a49 281fcc76b6
commit 026b6610a8
538 changed files with 179038 additions and 3387 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

96
MANIFEST
View File

@ -1,96 +0,0 @@
# file GENERATED by distutils, do NOT edit
LICENSE
setup.py
workspace_tools/__init__.py
workspace_tools/__init__.pyc
workspace_tools/autotest.py
workspace_tools/build.py
workspace_tools/build_api.py
workspace_tools/build_release.py
workspace_tools/client.py
workspace_tools/export_test.py
workspace_tools/hooks.py
workspace_tools/libraries.py
workspace_tools/make.py
workspace_tools/options.py
workspace_tools/patch.py
workspace_tools/paths.py
workspace_tools/project.py
workspace_tools/server.py
workspace_tools/settings.py
workspace_tools/size.py
workspace_tools/syms.py
workspace_tools/synch.py
workspace_tools/targets.py
workspace_tools/tests.py
workspace_tools/utils.py
workspace_tools/data/__init__.py
workspace_tools/data/example_test_spec.json
workspace_tools/data/support.py
workspace_tools/data/rpc/RPCClasses.h
workspace_tools/data/rpc/class.cpp
workspace_tools/dev/__init__.py
workspace_tools/dev/dsp_fir.py
workspace_tools/dev/rpc_classes.py
workspace_tools/export/__init__.py
workspace_tools/export/codered.py
workspace_tools/export/codered_lpc1768_cproject.tmpl
workspace_tools/export/codered_lpc1768_project.tmpl
workspace_tools/export/codered_lpc4088_cproject.tmpl
workspace_tools/export/codered_lpc4088_project.tmpl
workspace_tools/export/codesourcery.py
workspace_tools/export/codesourcery_lpc1768.tmpl
workspace_tools/export/ds5_5.py
workspace_tools/export/ds5_5_lpc11u24.cproject.tmpl
workspace_tools/export/ds5_5_lpc11u24.launch.tmpl
workspace_tools/export/ds5_5_lpc11u24.project.tmpl
workspace_tools/export/ds5_5_lpc1768.cproject.tmpl
workspace_tools/export/ds5_5_lpc1768.launch.tmpl
workspace_tools/export/ds5_5_lpc1768.project.tmpl
workspace_tools/export/exporters.py
workspace_tools/export/gcc_arm_lpc1768.tmpl
workspace_tools/export/gccarm.py
workspace_tools/export/iar.ewp.tmpl
workspace_tools/export/iar.eww.tmpl
workspace_tools/export/iar.py
workspace_tools/export/uvision4.py
workspace_tools/export/uvision4_kl25z.uvopt.tmpl
workspace_tools/export/uvision4_kl25z.uvproj.tmpl
workspace_tools/export/uvision4_lpc1114.uvopt.tmpl
workspace_tools/export/uvision4_lpc1114.uvproj.tmpl
workspace_tools/export/uvision4_lpc11c24.uvopt.tmpl
workspace_tools/export/uvision4_lpc11c24.uvproj.tmpl
workspace_tools/export/uvision4_lpc11u24.uvopt.tmpl
workspace_tools/export/uvision4_lpc11u24.uvproj.tmpl
workspace_tools/export/uvision4_lpc1347.uvopt.tmpl
workspace_tools/export/uvision4_lpc1347.uvproj.tmpl
workspace_tools/export/uvision4_lpc1768.uvopt.tmpl
workspace_tools/export/uvision4_lpc1768.uvproj.tmpl
workspace_tools/export/uvision4_lpc4088.uvopt.tmpl
workspace_tools/export/uvision4_lpc4088.uvproj.tmpl
workspace_tools/export/uvision4_lpc812.uvopt.tmpl
workspace_tools/export/uvision4_lpc812.uvproj.tmpl
workspace_tools/host_tests/__init__.py
workspace_tools/host_tests/echo.py
workspace_tools/host_tests/host_test.py
workspace_tools/host_tests/mbedrpc.py
workspace_tools/host_tests/net_test.py
workspace_tools/host_tests/rpc.py
workspace_tools/host_tests/tcpecho_client.py
workspace_tools/host_tests/tcpecho_server.py
workspace_tools/host_tests/tcpecho_server_loop.py
workspace_tools/host_tests/udpecho_client.py
workspace_tools/host_tests/udpecho_server.py
workspace_tools/host_tests/example/BroadcastReceive.py
workspace_tools/host_tests/example/BroadcastSend.py
workspace_tools/host_tests/example/MulticastReceive.py
workspace_tools/host_tests/example/MulticastSend.py
workspace_tools/host_tests/example/TCPEchoClient.py
workspace_tools/host_tests/example/TCPEchoServer.py
workspace_tools/host_tests/example/UDPEchoClient.py
workspace_tools/host_tests/example/UDPEchoServer.py
workspace_tools/host_tests/example/__init__.py
workspace_tools/toolchains/__init__.py
workspace_tools/toolchains/arm.py
workspace_tools/toolchains/gcc.py
workspace_tools/toolchains/iar.py

3
MANIFEST.in
View File

@ -1,2 +1,3 @@
graft workspace_tools
include __init__.py LICENSE
recursive-exclude workspace_tools *.pyc
include LICENSE

8
README.md
View File

@ -1,5 +1,5 @@
mbed SDK
========
mbed SDK
========
[![Build Status](https://travis-ci.org/mbedmicro/mbed.png)](https://travis-ci.org/mbedmicro/mbed/builds)
@ -24,6 +24,7 @@ Supported Microcontrollers
--------------------------
NXP:
* [LPC1768](http://mbed.org/platforms/mbed-LPC1768/) (Cortex-M3)
* [LPC1768](http://mbed.org/platforms/u-blox-C027/) (Cortex-M3)
* [LPC11U24](http://mbed.org/platforms/mbed-LPC11U24/) (Cortex-M0)
* LPC2368 (ARM7TDMI-S)
* LPC810 (Cortex-M0+)
@ -35,8 +36,9 @@ NXP:
* LPC11C24 (Cortex-M0)
Freescale:
* [KL25Z](http://mbed.org/platforms/KL25Z/) (Cortex-M0+)
* KL05Z (Cortex-M0+)
* [KL25Z](http://mbed.org/platforms/KL25Z/) (Cortex-M0+)
* [KL46Z](https://mbed.org/platforms/FRDM-KL46Z/) (Cortex-M0+)
STMicroelectronics:
* STM32F407 (Cortex-M4)

2
libraries/USBDevice/USBDevice/USBDevice.cpp
View File

@ -926,7 +926,7 @@ uint8_t * USBDevice::stringLangidDesc() {
static uint8_t stringLangidDescriptor[] = {
0x04, /*bLength*/
STRING_DESCRIPTOR, /*bDescriptorType 0x03*/
0x09,0x00, /*bString Lang ID - 0x009 - English*/
0x09,0x04, /*bString Lang ID - 0x0409 - English*/
};
return stringLangidDescriptor;
}

2
libraries/USBDevice/USBDevice/USBDevice_Types.h
View File

@ -49,7 +49,7 @@
/* Descriptors */
#define DESCRIPTOR_TYPE(wValue) (wValue >> 8)
#define DESCRIPTOR_INDEX(wValue) (wValue & 0xf)
#define DESCRIPTOR_INDEX(wValue) (wValue & 0xff)
typedef struct {
struct {

2
libraries/USBDevice/USBDevice/USBEndpoints.h
View File

@ -43,6 +43,8 @@ typedef enum {
#include "USBEndpoints_LPC11U.h"
#elif defined(TARGET_KL25Z)
#include "USBEndpoints_KL25Z.h"
#elif defined (TARGET_STM32F4XX)
#include "USBEndpoints_STM32F4.h"
#else
#error "Unknown target type"
#endif

61
libraries/USBDevice/USBDevice/USBEndpoints_STM32F4.h Normal file
View File

@ -0,0 +1,61 @@
/* Copyright (c) 2010-2011 mbed.org, MIT License
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define NUMBER_OF_LOGICAL_ENDPOINTS (4)
#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS * 2)
/* Define physical endpoint numbers */
/* Endpoint No. Type(s) MaxPacket DoubleBuffer */
/* ---------------- ------------ ---------- --- */
#define EP0OUT (0) /* Control 64 No */
#define EP0IN (1) /* Control 64 No */
#define EP1OUT (2) /* Int/Bulk/Iso 64/64/1023 Yes */
#define EP1IN (3) /* Int/Bulk/Iso 64/64/1023 Yes */
#define EP2OUT (4) /* Int/Bulk/Iso 64/64/1023 Yes */
#define EP2IN (5) /* Int/Bulk/Iso 64/64/1023 Yes */
#define EP3OUT (6) /* Int/Bulk/Iso 64/64/1023 Yes */
#define EP3IN (7) /* Int/Bulk/Iso 64/64/1023 Yes */
/* Maximum Packet sizes */
#define MAX_PACKET_SIZE_EP0 (64)
#define MAX_PACKET_SIZE_EP1 (64) /* Int/Bulk */
#define MAX_PACKET_SIZE_EP2 (64) /* Int/Bulk */
#define MAX_PACKET_SIZE_EP3 (64) /* Int/Bulk */
#define MAX_PACKET_SIZE_EP1_ISO (1023) /* Isochronous */
#define MAX_PACKET_SIZE_EP2_ISO (1023) /* Isochronous */
#define MAX_PACKET_SIZE_EP3_ISO (1023) /* Isochronous */
/* Generic endpoints - intended to be portable accross devices */
/* and be suitable for simple USB devices. */
/* Bulk endpoint */
#define EPBULK_OUT (EP2OUT)
#define EPBULK_IN (EP2IN)
/* Interrupt endpoint */
#define EPINT_OUT (EP1OUT)
#define EPINT_IN (EP1IN)
/* Isochronous endpoint */
#define EPISO_OUT (EP3OUT)
#define EPISO_IN (EP3IN)
#define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2)
#define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1)
#define MAX_PACKET_SIZE_EPISO (MAX_PACKET_SIZE_EP3_ISO)

5
libraries/USBDevice/USBDevice/USBHAL.h
View File

@ -74,9 +74,9 @@ protected:
virtual bool EP2_IN_callback(){return false;};
virtual bool EP3_OUT_callback(){return false;};
virtual bool EP3_IN_callback(){return false;};
#if !defined(TARGET_STM32F4)
virtual bool EP4_OUT_callback(){return false;};
virtual bool EP4_IN_callback(){return false;};
#if !defined(TARGET_LPC11U24)
virtual bool EP5_OUT_callback(){return false;};
virtual bool EP5_IN_callback(){return false;};
@ -101,6 +101,7 @@ protected:
virtual bool EP15_OUT_callback(){return false;};
virtual bool EP15_IN_callback(){return false;};
#endif
#endif
private:
void usbisr(void);
@ -109,6 +110,8 @@ private:
#if defined(TARGET_LPC11U24)
bool (USBHAL::*epCallback[10 - 2])(void);
#elif defined(TARGET_STM32F4XX)
bool (USBHAL::*epCallback[8 - 2])(void);
#else
bool (USBHAL::*epCallback[32 - 2])(void);
#endif

9
libraries/USBDevice/USBDevice/USBHAL_LPC11U.cpp
View File

@ -16,11 +16,11 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#if defined(TARGET_LPC11U24) || defined(TARGET_LPC1347)
#if defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC1347)
#if defined(TARGET_LPC1347)
#define USB_IRQ USB_IRQ_IRQn
#elif defined(TARGET_LPC11U24)
#elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401)
#define USB_IRQ USB_IRQn
#endif
@ -145,6 +145,11 @@ USBHAL::USBHAL(void) {
epCallback[6] = &USBHAL::EP4_OUT_callback;
epCallback[7] = &USBHAL::EP4_IN_callback;
#if defined(TARGET_LPC11U35_401)
// USB_VBUS input with pull-down
LPC_IOCON->PIO0_3 = 0x00000009;
#endif
// nUSB_CONNECT output
LPC_IOCON->PIO0_6 = 0x00000001;

402
libraries/USBDevice/USBDevice/USBHAL_STM32F4.cpp Normal file
View File

@ -0,0 +1,402 @@
/* Copyright (c) 2010-2011 mbed.org, MIT License
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#if defined(TARGET_STM32F4XX)
#include "USBHAL.h"
#include "USBRegs_STM32.h"
#include "pinmap.h"
USBHAL * USBHAL::instance;
static volatile int epComplete = 0;
static uint32_t bufferEnd = 0;
static const uint32_t rxFifoSize = 512;
static uint32_t rxFifoCount = 0;
static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2];
uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
return 0;
}
USBHAL::USBHAL(void) {
NVIC_DisableIRQ(OTG_FS_IRQn);
epCallback[0] = &USBHAL::EP1_OUT_callback;
epCallback[1] = &USBHAL::EP1_IN_callback;
epCallback[2] = &USBHAL::EP2_OUT_callback;
epCallback[3] = &USBHAL::EP2_IN_callback;
epCallback[4] = &USBHAL::EP3_OUT_callback;
epCallback[5] = &USBHAL::EP3_IN_callback;
// Enable power and clocking
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
pin_function(PA_8, STM_PIN_DATA(2, 10));
pin_function(PA_9, STM_PIN_DATA(0, 0));
pin_function(PA_10, STM_PIN_DATA(2, 10));
pin_function(PA_11, STM_PIN_DATA(2, 10));
pin_function(PA_12, STM_PIN_DATA(2, 10));
// Set ID pin to open drain with pull-up resistor
pin_mode(PA_10, OpenDrain);
GPIOA->PUPDR &= ~(0x3 << 20);
GPIOA->PUPDR |= 1 << 20;
// Set VBUS pin to open drain
pin_mode(PA_9, OpenDrain);
RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
// Enable interrupts
OTG_FS->GREGS.GAHBCFG |= (1 << 0);
// Turnaround time to maximum value - too small causes packet loss
OTG_FS->GREGS.GUSBCFG |= (0xF << 10);
// Unmask global interrupts
OTG_FS->GREGS.GINTMSK |= (1 << 3) | // SOF
(1 << 4) | // RX FIFO not empty
(1 << 12); // USB reset
OTG_FS->DREGS.DCFG |= (0x3 << 0) | // Full speed
(1 << 2); // Non-zero-length status OUT handshake
OTG_FS->GREGS.GCCFG |= (1 << 19) | // Enable VBUS sensing
(1 << 16); // Power Up
instance = this;
NVIC_SetVector(OTG_FS_IRQn, (uint32_t)&_usbisr);
NVIC_SetPriority(OTG_FS_IRQn, 1);
}
USBHAL::~USBHAL(void) {
}
void USBHAL::connect(void) {
NVIC_EnableIRQ(OTG_FS_IRQn);
}
void USBHAL::disconnect(void) {
NVIC_DisableIRQ(OTG_FS_IRQn);
}
void USBHAL::configureDevice(void) {
// Not needed
}
void USBHAL::unconfigureDevice(void) {
// Not needed
}
void USBHAL::setAddress(uint8_t address) {
OTG_FS->DREGS.DCFG |= (address << 4);
EP0write(0, 0);
}
bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
uint32_t flags) {
uint32_t epIndex = endpoint >> 1;
uint32_t type;
switch (endpoint) {
case EP0IN:
case EP0OUT:
type = 0;
break;
case EPISO_IN:
case EPISO_OUT:
type = 1;
case EPBULK_IN:
case EPBULK_OUT:
type = 2;
break;
case EPINT_IN:
case EPINT_OUT:
type = 3;
break;
}
// Generic in or out EP controls
uint32_t control = (maxPacket << 0) | // Packet size
(1 << 15) | // Active endpoint
(type << 18); // Endpoint type
if (endpoint & 0x1) { // In Endpoint
// Set up the Tx FIFO
if (endpoint == EP0IN) {
OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) |
(bufferEnd << 0);
}
else {
OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
(bufferEnd << 0);
}
bufferEnd += maxPacket >> 2;
// Set the In EP specific control settings
if (endpoint != EP0IN) {
control |= (1 << 28); // SD0PID
}
control |= (epIndex << 22) | // TxFIFO index
(1 << 27); // SNAK
OTG_FS->INEP_REGS[epIndex].DIEPCTL = control;
// Unmask the interrupt
OTG_FS->DREGS.DAINTMSK |= (1 << epIndex);
}
else { // Out endpoint
// Set the out EP specific control settings
control |= (1 << 26); // CNAK
OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control;
// Unmask the interrupt
OTG_FS->DREGS.DAINTMSK |= (1 << (epIndex + 16));
}
return true;
}
// read setup packet
void USBHAL::EP0setup(uint8_t *buffer) {
memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0);
}
void USBHAL::EP0readStage(void) {
}
void USBHAL::EP0read(void) {
}
uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
uint32_t* buffer32 = (uint32_t *) buffer;
uint32_t length = rxFifoCount;
for (uint32_t i = 0; i < length; i += 4) {
buffer32[i >> 2] = OTG_FS->FIFO[0][0];
}
rxFifoCount = 0;
return length;
}
void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
endpointWrite(0, buffer, size);
}
void USBHAL::EP0getWriteResult(void) {
}
void USBHAL::EP0stall(void) {
// If we stall the out endpoint here then we have problems transferring
// and setup requests after the (stalled) get device qualifier requests.
// TODO: Find out if this is correct behavior, or whether we are doing
// something else wrong
stallEndpoint(EP0IN);
// stallEndpoint(EP0OUT);
}
EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
uint32_t epIndex = endpoint >> 1;
uint32_t size = (1 << 19) | // 1 packet
(maximumSize << 0); // Packet size
// if (endpoint == EP0OUT) {
size |= (1 << 29); // 1 setup packet
// }
OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = size;
OTG_FS->OUTEP_REGS[epIndex].DOEPCTL |= (1 << 31) | // Enable endpoint
(1 << 26); // Clear NAK
epComplete &= ~(1 << endpoint);
return EP_PENDING;
}
EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
if (!(epComplete & (1 << endpoint))) {
return EP_PENDING;
}
uint32_t* buffer32 = (uint32_t *) buffer;
uint32_t length = rxFifoCount;
for (uint32_t i = 0; i < length; i += 4) {
buffer32[i >> 2] = OTG_FS->FIFO[endpoint >> 1][0];
}
rxFifoCount = 0;
*bytesRead = length;
return EP_COMPLETED;
}
EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
uint32_t epIndex = endpoint >> 1;
OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet
(size << 0); // Size of packet
OTG_FS->INEP_REGS[epIndex].DIEPCTL |= (1 << 31) | // Enable endpoint
(1 << 26); // CNAK
OTG_FS->DREGS.DIEPEMPMSK = (1 << epIndex);
while ((OTG_FS->INEP_REGS[epIndex].DTXFSTS & 0XFFFF) < ((size + 3) >> 2));
for (uint32_t i=0; i<(size + 3) >> 2; i++, data+=4) {
OTG_FS->FIFO[epIndex][0] = *(uint32_t *)data;
}
epComplete &= ~(1 << endpoint);
return EP_PENDING;
}
EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
if (epComplete & (1 << endpoint)) {
epComplete &= ~(1 << endpoint);
return EP_COMPLETED;
}
return EP_PENDING;
}
void USBHAL::stallEndpoint(uint8_t endpoint) {
if (endpoint & 0x1) { // In EP
OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable
(1 << 21); // Stall
}
else { // Out EP
OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK
OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable
(1 << 21); // Stall
}
}
void USBHAL::unstallEndpoint(uint8_t endpoint) {
}
bool USBHAL::getEndpointStallState(uint8_t endpoint) {
return false;
}
void USBHAL::remoteWakeup(void) {
}
void USBHAL::_usbisr(void) {
instance->usbisr();
}
void USBHAL::usbisr(void) {
if (OTG_FS->GREGS.GINTSTS & (1 << 12)) { // USB Reset
// Set SNAK bits
OTG_FS->OUTEP_REGS[0].DOEPCTL |= (1 << 27);
OTG_FS->OUTEP_REGS[1].DOEPCTL |= (1 << 27);
OTG_FS->OUTEP_REGS[2].DOEPCTL |= (1 << 27);
OTG_FS->OUTEP_REGS[3].DOEPCTL |= (1 << 27);
OTG_FS->DREGS.DIEPMSK = (1 << 0);
bufferEnd = 0;
// Set the receive FIFO size
OTG_FS->GREGS.GRXFSIZ = rxFifoSize >> 2;
bufferEnd += rxFifoSize >> 2;
// Create the endpoints, and wait for setup packets on out EP0
realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
OTG_FS->GREGS.GINTSTS = (1 << 12);
}
if (OTG_FS->GREGS.GINTSTS & (1 << 4)) { // RX FIFO not empty
uint32_t status = OTG_FS->GREGS.GRXSTSP;
uint32_t endpoint = (status & 0xF) << 1;
uint32_t length = (status >> 4) & 0x7FF;
uint32_t type = (status >> 17) & 0xF;
rxFifoCount = length;
if (type == 0x6) {
// Setup packet
for (uint32_t i=0; i<length; i+=4) {
setupBuffer[i >> 2] = OTG_FS->FIFO[0][i >> 2];
}
rxFifoCount = 0;
}
if (type == 0x4) {
// Setup complete
EP0setupCallback();
endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
}
if (type == 0x2) {
// Out packet
if (endpoint == EP0OUT) {
EP0out();
}
else {
epComplete |= (1 << endpoint);
if ((instance->*(epCallback[endpoint - 2]))()) {
epComplete &= (1 << endpoint);
}
}
}
for (uint32_t i=0; i<rxFifoCount; i+=4) {
(void) OTG_FS->FIFO[0][0];
}
OTG_FS->GREGS.GINTSTS = (1 << 4);
}
if (OTG_FS->GREGS.GINTSTS & (1 << 18)) { // In endpoint interrupt
// Loop through the in endpoints
for (uint32_t i=0; i<4; i++) {
if (OTG_FS->DREGS.DAINT & (1 << i)) { // Interrupt is on endpoint
if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 7)) {// Tx FIFO empty
// If the Tx FIFO is empty on EP0 we need to send a further
// packet, so call EP0in()
if (i == 0) {
EP0in();
}
// Clear the interrupt
OTG_FS->INEP_REGS[i].DIEPINT = (1 << 7);
// Stop firing Tx empty interrupts
// Will get turned on again if another write is called
OTG_FS->DREGS.DIEPEMPMSK &= ~(1 << i);
}
// If the transfer is complete
if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 0)) { // Tx Complete
epComplete |= (1 << (1 + (i << 1)));
OTG_FS->INEP_REGS[i].DIEPINT = (1 << 0);
}
}
}
OTG_FS->GREGS.GINTSTS = (1 << 18);
}
if (OTG_FS->GREGS.GINTSTS & (1 << 3)) { // Start of frame
SOF((OTG_FS->GREGS.GRXSTSR >> 17) & 0xF);
OTG_FS->GREGS.GINTSTS = (1 << 3);
}
}
#endif

149
libraries/USBDevice/USBDevice/USBRegs_STM32.h Normal file
View File

@ -0,0 +1,149 @@
/**
******************************************************************************
* @file usb_regs.h
* @author MCD Application Team
* @version V2.1.0
* @date 19-March-2012
* @brief hardware registers
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
#ifndef __USB_OTG_REGS_H__
#define __USB_OTG_REGS_H__
typedef struct //000h
{
__IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/
__IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
__IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
__IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/
__IO uint32_t GRSTCTL; /* Core Reset Register 010h*/
__IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/
__IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/
__IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/
__IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/
__IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
__IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/
__IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
uint32_t Reserved30[2]; /* Reserved 030h*/
__IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
__IO uint32_t CID; /* User ID Register 03Ch*/
uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
__IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
__IO uint32_t DIEPTXF[3];/* dev Periodic Transmit FIFO */
}
USB_OTG_GREGS;
typedef struct // 800h
{
__IO uint32_t DCFG; /* dev Configuration Register 800h*/
__IO uint32_t DCTL; /* dev Control Register 804h*/
__IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
uint32_t Reserved0C; /* Reserved 80Ch*/
__IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
__IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
__IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
__IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
uint32_t Reserved20; /* Reserved 820h*/
uint32_t Reserved9; /* Reserved 824h*/
__IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
__IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
__IO uint32_t DTHRCTL; /* dev thr 830h*/
__IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
}
USB_OTG_DREGS;
typedef struct
{
__IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
__IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
__IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
uint32_t Reserved14;
__IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
uint32_t Reserved1C; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
}
USB_OTG_INEPREGS;
typedef struct
{
__IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
__IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
__IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
uint32_t Reserved14[3];
}
USB_OTG_OUTEPREGS;
typedef struct
{
__IO uint32_t HCFG; /* Host Configuration Register 400h*/
__IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
__IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
uint32_t Reserved40C; /* Reserved 40Ch*/
__IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
__IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
__IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
}
USB_OTG_HREGS;
typedef struct
{
__IO uint32_t HCCHAR;
__IO uint32_t HCSPLT;
__IO uint32_t HCINT;
__IO uint32_t HCINTMSK;
__IO uint32_t HCTSIZ;
uint32_t Reserved[3];
}
USB_OTG_HC_REGS;
typedef struct
{
USB_OTG_GREGS GREGS;
uint32_t RESERVED0[188];
USB_OTG_HREGS HREGS;
uint32_t RESERVED1[9];
__IO uint32_t HPRT;
uint32_t RESERVED2[47];
USB_OTG_HC_REGS HC_REGS[8];
uint32_t RESERVED3[128];
USB_OTG_DREGS DREGS;
uint32_t RESERVED4[50];
USB_OTG_INEPREGS INEP_REGS[4];
uint32_t RESERVED5[96];
USB_OTG_OUTEPREGS OUTEP_REGS[4];
uint32_t RESERVED6[160];
__IO uint32_t PCGCCTL;
uint32_t RESERVED7[127];
__IO uint32_t FIFO[4][1024];
}
USB_OTG_CORE_REGS;
#define OTG_FS_BASE (AHB2PERIPH_BASE + 0x0000)
#define OTG_FS ((USB_OTG_CORE_REGS *) OTG_FS_BASE)
#endif //__USB_OTG_REGS_H__
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

2
libraries/USBHost/USBHost/USBHost.cpp
View File

@ -855,7 +855,7 @@ USB_TYPE USBHost::enumerate(USBDeviceConnected * dev, IUSBEnumerator* pEnumerato
return res;
}
#if DEBUG
#if (DEBUG > 3)
USB_DBG("CONFIGURATION DESCRIPTOR:\r\n");
for (int i = 0; i < total_conf_descr_length; i++)
printf("%02X ", data[i]);

2
libraries/USBHost/USBHost/USBHostConf.h
View File

@ -49,7 +49,7 @@
#define USBHOST_MOUSE 1
/*
* Enable USBHostSerial
* Enable USBHostSerial or USBHostMultiSerial (if set > 1)
*/
#define USBHOST_SERIAL 1

25
libraries/USBHost/USBHost/dbg.h
View File

@ -18,17 +18,35 @@
#define USB_DEBUG_H
//Debug is disabled by default
#define DEBUG 0
#define DEBUG 3 /*INFO,ERR,WARN*/
#define DEBUG_TRANSFER 0
#define DEBUG_EP_STATE 0
#define DEBUG_EVENT 0
#if (DEBUG)
#if (DEBUG > 3)
#define USB_DBG(x, ...) std::printf("[USB_DBG: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
#else
#define USB_DBG(x, ...)
#endif
#if (DEBUG > 2)
#define USB_INFO(x, ...) std::printf("[USB_INFO: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
#else
#define USB_INFO(x, ...)
#endif
#if (DEBUG > 1)
#define USB_WARN(x, ...) std::printf("[USB_WARNING: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
#else
#define USB_WARN(x, ...)
#endif
#if (DEBUG > 0)
#define USB_ERR(x, ...) std::printf("[USB_ERR: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
#else
#define USB_ERR(x, ...)
#endif
#if (DEBUG_TRANSFER)
#define USB_DBG_TRANSFER(x, ...) std::printf("[USB_TRANSFER: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
#else
@ -41,9 +59,6 @@
#define USB_DBG_EVENT(x, ...)
#endif
#define USB_INFO(x, ...) std::printf("[USB_INFO: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
#define USB_WARN(x, ...) std::printf("[USB_WARNING: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
#define USB_ERR(x, ...) std::printf("[USB_ERR: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
#endif

321
libraries/USBHost/USBHostSerial/USBHostSerial.cpp
View File

@ -20,27 +20,17 @@
#include "dbg.h"
#define SET_LINE_CODING 0x20
#define CHECK_INTERFACE(cls,subcls,proto) \
(((cls == 0xFF) && (subcls == 0xFF) && (proto == 0xFF)) /* QUALCOM CDC */ || \
((cls == SERIAL_CLASS) && (subcls == 0x00) && (proto == 0x00)) /* STANDARD CDC */ )
USBHostSerial::USBHostSerial(): circ_buf() {
#if (USBHOST_SERIAL <= 1)
USBHostSerial::USBHostSerial()
{
host = USBHost::getHostInst();
size_bulk_in = 0;
size_bulk_out = 0;
init();
}
void USBHostSerial::init() {
dev = NULL;
bulk_in = NULL;
bulk_out = NULL;
ports_found = 0;
dev_connected = false;
serial_intf = -1;
serial_device_found = false;
line_coding.baudrate = 9600;
line_coding.data_bits = 8;
line_coding.parity = None;
line_coding.stop_bits = 1;
circ_buf.flush();
}
bool USBHostSerial::connected()
@ -48,49 +38,219 @@ bool USBHostSerial::connected()
return dev_connected;
}
void USBHostSerial::disconnect(void)
{
ports_found = 0;
dev = NULL;
}
bool USBHostSerial::connect() {
if (dev_connected) {
return true;
if (dev)
{
for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++)
{
USBDeviceConnected* d = host->getDevice(i);
if (dev == d)
return true;
}
disconnect();
}
for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++) {
if ((dev = host->getDevice(i)) != NULL) {
for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++)
{
USBDeviceConnected* d = host->getDevice(i);
if (d != NULL) {
USB_DBG("Trying to connect serial device\r\n");
if(host->enumerate(dev, this))
USB_DBG("Trying to connect serial device \r\n");
if(host->enumerate(d, this))
break;
if (serial_device_found) {
bulk_in = dev->getEndpoint(serial_intf, BULK_ENDPOINT, IN);
bulk_out = dev->getEndpoint(serial_intf, BULK_ENDPOINT, OUT);
if (!bulk_in || !bulk_out)
break;
USB_INFO("New Serial device: VID:%04x PID:%04x [dev: %p - intf: %d]", dev->getVid(), dev->getPid(), dev, serial_intf);
dev->setName("Serial", serial_intf);
host->registerDriver(dev, serial_intf, this, &USBHostSerial::init);
baud(9600);
size_bulk_in = bulk_in->getSize();
size_bulk_out = bulk_out->getSize();
bulk_in->attach(this, &USBHostSerial::rxHandler);
bulk_out->attach(this, &USBHostSerial::txHandler);
host->bulkRead(dev, bulk_in, buf, size_bulk_in, false);
dev_connected = true;
return true;
USBEndpoint* bulk_in = d->getEndpoint(port_intf, BULK_ENDPOINT, IN);
USBEndpoint* bulk_out = d->getEndpoint(port_intf, BULK_ENDPOINT, OUT);
if (bulk_in && bulk_out)
{
USBHostSerialPort::connect(host,d,port_intf,bulk_in, bulk_out);
dev = d;
}
}
}
init();
return dev != NULL;
}
/*virtual*/ void USBHostSerial::setVidPid(uint16_t vid, uint16_t pid)
{
// we don't check VID/PID for MSD driver
}
/*virtual*/ bool USBHostSerial::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
{
if (!ports_found &&
CHECK_INTERFACE(intf_class, intf_subclass, intf_protocol)) {
port_intf = intf_nb;
ports_found = true;
return true;
}
return false;
}
void USBHostSerial::rxHandler() {
/*virtual*/ bool USBHostSerial::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
{
if (ports_found && (intf_nb == port_intf)) {
if (type == BULK_ENDPOINT)
return true;
}
return false;
}
#else // (USBHOST_SERIAL > 1)
//------------------------------------------------------------------------------
USBHostMultiSerial::USBHostMultiSerial()
{
host = USBHost::getHostInst();
dev = NULL;
memset(ports, NULL, sizeof(ports));
ports_found = 0;
dev_connected = false;
}
USBHostMultiSerial::~USBHostMultiSerial()
{
disconnect();
}
bool USBHostMultiSerial::connected()
{
return dev_connected;
}
void USBHostMultiSerial::disconnect(void)
{
for (int port = 0; port < USBHOST_SERIAL; port ++)
{
if (ports[port])
{
delete ports[port];
ports[port] = NULL;
}
}
ports_found = 0;
dev = NULL;
}
bool USBHostMultiSerial::connect() {
if (dev)
{
for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++)
{
USBDeviceConnected* d = host->getDevice(i);
if (dev == d)
return true;
}
disconnect();
}
for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++)
{
USBDeviceConnected* d = host->getDevice(i);
if (d != NULL) {
USB_DBG("Trying to connect serial device \r\n");
if(host->enumerate(d, this))
break;
for (int port = 0; port < ports_found; port ++)
{
USBEndpoint* bulk_in = d->getEndpoint(port_intf[port], BULK_ENDPOINT, IN);
USBEndpoint* bulk_out = d->getEndpoint(port_intf[port], BULK_ENDPOINT, OUT);
if (bulk_in && bulk_out)
{
ports[port] = new USBHostSerialPort();
if (ports[port])
{
ports[port]->connect(host,d,port_intf[port],bulk_in, bulk_out);
dev = d;
}
}
}
}
}
return dev != NULL;
}
/*virtual*/ void USBHostMultiSerial::setVidPid(uint16_t vid, uint16_t pid)
{
// we don't check VID/PID for MSD driver
}
/*virtual*/ bool USBHostMultiSerial::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
{
if ((ports_found < USBHOST_SERIAL) &&
CHECK_INTERFACE(intf_class, intf_subclass, intf_protocol)) {
port_intf[ports_found++] = intf_nb;
return true;
}
return false;
}
/*virtual*/ bool USBHostMultiSerial::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
{
if ((ports_found > 0) && (intf_nb == port_intf[ports_found-1])) {
if (type == BULK_ENDPOINT)
return true;
}
return false;
}
#endif
//------------------------------------------------------------------------------
#define SET_LINE_CODING 0x20
USBHostSerialPort::USBHostSerialPort(): circ_buf()
{
init();
}
void USBHostSerialPort::init(void)
{
host = NULL;
dev = NULL;
serial_intf = NULL;
size_bulk_in = 0;
size_bulk_out = 0;
bulk_in = NULL;
bulk_out = NULL;
line_coding.baudrate = 9600;
line_coding.data_bits = 8;
line_coding.parity = None;
line_coding.stop_bits = 1;
circ_buf.flush();
}
void USBHostSerialPort::connect(USBHost* _host, USBDeviceConnected * _dev,
uint8_t _serial_intf, USBEndpoint* _bulk_in, USBEndpoint* _bulk_out)
{
host = _host;
dev = _dev;
serial_intf = _serial_intf;
bulk_in = _bulk_in;
bulk_out = _bulk_out;
USB_INFO("New Serial device: VID:%04x PID:%04x [dev: %p - intf: %d]", dev->getVid(), dev->getPid(), dev, serial_intf);
dev->setName("Serial", serial_intf);
host->registerDriver(dev, serial_intf, this, &USBHostSerialPort::init);
//baud(9600);
size_bulk_in = bulk_in->getSize();
size_bulk_out = bulk_out->getSize();
bulk_in->attach(this, &USBHostSerialPort::rxHandler);
bulk_out->attach(this, &USBHostSerialPort::txHandler);
host->bulkRead(dev, bulk_in, buf, size_bulk_in, false);
}
void USBHostSerialPort::rxHandler() {
if (bulk_in) {
int len = bulk_in->getLengthTransferred();
if (bulk_in->getState() == USB_TYPE_IDLE) {
@ -103,7 +263,7 @@ void USBHostSerial::rxHandler() {
}
}
void USBHostSerial::txHandler() {
void USBHostSerialPort::txHandler() {
if (bulk_out) {
if (bulk_out->getState() == USB_TYPE_IDLE) {
tx.call();
@ -111,7 +271,7 @@ void USBHostSerial::txHandler() {
}
}
int USBHostSerial::_putc(int c) {
int USBHostSerialPort::_putc(int c) {
if (bulk_out) {
if (host->bulkWrite(dev, bulk_out, (uint8_t *)&c, 1) == USB_TYPE_OK) {
return 1;
@ -120,12 +280,12 @@ int USBHostSerial::_putc(int c) {
return -1;
}
void USBHostSerial::baud(int baudrate) {
void USBHostSerialPort::baud(int baudrate) {
line_coding.baudrate = baudrate;
format(line_coding.data_bits, (Parity)line_coding.parity, line_coding.stop_bits);
}
void USBHostSerial::format(int bits, Parity parity, int stop_bits) {
void USBHostSerialPort::format(int bits, Parity parity, int stop_bits) {
line_coding.data_bits = bits;
line_coding.parity = parity;
line_coding.stop_bits = (stop_bits == 1) ? 0 : 2;
@ -137,7 +297,7 @@ void USBHostSerial::format(int bits, Parity parity, int stop_bits) {
0, serial_intf, (uint8_t *)&line_coding, 7);
}
int USBHostSerial::_getc() {
int USBHostSerialPort::_getc() {
uint8_t c = 0;
if (bulk_in == NULL) {
init();
@ -148,37 +308,36 @@ int USBHostSerial::_getc() {
return c;
}
int USBHostSerialPort::writeBuf(const char* b, int s)
{
int c = 0;
if (bulk_out)
{
while (c < s)
{
int i = (s < size_bulk_out) ? s : size_bulk_out;
if (host->bulkWrite(dev, bulk_out, (uint8_t *)(b+c), i) == USB_TYPE_OK)
c += i;
}
}
return s;
}
uint8_t USBHostSerial::available() {
int USBHostSerialPort::readBuf(char* b, int s)
{
int i = 0;
if (bulk_in)
{
for (i = 0; i < s; )
b[i++] = getc();
}
return i;
}
uint8_t USBHostSerialPort::available() {
return circ_buf.available();
}
/*virtual*/ void USBHostSerial::setVidPid(uint16_t vid, uint16_t pid)
{
// we don't check VID/PID for MSD driver
}
/*virtual*/ bool USBHostSerial::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
{
if ((serial_intf == -1) &&
(intf_class == SERIAL_CLASS) &&
(intf_subclass == 0x00) &&
(intf_protocol == 0x00)) {
serial_intf = intf_nb;
return true;
}
return false;
}
/*virtual*/ bool USBHostSerial::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
{
if (intf_nb == serial_intf) {
if (type == BULK_ENDPOINT) {
serial_device_found = true;
return true;
}
}
return false;
}
#endif

125
libraries/USBHost/USBHostSerial/USBHostSerial.h
View File

@ -28,12 +28,12 @@
/**
* A class to communicate a USB virtual serial port
*/
class USBHostSerial : public IUSBEnumerator, public Stream {
class USBHostSerialPort : public Stream {
public:
/**
* Constructor
*/
USBHostSerial();
USBHostSerialPort();
enum IrqType {
RxIrq,
@ -48,20 +48,9 @@ public:
Space
};
/**
* Check if a virtual serial port is connected
*
* @returns true if a serial device is connected
*/
bool connected();
/**
* Try to connect a serial device
*
* @return true if connection was successful
*/
bool connect();
void connect(USBHost* _host, USBDeviceConnected * _dev,
uint8_t _serial_intf, USBEndpoint* _bulk_in, USBEndpoint* _bulk_out);
/**
* Check the number of bytes available.
*
@ -111,34 +100,29 @@ public:
/** Set the transmission format used by the Serial port
*
* @param bits The number of bits in a word (default = 8)
* @param parity The parity used (USBHostSerial::None, USBHostSerial::Odd, USBHostSerial::Even, USBHostSerial::Mark, USBHostSerial::Space; default = USBHostSerial::None)
* @param parity The parity used (USBHostSerialPort::None, USBHostSerialPort::Odd, USBHostSerialPort::Even, USBHostSerialPort::Mark, USBHostSerialPort::Space; default = USBHostSerialPort::None)
* @param stop The number of stop bits (1 or 2; default = 1)
*/
void format(int bits = 8, Parity parity = USBHostSerial::None, int stop_bits = 1);
void format(int bits = 8, Parity parity = USBHostSerialPort::None, int stop_bits = 1);
virtual int writeBuf(const char* b, int s);
virtual int readBuf(char* b, int s);
protected:
//From IUSBEnumerator
virtual void setVidPid(uint16_t vid, uint16_t pid);
virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
virtual int _getc();
virtual int _putc(int c);
private:
USBHost * host;
USBDeviceConnected * dev;
USBEndpoint * bulk_in;
USBEndpoint * bulk_out;
uint32_t size_bulk_in;
uint32_t size_bulk_out;
bool dev_connected;
void init();
MtxCircBuffer<uint8_t, 64> circ_buf;
MtxCircBuffer<uint8_t, 128> circ_buf;
uint8_t buf[64];
@ -156,11 +140,92 @@ private:
FunctionPointer rx;
FunctionPointer tx;
int serial_intf;
bool serial_device_found;
uint8_t serial_intf;
};
#if (USBHOST_SERIAL <= 1)
class USBHostSerial : public IUSBEnumerator, public USBHostSerialPort
{
public:
USBHostSerial();
/**
* Try to connect a serial device
*
* @return true if connection was successful
*/
bool connect();
void disconnect();
/**
* Check if a any serial port is connected
*
* @returns true if a serial device is connected
*/
bool connected();
protected:
USBHost* host;
USBDeviceConnected* dev;
uint8_t port_intf;
int ports_found;
//From IUSBEnumerator
virtual void setVidPid(uint16_t vid, uint16_t pid);
virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
private:
bool dev_connected;
};
#else // (USBHOST_SERIAL > 1)
class USBHostMultiSerial : public IUSBEnumerator {
public:
USBHostMultiSerial();
virtual ~USBHostMultiSerial();
USBHostSerialPort* getPort(int port)
{
return port < USBHOST_SERIAL ? ports[port] : NULL;
}
/**
* Try to connect a serial device
*
* @return true if connection was successful
*/
bool connect();
void disconnect();
/**
* Check if a any serial port is connected
*
* @returns true if a serial device is connected
*/
bool connected();
protected:
USBHost* host;
USBDeviceConnected* dev;
USBHostSerialPort* ports[USBHOST_SERIAL];
uint8_t port_intf[USBHOST_SERIAL];
int ports_found;
//From IUSBEnumerator
virtual void setVidPid(uint16_t vid, uint16_t pid);
virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
private:
bool dev_connected;
};
#endif // (USBHOST_SERIAL <= 1)
#endif
#endif

6
libraries/mbed/api/InterruptIn.h
View File

@ -108,11 +108,13 @@ public:
*/
void mode(PinMode pull);
/** Enable IRQ
/** Enable IRQ. This method depends on hw implementation, might enable one
* port interrupts. For further information, check gpio_irq_enable().
*/
void enable_irq();
/** Disable IRQ
/** Disable IRQ. This method depends on hw implementation, might disable one
* port interrupts. For further information, check gpio_irq_disable().
*/
void disable_irq();

10
libraries/mbed/api/RawSerial.h
View File

@ -71,6 +71,16 @@ public:
* @returns The char read from the serial port
*/
int getc();
/** Write a string to the serial port
*
* @param str The string to write
*
* @returns 0 if the write succeeds, EOF for error
*/
int puts(const char *str);
int printf(const char *format, ...);
};
} // namespace mbed

17
libraries/mbed/api/SerialBase.h
View File

@ -51,6 +51,13 @@ public:
TxIrq
};
enum Flow {
Disabled = 0,
RTS,
CTS,
RTSCTS
};
/** Set the transmission format used by the serial port
*
* @param bits The number of bits in a word (5-8; default = 8)
@ -99,6 +106,16 @@ public:
/** Generate a break condition on the serial line
*/
void send_break();
#if DEVICE_SERIAL_FC
/** Set the flow control type on the serial port
*
* @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
* @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
* @param flow2 the second flow control pin (CTS for RTSCTS)
*/
void set_flow_control(Flow type, PinName flow1=NC, PinName flow2=NC);
#endif
static void _irq_handler(uint32_t id, SerialIrq irq_type);

31
libraries/mbed/common/RawSerial.cpp
View File

@ -15,9 +15,12 @@
*/
#include "RawSerial.h"
#include "wait_api.h"
#include <cstdarg>
#if DEVICE_SERIAL
#define STRING_STACK_LIMIT 120
namespace mbed {
RawSerial::RawSerial(PinName tx, PinName rx) : SerialBase(tx, rx) {
@ -31,6 +34,34 @@ int RawSerial::putc(int c) {
return _base_putc(c);
}
int RawSerial::puts(const char *str) {
while (*str)
putc(*str ++);
return 0;
}
// Experimental support for printf in RawSerial. No Stream inheritance
// means we can't call printf() directly, so we use sprintf() instead.
// We only call malloc() for the sprintf() buffer if the buffer
// length is above a certain threshold, otherwise we use just the stack.
int RawSerial::printf(const char *format, ...) {
std::va_list arg;
va_start(arg, format);
int len = vsnprintf(NULL, 0, format, arg);
if (len < STRING_STACK_LIMIT) {
char temp[STRING_STACK_LIMIT];
vsprintf(temp, format, arg);
puts(temp);
} else {
char *temp = new char[len + 1];
vsprintf(temp, format, arg);
puts(temp);
delete[] temp;
}
va_end(arg);
return len;
}
} // namespace mbed
#endif

23
libraries/mbed/common/SerialBase.cpp
View File

@ -81,6 +81,29 @@ void SerialBase::send_break() {
serial_break_clear(&_serial);
}
#ifdef DEVICE_SERIAL_FC
void SerialBase::set_flow_control(Flow type, PinName flow1, PinName flow2) {
FlowControl flow_type = (FlowControl)type;
switch(type) {
case RTS:
serial_set_flow_control(&_serial, flow_type, flow1, NC);
break;
case CTS:
serial_set_flow_control(&_serial, flow_type, NC, flow1);
break;
case RTSCTS:
case Disabled:
serial_set_flow_control(&_serial, flow_type, flow1, flow2);
break;
default:
break;
}
}
#endif
} // namespace mbed
#endif

16
libraries/mbed/common/board.c
View File

@ -19,10 +19,12 @@
WEAK void mbed_die(void);
WEAK void mbed_die(void) {
#if defined(DEVICE_ERROR_RED)
__disable_irq(); // dont allow interrupts to disturb the flash pattern
#if (DEVICE_ERROR_RED == 1)
gpio_t led_red; gpio_init(&led_red, LED_RED, PIN_OUTPUT);
#elif defined(DEVICE_ERROR_PATTERN)
#elif (DEVICE_ERROR_PATTERN == 1)
gpio_t led_1; gpio_init(&led_1, LED1, PIN_OUTPUT);
gpio_t led_2; gpio_init(&led_2, LED2, PIN_OUTPUT);
gpio_t led_3; gpio_init(&led_3, LED3, PIN_OUTPUT);
@ -30,26 +32,28 @@ WEAK void mbed_die(void) {
#endif
while (1) {
#if defined(DEVICE_ERROR_RED)
#if (DEVICE_ERROR_RED == 1)
gpio_write(&led_red, 1);
#elif defined(DEVICE_ERROR_PATTERN)
#elif (DEVICE_ERROR_PATTERN == 1)
gpio_write(&led_1, 1);
gpio_write(&led_2, 0);
gpio_write(&led_3, 0);
gpio_write(&led_4, 1);
#endif
wait_ms(150);
#if defined(DEVICE_ERROR_RED)
#if (DEVICE_ERROR_RED == 1)
gpio_write(&led_red, 0);
#elif defined(DEVICE_ERROR_PATTERN)
#elif (DEVICE_ERROR_PATTERN == 1)
gpio_write(&led_1, 0);
gpio_write(&led_2, 1);
gpio_write(&led_3, 1);
gpio_write(&led_4, 0);
#endif
wait_ms(150);
}
}

19
libraries/mbed/common/pinmap_common.c
View File

@ -44,17 +44,22 @@ uint32_t pinmap_merge(uint32_t a, uint32_t b) {
return (uint32_t)NC;
}
uint32_t pinmap_peripheral(PinName pin, const PinMap* map) {
if (pin == (PinName)NC)
return (uint32_t)NC;
uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map) {
while (map->pin != NC) {
if (map->pin == pin)
return map->peripheral;
map++;
}
// no mapping available
error("pinmap not found for peripheral");
return (uint32_t)NC;
}
uint32_t pinmap_peripheral(PinName pin, const PinMap* map) {
uint32_t peripheral = (uint32_t)NC;
if (pin == (PinName)NC)
return (uint32_t)NC;
peripheral = pinmap_find_peripheral(pin, map);
if ((uint32_t)NC == peripheral) // no mapping available
error("pinmap not found for peripheral");
return peripheral;
}

10
libraries/mbed/common/retarget.cpp
View File

@ -398,15 +398,23 @@ extern "C" WEAK void __cxa_pure_virtual(void) {
// ****************************************************************************
// mbed_main is a function that is called before main()
// mbed_sdk_init() is also a function that is called before main(), but unlike
// mbed_main(), it is not meant for user code, but for the SDK itself to perform
// initializations before main() is called.
extern "C" WEAK void mbed_main(void);
extern "C" WEAK void mbed_main(void) {
}
extern "C" WEAK void mbed_sdk_init(void);
extern "C" WEAK void mbed_sdk_init(void) {
}
#if defined(TOOLCHAIN_ARM)
extern "C" int $Super$$main(void);
extern "C" int $Sub$$main(void) {
mbed_sdk_init();
mbed_main();
return $Super$$main();
}
@ -414,6 +422,7 @@ extern "C" int $Sub$$main(void) {
extern "C" int __real_main(void);
extern "C" int __wrap_main(void) {
mbed_sdk_init();
mbed_main();
return __real_main();
}
@ -424,6 +433,7 @@ extern "C" int __wrap_main(void) {
// code will call a function to setup argc and argv (__iar_argc_argv) if it is defined.
// Since mbed doesn't use argc/argv, we use this function to call our mbed_main.
extern "C" void __iar_argc_argv() {
mbed_sdk_init();
mbed_main();
}
#endif

1
libraries/mbed/hal/pinmap.h
View File

@ -34,6 +34,7 @@ void pin_mode (PinName pin, PinMode mode);
uint32_t pinmap_peripheral(PinName pin, const PinMap* map);
uint32_t pinmap_merge (uint32_t a, uint32_t b);
void pinmap_pinout (PinName pin, const PinMap *map);
uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map);
#ifdef __cplusplus
}

9
libraries/mbed/hal/serial_api.h
View File

@ -37,6 +37,13 @@ typedef enum {
TxIrq
} SerialIrq;
typedef enum {
FlowControlNone,
FlowControlRTS,
FlowControlCTS,
FlowControlRTSCTS
} FlowControl;
typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event);
typedef struct serial_s serial_t;
@ -60,6 +67,8 @@ void serial_break_clear(serial_t *obj);
void serial_pinout_tx(PinName tx);
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow);
#ifdef __cplusplus
}
#endif

5836
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/MK20D5.h Normal file
View File

File diff suppressed because it is too large Load Diff

14
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/TOOLCHAIN_ARM_STD/MK20D5.sct Normal file
View File

@ -0,0 +1,14 @@
LR_IROM1 0x00000000 0x20000 { ; load region size_region (132k)
ER_IROM1 0x00000000 0x20000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0xF8) = 0xF8
; 0x4000 - 0xF8 = 0x3F08
RW_IRAM1 0x1FFFE0F8 0x3F08 {
.ANY (+RW +ZI)
}
}

412
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/TOOLCHAIN_ARM_STD/startup_MK20D5.s Normal file
View File

@ -0,0 +1,412 @@
;/*****************************************************************************
; * @file: startup_MK20D5.s
; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
; * MK20D5
; * @version: 1.0
; * @date: 2011-12-15
; *
; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
;*
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; *****************************************************************************/
__initial_sp EQU 0x20002000 ; Top of RAM
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
DCD DMA_Error_IRQHandler ; DMA error interrupt
DCD Reserved21_IRQHandler ; Reserved interrupt 21
DCD FTFL_IRQHandler ; FTFL interrupt
DCD Read_Collision_IRQHandler ; Read collision interrupt
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
DCD LLW_IRQHandler ; Low Leakage Wakeup
DCD Watchdog_IRQHandler ; WDOG interrupt
DCD I2C0_IRQHandler ; I2C0 interrupt
DCD SPI0_IRQHandler ; SPI0 interrupt
DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
DCD UART0_LON_IRQHandler ; UART0 LON interrupt
DCD UART0_RX_TX_IRQHandler ; UART0 receive/transmit interrupt
DCD UART0_ERR_IRQHandler ; UART0 error interrupt
DCD UART1_RX_TX_IRQHandler ; UART1 receive/transmit interrupt
DCD UART1_ERR_IRQHandler ; UART1 error interrupt
DCD UART2_RX_TX_IRQHandler ; UART2 receive/transmit interrupt
DCD UART2_ERR_IRQHandler ; UART2 error interrupt
DCD ADC0_IRQHandler ; ADC0 interrupt
DCD CMP0_IRQHandler ; CMP0 interrupt
DCD CMP1_IRQHandler ; CMP1 interrupt
DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
DCD CMT_IRQHandler ; CMT interrupt
DCD RTC_IRQHandler ; RTC interrupt
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
DCD PDB0_IRQHandler ; PDB0 interrupt
DCD USB0_IRQHandler ; USB0 interrupt
DCD USBDCD_IRQHandler ; USBDCD interrupt
DCD TSI0_IRQHandler ; TSI0 interrupt
DCD MCG_IRQHandler ; MCG interrupt
DCD LPTimer_IRQHandler ; LPTimer interrupt
DCD PORTA_IRQHandler ; Port A interrupt
DCD PORTB_IRQHandler ; Port B interrupt
DCD PORTC_IRQHandler ; Port C interrupt
DCD PORTD_IRQHandler ; Port D interrupt
DCD PORTE_IRQHandler ; Port E interrupt
DCD SWI_IRQHandler ; Software interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
; <h> Flash Configuration
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
; <i> and security information that allows the MCU to restrict acces to the FTFL module.
; <h> Backdoor Comparison Key
; <o0> Backdoor Key 0 <0x0-0xFF:2>
; <o1> Backdoor Key 1 <0x0-0xFF:2>
; <o2> Backdoor Key 2 <0x0-0xFF:2>
; <o3> Backdoor Key 3 <0x0-0xFF:2>
; <o4> Backdoor Key 4 <0x0-0xFF:2>
; <o5> Backdoor Key 5 <0x0-0xFF:2>
; <o6> Backdoor Key 6 <0x0-0xFF:2>
; <o7> Backdoor Key 7 <0x0-0xFF:2>
BackDoorK0 EQU 0xFF
BackDoorK1 EQU 0xFF
BackDoorK2 EQU 0xFF
BackDoorK3 EQU 0xFF
BackDoorK4 EQU 0xFF
BackDoorK5 EQU 0xFF
BackDoorK6 EQU 0xFF
BackDoorK7 EQU 0xFF
; </h>
; <h> Program flash protection bytes (FPROT)
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
; <i> Each bit protects a 1/32 region of the program flash memory.
; <h> FPROT0
; <i> Program flash protection bytes
; <i> 1/32 - 8/32 region
; <o.0> FPROT0.0
; <o.1> FPROT0.1
; <o.2> FPROT0.2
; <o.3> FPROT0.3
; <o.4> FPROT0.4
; <o.5> FPROT0.5
; <o.6> FPROT0.6
; <o.7> FPROT0.7
nFPROT0 EQU 0x00
FPROT0 EQU nFPROT0:EOR:0xFF
; </h>
; <h> FPROT1
; <i> Program Flash Region Protect Register 1
; <i> 9/32 - 16/32 region
; <o.0> FPROT1.0
; <o.1> FPROT1.1
; <o.2> FPROT1.2
; <o.3> FPROT1.3
; <o.4> FPROT1.4
; <o.5> FPROT1.5
; <o.6> FPROT1.6
; <o.7> FPROT1.7
nFPROT1 EQU 0x00
FPROT1 EQU nFPROT1:EOR:0xFF
; </h>
; <h> FPROT2
; <i> Program Flash Region Protect Register 2
; <i> 17/32 - 24/32 region
; <o.0> FPROT2.0
; <o.1> FPROT2.1
; <o.2> FPROT2.2
; <o.3> FPROT2.3
; <o.4> FPROT2.4
; <o.5> FPROT2.5
; <o.6> FPROT2.6
; <o.7> FPROT2.7
nFPROT2 EQU 0x00
FPROT2 EQU nFPROT2:EOR:0xFF
; </h>
; <h> FPROT3
; <i> Program Flash Region Protect Register 3
; <i> 25/32 - 32/32 region
; <o.0> FPROT3.0
; <o.1> FPROT3.1
; <o.2> FPROT3.2
; <o.3> FPROT3.3
; <o.4> FPROT3.4
; <o.5> FPROT3.5
; <o.6> FPROT3.6
; <o.7> FPROT3.7
nFPROT3 EQU 0x00
FPROT3 EQU nFPROT3:EOR:0xFF
; </h>
; </h>
; <h> Data flash protection byte (FDPROT)
; <i> Each bit protects a 1/8 region of the data flash memory.
; <i> (Program flash only devices: Reserved)
; <o.0> FDPROT.0
; <o.1> FDPROT.1
; <o.2> FDPROT.2
; <o.3> FDPROT.3
; <o.4> FDPROT.4
; <o.5> FDPROT.5
; <o.6> FDPROT.6
; <o.7> FDPROT.7
nFDPROT EQU 0x00
FDPROT EQU nFDPROT:EOR:0xFF
; </h>
; <h> EEPROM protection byte (FEPROT)
; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
; <i> (Program flash only devices: Reserved)
; <o.0> FEPROT.0
; <o.1> FEPROT.1
; <o.2> FEPROT.2
; <o.3> FEPROT.3
; <o.4> FEPROT.4
; <o.5> FEPROT.5
; <o.6> FEPROT.6
; <o.7> FEPROT.7
nFEPROT EQU 0x00
FEPROT EQU nFEPROT:EOR:0xFF
; </h>
; <h> Flash nonvolatile option byte (FOPT)
; <i> Allows the user to customize the operation of the MCU at boot time.
; <o.0> LPBOOT
; <0=> Low-power boot
; <1=> normal boot
; <o.1> EZPORT_DIS
; <0=> EzPort operation is enabled
; <1=> EzPort operation is disabled
FOPT EQU 0xFF
; </h>
; <h> Flash security byte (FSEC)
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
; <o.0..1> SEC
; <2=> MCU security status is unsecure
; <3=> MCU security status is secure
; <i> Flash Security
; <i> This bits define the security state of the MCU.
; <o.2..3> FSLACC
; <2=> Freescale factory access denied
; <3=> Freescale factory access granted
; <i> Freescale Failure Analysis Access Code
; <i> This bits define the security state of the MCU.
; <o.4..5> MEEN
; <2=> Mass erase is disabled
; <3=> Mass erase is enabled
; <i> Mass Erase Enable Bits
; <i> Enables and disables mass erase capability of the FTFL module
; <o.6..7> KEYEN
; <2=> Backdoor key access enabled
; <3=> Backdoor key access disabled
; <i> Backdoor key Security Enable
; <i> These bits enable and disable backdoor key access to the FTFL module.
FSEC EQU 0xFE
; </h>
; </h>
IF :LNOT::DEF:RAM_TARGET
AREA |.ARM.__at_0x400|, CODE, READONLY
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
DCB FPROT0, FPROT1, FPROT2, FPROT3
DCB FSEC, FOPT, FEPROT, FDPROT
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DMA0_IRQHandler [WEAK]
EXPORT DMA1_IRQHandler [WEAK]
EXPORT DMA2_IRQHandler [WEAK]
EXPORT DMA3_IRQHandler [WEAK]
EXPORT DMA_Error_IRQHandler [WEAK]
EXPORT Reserved21_IRQHandler [WEAK]
EXPORT FTFL_IRQHandler [WEAK]
EXPORT Read_Collision_IRQHandler [WEAK]
EXPORT LVD_LVW_IRQHandler [WEAK]
EXPORT LLW_IRQHandler [WEAK]
EXPORT Watchdog_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT I2S0_Tx_IRQHandler [WEAK]
EXPORT I2S0_Rx_IRQHandler [WEAK]
EXPORT UART0_LON_IRQHandler [WEAK]
EXPORT UART0_RX_TX_IRQHandler [WEAK]
EXPORT UART0_ERR_IRQHandler [WEAK]
EXPORT UART1_RX_TX_IRQHandler [WEAK]
EXPORT UART1_ERR_IRQHandler [WEAK]
EXPORT UART2_RX_TX_IRQHandler [WEAK]
EXPORT UART2_ERR_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT CMP0_IRQHandler [WEAK]
EXPORT CMP1_IRQHandler [WEAK]
EXPORT FTM0_IRQHandler [WEAK]
EXPORT FTM1_IRQHandler [WEAK]
EXPORT CMT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RTC_Seconds_IRQHandler [WEAK]
EXPORT PIT0_IRQHandler [WEAK]
EXPORT PIT1_IRQHandler [WEAK]
EXPORT PIT2_IRQHandler [WEAK]
EXPORT PIT3_IRQHandler [WEAK]
EXPORT PDB0_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USBDCD_IRQHandler [WEAK]
EXPORT TSI0_IRQHandler [WEAK]
EXPORT MCG_IRQHandler [WEAK]
EXPORT LPTimer_IRQHandler [WEAK]
EXPORT PORTA_IRQHandler [WEAK]
EXPORT PORTB_IRQHandler [WEAK]
EXPORT PORTC_IRQHandler [WEAK]
EXPORT PORTD_IRQHandler [WEAK]
EXPORT PORTE_IRQHandler [WEAK]
EXPORT SWI_IRQHandler [WEAK]
EXPORT DefaultISR [WEAK]
DMA0_IRQHandler
DMA1_IRQHandler
DMA2_IRQHandler
DMA3_IRQHandler
DMA_Error_IRQHandler
Reserved21_IRQHandler
FTFL_IRQHandler
Read_Collision_IRQHandler
LVD_LVW_IRQHandler
LLW_IRQHandler
Watchdog_IRQHandler
I2C0_IRQHandler
SPI0_IRQHandler
I2S0_Tx_IRQHandler
I2S0_Rx_IRQHandler
UART0_LON_IRQHandler
UART0_RX_TX_IRQHandler
UART0_ERR_IRQHandler
UART1_RX_TX_IRQHandler
UART1_ERR_IRQHandler
UART2_RX_TX_IRQHandler
UART2_ERR_IRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
CMP1_IRQHandler
FTM0_IRQHandler
FTM1_IRQHandler
CMT_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
PIT0_IRQHandler
PIT1_IRQHandler
PIT2_IRQHandler
PIT3_IRQHandler
PDB0_IRQHandler
USB0_IRQHandler
USBDCD_IRQHandler
TSI0_IRQHandler
MCG_IRQHandler
LPTimer_IRQHandler
PORTA_IRQHandler
PORTB_IRQHandler
PORTC_IRQHandler
PORTD_IRQHandler
PORTE_IRQHandler
SWI_IRQHandler
DefaultISR
B .
ENDP
ALIGN
END

31
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/TOOLCHAIN_ARM_STD/sys.cpp Normal file
View File

@ -0,0 +1,31 @@
/* mbed Microcontroller Library - stackheap
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* Setup a fixed single stack/heap memory model,
* between the top of the RW/ZI region and the stackpointer
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$RW_IRAM1$$ZI$$Limit[];
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
return r;
}
#ifdef __cplusplus
}
#endif

163
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/TOOLCHAIN_GCC_ARM/MK20D5.ld Normal file
View File

@ -0,0 +1,163 @@
/*
* K20 ARM GCC linker script file
*/
MEMORY
{
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 128K - 0x00000410
RAM (rwx) : ORIGIN = 0x1FFFE0F8, LENGTH = 16K - 0xF8
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* _reset_init : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
*(.text.Reset_Handler)
*(.text.System_Init)
. = ALIGN(4);
} > VECTORS
.flash_protect :
{
KEEP(*(.kinetis_flash_config_field))
. = ALIGN(4);
} > FLASH_PROTECTION
.text :
{
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
{
*(.stack)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

259
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s Normal file
View File

@ -0,0 +1,259 @@
/* File: startup_MK20D5.s
* Purpose: startup file for Cortex-M4 devices. Should use with
* GCC for ARM Embedded Processors
* Version: V1.3
* Date: 08 Feb 2012
*
* Copyright (c) 2012, ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the ARM Limited nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.syntax unified
.arch armv7-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0xC00
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .isr_vector
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long DMA0_IRQHandler /* 0: Watchdog Timer */
.long DMA1_IRQHandler /* 1: Real Time Clock */
.long DMA2_IRQHandler /* 2: Timer0 / Timer1 */
.long DMA3_IRQHandler /* 3: Timer2 / Timer3 */
.long DMA_Error_IRQHandler /* 4: MCIa */
.long 0 /* 5: MCIb */
.long FTFL_IRQHandler /* 6: UART0 - DUT FPGA */
.long Read_Collision_IRQHandler /* 7: UART1 - DUT FPGA */
.long LVD_LVW_IRQHandler /* 8: UART2 - DUT FPGA */
.long LLW_IRQHandler /* 9: UART4 - not connected */
.long Watchdog_IRQHandler /* 10: AACI / AC97 */
.long I2C0_IRQHandler /* 11: CLCD Combined Interrupt */
.long SPI0_IRQHandler /* 12: Ethernet */
.long I2S0_Tx_IRQHandler /* 13: USB Device */
.long I2S0_Rx_IRQHandler /* 14: USB Host Controller */
.long UART0_LON_IRQHandler /* 15: Character LCD */
.long UART0_RX_TX_IRQHandler /* 16: Flexray */
.long UART0_ERR_IRQHandler /* 17: CAN */
.long UART1_RX_TX_IRQHandler /* 18: LIN */
.long UART1_ERR_IRQHandler /* 19: I2C ADC/DAC */
.long UART2_RX_TX_IRQHandler /* 20: Reserved */
.long UART2_ERR_IRQHandler /* 21: Reserved */
.long ADC0_IRQHandler /* 22: Reserved */
.long CMP0_IRQHandler /* 23: Reserved */
.long CMP1_IRQHandler /* 24: Reserved */
.long FTM0_IRQHandler /* 25: Reserved */
.long FTM1_IRQHandler /* 26: Reserved */
.long CMT_IRQHandler /* 27: Reserved */
.long RTC_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
.long RTC_Seconds_IRQHandler /* 29: Reserved - CPU FPGA */
.long PIT0_IRQHandler /* 30: UART3 - CPU FPGA */
.long PIT1_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
.long PIT2_IRQHandler
.long PIT3_IRQHandler
.long PDB0_IRQHandler
.long USB0_IRQHandler
.long USBDCD_IRQHandler
.long TSI0_IRQHandler
.long MCG_IRQHandler
.long LPTimer_IRQHandler
.long PORTA_IRQHandler
.long PORTB_IRQHandler
.long PORTC_IRQHandler
.long PORTD_IRQHandler
.long PORTE_IRQHandler
.long SWI_IRQHandler
.size __isr_vector, . - __isr_vector
.section .text.Reset_Handler
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.Lflash_to_ram_loop:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
def_default_handler BusFault_Handler
def_default_handler UsageFault_Handler
def_default_handler SVC_Handler
def_default_handler DebugMon_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_default_handler DMA0_IRQHandler
def_irq_default_handler DMA1_IRQHandler
def_irq_default_handler DMA2_IRQHandler
def_irq_default_handler DMA3_IRQHandler
def_irq_default_handler DMA_Error_IRQHandler
def_irq_default_handler FTFL_IRQHandler
def_irq_default_handler Read_Collision_IRQHandler
def_irq_default_handler LVD_LVW_IRQHandler
def_irq_default_handler LLW_IRQHandler
def_irq_default_handler Watchdog_IRQHandler
def_irq_default_handler I2C0_IRQHandler
def_irq_default_handler SPI0_IRQHandler
def_irq_default_handler I2S0_Tx_IRQHandler
def_irq_default_handler I2S0_Rx_IRQHandler
def_irq_default_handler UART0_LON_IRQHandler
def_irq_default_handler UART0_RX_TX_IRQHandler
def_irq_default_handler UART0_ERR_IRQHandler
def_irq_default_handler UART1_RX_TX_IRQHandler
def_irq_default_handler UART1_ERR_IRQHandler
def_irq_default_handler UART2_RX_TX_IRQHandler
def_irq_default_handler UART2_ERR_IRQHandler
def_irq_default_handler ADC0_IRQHandler
def_irq_default_handler CMP0_IRQHandler
def_irq_default_handler CMP1_IRQHandler
def_irq_default_handler FTM0_IRQHandler
def_irq_default_handler FTM1_IRQHandler
def_irq_default_handler CMT_IRQHandler
def_irq_default_handler RTC_IRQHandler
def_irq_default_handler RTC_Seconds_IRQHandler
def_irq_default_handler PIT0_IRQHandler
def_irq_default_handler PIT1_IRQHandler
def_irq_default_handler PIT2_IRQHandler
def_irq_default_handler PIT3_IRQHandler
def_irq_default_handler PDB0_IRQHandler
def_irq_default_handler USB0_IRQHandler
def_irq_default_handler USBDCD_IRQHandler
def_irq_default_handler TSI0_IRQHandler
def_irq_default_handler MCG_IRQHandler
def_irq_default_handler LPTimer_IRQHandler
def_irq_default_handler PORTA_IRQHandler
def_irq_default_handler PORTB_IRQHandler
def_irq_default_handler PORTC_IRQHandler
def_irq_default_handler PORTD_IRQHandler
def_irq_default_handler PORTE_IRQHandler
def_irq_default_handler SWI_IRQHandler
def_irq_default_handler DEF_IRQHandler
/* Flash protection region, placed at 0x400 */
.text
.thumb
.align 2
.section .kinetis_flash_config_field,"a",%progbits
kinetis_flash_config:
.long 0xffffffff
.long 0xffffffff
.long 0xffffffff
.long 0xfffffffe
.end

13
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/cmsis.h Normal file
View File

@ -0,0 +1,13 @@
/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in LPC11U24 specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "MK20D5.h"
#include "cmsis_nvic.h"
#endif

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/cmsis_nvic.c → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/cmsis_nvic.c
View File

26
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/cmsis_nvic.h Normal file
View File

@ -0,0 +1,26 @@
/* mbed Microcontroller Library - cmsis_nvic
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 46) // CORE + MCU Peripherals
#define NVIC_USER_IRQ_OFFSET 16
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

278
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/system_MK20D5.c Normal file
View File

@ -0,0 +1,278 @@
/*
** ###################################################################
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
** K20P32M50SF0RM Rev. 1, Oct 2011
** K20P48M50SF0RM Rev. 1, Oct 2011
**
** Version: rev. 1.0, 2011-12-15
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2011 Freescale Semiconductor, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2011-12-15)
** Initial version
**
** ###################################################################
*/
/**
* @file MK20D5
* @version 1.0
* @date 2011-12-15
* @brief Device specific configuration file for MK20D5 (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "MK20D5.h"
#define DISABLE_WDOG 1
#define CLOCK_SETUP 1
/* Predefined clock setups
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
Reference clock source for MCG module is the slow internal clock source 32.768kHz
Core clock = 41.94MHz, BusClock = 41.94MHz
1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
Reference clock source for MCG module is an external crystal 8MHz
Core clock = 48MHz, BusClock = 48MHz
2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
Core clock = 8MHz, BusClock = 8MHz
*/
/*----------------------------------------------------------------------------
Define clock source values
*----------------------------------------------------------------------------*/
#if (CLOCK_SETUP == 0)
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
#elif (CLOCK_SETUP == 1)
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
#elif (CLOCK_SETUP == 2)
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
#endif /* (CLOCK_SETUP == 2) */
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit (void) {
#if (DISABLE_WDOG)
/* Disable the WDOG module */
/* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
/* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
/* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
WDOG->STCTRLH = (uint16_t)0x01D2u;
#endif /* (DISABLE_WDOG) */
#if (CLOCK_SETUP == 0)
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
/* Switch to FEI Mode */
/* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (uint8_t)0x06u;
/* MCG->C2: ??=0,??=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
MCG->C2 = (uint8_t)0x00u;
/* MCG_C4: DMX32=0,DRST_DRS=1 */
MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u);
/* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
MCG->C5 = (uint8_t)0x00u;
/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
MCG->C6 = (uint8_t)0x00u;
while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */
}
while((MCG->S & 0x0Cu) != 0x00u) { /* Wait until output of the FLL is selected */
}
#elif (CLOCK_SETUP == 1)
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
/* Switch to FBE Mode */
/* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0->CR = (uint8_t)0x00u;
/* MCG->C7: OSCSEL=0 */
MCG->C7 = (uint8_t)0x00u;
/* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
MCG->C2 = (uint8_t)0x24u;
/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (uint8_t)0x9Au;
/* MCG->C4: DMX32=0,DRST_DRS=0 */
MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
/* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
MCG->C5 = (uint8_t)0x03u;
/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
MCG->C6 = (uint8_t)0x00u;
while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
}
#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
#endif
while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
}
/* Switch to PBE Mode */
/* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
MCG->C5 = (uint8_t)0x03u;
/* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */
MCG->C6 = (uint8_t)0x40u;
while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */
}
while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
}
/* Switch to PEE Mode */
/* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (uint8_t)0x1Au;
while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */
}
while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
}
#elif (CLOCK_SETUP == 2)
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
/* Switch to FBE Mode */
/* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0->CR = (uint8_t)0x00u;
/* MCG->C7: OSCSEL=0 */
MCG->C7 = (uint8_t)0x00u;
/* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
MCG->C2 = (uint8_t)0x24u;
/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (uint8_t)0x9Au;
/* MCG->C4: DMX32=0,DRST_DRS=0 */
MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
/* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
MCG->C5 = (uint8_t)0x00u;
/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
MCG->C6 = (uint8_t)0x00u;
while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
}
#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
#endif
while((MCG->S & 0x0CU) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
}
/* Switch to BLPE Mode */
/* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
MCG->C2 = (uint8_t)0x24u;
#endif /* (CLOCK_SETUP == 2) */
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate (void) {
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
uint8_t Divider;
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
/* Output of FLL or PLL is selected */
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
/* FLL is selected */
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
/* External reference clock is selected */
if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
} else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
} /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
} /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
/* Select correct multiplier to calculate the MCG output clock */
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
case 0x0u:
MCGOUTClock *= 640u;
break;
case 0x20u:
MCGOUTClock *= 1280u;
break;
case 0x40u:
MCGOUTClock *= 1920u;
break;
case 0x60u:
MCGOUTClock *= 2560u;
break;
case 0x80u:
MCGOUTClock *= 732u;
break;
case 0xA0u:
MCGOUTClock *= 1464u;
break;
case 0xC0u:
MCGOUTClock *= 2197u;
break;
case 0xE0u:
MCGOUTClock *= 2929u;
break;
default:
break;
}
} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
/* PLL is selected */
Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
MCGOUTClock *= Divider; /* Calculate the MCG output clock */
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
/* Internal reference clock is selected */
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
/* External reference clock is selected */
if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
} else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
} /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
/* Reserved value */
return;
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
}

87
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D5M/system_MK20D5.h Normal file
View File

@ -0,0 +1,87 @@
/*
** ###################################################################
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
** K20P32M50SF0RM Rev. 1, Oct 2011
** K20P48M50SF0RM Rev. 1, Oct 2011
**
** Version: rev. 2.0, 2012-03-19
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2011-12-15)
** Initial version
** - rev. 2.0 (2012-03-19)
** PDB Peripheral register structure updated.
** DMA Registers and bits for unsupported DMA channels removed.
**
** ###################################################################
*/
/**
* @file MK20D5
* @version 2.0
* @date 2012-03-19
* @brief Device specific configuration file for MK20D5 (header file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#ifndef SYSTEM_MK20D5_H_
#define SYSTEM_MK20D5_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit (void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* #if !defined(SYSTEM_MK20D5_H_) */

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL05Z/MKL05Z4.h → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/MKL05Z4.h
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL05Z/TOOLCHAIN_ARM_STD/MKL05Z4.sct → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/MKL05Z4.sct
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL05Z/TOOLCHAIN_ARM_STD/startup_MKL05Z4.s → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/startup_MKL05Z4.s
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL05Z/TOOLCHAIN_ARM_STD/sys.cpp → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/sys.cpp
View File

154
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_GCC_ARM/MKL05Z4.ld Normal file
View File

@ -0,0 +1,154 @@
/*
* KL05Z ARM GCC linker script file, Martin Kojtal (0xc0170)
*/
MEMORY
{
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000410
FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 32K - 0x00000410
RAM (rwx) : ORIGIN = 0x1FFFFC00, LENGTH = 4K - 0xC0
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* _reset_init : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
. = ALIGN(4);
} > VECTORS
.text :
{
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
{
*(.stack)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

225
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_GCC_ARM/startup_MKL05Z4.s Normal file
View File

@ -0,0 +1,225 @@
/* KL05Z startup ARM GCC, Martin Kojtal (0xc0170)
* Purpose: startup file for Cortex-M0 devices. Should use with
* GCC for ARM Embedded Processors
* Version: V1.2
* Date: 15 Nov 2011
*
* Copyright (c) 2011, ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the ARM Limited nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.syntax unified
.arch armv6-m
/* Memory Model
The HEAP starts at the end of the DATA section and grows upward.
The STACK starts at the end of the RAM and grows downward.
The HEAP and stack STACK are only checked at compile time:
(DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
This is just a check for the bare minimum for the Heap+Stack area before
aborting compilation, it is not the run time limit:
Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
*/
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x80
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x80
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.space Heap_Size
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vector_table,"a",%progbits
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long DMA0_IRQHandler /* DMA channel 0 transfer complete interrupt */
.long DMA1_IRQHandler /* DMA channel 1 transfer complete interrupt */
.long DMA2_IRQHandler /* DMA channel 2 transfer complete interrupt */
.long DMA3_IRQHandler /* DMA channel 3 transfer complete interrupt */
.long Default_Handler /* Reserved interrupt 20 */
.long FTFA_IRQHandler /* FTFA interrupt */
.long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */
.long LLW_IRQHandler /* Low Leakage Wakeup */
.long I2C0_IRQHandler /* I2C0 interrupt */
.long Default_Handler /* Reserved interrupt 25 */
.long SPI0_IRQHandler /* SPI0 interrupt */
.long Default_Handler /* Reserved interrupt 27 */
.long UART0_IRQHandler /* UART0 status/error interrupt */
.long Default_Handler /* Reserved interrupt 29 */
.long Default_Handler /* Reserved interrupt 30 */
.long ADC0_IRQHandler /* ADC0 interrupt */
.long CMP0_IRQHandler /* CMP0 interrupt */
.long TPM0_IRQHandler /* TPM0 fault, overflow and channels interrupt */
.long TPM1_IRQHandler /* TPM1 fault, overflow and channels interrupt */
.long Default_Handler /* Reserved interrupt 35 */
.long RTC_IRQHandler /* RTC interrupt */
.long RTC_Seconds_IRQHandler /* RTC seconds interrupt */
.long PIT_IRQHandler /* PIT timer interrupt */
.long Default_Handler /* Reserved interrupt 39 */
.long Default_Handler /* Reserved interrupt 40 */
.long DAC0_IRQHandler /* DAC interrupt */
.long TSI0_IRQHandler /* TSI0 interrupt */
.long MCG_IRQHandler /* MCG interrupt */
.long LPTimer_IRQHandler /* LPTimer interrupt */
.long Default_Handler /* Reserved interrupt 45 */
.long PORTA_IRQHandler /* Port A interrupt */
.long PORTB_IRQHandler /* Port B interrupt */
.size __isr_vector, . - __isr_vector
.org 0x400, 0xff
.long 0xffffffff
.long 0xffffffff
.long 0xffffffff
.long 0xfffffffe
.section .text.Reset_Handler
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .flash_to_ram_loop_end
movs r4, 0
.flash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .flash_to_ram_loop
.flash_to_ram_loop_end:
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler SVC_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
def_default_handler DMA0_IRQHandler
def_default_handler DMA1_IRQHandler
def_default_handler DMA2_IRQHandler
def_default_handler DMA3_IRQHandler
def_default_handler FTFA_IRQHandler
def_default_handler LVD_LVW_IRQHandler
def_default_handler LLW_IRQHandler
def_default_handler I2C0_IRQHandler
def_default_handler SPI0_IRQHandler
def_default_handler UART0_IRQHandler
def_default_handler ADC0_IRQHandler
def_default_handler CMP0_IRQHandler
def_default_handler TPM0_IRQHandler
def_default_handler TPM1_IRQHandler
def_default_handler RTC_IRQHandler
def_default_handler RTC_Seconds_IRQHandler
def_default_handler PIT_IRQHandler
def_default_handler DAC0_IRQHandler
def_default_handler TSI0_IRQHandler
def_default_handler MCG_IRQHandler
def_default_handler LPTimer_IRQHandler
def_default_handler PORTA_IRQHandler
def_default_handler PORTB_IRQHandler
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
.end

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL05Z/cmsis.h → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis.h
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL05Z/cmsis_nvic.c → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis_nvic.c
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL05Z/cmsis_nvic.h → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis_nvic.h
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL05Z/system_MKL05Z4.c → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.c
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL05Z/system_MKL05Z4.h → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.h
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/MKL25Z4.h → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/MKL25Z4.h
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/MKL25Z4.sct → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/MKL25Z4.sct
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/startup_MKL25Z4.s → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/startup_MKL25Z4.s
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/sys.cpp → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/sys.cpp
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_ARM_STD/MKL25Z4.sct → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/MKL25Z4.sct
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_ARM_STD/startup_MKL25Z4.s → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/startup_MKL25Z4.s
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_ARM_STD/sys.cpp → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/sys.cpp
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/MKL25Z4.ld → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/MKL25Z4.ld
View File

73
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/startup_MKL25Z4.s → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/startup_MKL25Z4.s
View File

@ -150,16 +150,16 @@ Reset_Handler:
ldr r3, =__data_end__
subs r3, r2
ble .flash_to_ram_loop_end
ble .Lflash_to_ram_loop_end
movs r4, 0
.flash_to_ram_loop:
.Lflash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .flash_to_ram_loop
.flash_to_ram_loop_end:
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
ldr r0, =SystemInit
blx r0
@ -189,38 +189,41 @@ Reset_Handler:
def_default_handler SysTick_Handler
def_default_handler Default_Handler
def_default_handler DMA0_IRQHandler
def_default_handler DMA1_IRQHandler
def_default_handler DMA2_IRQHandler
def_default_handler DMA3_IRQHandler
def_default_handler FTFA_IRQHandler
def_default_handler LVD_LVW_IRQHandler
def_default_handler LLW_IRQHandler
def_default_handler I2C0_IRQHandler
def_default_handler I2C1_IRQHandler
def_default_handler SPI0_IRQHandler
def_default_handler SPI1_IRQHandler
def_default_handler UART0_IRQHandler
def_default_handler UART1_IRQHandler
def_default_handler UART2_IRQHandler
def_default_handler ADC0_IRQHandler
def_default_handler CMP0_IRQHandler
def_default_handler TPM0_IRQHandler
def_default_handler TPM1_IRQHandler
def_default_handler TPM2_IRQHandler
def_default_handler RTC_IRQHandler
def_default_handler RTC_Seconds_IRQHandler
def_default_handler PIT_IRQHandler
def_default_handler USB0_IRQHandler
def_default_handler DAC0_IRQHandler
def_default_handler TSI0_IRQHandler
def_default_handler MCG_IRQHandler
def_default_handler LPTimer_IRQHandler
def_default_handler PORTA_IRQHandler
def_default_handler PORTD_IRQHandler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
def_irq_default_handler DMA0_IRQHandler
def_irq_default_handler DMA1_IRQHandler
def_irq_default_handler DMA2_IRQHandler
def_irq_default_handler DMA3_IRQHandler
def_irq_default_handler FTFA_IRQHandler
def_irq_default_handler LVD_LVW_IRQHandler
def_irq_default_handler LLW_IRQHandler
def_irq_default_handler I2C0_IRQHandler
def_irq_default_handler I2C1_IRQHandler
def_irq_default_handler SPI0_IRQHandler
def_irq_default_handler SPI1_IRQHandler
def_irq_default_handler UART0_IRQHandler
def_irq_default_handler UART1_IRQHandler
def_irq_default_handler UART2_IRQHandler
def_irq_default_handler ADC0_IRQHandler
def_irq_default_handler CMP0_IRQHandler
def_irq_default_handler TPM0_IRQHandler
def_irq_default_handler TPM1_IRQHandler
def_irq_default_handler TPM2_IRQHandler
def_irq_default_handler RTC_IRQHandler
def_irq_default_handler RTC_Seconds_IRQHandler
def_irq_default_handler PIT_IRQHandler
def_irq_default_handler USB0_IRQHandler
def_irq_default_handler DAC0_IRQHandler
def_irq_default_handler TSI0_IRQHandler
def_irq_default_handler MCG_IRQHandler
def_irq_default_handler LPTimer_IRQHandler
def_irq_default_handler PORTA_IRQHandler
def_irq_default_handler PORTD_IRQHandler
def_irq_default_handler DEF_IRQHandler
/* Flash protection region, placed at 0x400 */
.text

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_GCC_CW_EWL/MKL25Z4.ld → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_EWL/MKL25Z4.ld
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_GCC_CW_EWL/startup_MKL25Z4.c → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_EWL/startup_MKL25Z4.c
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_GCC_CW_NEWLIB/MKL25Z4.ld → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_NEWLIB/MKL25Z4.ld
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_GCC_CW_NEWLIB/startup_MKL25Z4.s → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_NEWLIB/startup_MKL25Z4.s
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/cmsis.h → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis.h
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/cmsis_nvic.c → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis_nvic.c
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/cmsis_nvic.h → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis_nvic.h
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.c → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.c
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.h → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.h
View File

301
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/MKL46Z4.h → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/MKL46Z4.h
View File

File diff suppressed because it is too large Load Diff

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/TOOLCHAIN_ARM_STD/MKL46Z4.sct → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/MKL46Z4.sct
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/TOOLCHAIN_ARM_STD/startup_MKL46Z4.s → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/startup_MKL46Z4.s
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/TOOLCHAIN_ARM_STD/sys.cpp → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/sys.cpp
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/MKL46Z4.ld → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/MKL46Z4.ld
View File

81
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/startup_MKL46Z4.s → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/startup_MKL46Z4.s
View File

@ -150,16 +150,16 @@ Reset_Handler:
ldr r3, =__data_end__
subs r3, r2
ble .flash_to_ram_loop_end
ble .Lflash_to_ram_loop_end
movs r4, 0
.flash_to_ram_loop:
.Lflash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .flash_to_ram_loop
.flash_to_ram_loop_end:
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
ldr r0, =SystemInit
blx r0
@ -187,44 +187,45 @@ Reset_Handler:
def_default_handler SVC_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
def_default_handler Default_Handler
def_default_handler DMA0_IRQHandler
def_default_handler DMA1_IRQHandler
def_default_handler DMA2_IRQHandler
def_default_handler DMA3_IRQHandler
def_default_handler FTFA_IRQHandler
def_default_handler LVD_LVW_IRQHandler
def_default_handler LLW_IRQHandler
def_default_handler I2C0_IRQHandler
def_default_handler I2C1_IRQHandler
def_default_handler SPI0_IRQHandler
def_default_handler SPI1_IRQHandler
def_default_handler UART0_IRQHandler
def_default_handler UART1_IRQHandler
def_default_handler UART2_IRQHandler
def_default_handler ADC0_IRQHandler
def_default_handler CMP0_IRQHandler
def_default_handler TPM0_IRQHandler
def_default_handler TPM1_IRQHandler
def_default_handler TPM2_IRQHandler
def_default_handler RTC_IRQHandler
def_default_handler RTC_Seconds_IRQHandler
def_default_handler PIT_IRQHandler
def_default_handler I2S_IRQHandler
def_default_handler USB0_IRQHandler
def_default_handler DAC0_IRQHandler
def_default_handler TSI0_IRQHandler
def_default_handler MCG_IRQHandler
def_default_handler LPTimer_IRQHandler
def_default_handler LCD_IRQHandler
def_default_handler PORTA_IRQHandler
def_default_handler PORTD_IRQHandler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
def_irq_default_handler DMA0_IRQHandler
def_irq_default_handler DMA1_IRQHandler
def_irq_default_handler DMA2_IRQHandler
def_irq_default_handler DMA3_IRQHandler
def_irq_default_handler FTFA_IRQHandler
def_irq_default_handler LVD_LVW_IRQHandler
def_irq_default_handler LLW_IRQHandler
def_irq_default_handler I2C0_IRQHandler
def_irq_default_handler I2C1_IRQHandler
def_irq_default_handler SPI0_IRQHandler
def_irq_default_handler SPI1_IRQHandler
def_irq_default_handler UART0_IRQHandler
def_irq_default_handler UART1_IRQHandler
def_irq_default_handler UART2_IRQHandler
def_irq_default_handler ADC0_IRQHandler
def_irq_default_handler CMP0_IRQHandler
def_irq_default_handler TPM0_IRQHandler
def_irq_default_handler TPM1_IRQHandler
def_irq_default_handler TPM2_IRQHandler
def_irq_default_handler RTC_IRQHandler
def_irq_default_handler RTC_Seconds_IRQHandler
def_irq_default_handler PIT_IRQHandler
def_irq_default_handler I2S_IRQHandler
def_irq_default_handler USB0_IRQHandler
def_irq_default_handler DAC0_IRQHandler
def_irq_default_handler TSI0_IRQHandler
def_irq_default_handler MCG_IRQHandler
def_irq_default_handler LPTimer_IRQHandler
def_irq_default_handler LCD_IRQHandler
def_irq_default_handler PORTA_IRQHandler
def_irq_default_handler PORTD_IRQHandler
def_irq_default_handler DEF_IRQHandler
/* Flash protection region, placed at 0x400 */
.text

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/cmsis.h → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis.h
View File

30
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis_nvic.c Normal file
View File

@ -0,0 +1,30 @@
/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
* Copyright (c) 2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFE000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
uint32_t i;
// Copy and switch to dynamic vectors if the first time called
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
uint32_t *old_vectors = vectors;
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
for (i=0; i<NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
}
vectors[IRQn + 16] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + 16];
}

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/cmsis_nvic.h → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis_nvic.h
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/system_MKL46Z4.c → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.c
View File

0
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/system_MKL46Z4.h → libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.h
View File

63
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s
View File

@ -150,16 +150,16 @@ Reset_Handler:
ldr r3, =__data_end__
subs r3, r2
ble .flash_to_ram_loop_end
ble .Lflash_to_ram_loop_end
movs r4, 0
.flash_to_ram_loop:
.Lflash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .flash_to_ram_loop
.flash_to_ram_loop_end:
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
ldr r0, =SystemInit
blx r0
@ -181,33 +181,36 @@ Reset_Handler:
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler SVC_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
def_default_handler WAKEUP_IRQHandler
def_default_handler SSP1_IRQHandler
def_default_handler I2C_IRQHandler
def_default_handler TIMER16_0_IRQHandler
def_default_handler TIMER16_1_IRQHandler
def_default_handler TIMER32_0_IRQHandler
def_default_handler TIMER32_1_IRQHandler
def_default_handler SSP0_IRQHandler
def_default_handler UART_IRQHandler
def_default_handler ADC_IRQHandler
def_default_handler WDT_IRQHandler
def_default_handler BOD_IRQHandler
def_default_handler PIOINT3_IRQHandler
def_default_handler PIOINT2_IRQHandler
def_default_handler PIOINT1_IRQHandler
def_default_handler PIOINT0_IRQHandler
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler SVC_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_default_handler WAKEUP_IRQHandler
def_irq_default_handler SSP1_IRQHandler
def_irq_default_handler I2C_IRQHandler
def_irq_default_handler TIMER16_0_IRQHandler
def_irq_default_handler TIMER16_1_IRQHandler
def_irq_default_handler TIMER32_0_IRQHandler
def_irq_default_handler TIMER32_1_IRQHandler
def_irq_default_handler SSP0_IRQHandler
def_irq_default_handler UART_IRQHandler
def_irq_default_handler ADC_IRQHandler
def_irq_default_handler WDT_IRQHandler
def_irq_default_handler BOD_IRQHandler
def_irq_default_handler PIOINT3_IRQHandler
def_irq_default_handler PIOINT2_IRQHandler
def_irq_default_handler PIOINT1_IRQHandler
def_irq_default_handler PIOINT0_IRQHandler
def_irq_default_handler DEF_IRQHandler
.end

1
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/LPC11U24.ld
View File

@ -145,6 +145,7 @@ SECTIONS
. = ALIGN(4) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
} > RamLoc8
PROVIDE(_pvHeapStart = .);

16
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp
View File

@ -9,7 +9,7 @@ extern "C" {
void ResetISR (void);
WEAK void NMI_Handler (void);
WEAK void HardFault_Handler (void);
WEAK void SVCall_Handler (void);
WEAK void SVC_Handler (void);
WEAK void PendSV_Handler (void);
WEAK void SysTick_Handler (void);
WEAK void IntDefaultHandler (void);
@ -57,7 +57,7 @@ void (* const g_pfnVectors[])(void) = {
0,
0,
0,
SVCall_Handler,
SVC_Handler,
0,
0,
PendSV_Handler,
@ -113,6 +113,8 @@ extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table_end;
extern "C" void software_init_hook(void) __attribute__((weak));
AFTER_VECTORS void ResetISR(void) {
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
@ -134,14 +136,18 @@ AFTER_VECTORS void ResetISR(void) {
}
SystemInit();
__libc_init_array();
main();
if (software_init_hook) // give control to the RTOS
software_init_hook(); // this will also call __libc_init_array
else {
__libc_init_array();
main();
}
while (1) {;}
}
AFTER_VECTORS void NMI_Handler (void) {while(1){}}
AFTER_VECTORS void HardFault_Handler(void) {while(1){}}
AFTER_VECTORS void SVCall_Handler (void) {while(1){}}
AFTER_VECTORS void SVC_Handler (void) {while(1){}}
AFTER_VECTORS void PendSV_Handler (void) {while(1){}}
AFTER_VECTORS void SysTick_Handler (void) {while(1){}}
AFTER_VECTORS void IntDefaultHandler(void) {while(1){}}

63
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s
View File

@ -150,16 +150,16 @@ Reset_Handler:
ldr r3, =__data_end__
subs r3, r2
ble .flash_to_ram_loop_end
ble .Lflash_to_ram_loop_end
movs r4, 0
.flash_to_ram_loop:
.Lflash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .flash_to_ram_loop
.flash_to_ram_loop_end:
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
ldr r0, =SystemInit
blx r0
@ -181,33 +181,36 @@ Reset_Handler:
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler SVC_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
def_default_handler WAKEUP_IRQHandler
def_default_handler SSP1_IRQHandler
def_default_handler I2C_IRQHandler
def_default_handler TIMER16_0_IRQHandler
def_default_handler TIMER16_1_IRQHandler
def_default_handler TIMER32_0_IRQHandler
def_default_handler TIMER32_1_IRQHandler
def_default_handler SSP0_IRQHandler
def_default_handler UART_IRQHandler
def_default_handler ADC_IRQHandler
def_default_handler WDT_IRQHandler
def_default_handler BOD_IRQHandler
def_default_handler PIOINT3_IRQHandler
def_default_handler PIOINT2_IRQHandler
def_default_handler PIOINT1_IRQHandler
def_default_handler PIOINT0_IRQHandler
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler SVC_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_default_handler WAKEUP_IRQHandler
def_irq_default_handler SSP1_IRQHandler
def_irq_default_handler I2C_IRQHandler
def_irq_default_handler TIMER16_0_IRQHandler
def_irq_default_handler TIMER16_1_IRQHandler
def_irq_default_handler TIMER32_0_IRQHandler
def_irq_default_handler TIMER32_1_IRQHandler
def_irq_default_handler SSP0_IRQHandler
def_irq_default_handler UART_IRQHandler
def_irq_default_handler ADC_IRQHandler
def_irq_default_handler WDT_IRQHandler
def_irq_default_handler BOD_IRQHandler
def_irq_default_handler PIOINT3_IRQHandler
def_irq_default_handler PIOINT2_IRQHandler
def_irq_default_handler PIOINT1_IRQHandler
def_irq_default_handler PIOINT0_IRQHandler
def_irq_default_handler DEF_IRQHandler
.end

16
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp
View File

@ -9,7 +9,7 @@ extern "C" {
void ResetISR (void);
WEAK void NMI_Handler (void);
WEAK void HardFault_Handler (void);
WEAK void SVCall_Handler (void);
WEAK void SVC_Handler (void);
WEAK void PendSV_Handler (void);
WEAK void SysTick_Handler (void);
WEAK void IntDefaultHandler (void);
@ -57,7 +57,7 @@ void (* const g_pfnVectors[])(void) = {
0,
0,
0,
SVCall_Handler,
SVC_Handler,
0,
0,
PendSV_Handler,
@ -113,6 +113,8 @@ extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table_end;
extern "C" void software_init_hook(void) __attribute__((weak));
AFTER_VECTORS void ResetISR(void) {
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
@ -134,14 +136,18 @@ AFTER_VECTORS void ResetISR(void) {
}
SystemInit();
__libc_init_array();
main();
if (software_init_hook) // give control to the RTOS
software_init_hook(); // this will also call __libc_init_array
else {
__libc_init_array();
main();
}
while (1) {;}
}
AFTER_VECTORS void NMI_Handler (void) {while(1){}}
AFTER_VECTORS void HardFault_Handler(void) {while(1){}}
AFTER_VECTORS void SVCall_Handler (void) {while(1){}}
AFTER_VECTORS void SVC_Handler (void) {while(1){}}
AFTER_VECTORS void PendSV_Handler (void) {while(1){}}
AFTER_VECTORS void SysTick_Handler (void) {while(1){}}
AFTER_VECTORS void IntDefaultHandler(void) {while(1){}}

70
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_GCC_ARM/startup_LPC13xx.s
View File

@ -135,12 +135,12 @@ Reset_Handler:
ldr r2, =__data_start__
ldr r3, =__data_end__
.flash_to_ram_loop:
.Lflash_to_ram_loop:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .flash_to_ram_loop
blt .Lflash_to_ram_loop
ldr r0, =SystemInit
blx r0
@ -149,6 +149,7 @@ Reset_Handler:
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
@ -161,7 +162,7 @@ Reset_Handler:
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
@ -173,37 +174,40 @@ Reset_Handler:
def_default_handler SysTick_Handler
def_default_handler Default_Handler
def_default_handler PIN_INT0_Handler
def_default_handler PIN_INT1_Handler
def_default_handler PIN_INT2_Handler
def_default_handler PIN_INT3_Handler
def_default_handler PIN_INT4_Handler
def_default_handler PIN_INT5_Handler
def_default_handler PIN_INT6_Handler
def_default_handler PIN_INT7_Handler
def_default_handler GINT0_Handler
def_default_handler GINT1_Handler
def_default_handler OSTIMER_Handler
def_default_handler SSP1_Handler
def_default_handler I2C_Handler
def_default_handler CT16B0_Handler
def_default_handler CT16B1_Handler
def_default_handler CT32B0_Handler
def_default_handler CT32B1_Handler
def_default_handler SSP0_Handler
def_default_handler USART_Handler
def_default_handler USB_Handler
def_default_handler USB_FIQHandler
def_default_handler ADC_Handler
def_default_handler WDT_Handler
def_default_handler BOD_Handler
def_default_handler FMC_Handler
def_default_handler OSCFAIL_Handler
def_default_handler PVTCIRCUIT_Handler
def_default_handler USBWakeup_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
def_irq_default_handler PIN_INT0_Handler
def_irq_default_handler PIN_INT1_Handler
def_irq_default_handler PIN_INT2_Handler
def_irq_default_handler PIN_INT3_Handler
def_irq_default_handler PIN_INT4_Handler
def_irq_default_handler PIN_INT5_Handler
def_irq_default_handler PIN_INT6_Handler
def_irq_default_handler PIN_INT7_Handler
def_irq_default_handler GINT0_Handler
def_irq_default_handler GINT1_Handler
def_irq_default_handler OSTIMER_Handler
def_irq_default_handler SSP1_Handler
def_irq_default_handler I2C_Handler
def_irq_default_handler CT16B0_Handler
def_irq_default_handler CT16B1_Handler
def_irq_default_handler CT32B0_Handler
def_irq_default_handler CT32B1_Handler
def_irq_default_handler SSP0_Handler
def_irq_default_handler USART_Handler
def_irq_default_handler USB_Handler
def_irq_default_handler USB_FIQHandler
def_irq_default_handler ADC_Handler
def_irq_default_handler WDT_Handler
def_irq_default_handler BOD_Handler
def_irq_default_handler FMC_Handler
def_irq_default_handler OSCFAIL_Handler
def_irq_default_handler PVTCIRCUIT_Handler
def_irq_default_handler USBWakeup_Handler
def_irq_default_handler DEF_IRQHandler
.end

86
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_ARM/startup_LPC17xx.s
View File

@ -138,12 +138,12 @@ Reset_Handler:
ldr r2, =__data_start__
ldr r3, =__data_end__
.flash_to_ram_loop:
.Lflash_to_ram_loop:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .flash_to_ram_loop
blt .Lflash_to_ram_loop
ldr r0, =SystemInit
blx r0
@ -152,6 +152,7 @@ Reset_Handler:
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
@ -164,7 +165,7 @@ Reset_Handler:
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
@ -175,45 +176,48 @@ Reset_Handler:
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
def_default_handler WDT_IRQHandler
def_default_handler TIMER0_IRQHandler
def_default_handler TIMER1_IRQHandler
def_default_handler TIMER2_IRQHandler
def_default_handler TIMER3_IRQHandler
def_default_handler UART0_IRQHandler
def_default_handler UART1_IRQHandler
def_default_handler UART2_IRQHandler
def_default_handler UART3_IRQHandler
def_default_handler PWM1_IRQHandler
def_default_handler I2C0_IRQHandler
def_default_handler I2C1_IRQHandler
def_default_handler I2C2_IRQHandler
def_default_handler SPI_IRQHandler
def_default_handler SSP0_IRQHandler
def_default_handler SSP1_IRQHandler
def_default_handler PLL0_IRQHandler
def_default_handler RTC_IRQHandler
def_default_handler EINT0_IRQHandler
def_default_handler EINT1_IRQHandler
def_default_handler EINT2_IRQHandler
def_default_handler EINT3_IRQHandler
def_default_handler ADC_IRQHandler
def_default_handler BOD_IRQHandler
def_default_handler USB_IRQHandler
def_default_handler CAN_IRQHandler
def_default_handler DMA_IRQHandler
def_default_handler I2S_IRQHandler
def_default_handler ENET_IRQHandler
def_default_handler RIT_IRQHandler
def_default_handler MCPWM_IRQHandler
def_default_handler QEI_IRQHandler
def_default_handler PLL1_IRQHandler
def_default_handler USBActivity_IRQHandler
def_default_handler CANActivity_IRQHandler
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_default_handler WDT_IRQHandler
def_irq_default_handler TIMER0_IRQHandler
def_irq_default_handler TIMER1_IRQHandler
def_irq_default_handler TIMER2_IRQHandler
def_irq_default_handler TIMER3_IRQHandler
def_irq_default_handler UART0_IRQHandler
def_irq_default_handler UART1_IRQHandler
def_irq_default_handler UART2_IRQHandler
def_irq_default_handler UART3_IRQHandler
def_irq_default_handler PWM1_IRQHandler
def_irq_default_handler I2C0_IRQHandler
def_irq_default_handler I2C1_IRQHandler
def_irq_default_handler I2C2_IRQHandler
def_irq_default_handler SPI_IRQHandler
def_irq_default_handler SSP0_IRQHandler
def_irq_default_handler SSP1_IRQHandler
def_irq_default_handler PLL0_IRQHandler
def_irq_default_handler RTC_IRQHandler
def_irq_default_handler EINT0_IRQHandler
def_irq_default_handler EINT1_IRQHandler
def_irq_default_handler EINT2_IRQHandler
def_irq_default_handler EINT3_IRQHandler
def_irq_default_handler ADC_IRQHandler
def_irq_default_handler BOD_IRQHandler
def_irq_default_handler USB_IRQHandler
def_irq_default_handler CAN_IRQHandler
def_irq_default_handler DMA_IRQHandler
def_irq_default_handler I2S_IRQHandler
def_irq_default_handler ENET_IRQHandler
def_irq_default_handler RIT_IRQHandler
def_irq_default_handler MCPWM_IRQHandler
def_irq_default_handler QEI_IRQHandler
def_irq_default_handler PLL1_IRQHandler
def_irq_default_handler USBActivity_IRQHandler
def_irq_default_handler CANActivity_IRQHandler
def_irq_default_handler DEF_IRQHandler
.end

1
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CR/LPC1768.ld
View File

@ -146,6 +146,7 @@ SECTIONS
. = ALIGN(4) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
} > RamLoc32
PROVIDE(_pvHeapStart = .);

16
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CR/startup_LPC17xx.cpp
View File

@ -22,7 +22,7 @@ WEAK void HardFault_Handler (void);
WEAK void MemManage_Handler (void);
WEAK void BusFault_Handler (void);
WEAK void UsageFault_Handler(void);
WEAK void SVCall_Handler (void);
WEAK void SVC_Handler (void);
WEAK void DebugMon_Handler (void);
WEAK void PendSV_Handler (void);
WEAK void SysTick_Handler (void);
@ -75,7 +75,7 @@ void (* const g_pfnVectors[])(void) = {
0,
0,
0,
SVCall_Handler,
SVC_Handler,
DebugMon_Handler,
0,
PendSV_Handler,
@ -130,6 +130,8 @@ AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
}
extern "C" void software_init_hook(void) __attribute__((weak));
AFTER_VECTORS void ResetISR(void) {
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
@ -149,8 +151,12 @@ AFTER_VECTORS void ResetISR(void) {
}
SystemInit();
__libc_init_array();
main();
if (software_init_hook) // give control to the RTOS
software_init_hook(); // this will also call __libc_init_array
else {
__libc_init_array();
main();
}
while (1) {;}
}
@ -159,7 +165,7 @@ AFTER_VECTORS void HardFault_Handler (void) {}
AFTER_VECTORS void MemManage_Handler (void) {}
AFTER_VECTORS void BusFault_Handler (void) {}
AFTER_VECTORS void UsageFault_Handler(void) {}
AFTER_VECTORS void SVCall_Handler (void) {}
AFTER_VECTORS void SVC_Handler (void) {}
AFTER_VECTORS void DebugMon_Handler (void) {}
AFTER_VECTORS void PendSV_Handler (void) {}
AFTER_VECTORS void SysTick_Handler (void) {}

7
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/TARGET_LPC4088_EA/LPC407X_8X.sct → libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/LPC407X_8X.sct
View File

@ -6,7 +6,9 @@ LR_IROM1 0x00000000 0x00080000 { ; load region size_region
ER_IROM1 0x00000000 0x00080000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
*.o (+RO-CODE) ; forces all CODE to IFLASH
.ANY2 (+RO-DATA) ; prioritizes DATA in IFLASH before SPIFI
.ANY (+RO) ; remaining RO
}
RW_IRAM1 0x100000E8 0x0000FF18 { ; RW data
.ANY (+RW +ZI)
@ -21,7 +23,8 @@ LR_IROM1 0x00000000 0x00080000 { ; load region size_region
LR_IROM2 0x28000000 0x01000000 {
ER_IROM2 0x28000000 0x01000000 { ; load address = execution address
.ANY (+RO)
.ANY1 (+RO-DATA) ; all DATA not fitting in IFLASH
.ANY (SPIFI_MEM) ; DATA tagged as SPIFI_MEM
}
}

18
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/TARGET_LPC4088/LPC407X_8X.sct
View File

@ -1,18 +0,0 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00080000 { ; load region size_region
ER_IROM1 0x00000000 0x00080000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x100000E8 0x0000FF18 { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM2 0x20000000 0x00008000 {
.ANY (AHBSRAM1)
}
}

3
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/sys.cpp
View File

@ -11,6 +11,7 @@ extern "C" {
#include <rt_misc.h>
#include <stdint.h>
#include "sys_helper.h"
extern char Image$$RW_IRAM1$$ZI$$Limit[];
@ -22,7 +23,7 @@ extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
r.heap_limit = sp_limit - __reserved_stack_size();
return r;
}

19
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/sys_helper.cpp Normal file
View File

@ -0,0 +1,19 @@
/* mbed Microcontroller Library - stackheap
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
*/
#include "sys_helper.h"
/* This function specifies the amount of memory of the internal RAM to
reserve for the stack. The default implementation will reserve 0 bytes
which gives the normal behaviour where the stack and heap share all the
internal RAM.
You can override this function in your code to reserve a number of bytes
for the stack.
*/
extern "C" __attribute__((weak)) uint32_t __reserved_stack_size();
extern "C" __attribute__((weak)) uint32_t __reserved_stack_size() {
return 0; // return 0 to indicate that nothing is reserved
}

16
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/sys_helper.h Normal file
View File

@ -0,0 +1,16 @@
#ifndef SYS_HELPER_H
#define SYS_HELPER_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
uint32_t __reserved_stack_size();
#ifdef __cplusplus
}
#endif
#endif

2
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_ARM/LPC4088.ld
View File

@ -4,7 +4,7 @@
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
RAM (rwx) : ORIGIN = 0x100000E8, LENGTH = (32K - 0xE8)
RAM (rwx) : ORIGIN = 0x100000E8, LENGTH = (64K - 0xE8)
USB_RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 16K
ETH_RAM(rwx) : ORIGIN = 0x20004000, LENGTH = 16K

98
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_ARM/startup_LPC408x.s
View File

@ -144,12 +144,12 @@ Reset_Handler:
ldr r2, =__data_start__
ldr r3, =__data_end__
.flash_to_ram_loop:
.Lflash_to_ram_loop:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .flash_to_ram_loop
blt .Lflash_to_ram_loop
ldr r0, =SystemInit
blx r0
@ -158,6 +158,7 @@ Reset_Handler:
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
@ -170,7 +171,7 @@ Reset_Handler:
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
@ -181,51 +182,54 @@ Reset_Handler:
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
def_default_handler WDT_IRQHandler
def_default_handler TIMER0_IRQHandler
def_default_handler TIMER1_IRQHandler
def_default_handler TIMER2_IRQHandler
def_default_handler TIMER3_IRQHandler
def_default_handler UART0_IRQHandler
def_default_handler UART1_IRQHandler
def_default_handler UART2_IRQHandler
def_default_handler UART3_IRQHandler
def_default_handler PWM1_IRQHandler
def_default_handler I2C0_IRQHandler
def_default_handler I2C1_IRQHandler
def_default_handler I2C2_IRQHandler
/* def_default_handler SPI_IRQHandler */
def_default_handler SSP0_IRQHandler
def_default_handler SSP1_IRQHandler
def_default_handler PLL0_IRQHandler
def_default_handler RTC_IRQHandler
def_default_handler EINT0_IRQHandler
def_default_handler EINT1_IRQHandler
def_default_handler EINT2_IRQHandler
def_default_handler EINT3_IRQHandler
def_default_handler ADC_IRQHandler
def_default_handler BOD_IRQHandler
def_default_handler USB_IRQHandler
def_default_handler CAN_IRQHandler
def_default_handler DMA_IRQHandler
def_default_handler I2S_IRQHandler
def_default_handler ENET_IRQHandler
def_default_handler MCI_IRQHandler
def_default_handler MCPWM_IRQHandler
def_default_handler QEI_IRQHandler
def_default_handler PLL1_IRQHandler
def_default_handler USBActivity_IRQHandler
def_default_handler CANActivity_IRQHandler
def_default_handler UART4_IRQHandler
def_default_handler SSP2_IRQHandler
def_default_handler LCD_IRQHandler
def_default_handler GPIO_IRQHandler
def_default_handler PWM0_IRQHandler
def_default_handler EEPROM_IRQHandler
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_default_handler WDT_IRQHandler
def_irq_default_handler TIMER0_IRQHandler
def_irq_default_handler TIMER1_IRQHandler
def_irq_default_handler TIMER2_IRQHandler
def_irq_default_handler TIMER3_IRQHandler
def_irq_default_handler UART0_IRQHandler
def_irq_default_handler UART1_IRQHandler
def_irq_default_handler UART2_IRQHandler
def_irq_default_handler UART3_IRQHandler
def_irq_default_handler PWM1_IRQHandler
def_irq_default_handler I2C0_IRQHandler
def_irq_default_handler I2C1_IRQHandler
def_irq_default_handler I2C2_IRQHandler
/* def_irq_default_handler SPI_IRQHandler */
def_irq_default_handler SSP0_IRQHandler
def_irq_default_handler SSP1_IRQHandler
def_irq_default_handler PLL0_IRQHandler
def_irq_default_handler RTC_IRQHandler
def_irq_default_handler EINT0_IRQHandler
def_irq_default_handler EINT1_IRQHandler
def_irq_default_handler EINT2_IRQHandler
def_irq_default_handler EINT3_IRQHandler
def_irq_default_handler ADC_IRQHandler
def_irq_default_handler BOD_IRQHandler
def_irq_default_handler USB_IRQHandler
def_irq_default_handler CAN_IRQHandler
def_irq_default_handler DMA_IRQHandler
def_irq_default_handler I2S_IRQHandler
def_irq_default_handler ENET_IRQHandler
def_irq_default_handler MCI_IRQHandler
def_irq_default_handler MCPWM_IRQHandler
def_irq_default_handler QEI_IRQHandler
def_irq_default_handler PLL1_IRQHandler
def_irq_default_handler USBActivity_IRQHandler
def_irq_default_handler CANActivity_IRQHandler
def_irq_default_handler UART4_IRQHandler
def_irq_default_handler SSP2_IRQHandler
def_irq_default_handler LCD_IRQHandler
def_irq_default_handler GPIO_IRQHandler
def_irq_default_handler PWM0_IRQHandler
def_irq_default_handler EEPROM_IRQHandler
def_irq_default_handler DEF_IRQHandler
.end

1
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_CR/LPC407x_8x.ld
View File

@ -156,6 +156,7 @@ SECTIONS
. = ALIGN(4) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
} > RamLoc64
/* NOINIT section for RamPeriph32 */

23
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_CR/startup_lpc407x_8x.cpp
View File

@ -259,6 +259,9 @@ extern unsigned int __bss_section_table_end;
// Sets up a simple runtime environment and initializes the C/C++
// library.
//*****************************************************************************
extern "C" void software_init_hook(void) __attribute__((weak));
__attribute__ ((section(".after_vectors")))
void
ResetISR(void) {
@ -319,21 +322,23 @@ ResetISR(void) {
//#ifdef __USE_CMSIS
SystemInit();
//#endif
if (software_init_hook) // give control to the RTOS
software_init_hook(); // this will also call __libc_init_array
else {
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
// Call the Redlib library, which in turn calls main()
__main() ;
#else
main();
main();
#endif
}
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//

170
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_ARM/startup_LPC43xx.s
View File

@ -164,62 +164,25 @@ Reset_Handler:
ldr r2, =__data_start__
ldr r3, =__data_end__
.if 1
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
.LC0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC0
.else
subs r3, r2
ble .LC1
.LC0:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC0
.LC1:
.endif
.ifdef __STARTUP_CLEAR_BSS
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.LC2:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LC2
.endif /* __STARTUP_CLEAR_BSS */
.ifndef __NO_SYSTEM_INIT
bl SystemInit
.endif
.ifndef __START
.set __START,_start
.endif
bl __START
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
@ -229,64 +192,69 @@ Reset_Handler:
.size \handler_name, . - \handler_name
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler Default_Handler
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
def_default_handler BusFault_Handler
def_default_handler UsageFault_Handler
def_default_handler SVC_Handler
def_default_handler DebugMon_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
def_irq_handler DAC_IRQHandler
def_irq_handler M0CORE_IRQHandler
def_irq_handler DMA_IRQHandler
def_irq_handler FLASHEEPROM_IRQHandler
def_irq_handler ETHERNET_IRQHandler
def_irq_handler SDIO_IRQHandler
def_irq_handler LCD_IRQHandler
def_irq_handler USB0_IRQHandler
def_irq_handler USB1_IRQHandler
def_irq_handler SCT_IRQHandler
def_irq_handler RITIMER_IRQHandler
def_irq_handler TIMER0_IRQHandler
def_irq_handler TIMER1_IRQHandler
def_irq_handler TIMER2_IRQHandler
def_irq_handler TIMER3_IRQHandler
def_irq_handler MCPWM_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler I2C0_IRQHandler
def_irq_handler I2C1_IRQHandler
def_irq_handler SPI_IRQHandler
def_irq_handler ADC1_IRQHandler
def_irq_handler SSP0_IRQHandler
def_irq_handler SSP1_IRQHandler
def_irq_handler USART0_IRQHandler
def_irq_handler UART1_IRQHandler
def_irq_handler USART2_IRQHandler
def_irq_handler USART3_IRQHandler
def_irq_handler I2S0_IRQHandler
def_irq_handler I2S1_IRQHandler
def_irq_handler SPIFI_IRQHandler
def_irq_handler SGPIO_IRQHandler
def_irq_handler PIN_INT0_IRQHandler
def_irq_handler PIN_INT1_IRQHandler
def_irq_handler PIN_INT2_IRQHandler
def_irq_handler PIN_INT3_IRQHandler
def_irq_handler PIN_INT4_IRQHandler
def_irq_handler PIN_INT5_IRQHandler
def_irq_handler PIN_INT6_IRQHandler
def_irq_handler PIN_INT7_IRQHandler
def_irq_handler GINT0_IRQHandler
def_irq_handler GINT1_IRQHandler
def_irq_handler EVENTROUTER_IRQHandler
def_irq_handler C_CAN1_IRQHandler
def_irq_handler ATIMER_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler WWDT_IRQHandler
def_irq_handler C_CAN0_IRQHandler
def_irq_handler QEI_IRQHandler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_default_handler DAC_IRQHandler
def_irq_default_handler M0CORE_IRQHandler
def_irq_default_handler DMA_IRQHandler
def_irq_default_handler FLASHEEPROM_IRQHandler
def_irq_default_handler ETHERNET_IRQHandler
def_irq_default_handler SDIO_IRQHandler
def_irq_default_handler LCD_IRQHandler
def_irq_default_handler USB0_IRQHandler
def_irq_default_handler USB1_IRQHandler
def_irq_default_handler SCT_IRQHandler
def_irq_default_handler RITIMER_IRQHandler
def_irq_default_handler TIMER0_IRQHandler
def_irq_default_handler TIMER1_IRQHandler
def_irq_default_handler TIMER2_IRQHandler
def_irq_default_handler TIMER3_IRQHandler
def_irq_default_handler MCPWM_IRQHandler
def_irq_default_handler ADC0_IRQHandler
def_irq_default_handler I2C0_IRQHandler
def_irq_default_handler I2C1_IRQHandler
def_irq_default_handler SPI_IRQHandler
def_irq_default_handler ADC1_IRQHandler
def_irq_default_handler SSP0_IRQHandler
def_irq_default_handler SSP1_IRQHandler
def_irq_default_handler USART0_IRQHandler
def_irq_default_handler UART1_IRQHandler
def_irq_default_handler USART2_IRQHandler
def_irq_default_handler USART3_IRQHandler
def_irq_default_handler I2S0_IRQHandler
def_irq_default_handler I2S1_IRQHandler
def_irq_default_handler SPIFI_IRQHandler
def_irq_default_handler SGPIO_IRQHandler
def_irq_default_handler PIN_INT0_IRQHandler
def_irq_default_handler PIN_INT1_IRQHandler
def_irq_default_handler PIN_INT2_IRQHandler
def_irq_default_handler PIN_INT3_IRQHandler
def_irq_default_handler PIN_INT4_IRQHandler
def_irq_default_handler PIN_INT5_IRQHandler
def_irq_default_handler PIN_INT6_IRQHandler
def_irq_default_handler PIN_INT7_IRQHandler
def_irq_default_handler GINT0_IRQHandler
def_irq_default_handler GINT1_IRQHandler
def_irq_default_handler EVENTROUTER_IRQHandler
def_irq_default_handler C_CAN1_IRQHandler
def_irq_default_handler ATIMER_IRQHandler
def_irq_default_handler RTC_IRQHandler
def_irq_default_handler WWDT_IRQHandler
def_irq_default_handler C_CAN0_IRQHandler
def_irq_default_handler QEI_IRQHandler
.end

32
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/startup_LPC43xx.cpp
View File

@ -312,6 +312,9 @@ extern unsigned int __bss_section_table_end;
// library.
//
// *****************************************************************************
extern "C" void software_init_hook(void) __attribute__((weak));
void
ResetISR(void) {
@ -342,20 +345,23 @@ ResetISR(void) {
bss_init(ExeAddr, SectionLen);
}
#if defined(__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined(__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main();
#else
main();
#endif
if (software_init_hook) // give control to the RTOS
software_init_hook(); // this will also call __libc_init_array
else {
#if defined(__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined(__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main();
#else
main();
#endif
}
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//

244
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/lib_startup_stm32f030.s Normal file
View File

@ -0,0 +1,244 @@
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f030.s
;* Author : MCD Application Team
;* Version : V1.3.1
;* Date : 17-January-2014
;* Description : STM32F030 devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; @attention
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD 0 ; Reserved
DCD RTC_IRQHandler ; RTC through EXTI Line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
DCD 0 ; Reserved
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
DCD ADC1_IRQHandler ; ADC1
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD 0 ; Reserved
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM14_IRQHandler ; TIM14
DCD TIM15_IRQHandler ; TIM15
DCD TIM16_IRQHandler ; TIM16
DCD TIM17_IRQHandler ; TIM17
DCD I2C1_IRQHandler ; I2C1
DCD I2C2_IRQHandler ; I2C2
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_15_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM15_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
WWDG_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_15_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_3_IRQHandler
DMA1_Channel4_5_IRQHandler
ADC1_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM3_IRQHandler
TIM14_IRQHandler
TIM15_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

216
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/startup_stm32f030.s Normal file
View File

@ -0,0 +1,216 @@
; STM32F030 devices vector table for MDK ARM_MICRO toolchain
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright (c) 2014, STMicroelectronics
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
; 3. Neither the name of STMicroelectronics nor the names of its contributors
; may be used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
EXPORT __initial_sp
Stack_Mem SPACE Stack_Size
__initial_sp EQU 0x20002000 ; Top of RAM (8 KB for STM32F030R8)
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
EXPORT __heap_base
EXPORT __heap_limit
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD 0 ; Reserved
DCD RTC_IRQHandler ; RTC through EXTI Line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
DCD 0 ; Reserved
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
DCD ADC1_IRQHandler ; ADC1
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD 0 ; Reserved
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM14_IRQHandler ; TIM14
DCD TIM15_IRQHandler ; TIM15
DCD TIM16_IRQHandler ; TIM16
DCD TIM17_IRQHandler ; TIM17
DCD I2C1_IRQHandler ; I2C1
DCD I2C2_IRQHandler ; I2C2
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_15_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM15_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
WWDG_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_15_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_3_IRQHandler
DMA1_Channel4_5_IRQHandler
ADC1_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM3_IRQHandler
TIM14_IRQHandler
TIM15_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
B .
ENDP
ALIGN
END

45
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx.sct Normal file
View File

@ -0,0 +1,45 @@
; Scatter-Loading Description File
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright (c) 2014, STMicroelectronics
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
; 3. Neither the name of STMicroelectronics nor the names of its contributors
; may be used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; STM32F030R8: 64KB FLASH (0x10000) + 8KB RAM (0x2000)
LR_IROM1 0x08000000 0x10000 { ; load region size_region
ER_IROM1 0x08000000 0x10000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 45 vectors = 180 bytes (0xB4) to be reserved in RAM
RW_IRAM1 (0x20000000+0xB4) (0x2000-0xB4) { ; RW data
.ANY (+RW +ZI)
}
}

Some files were not shown because too many files have changed in this diff Show More