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A fix to enum issue

pull/4438/head
Yuguo Zou 2017-03-08 20:48:40 +08:00 committed by Martin Kojtal
parent 9a0cb73447
commit 02687b5ec5
61 changed files with 955 additions and 550 deletions
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15
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/diag.h
View File

@ -60,12 +60,13 @@ extern u32 CfgSysDebugWarn;
#define _DBG_MISC_ 0x40000000
#define _DBG_FAULT_ 0x80000000
typedef enum _SYSTEM_DBG_DEFINE_ {
enum _SYSTEM_DBG_DEFINE_ {
_SYSDBG_MISC_ = 1<<0,
_SYSDBG_MAILBOX_ = 1<<1,
_SYSDBG_TIMER_ = 1<<2
} SYSTEM_DBG;
};
typedef uint32_t SYSTEM_DBG;
extern
_LONG_CALL_ROM_ u32
@ -826,11 +827,12 @@ prvDiagSPrintf(
#define IDENT_EIGHT_SPACE " "
#ifdef CONFIG_DEBUG_LOG
typedef enum _DBG_CFG_TYPE_ {
enum _DBG_CFG_TYPE_ {
DBG_CFG_ERR=0,
DBG_CFG_WARN=1,
DBG_CFG_INFO=2
} DBG_CFG_TYPE;
};
typedef uint32_t DBG_CFG_TYPE;
typedef struct _DBG_CFG_CMD_ {
u8 cmd_name[16];
@ -839,9 +841,10 @@ typedef struct _DBG_CFG_CMD_ {
#endif
typedef enum _CONSOLE_OP_STAGE_ {
enum _CONSOLE_OP_STAGE_ {
ROM_STAGE = 0,
RAM_STAGE = 1
}CONSOLE_OP_STAGE;
};
typedef uint32_t CONSOLE_OP_STAGE;
#endif //_DIAG_H_

48
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_gdma.h
View File

@ -321,7 +321,7 @@
#define BIT_CFGX_UP_DEST_PER(x)(((x) & BIT_MASK_CFGX_UP_DEST_PER) << BIT_SHIFT_CFGX_UP_DEST_PER)
#define BIT_INVC_CFGX_UP_DEST_PER (~(BIT_MASK_CFGX_UP_DEST_PER << BIT_SHIFT_CFGX_UP_DEST_PER))
typedef enum _GDMA_CHANNEL_NUM_ {
enum _GDMA_CHANNEL_NUM_ {
GdmaNoCh = 0x0000,
GdmaCh0 = 0x0101,
GdmaCh1 = 0x0202,
@ -332,35 +332,45 @@ typedef enum _GDMA_CHANNEL_NUM_ {
GdmaCh6 = 0x4040,
GdmaCh7 = 0x8080,
GdmaAllCh = 0xffff
}GDMA_CHANNEL_NUM, *PGDMA_CHANNEL_NUM;
};
typedef uint32_t GDMA_CHANNEL_NUM;
typedef uint32_t *PGDMA_CHANNEL_NUM;
//3 CTL register struct
typedef enum _GDMA_CTL_TT_FC_TYPE_ {
enum _GDMA_CTL_TT_FC_TYPE_ {
TTFCMemToMem = 0x00,
TTFCMemToPeri = 0x01,
TTFCPeriToMem = 0x02
}GDMA_CTL_TT_FC_TYPE, *PGDMA_CTL_TT_FC_TYPE;
};
typedef uint32_t GDMA_CTL_TT_FC_TYPE;
typedef uint32_t *PGDMA_CTL_TT_FC_TYPE;
//Max type = Bus Width
typedef enum _GDMA_CTL_TR_WIDTH_ {
enum _GDMA_CTL_TR_WIDTH_ {
TrWidthOneByte = 0x00,
TrWidthTwoBytes = 0x01,
TrWidthFourBytes = 0x02
}GDMA_CTL_TR_WIDTH, *PGDMA_CTL_TR_WIDTH;
};
typedef uint32_t GDMA_CTL_TR_WIDTH;
typedef uint32_t *PGDMA_CTL_TR_WIDTH;
typedef enum _GDMA_CTL_MSIZE_ {
enum _GDMA_CTL_MSIZE_ {
MsizeOne = 0x00,
MsizeFour = 0x01,
MsizeEight = 0x02
}GDMA_CTL_MSIZE, *PGDMA_CTL_MSIZE;
};
typedef uint32_t GDMA_CTL_MSIZE;
typedef uint32_t *PGDMA_CTL_MSIZE;
typedef enum _GDMA_INC_TYPE_ {
enum _GDMA_INC_TYPE_ {
IncType = 0x00,
DecType = 0x01,
NoChange = 0x02
}GDMA_INC_TYPE, *PGDMA_INC_TYPE;
};
typedef uint32_t GDMA_INC_TYPE;
typedef uint32_t *PGDMA_INC_TYPE;
typedef struct _GDMA_CTL_REG_ {
@ -386,7 +396,7 @@ typedef struct _GDMA_CTL_REG_ {
//3 CFG Register Structure
typedef enum _GDMA_CH_PRIORITY_ {
enum _GDMA_CH_PRIORITY_ {
Prior0 = 0,
Prior1 = 1,
Prior2 = 2,
@ -395,13 +405,17 @@ typedef enum _GDMA_CH_PRIORITY_ {
Prior5 = 5,
Prior6 = 6,
Prior7 = 7
}GDMA_CH_PRIORITY, *PGDMA_CH_PRIORITY;
};
typedef uint32_t GDMA_CH_PRIORITY;
typedef uint32_t *PGDMA_CH_PRIORITY;
typedef enum _GDMA_LOCK_LEVEL_ {
enum _GDMA_LOCK_LEVEL_ {
OverComplDmaTransfer = 0x00,
OverComplDmaBlockTransfer = 0x01,
OverComplDmaTransation = 0x02
}GDMA_LOCK_LEVEL, *PGDMA_LOCK_LEVEL;
};
typedef uint32_t GDMA_LOCK_LEVEL;
typedef uint32_t *PGDMA_LOCK_LEVEL;
typedef struct _GDMA_CFG_REG_ {
@ -427,13 +441,15 @@ typedef struct _GDMA_CFG_REG_ {
u16 Rsvd13To15 :3;
}GDMA_CFG_REG, *PGDMA_CFG_REG;
typedef enum _GDMA_ISR_TYPE_ {
enum _GDMA_ISR_TYPE_ {
TransferType = 0x1,
BlockType = 0x2,
SrcTransferType = 0x4,
DstTransferType = 0x8,
ErrType = 0x10
}GDMA_ISR_TYPE, *PGDMA_ISR_TYPE;
};
typedef uint32_t GDMA_ISR_TYPE;
typedef uint32_t *PGDMA_ISR_TYPE;
VOID

12
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_i2c.h
View File

@ -790,17 +790,21 @@
//======================================================
// I2C related enumeration
// I2C Address Mode
typedef enum _I2C_ADDR_MODE_ {
enum _I2C_ADDR_MODE_ {
I2C_ADDR_7BIT = 0,
I2C_ADDR_10BIT = 1,
}I2C_ADDR_MODE,*PI2C_ADDR_MODE;
};
typedef uint32_t I2C_ADDR_MODE;
typedef uint32_t *PI2C_ADDR_MODE;
// I2C Speed Mode
typedef enum _I2C_SPD_MODE_ {
enum _I2C_SPD_MODE_ {
I2C_SS_MODE = 1,
I2C_FS_MODE = 2,
I2C_HS_MODE = 3,
}I2C_SPD_MODE,*PI2C_SPD_MODE;
};
typedef uint32_t I2C_SPD_MODE;
typedef uint32_t *PI2C_SPD_MODE;
//I2C Timing Parameters
#define I2C_SS_MIN_SCL_HTIME 4000 //the unit is ns.

102
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_ssi.h
View File

@ -326,46 +326,60 @@
// SSI Pinmux Select
typedef enum _SSI0_PINMUX_SELECT_ {
enum _SSI0_PINMUX_SELECT_ {
SSI0_MUX_TO_GPIOE = S0,
SSI0_MUX_TO_GPIOC = S1
}SSI0_PINMUX_SELECT, *PSSI0_PINMUX_SELECT;
};
typedef uint32_t SSI0_PINMUX_SELECT;
typedef uint32_t *PSSI0_PINMUX_SELECT;
typedef enum _SSI1_PINMUX_SELECT_ {
enum _SSI1_PINMUX_SELECT_ {
SSI1_MUX_TO_GPIOA = S0,
SSI1_MUX_TO_GPIOB = S1,
SSI1_MUX_TO_GPIOD = S2
}SSI1_PINMUX_SELECT, *PSSI1_PINMUX_SELECT;
};
typedef uint32_t SSI1_PINMUX_SELECT;
typedef uint32_t *PSSI1_PINMUX_SELECT;
typedef enum _SSI2_PINMUX_SELECT_ {
enum _SSI2_PINMUX_SELECT_ {
SSI2_MUX_TO_GPIOG = S0,
SSI2_MUX_TO_GPIOE = S1,
SSI2_MUX_TO_GPIOD = S2
}SSI2_PINMUX_SELECT, *PSSI2_PINMUX_SELECT;
};
typedef uint32_t SSI2_PINMUX_SELECT;
typedef uint32_t *PSSI2_PINMUX_SELECT;
typedef enum _SSI0_MULTI_CS_PINMUX_SELECT_ {
enum _SSI0_MULTI_CS_PINMUX_SELECT_ {
SSI0_CS_MUX_TO_GPIOE = S0,
SSI0_CS_MUX_TO_GPIOC = S1
}SSI0_MULTI_CS_PINMUX_SELECT, *PSSI0_MULTI_CS_PINMUX_SELECT;
};
typedef uint32_t SSI0_MULTI_CS_PINMUX_SELECT;
typedef uint32_t *PSSI0_MULTI_CS_PINMUX_SELECT;
typedef enum _SSI_CTRLR0_TMOD_ {
enum _SSI_CTRLR0_TMOD_ {
TMOD_TR = 0,
TMOD_TO = 1,
TMOD_RO = 2,
TMOD_EEPROM_R = 3
}SSI_CTRLR0_TMOD, *PSSI_CTRLR0_TMOD;
};
typedef uint32_t SSI_CTRLR0_TMOD;
typedef uint32_t *PSSI_CTRLR0_TMOD;
typedef enum _SSI_CTRLR0_SCPOL_ {
enum _SSI_CTRLR0_SCPOL_ {
SCPOL_INACTIVE_IS_LOW = 0,
SCPOL_INACTIVE_IS_HIGH = 1
}SSI_CTRLR0_SCPOL, *PSSI_CTRLR0_SCPOL;
};
typedef uint32_t SSI_CTRLR0_SCPOL;
typedef uint32_t *PSSI_CTRLR0_SCPOL;
typedef enum _SSI_CTRLR0_SCPH_ {
enum _SSI_CTRLR0_SCPH_ {
SCPH_TOGGLES_IN_MIDDLE = 0,
SCPH_TOGGLES_AT_START = 1
}SSI_CTRLR0_SCPH, *PSSI_CTRLR0_SCPH;
};
typedef uint32_t SSI_CTRLR0_SCPH;
typedef uint32_t *PSSI_CTRLR0_SCPH;
typedef enum _SSI_CTRLR0_DFS_ {
enum _SSI_CTRLR0_DFS_ {
DFS_4_BITS = 3,
DFS_5_BITS = 4,
DFS_6_BITS = 5,
@ -379,9 +393,11 @@ typedef enum _SSI_CTRLR0_DFS_ {
DFS_14_BITS = 13,
DFS_15_BITS = 14,
DFS_16_BITS = 15,
}SSI_CTRLR0_DFS, *PSSI_CTRLR0_DFS;
};
typedef uint32_t SSI_CTRLR0_DFS;
typedef uint32_t *PSSI_CTRLR0_DFS;
typedef enum _SSI_CTRLR0_CFS_ {
enum _SSI_CTRLR0_CFS_ {
CFS_1_BIT = 0,
CFS_2_BITS = 1,
CFS_3_BITS = 2,
@ -398,52 +414,70 @@ typedef enum _SSI_CTRLR0_CFS_ {
CFS_14_BITS = 13,
CFS_15_BITS = 14,
CFS_16_BITS = 15
}SSI_CTRLR0_CFS, *PSSI_CTRLR0_CFS;
};
typedef uint32_t SSI_CTRLR0_CFS;
typedef uint32_t *PSSI_CTRLR0_CFS;
typedef enum _SSI_CTRLR0_SLV_OE_ {
enum _SSI_CTRLR0_SLV_OE_ {
SLV_TXD_ENABLE = 0,
SLV_TXD_DISABLE = 1
}SSI_CTRLR0_SLV_OE, *PSSI_CTRLR0_SLV_OE;
};
typedef uint32_t SSI_CTRLR0_SLV_OE;
typedef uint32_t *PSSI_CTRLR0_SLV_OE;
typedef enum _SSI_ROLE_SELECT_ {
enum _SSI_ROLE_SELECT_ {
SSI_SLAVE = 0,
SSI_MASTER = 1
}SSI_ROLE_SELECT, *PSSI_ROLE_SELECT;
};
typedef uint32_t SSI_ROLE_SELECT;
typedef uint32_t *PSSI_ROLE_SELECT;
typedef enum _SSI_FRAME_FORMAT_ {
enum _SSI_FRAME_FORMAT_ {
FRF_MOTOROLA_SPI = 0,
FRF_TI_SSP = 1,
FRF_NS_MICROWIRE = 2,
FRF_RSVD = 3
}SSI_FRAME_FORMAT, *PSSI_FRAME_FORMAT;
};
typedef uint32_t SSI_FRAME_FORMAT;
typedef uint32_t *PSSI_FRAME_FORMAT;
typedef enum _SSI_DMACR_ENABLE_ {
enum _SSI_DMACR_ENABLE_ {
SSI_NODMA = 0,
SSI_RXDMA_ENABLE = 1,
SSI_TXDMA_ENABLE = 2,
SSI_TRDMA_ENABLE = 3
}SSI_DMACR_ENABLE, *PSSI_DMACR_ENABLE;
};
typedef uint32_t SSI_DMACR_ENABLE;
typedef uint32_t *PSSI_DMACR_ENABLE;
typedef enum _SSI_MWCR_HANDSHAKE_ {
enum _SSI_MWCR_HANDSHAKE_ {
MW_HANDSHAKE_DISABLE = 0,
MW_HANDSHAKE_ENABLE = 1
}SSI_MWCR_HANDSHAKE, *PSSI_MWCR_HANDSHAKE;
};
typedef uint32_t SSI_MWCR_HANDSHAKE;
typedef uint32_t *PSSI_MWCR_HANDSHAKE;
typedef enum _SSI_MWCR_DIRECTION_ {
enum _SSI_MWCR_DIRECTION_ {
MW_DIRECTION_SLAVE_TO_MASTER = 0,
MW_DIRECTION_MASTER_TO_SLAVE = 1
}SSI_MWCR_DIRECTION, *PSSI_MWCR_DIRECTION;
};
typedef uint32_t SSI_MWCR_DIRECTION;
typedef uint32_t *PSSI_MWCR_DIRECTION;
typedef enum _SSI_MWCR_TMOD_ {
enum _SSI_MWCR_TMOD_ {
MW_TMOD_NONSEQUENTIAL = 0,
MW_TMOD_SEQUENTIAL = 1
}SSI_MWCR_TMOD, *PSSI_MWCR_TMOD;
};
typedef uint32_t SSI_MWCR_TMOD;
typedef uint32_t *PSSI_MWCR_TMOD;
typedef enum _SSI_DATA_TRANSFER_MECHANISM_ {
enum _SSI_DATA_TRANSFER_MECHANISM_ {
SSI_DTM_BASIC,
SSI_DTM_INTERRUPT,
SSI_DTM_DMA
}SSI_DATA_TRANSFER_MECHANISM, *PSSI_DATA_TRANSFER_MECHANISM;
};
typedef uint32_t SSI_DATA_TRANSFER_MECHANISM;
typedef uint32_t *PSSI_DATA_TRANSFER_MECHANISM;
_LONG_CALL_ HAL_Status HalSsiPinmuxEnableRtl8195a(VOID *Adaptor);

78
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_uart.h
View File

@ -156,70 +156,92 @@ typedef struct _RUART_SPEED_SETTING_ {
#endif
}RUART_SPEED_SETTING, *PRUART_SPEED_SETTING;
typedef enum _UART_RXFIFO_TRIGGER_LEVEL_ {
enum _UART_RXFIFO_TRIGGER_LEVEL_ {
OneByte = 0x00,
FourBytes = 0x01,
EightBytes = 0x10,
FourteenBytes = 0x11
}UART_RXFIFO_TRIGGER_LEVEL, *PUART_RXFIFO_TRIGGER_LEVEL;
};
typedef uint32_t UART_RXFIFO_TRIGGER_LEVEL;
typedef uint32_t *PUART_RXFIFO_TRIGGER_LEVEL;
typedef enum _RUART0_PINMUX_SELECT_ {
enum _RUART0_PINMUX_SELECT_ {
RUART0_MUX_TO_GPIOC = S0,
RUART0_MUX_TO_GPIOE = S1,
RUART0_MUX_TO_GPIOA = S2
}RUART0_PINMUX_SELECT, *PRUART0_PINMUX_SELECT;
};
typedef uint32_t RUART0_PINMUX_SELECT;
typedef uint32_t *PRUART0_PINMUX_SELECT;
typedef enum _RUART1_PINMUX_SELECT_ {
enum _RUART1_PINMUX_SELECT_ {
RUART1_MUX_TO_GPIOD = S0,
RUART1_MUX_TO_GPIOE = S1,
RUART1_MUX_TO_GPIOB = S2
}RUART1_PINMUX_SELECT, *PRUART1_PINMUX_SELECT;
};
typedef uint32_t RUART1_PINMUX_SELECT;
typedef uint32_t *PRUART1_PINMUX_SELECT;
typedef enum _RUART2_PINMUX_SELECT_ {
enum _RUART2_PINMUX_SELECT_ {
RUART2_MUX_TO_GPIOA = S0,
RUART2_MUX_TO_GPIOC = S1,
RUART2_MUX_TO_GPIOD = S2
}RUART2_PINMUX_SELECT, *PRUART2_PINMUX_SELECT;
};
typedef uint32_t RUART2_PINMUX_SELECT;
typedef uint32_t *PRUART2_PINMUX_SELECT;
typedef enum _RUART_FLOW_CONTROL_ {
enum _RUART_FLOW_CONTROL_ {
AUTOFLOW_DISABLE = 0,
AUTOFLOW_ENABLE = 1
}RUART_FLOW_CONTROL, *PRUART_FLOW_CONTROL;
};
typedef uint32_t RUART_FLOW_CONTROL;
typedef uint32_t *PRUART_FLOW_CONTROL;
typedef enum _RUART_WORD_LEN_SEL_ {
enum _RUART_WORD_LEN_SEL_ {
RUART_WLS_7BITS = 0,
RUART_WLS_8BITS = 1
}RUART_WORD_LEN_SEL, *PRUART_WORD_LEN_SEL;
};
typedef uint32_t RUART_WORD_LEN_SEL;
typedef uint32_t *PRUART_WORD_LEN_SEL;
typedef enum _RUART_STOP_BITS_ {
enum _RUART_STOP_BITS_ {
RUART_STOP_BIT_1 = 0,
RUART_STOP_BIT_2 = 1
}RUART_STOP_BITS, *PRUART_STOP_BITS;
};
typedef uint32_t RUART_STOP_BITS;
typedef uint32_t *PRUART_STOP_BITS;
typedef enum _RUART_PARITY_CONTROL_ {
enum _RUART_PARITY_CONTROL_ {
RUART_PARITY_DISABLE = 0,
RUART_PARITY_ENABLE = 1
}RUART_PARITY_CONTROL, *PRUART_PARITY_CONTROL;
};
typedef uint32_t RUART_PARITY_CONTROL;
typedef uint32_t *PRUART_PARITY_CONTROL;
typedef enum _RUART_PARITY_TYPE_ {
enum _RUART_PARITY_TYPE_ {
RUART_ODD_PARITY = 0,
RUART_EVEN_PARITY = 1
}RUART_PARITY_TYPE, *PRUART_PARITY_TYPE;
};
typedef uint32_t RUART_PARITY_TYPE;
typedef uint32_t *PRUART_PARITY_TYPE;
typedef enum _RUART_STICK_PARITY_CONTROL_ {
enum _RUART_STICK_PARITY_CONTROL_ {
RUART_STICK_PARITY_DISABLE = 0,
RUART_STICK_PARITY_ENABLE = 1
}RUART_STICK_PARITY_CONTROL, *PRUART_STICK_PARITY_CONTROL;
};
typedef uint32_t RUART_STICK_PARITY_CONTROL;
typedef uint32_t *PRUART_STICK_PARITY_CONTROL;
typedef enum _UART_INT_ID_ {
enum _UART_INT_ID_ {
ModemStatus = 0,
TxFifoEmpty = 1,
ReceiverDataAvailable = 2,
ReceivLineStatus = 3,
TimeoutIndication = 6
}UART_INT_ID, *PUART_INT_ID;
};
typedef uint32_t UART_INT_ID;
typedef uint32_t *PUART_INT_ID;
typedef enum _HAL_UART_State_
enum _HAL_UART_State_
{
HAL_UART_STATE_NULL = 0x00, // UART hardware not been initial yet
HAL_UART_STATE_READY = 0x10, // UART is initialed, ready to use
@ -229,9 +251,11 @@ typedef enum _HAL_UART_State_
HAL_UART_STATE_BUSY_TX_RX = 0x23, // UART is busy on TX an RX
HAL_UART_STATE_TIMEOUT = 0x30, // Transfer timeout
HAL_UART_STATE_ERROR = 0x40 // UART Error
}HAL_UART_State, *PHAL_UART_State;
};
typedef uint32_t HAL_UART_State;
typedef uint32_t *PHAL_UART_State;
typedef enum _HAL_UART_Status_
enum _HAL_UART_Status_
{
HAL_UART_STATUS_OK = 0x00, // Transfer OK
HAL_UART_STATUS_TIMEOUT = 0x01, // Transfer Timeout
@ -241,7 +265,9 @@ typedef enum _HAL_UART_Status_
HAL_UART_STATUS_ERR_BREAK = 0x10, // Break Interrupt
HAL_UART_STATUS_ERR_PARA = 0x20, // Parameter error
HAL_UART_STATUS_ERR_RXFIFO = 0x80, // RX FIFO error
}HAL_UART_Status, *PHAL_UART_Status;
};
typedef uint32_t HAL_UART_Status;
typedef uint32_t *PHAL_UART_Status;
u32
HalRuartGetDebugValueRtl8195a(

12
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_wdt.h
View File

@ -35,7 +35,7 @@ typedef struct _WDG_ADAPTER_ {
u32 callback_id;
}WDG_ADAPTER, *PWDG_ADAPTER;
typedef enum _WDG_CNTLMT_ {
enum _WDG_CNTLMT_ {
CNT1H = 0,
CNT3H = 1,
CNT7H = 2,
@ -48,13 +48,17 @@ typedef enum _WDG_CNTLMT_ {
CNT3FFH = 9,
CNT7FFH = 10,
CNTFFFH = 11
}WDG_CNTLMT, *PWDG_CNTLMT;
};
typedef uint32_t WDG_CNTLMT;
typedef uint32_t *PWDG_CNTLMT;
typedef enum _WDG_MODE_ {
enum _WDG_MODE_ {
INT_MODE = 0,
RESET_MODE = 1
}WDG_MODE, *PWDG_MODE;
};
typedef uint32_t WDG_MODE;
typedef uint32_t *PWDG_MODE;
extern VOID
WDGInitial(

5
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/wifi/wifi_conf.h
View File

@ -737,11 +737,12 @@ int wifi_get_last_error(void);
/**
* @brief The enumeration is transmission type for wifi custom ie.
*/
typedef enum CUSTOM_IE_TYPE{
enum CUSTOM_IE_TYPE{
PROBE_REQ = BIT(0),
PROBE_RSP = BIT(1),
BEACON = BIT(2),
}rtw_custom_ie_type_t;
};
typedef uint32_t rtw_custom_ie_type_t;
#endif /* _CUSTOM_IE_TYPE_ */
/* ie format

5
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/HalPwrSeqCmd.h
View File

@ -93,11 +93,12 @@
#define PWR_CUT_ALL_MSK 0xFF
typedef enum _PWRSEQ_CMD_DELAY_UNIT_
enum _PWRSEQ_CMD_DELAY_UNIT_
{
PWRSEQ_DELAY_US,
PWRSEQ_DELAY_MS,
} PWRSEQ_DELAY_UNIT;
};
typedef uint32_t PWRSEQ_DELAY_UNIT;
typedef struct _WL_PWR_CFG_
{

25
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/HalVerDef.h
View File

@ -28,7 +28,7 @@
#endif
// HAL_IC_TYPE_E
typedef enum tag_HAL_IC_Type_Definition
enum tag_HAL_IC_Type_Definition
{
CHIP_8192S = 0,
CHIP_8188C = 1,
@ -43,18 +43,20 @@ typedef enum tag_HAL_IC_Type_Definition
CHIP_8195A = 10,
CHIP_8710B = 11,
CHIP_8188F = 12,
}HAL_IC_TYPE_E;
};
typedef uint32_t HAL_IC_TYPE_E;
//HAL_CHIP_TYPE_E
typedef enum tag_HAL_CHIP_Type_Definition
enum tag_HAL_CHIP_Type_Definition
{
TEST_CHIP = 0,
NORMAL_CHIP = 1,
FPGA = 2,
}HAL_CHIP_TYPE_E;
};
typedef uint32_t HAL_CHIP_TYPE_E;
//HAL_CUT_VERSION_E
typedef enum tag_HAL_Cut_Version_Definition
enum tag_HAL_Cut_Version_Definition
{
A_CUT_VERSION = 0,
B_CUT_VERSION = 1,
@ -67,17 +69,19 @@ typedef enum tag_HAL_Cut_Version_Definition
I_CUT_VERSION = 8,
J_CUT_VERSION = 9,
K_CUT_VERSION = 10,
}HAL_CUT_VERSION_E;
};
typedef uint32_t HAL_CUT_VERSION_E;
// HAL_Manufacturer
typedef enum tag_HAL_Manufacturer_Version_Definition
enum tag_HAL_Manufacturer_Version_Definition
{
CHIP_VENDOR_TSMC = 0,
CHIP_VENDOR_UMC = 1,
CHIP_VENDOR_SMIC = 2,
}HAL_VENDOR_E;
};
typedef uint32_t HAL_VENDOR_E;
typedef enum tag_HAL_RF_Type_Definition
enum tag_HAL_RF_Type_Definition
{
RF_TYPE_1T1R = 0,
RF_TYPE_1T2R = 1,
@ -87,7 +91,8 @@ typedef enum tag_HAL_RF_Type_Definition
RF_TYPE_3T3R = 5,
RF_TYPE_3T4R = 6,
RF_TYPE_4T4R = 7,
}HAL_RF_TYPE_E;
};
typedef uint32_t HAL_RF_TYPE_E;
typedef struct tag_HAL_VERSION
{

5
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/drv_types.h
View File

@ -559,11 +559,12 @@ struct co_data_priv{
};
#endif //CONFIG_CONCURRENT_MODE
typedef enum _DRIVER_STATE{
enum _DRIVER_STATE{
DRIVER_NORMAL = 0,
DRIVER_DISAPPEAR = 1,
DRIVER_REPLACE_DONGLE = 2,
}DRIVER_STATE;
};
typedef uint32_t DRIVER_STATE;
#ifdef CONFIG_INTEL_PROXIM
struct proxim {

11
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/hal_com.h
View File

@ -203,10 +203,12 @@
#define DESC_RATEVHTSS4MCS8 0x52
#define DESC_RATEVHTSS4MCS9 0x53
typedef enum _FIRMWARE_SOURCE {
enum _FIRMWARE_SOURCE {
FW_SOURCE_IMG_FILE = 0,
FW_SOURCE_HEADER_FILE = 1, //from header file
} FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
};
typedef uint32_t FIRMWARE_SOURCE;
typedef uint32_t * PFIRMWARE_SOURCE;
// BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
//#define MAX_TX_QUEUE 9
@ -260,10 +262,11 @@ void SetHwReg(PADAPTER padapter, u8 variable, u8 *val);
void GetHwReg(PADAPTER padapter, u8 variable, u8 *val);
#if defined (CONFIG_RTL8188F) || defined (CONFIG_RTL8711B)
typedef enum _RT_MEDIA_STATUS {
enum _RT_MEDIA_STATUS {
RT_MEDIA_DISCONNECT = 0,
RT_MEDIA_CONNECT = 1
} RT_MEDIA_STATUS;
};
typedef uint32_t RT_MEDIA_STATUS;
void GetHalODMVar(

15
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/hal_com_phycfg.h
View File

@ -25,7 +25,7 @@
#define PathC 0x2
#define PathD 0x3
typedef enum _RATE_SECTION {
enum _RATE_SECTION {
CCK = 0,
OFDM,
HT_MCS0_MCS7,
@ -36,27 +36,30 @@ typedef enum _RATE_SECTION {
VHT_2SSMCS0_2SSMCS9,
VHT_3SSMCS0_3SSMCS9,
VHT_4SSMCS0_4SSMCS9,
} RATE_SECTION;
};
typedef uint32_t RATE_SECTION;
typedef enum _RF_TX_NUM {
enum _RF_TX_NUM {
RF_1TX = 0,
RF_2TX,
RF_3TX,
RF_4TX,
RF_MAX_TX_NUM,
RF_TX_NUM_NONIMPLEMENT,
} RF_TX_NUM;
};
typedef uint32_t RF_TX_NUM;
#define MAX_POWER_INDEX 0x3F
typedef enum _REGULATION_TXPWR_LMT {
enum _REGULATION_TXPWR_LMT {
TXPWR_LMT_FCC = 0,
TXPWR_LMT_MKK = 1,
TXPWR_LMT_ETSI = 2,
TXPWR_LMT_WW = 3, // WW13, The mininum of ETSI,MKK
TXPWR_LMT_GL = 4, // Global, The mininum of ETSI,MKK,FCC
TXPWR_LMT_MAX_REGULATION_NUM = 5
} REGULATION_TXPWR_LMT;
};
typedef uint32_t REGULATION_TXPWR_LMT;
/*------------------------------Define structure----------------------------*/
typedef struct _BB_REGISTER_DEFINITION{

25
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/hal_intf.h
View File

@ -46,7 +46,7 @@ enum _CHIP_TYPE {
};
typedef enum _HW_VARIABLES{
enum _HW_VARIABLES{
HW_VAR_MEDIA_STATUS,
HW_VAR_MEDIA_STATUS1,
HW_VAR_SET_OPMODE,
@ -152,9 +152,10 @@ typedef enum _HW_VARIABLES{
#ifdef CONFIG_PROMISC
HW_VAR_PROMISC,
#endif
}HW_VARIABLES;
};
typedef uint32_t HW_VARIABLES;
typedef enum _HAL_DEF_VARIABLE{
enum _HAL_DEF_VARIABLE{
HAL_DEF_UNDERCORATEDSMOOTHEDPWDB,
HAL_DEF_IS_SUPPORT_ANT_DIV,
HAL_DEF_CURRENT_ANTENNA,
@ -178,9 +179,10 @@ typedef enum _HAL_DEF_VARIABLE{
HAL_DEF_TX_PAGE_BOUNDARY,
HAL_DEF_MACID_SLEEP, // Support for MACID sleep
HAL_DEF_DBG_RX_INFO_DUMP,
}HAL_DEF_VARIABLE;
};
typedef uint32_t HAL_DEF_VARIABLE;
typedef enum _HAL_ODM_VARIABLE{
enum _HAL_ODM_VARIABLE{
HAL_ODM_STA_INFO,
// HAL_ODM_P2P_STATE,
// HAL_ODM_WIFI_DISPLAY_STATE,
@ -189,12 +191,14 @@ typedef enum _HAL_ODM_VARIABLE{
HAL_ODM_RX_INFO_DUMP,
HAL_ODM_NOISE_MONITOR,
HAL_ODM_REGULATION,
}HAL_ODM_VARIABLE;
};
typedef uint32_t HAL_ODM_VARIABLE;
typedef enum _HAL_INTF_PS_FUNC{
enum _HAL_INTF_PS_FUNC{
HAL_USB_SELECT_SUSPEND,
HAL_MAX_ID,
}HAL_INTF_PS_FUNC;
};
typedef uint32_t HAL_INTF_PS_FUNC;
typedef s32 (*c2h_id_filter)(u8 *c2h_evt);
@ -476,7 +480,7 @@ typedef struct eeprom_priv EEPROM_EFUSE_PRIV, *PEEPROM_EFUSE_PRIV;
//TODO
#ifdef CONFIG_WOWLAN
typedef enum _wowlan_subcode{
enum _wowlan_subcode{
WOWLAN_PATTERN_MATCH = 1,
WOWLAN_MAGIC_PACKET = 2,
WOWLAN_UNICAST = 3,
@ -488,7 +492,8 @@ typedef enum _wowlan_subcode{
WOWLAN_DEBUG_RELOAD_FW = 9,
WOWLAN_DEBUG_1 =10,
WOWLAN_DEBUG_2 =11
}wowlan_subcode;
};
typedef uint32_t wowlan_subcode;
struct wowlan_ioctl_param{
unsigned int subcode;

29
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/hal_phy.h
View File

@ -33,14 +33,16 @@
#define RF6052_MAX_PATH 2
/*--------------------------Define Parameters-------------------------------*/
typedef enum _BAND_TYPE{
enum _BAND_TYPE{
BAND_ON_2_4G = 0,
BAND_ON_5G,
BAND_ON_BOTH,
BANDMAX
}BAND_TYPE,*PBAND_TYPE;
};
typedef uint32_t BAND_TYPE;
typedef uint32_t *PBAND_TYPE;
typedef enum _RF_TYPE{
enum _RF_TYPE{
RF_TYPE_MIN = 0, // 0
RF_8225=1, // 1 11b/g RF for verification only
RF_8256=2, // 2 11b/g/n
@ -48,29 +50,35 @@ typedef enum _RF_TYPE{
RF_6052=4, // 4 11b/g/n RF
RF_PSEUDO_11N=5, // 5, It is a temporality RF.
RF_TYPE_MAX
}RF_TYPE_E,*PRF_TYPE_E;
};
typedef uint32_t RF_TYPE_E;
typedef uint32_t *PRF_TYPE_E;
typedef enum _RF_PATH{
enum _RF_PATH{
RF_PATH_A = 0,
RF_PATH_B,
RF_PATH_C,
RF_PATH_D
}RF_PATH, *PRF_PATH;
};
typedef uint32_t RF_PATH;
typedef uint32_t *PRF_PATH;
#define TX_1S 0
#define TX_2S 1
#define TX_3S 2
#define TX_4S 3
typedef enum _BaseBand_Config_Type{
enum _BaseBand_Config_Type{
BaseBand_Config_PHY_REG = 0, //Radio Path A
BaseBand_Config_AGC_TAB = 1, //Radio Path B
BaseBand_Config_AGC_TAB_2G = 2,
BaseBand_Config_AGC_TAB_5G = 3,
BaseBand_Config_PHY_REG_PG
}BaseBand_Config_Type, *PBaseBand_Config_Type;
};
typedef uint32_t BaseBand_Config_Type;
typedef uint32_t *PBaseBand_Config_Type;
typedef enum _WIRELESS_MODE {
enum _WIRELESS_MODE {
WIRELESS_MODE_UNKNOWN = 0x00,
WIRELESS_MODE_A = 0x01,
WIRELESS_MODE_B = 0x02,
@ -81,7 +89,8 @@ typedef enum _WIRELESS_MODE {
WIRELESS_MODE_AC_5G = 0x40,
WIRELESS_MODE_AC_24G = 0x80,
WIRELESS_MODE_AC_ONLY = 0x100,
} WIRELESS_MODE;
};
typedef uint32_t WIRELESS_MODE;
typedef struct RF_Shadow_Compare_Map {
// Shadow register value

6
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/ieee80211.h
View File

@ -143,7 +143,7 @@ enum {
//tern u8 RSN_CIPHER_SUITE_WRAP[];
typedef enum _RATEID_IDX_ {
enum _RATEID_IDX_ {
RATEID_IDX_BGN_40M_2SS = 0,
RATEID_IDX_BGN_40M_1SS = 1,
RATEID_IDX_BGN_20M_2SS_BN = 2,
@ -155,7 +155,9 @@ typedef enum _RATEID_IDX_ {
RATEID_IDX_B = 8,
RATEID_IDX_VHT_2SS = 9,
RATEID_IDX_VHT_1SS = 10,
} RATEID_IDX, *PRATEID_IDX;
};
typedef uint32_t RATEID_IDX;
typedef uint32_t *PRATEID_IDX;
enum NETWORK_TYPE
{

3
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/rom_ieee80211.h
View File

@ -85,7 +85,8 @@ struct rtw_ieee802_11_elems {
u8 vendor_ht_cap_len;
};
typedef enum { ParseOK = 0, ParseUnknown = 1, ParseFailed = -1 } ParseRes;
enum { ParseOK = 0, ParseUnknown = 1, ParseFailed = -1 };
typedef uint32_t ParseRes;
ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len,
struct rtw_ieee802_11_elems *elems,

5
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/rom_rtw_message.h
View File

@ -22,11 +22,12 @@
#include <platform_stdlib.h>
typedef enum {
enum {
#define ROM_E_RTW_MSGPOOL(name,str) ROM_E_RTW_MSGP_##name,
#include "rom_rtw_message_e.h"
ROM_E_RTW_MSGP_MAX
} rom_e_rtw_msgp_t;
};
typedef uint32_t rom_e_rtw_msgp_t;
#if ROM_E_RTW_MSG
extern const char *rom_e_rtw_msgp_str_[];

21
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/rtl8195a_hal.h
View File

@ -280,7 +280,7 @@ typedef struct _RT_8723B_FIRMWARE_HDR
// Description: Determine the types of C2H events that are the same in driver and Fw.
// Fisrt constructed by tynli. 2009.10.09.
typedef enum _C2H_EVT
enum _C2H_EVT
{
C2H_DBG = 0,
C2H_TSF = 1,
@ -293,7 +293,8 @@ typedef enum _C2H_EVT
C2H_HW_INFO_EXCH = 10,
C2H_8723B_BT_MP_INFO = 11,
MAX_C2HEVENT
} C2H_EVT;
};
typedef uint32_t C2H_EVT;
typedef _PACKED struct _C2H_EVT_HDR
{
@ -302,7 +303,7 @@ typedef _PACKED struct _C2H_EVT_HDR
u8 CmdSeq;
} C2H_EVT_HDR, *PC2H_EVT_HDR;
typedef enum tag_Package_Definition
enum tag_Package_Definition
{
PACKAGE_DEFAULT,
PACKAGE_QFN56,
@ -310,9 +311,10 @@ typedef enum tag_Package_Definition
PACKAGE_BGA96,
PACKAGE_QFN88,
PACKAGE_QFN216
}PACKAGE_TYPE_E;
};
typedef uint32_t PACKAGE_TYPE_E;
typedef enum tag_ChipID_Definition
enum tag_ChipID_Definition
{
CHIPID_8711AM = 0xFF,
CHIPID_8195AM = 0xFE,
@ -320,7 +322,8 @@ typedef enum tag_ChipID_Definition
CHIPID_8710AF = 0xFC,
CHIPID_8711AN = 0xFB,
CHIPID_8710AM = 0xFA
}CHIP_TD_E;
};
typedef uint32_t CHIP_TD_E;
#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
@ -398,7 +401,7 @@ typedef struct _LX_DMA_ELEMENT_ {
}LX_DMA_ELEMENT, *PLX_DMA_ELEMENT;
#if 1
typedef enum _LX_DMA_QUEUE_TYPE_{
enum _LX_DMA_QUEUE_TYPE_{
VO_QUEUE = 0,
VI_QUEUE = 1,
BE_QUEUE = 2,
@ -416,7 +419,9 @@ typedef enum _LX_DMA_QUEUE_TYPE_{
BCN_QUEUE = 14,
MAX_TX_QUEUE = 15,
ERROR_QUEUE = 16,
}LX_DMA_QUEUE_TYPE, *PLX_DMA_QUEUE_TYPE;
};
typedef uint32_t LX_DMA_QUEUE_TYPE;
typedef uint32_t *PLX_DMA_QUEUE_TYPE;
typedef struct _TX_FREE_QUEUE_ {
_queue FreeQueue;

21
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/rtl8711b_hal.h
View File

@ -243,7 +243,7 @@ typedef struct _RT_8723B_FIRMWARE_HDR
// Description: Determine the types of C2H events that are the same in driver and Fw.
// Fisrt constructed by tynli. 2009.10.09.
typedef enum _C2H_EVT
enum _C2H_EVT
{
C2H_DBG = 0,
C2H_TSF = 1,
@ -256,7 +256,8 @@ typedef enum _C2H_EVT
C2H_HW_INFO_EXCH = 10,
C2H_8723B_BT_MP_INFO = 11,
MAX_C2HEVENT
} C2H_EVT;
};
typedef uint32_t C2H_EVT;
typedef _PACKED struct _C2H_EVT_HDR
{
@ -265,21 +266,23 @@ typedef _PACKED struct _C2H_EVT_HDR
u8 CmdSeq;
} C2H_EVT_HDR, *PC2H_EVT_HDR;
typedef enum tag_Package_Definition
enum tag_Package_Definition
{
PACKAGE_QFN32,
PACKAGE_QFN48_MCM,
PACKAGE_QFN48,
PACKAGE_QFN68,
}PACKAGE_TYPE_E;
};
typedef uint32_t PACKAGE_TYPE_E;
typedef enum tag_ChipID_Definition
enum tag_ChipID_Definition
{
CHIPID_8710BN = 0xFF, /* PACKAGE_QFN32 */
CHIPID_8710BU = 0xFE, /* PACKAGE_QFN48_MCM */
CHIPID_8711BN = 0xFD, /* PACKAGE_QFN48 */
CHIPID_8711BG = 0xFC, /* PACKAGE_QFN68 */
}CHIP_TD_E;
};
typedef uint32_t CHIP_TD_E;
#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
@ -361,7 +364,7 @@ typedef struct _LX_DMA_ELEMENT_ {
}LX_DMA_ELEMENT, *PLX_DMA_ELEMENT;
#if 1
typedef enum _LX_DMA_QUEUE_TYPE_{
enum _LX_DMA_QUEUE_TYPE_{
VO_QUEUE = 0,
VI_QUEUE = 1,
BE_QUEUE = 2,
@ -379,7 +382,9 @@ typedef enum _LX_DMA_QUEUE_TYPE_{
BCN_QUEUE = 14,
MAX_TX_QUEUE = 15,
ERROR_QUEUE = 16,
}LX_DMA_QUEUE_TYPE, *PLX_DMA_QUEUE_TYPE;
};
typedef uint32_t LX_DMA_QUEUE_TYPE;
typedef uint32_t *PLX_DMA_QUEUE_TYPE;
typedef struct _TX_FREE_QUEUE_ {
_queue FreeQueue;

6
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/rtw_eeprom.h
View File

@ -62,7 +62,7 @@
// Besides, CustomerID of registry has precedence of that of EEPROM.
// defined below. 060703, by rcnjko.
//
typedef enum _RT_CUSTOMER_ID
enum _RT_CUSTOMER_ID
{
RT_CID_DEFAULT = 0,
RT_CID_8187_ALPHA0 = 1,
@ -106,7 +106,9 @@ typedef enum _RT_CUSTOMER_ID
RT_CID_819x_Xavi = 39,
RT_CID_819x_FUNAI_TV = 40,
RT_CID_819x_ALPHA_WD=41,
}RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
};
typedef uint32_t RT_CUSTOMER_ID;
typedef uint32_t *PRT_CUSTOMER_ID;
struct eeprom_priv
{

6
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/rtw_ht.h
View File

@ -51,7 +51,7 @@ struct ht_priv
#define STBC_HT_TEST_TX_ENABLE BIT2
#define STBC_HT_CAP_TX BIT3
typedef enum AGGRE_SIZE{
enum AGGRE_SIZE{
HT_AGG_SIZE_8K = 0,
HT_AGG_SIZE_16K = 1,
HT_AGG_SIZE_32K = 2,
@ -60,7 +60,9 @@ typedef enum AGGRE_SIZE{
VHT_AGG_SIZE_256K = 5,
VHT_AGG_SIZE_512K = 6,
VHT_AGG_SIZE_1024K = 7,
}AGGRE_SIZE_E, *PAGGRE_SIZE_E;
};
typedef uint32_t AGGRE_SIZE_E;
typedef uint32_t *PAGGRE_SIZE_E;
#endif //_RTL871X_HT_H_

5
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/rtw_led.h
View File

@ -60,7 +60,7 @@
#endif //#if 0
typedef enum _LED_CTL_MODE{
enum _LED_CTL_MODE{
LED_CTL_POWER_ON = 1,
LED_CTL_LINK = 2,
LED_CTL_NO_LINK = 3,
@ -75,7 +75,8 @@ typedef enum _LED_CTL_MODE{
LED_CTL_STOP_WPS_FAIL = 12, //added for ALPHA
LED_CTL_STOP_WPS_FAIL_OVERLAP = 13, //added for BELKIN
LED_CTL_CONNECTION_NO_TRANSFER = 14,
}LED_CTL_MODE;
};
typedef uint32_t LED_CTL_MODE;
//TODO
#if 0

24
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/rtw_mlme_ext.h
View File

@ -100,7 +100,7 @@ extern const u8 WMM_PARA_OUI[];
// If you just wnat to customize the acitions(scan period or join actions) about one of the channel plan,
// customize them in RT_CHANNEL_INFO in the RT_CHANNEL_LIST.
//
typedef enum _RT_CHANNEL_DOMAIN
enum _RT_CHANNEL_DOMAIN
{
//===== old channel plan mapping =====//
RT_CHANNEL_DOMAIN_FCC = 0x00,
@ -171,9 +171,11 @@ typedef enum _RT_CHANNEL_DOMAIN
//===== Add new channel plan above this line===============//
RT_CHANNEL_DOMAIN_MAX,
RT_CHANNEL_DOMAIN_REALTEK_DEFINE = 0x7F,
}RT_CHANNEL_DOMAIN, *PRT_CHANNEL_DOMAIN;
};
typedef uint32_t RT_CHANNEL_DOMAIN;
typedef uint32_t *PRT_CHANNEL_DOMAIN;
typedef enum _RT_CHANNEL_DOMAIN_2G
enum _RT_CHANNEL_DOMAIN_2G
{
RT_CHANNEL_DOMAIN_2G_WORLD1 = 0x00, //Worldwird 13, ch1~13 (ETSI, MKK)
RT_CHANNEL_DOMAIN_2G_ETSI1 = 0x01, //Europe, ch1~13
@ -185,9 +187,11 @@ typedef enum _RT_CHANNEL_DOMAIN_2G
RT_CHANNEL_DOMAIN_2G_WORLD2 = 0x07, //Worldwird 13, ch1~13 (ETSI, MKK, FCC)
//===== Add new channel plan above this line===============//
RT_CHANNEL_DOMAIN_2G_MAX,
}RT_CHANNEL_DOMAIN_2G, *PRT_CHANNEL_DOMAIN_2G;
};
typedef uint32_t RT_CHANNEL_DOMAIN_2G;
typedef uint32_t *PRT_CHANNEL_DOMAIN_2G;
typedef enum _RT_CHANNEL_DOMAIN_5G
enum _RT_CHANNEL_DOMAIN_5G
{
RT_CHANNEL_DOMAIN_5G_NULL = 0x00,
RT_CHANNEL_DOMAIN_5G_ETSI1 = 0x01, //Europe
@ -211,7 +215,9 @@ typedef enum _RT_CHANNEL_DOMAIN_5G
RT_CHANNEL_DOMAIN_5G_FCC = 0x11,
RT_CHANNEL_DOMAIN_5G_JAPAN_NO_DFS = 0x12,
RT_CHANNEL_DOMAIN_5G_MAX,
}RT_CHANNEL_DOMAIN_5G, *PRT_CHANNEL_DOMAIN_5G;
};
typedef uint32_t RT_CHANNEL_DOMAIN_5G;
typedef uint32_t *PRT_CHANNEL_DOMAIN_5G;
#define rtw_is_channel_plan_valid(chplan) (chplan<RT_CHANNEL_DOMAIN_MAX || chplan == RT_CHANNEL_DOMAIN_REALTEK_DEFINE)
@ -266,7 +272,7 @@ enum Associated_AP
maxAP,
};
typedef enum _HT_IOT_PEER
enum _HT_IOT_PEER
{
HT_IOT_PEER_UNKNOWN = 0,
HT_IOT_PEER_REALTEK = 1,
@ -285,7 +291,9 @@ typedef enum _HT_IOT_PEER
HT_IOT_PEER_REALTEK_81XX = 14,
HT_IOT_PEER_REALTEK_WOW = 15,
HT_IOT_PEER_MAX = 16
}HT_IOT_PEER_E, *PHTIOT_PEER_E;
};
typedef uint32_t HT_IOT_PEER_E;
typedef uint32_t *PHTIOT_PEER_E;
enum SCAN_STATE

31
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/rtw_mp.h
View File

@ -115,7 +115,7 @@
#define MPT_GET_THERMAL_METER 33
#endif
typedef enum _ANTENNA_PATH{
enum _ANTENNA_PATH{
ANTENNA_NONE = 0x00,
ANTENNA_D ,
ANTENNA_C ,
@ -132,7 +132,8 @@ typedef enum _ANTENNA_PATH{
ANTENNA_ABD ,
ANTENNA_ABC ,
ANTENNA_ABCD
} ANTENNA_PATH;
};
typedef uint32_t ANTENNA_PATH;
#define MAX_MP_XMITBUF_SZ 2048
@ -497,7 +498,7 @@ struct bb_reg_param {
#define _2MAC_MODE_ 0
#define _LOOPBOOK_MODE_ 1
#endif
typedef enum _MP_MODE_ {
enum _MP_MODE_ {
MP_OFF,
MP_ON,
MP_ERR,
@ -507,7 +508,8 @@ typedef enum _MP_MODE_ {
MP_SINGLE_TONE_TX,
MP_PACKET_TX,
MP_PACKET_RX
} MP_MODE;
};
typedef uint32_t MP_MODE;
#define MAX_RF_PATH_NUMS MAX_RF_PATH
@ -516,7 +518,7 @@ typedef enum _MP_MODE_ {
extern u8 mpdatarate[NumRates];
/* MP set force data rate base on the definition. */
typedef enum _MPT_RATE_INDEX
enum _MPT_RATE_INDEX
{
/* CCK rate. */
MPT_RATE_1M, /* 0 */
@ -552,14 +554,17 @@ typedef enum _MPT_RATE_INDEX
MPT_RATE_MCS14,
MPT_RATE_MCS15, /* 27 */
MPT_RATE_LAST
}MPT_RATE_E, *PMPT_RATE_E;
};
typedef uint32_t MPT_RATE_E;
typedef uint32_t *PMPT_RATE_E;
#define MAX_TX_PWR_INDEX_N_MODE 64 // 0x3F
typedef enum _POWER_MODE_ {
enum _POWER_MODE_ {
POWER_LOW = 0,
POWER_NORMAL
}POWER_MODE;
};
typedef uint32_t POWER_MODE;
#define RX_PKT_BROADCAST 1
@ -602,19 +607,21 @@ typedef enum _RXPHY_BITMASK_
} RXPHY_BITMASK;
#endif
typedef enum _ENCRY_CTRL_STATE_ {
enum _ENCRY_CTRL_STATE_ {
HW_CONTROL, //hw encryption& decryption
SW_CONTROL, //sw encryption& decryption
HW_ENCRY_SW_DECRY, //hw encryption & sw decryption
SW_ENCRY_HW_DECRY //sw encryption & hw decryption
}ENCRY_CTRL_STATE;
};
typedef uint32_t ENCRY_CTRL_STATE;
typedef enum _PREAMBLE {
enum _PREAMBLE {
Long_Preamble = 0x01,
Short_Preamble ,
Long_GI ,
Short_GI
} PREAMBLE;
};
typedef uint32_t PREAMBLE;

15
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/rtw_psk.h
View File

@ -111,20 +111,23 @@
#define GK_REKEY_TIME 3600000 //Set rekey period to 1 hour
typedef enum {
enum {
desc_type_RSN = 2,
desc_type_WPA = 254
} DescTypeRSN;
};
typedef uint32_t DescTypeRSN;
typedef enum {
enum {
type_Group = 0,
type_Pairwise = 1
} KeyType;
};
typedef uint32_t KeyType;
typedef enum {
enum {
key_desc_ver1 = 1,
key_desc_ver2 = 2
} KeyDescVer;
};
typedef uint32_t KeyDescVer;
enum {
PSK_WPA = 1,

5
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/rtw_pwrctrl.h
View File

@ -139,14 +139,15 @@ __inline static void _exit_pwrlock(_pwrlock *plock)
#define EXE_PWR_LPS 0x04
// RF state.
typedef enum _rt_rf_power_state
enum _rt_rf_power_state
{
rf_on, // RF is on after RFSleep or RFOff
rf_sleep, // 802.11 Power Save mode
rf_off, // HW/SW Radio OFF or Inactive Power Save
//=====Add the new RF state above this line=====//
rf_max
}rt_rf_power_state;
};
typedef uint32_t rt_rf_power_state;
// RF Off Level for IPS or HW/SW radio off
#define RT_RF_OFF_LEVL_ASPM BIT(0) // PCI ASPM

6
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/rtw_recv.h
View File

@ -615,13 +615,15 @@ union recv_frame{
};
typedef enum _RX_PACKET_TYPE{
enum _RX_PACKET_TYPE{
NORMAL_RX,//Normal rx packet
TX_REPORT1,//CCX
TX_REPORT2,//TX RPT
HIS_REPORT,// USB HISR RPT
C2H_PACKET
}RX_PACKET_TYPE, *PRX_PACKET_TYPE;
};
typedef uint32_t RX_PACKET_TYPE;
typedef uint32_t *PRX_PACKET_TYPE;
extern union recv_frame *_rtw_alloc_recvframe (_queue *pfree_recv_queue); //get a free recv_frame from pfree_recv_queue
extern void rtw_init_recvframe(union recv_frame *precvframe ,struct recv_priv *precvpriv);

35
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/rtw_rf.h
View File

@ -66,7 +66,7 @@ struct regulatory_class {
u8 modem;
};
typedef enum _CAPABILITY{
enum _CAPABILITY{
cESS = 0x0001,
cIBSS = 0x0002,
cPollable = 0x0004,
@ -83,7 +83,9 @@ typedef enum _CAPABILITY{
cDSSS_OFDM = 0x2000,
cDelayedBA = 0x4000,
cImmediateBA = 0x8000,
}CAPABILITY, *PCAPABILITY;
};
typedef uint32_t CAPABILITY;
typedef uint32_t *PCAPABILITY;
enum _REG_PREAMBLE_MODE{
PREAMBLE_LONG = 1,
@ -104,13 +106,15 @@ enum _RTL8712_RF_MIMO_CONFIG_{
};
typedef enum _RF90_RADIO_PATH{
enum _RF90_RADIO_PATH{
RF90_PATH_A = 0, //Radio Path A
RF90_PATH_B = 1, //Radio Path B
RF90_PATH_C = 2, //Radio Path C
RF90_PATH_D = 3 //Radio Path D
//RF90_PATH_MAX //Max RF number 90 support
}RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
};
typedef uint32_t RF90_RADIO_PATH_E;
typedef uint32_t *PRF90_RADIO_PATH_E;
// Bandwidth Offset
#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
@ -119,27 +123,31 @@ typedef enum _RF90_RADIO_PATH{
// Represent Channel Width in HT Capabilities
//
typedef enum _CHANNEL_WIDTH{
enum _CHANNEL_WIDTH{
CHANNEL_WIDTH_20 = 0,
CHANNEL_WIDTH_40 = 1,
CHANNEL_WIDTH_80 = 2,
CHANNEL_WIDTH_160 = 3,
CHANNEL_WIDTH_80_80 = 4,
CHANNEL_WIDTH_MAX = 5,
}CHANNEL_WIDTH, *PCHANNEL_WIDTH;
};
typedef uint32_t CHANNEL_WIDTH;
typedef uint32_t *PCHANNEL_WIDTH;
//
// Represent Extention Channel Offset in HT Capabilities
// This is available only in 40Mhz mode.
//
typedef enum _EXTCHNL_OFFSET{
enum _EXTCHNL_OFFSET{
EXTCHNL_OFFSET_NO_EXT = 0,
EXTCHNL_OFFSET_UPPER = 1,
EXTCHNL_OFFSET_NO_DEF = 2,
EXTCHNL_OFFSET_LOWER = 3,
}EXTCHNL_OFFSET, *PEXTCHNL_OFFSET;
};
typedef uint32_t EXTCHNL_OFFSET;
typedef uint32_t *PEXTCHNL_OFFSET;
typedef enum _VHT_DATA_SC{
enum _VHT_DATA_SC{
VHT_DATA_SC_DONOT_CARE = 0,
VHT_DATA_SC_20_UPPER_OF_80MHZ = 1,
VHT_DATA_SC_20_LOWER_OF_80MHZ = 2,
@ -151,12 +159,14 @@ typedef enum _VHT_DATA_SC{
VHT_DATA_SC_20_RECV4 = 8,
VHT_DATA_SC_40_UPPER_OF_80MHZ = 9,
VHT_DATA_SC_40_LOWER_OF_80MHZ = 10,
}VHT_DATA_SC, *PVHT_DATA_SC_E;
};
typedef uint32_t VHT_DATA_SC;
typedef uint32_t *PVHT_DATA_SC_E;
/* 2007/11/15 MH Define different RF type. */
typedef enum _RT_RF_TYPE_DEFINITION
enum _RT_RF_TYPE_DEFINITION
{
RF_1T2R = 0,
RF_2T4R = 1,
@ -164,7 +174,8 @@ typedef enum _RT_RF_TYPE_DEFINITION
RF_1T1R = 3,
RF_2T2R_GREEN = 4,
RF_819X_MAX_TYPE = 5,
}RT_RF_TYPE_DEF_E;
};
typedef uint32_t RT_RF_TYPE_DEF_E;
u32 rtw_ch2freq(u32 ch);

5
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/rtw_security.h
View File

@ -40,14 +40,15 @@
#define AES_PRIV_SIZE (4 * 44)
#define _AES_IV_LEN_ 8
typedef enum {
enum {
ENCRYP_PROTOCOL_OPENSYS, //open system
ENCRYP_PROTOCOL_WEP, //WEP
ENCRYP_PROTOCOL_WPA, //WPA
ENCRYP_PROTOCOL_WPA2, //WPA2
ENCRYP_PROTOCOL_WAPI, //WAPI: Not support in this version
ENCRYP_PROTOCOL_MAX
}ENCRYP_PROTOCOL_E;
};
typedef uint32_t ENCRYP_PROTOCOL_E;
#ifndef Ndis802_11AuthModeWPA2

10
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/wifi.h
View File

@ -939,12 +939,13 @@ struct ADDBA_request
#endif
typedef enum _HT_CAP_AMPDU_FACTOR {
enum _HT_CAP_AMPDU_FACTOR {
MAX_AMPDU_FACTOR_8K = 0,
MAX_AMPDU_FACTOR_16K = 1,
MAX_AMPDU_FACTOR_32K = 2,
MAX_AMPDU_FACTOR_64K = 3,
}HT_CAP_AMPDU_FACTOR;
};
typedef uint32_t HT_CAP_AMPDU_FACTOR;
/* 802.11n HT capabilities masks */
#define IEEE80211_HT_CAP_SUP_WIDTH 0x0002
@ -1358,11 +1359,12 @@ enum P2P_PS
#ifndef _CUSTOM_IE_TYPE_
#define _CUSTOM_IE_TYPE_
typedef enum CUSTOM_IE_TYPE{
enum CUSTOM_IE_TYPE{
PROBE_REQ = BIT(0),
PROBE_RSP = BIT(1),
BEACON = BIT(2),
}rtw_custom_ie_type_t;
};
typedef uint32_t rtw_custom_ie_type_t;
#endif /* _CUSTOM_IE_TYPE_ */
#endif // _WIFI_H_

110
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/wifi_constants.h
View File

@ -52,7 +52,7 @@ extern "C" {
/**
* @brief The enumeration lists the results of the function.
*/
typedef enum
enum
{
RTW_SUCCESS = 0, /**< Success */
RTW_PENDING = 1, /**< Pending */
@ -111,14 +111,15 @@ typedef enum
RTW_UNFINISHED = -41, /**< To be finished */
RTW_NONRESIDENT = -42, /**< access to nonresident overlay */
RTW_DISABLED = -43 /**< Disabled in this build */
} rtw_result_t;
};
typedef unsigned long rtw_result_t;
/**
* @brief The enumeration lists the possible security types to set when connection.\n
* Station mode supports OPEN, WEP, and WPA2.\n
* AP mode support OPEN and WPA2.
*/
typedef enum {
enum {
RTW_SECURITY_OPEN = 0, /**< Open security */
RTW_SECURITY_WEP_PSK = WEP_ENABLED, /**< WEP Security with open authentication */
RTW_SECURITY_WEP_SHARED = ( WEP_ENABLED | SHARED_ENABLED ), /**< WEP Security with shared authentication */
@ -135,9 +136,10 @@ typedef enum {
RTW_SECURITY_UNKNOWN = -1, /**< May be returned by scan function if security is unknown. Do not pass this to the join function! */
RTW_SECURITY_FORCE_32_BIT = 0x7fffffff /**< Exists only to force rtw_security_t type to 32 bits */
} rtw_security_t;
};
typedef unsigned long rtw_security_t;
typedef enum {
enum {
RTW_ENCRYPTION_UNKNOWN = 0,
RTW_ENCRYPTION_OPEN = 1,
RTW_ENCRYPTION_WEP40 = 2,
@ -148,25 +150,28 @@ typedef enum {
RTW_ENCRYPTION_WPA2_MIXED = 7,
RTW_ENCRYPTION_WEP104 = 9,
RTW_ENCRYPTION_UNDEF = 0xFF,
} rtw_encryption_t;
};
typedef unsigned long rtw_encryption_t;
typedef enum {
enum {
RTW_FALSE = 0,
RTW_TRUE = 1
} rtw_bool_t;
};
typedef unsigned long rtw_bool_t;
/**
* @brief The enumeration lists the band types.
*/
typedef enum {
enum {
RTW_802_11_BAND_5GHZ = 0, /**< Denotes 5GHz radio band */
RTW_802_11_BAND_2_4GHZ = 1 /**< Denotes 2.4GHz radio band */
} rtw_802_11_band_t;
};
typedef unsigned long rtw_802_11_band_t;
/**
* @brief The enumeration lists all the country codes able to set to Wi-Fi driver.
*/
typedef enum {
enum {
/* CHANNEL PLAN */
RTW_COUNTRY_WORLD1, // 0x20
RTW_COUNTRY_ETSI1, // 0x21
@ -362,73 +367,82 @@ typedef enum {
RTW_COUNTRY_MAX
}rtw_country_code_t;
};
typedef unsigned long rtw_country_code_t;
/**
* @brief The enumeration lists the adaptivity types.
*/
typedef enum {
enum {
RTW_ADAPTIVITY_DISABLE = 0,
RTW_ADAPTIVITY_NORMAL, // CE
RTW_ADAPTIVITY_CARRIER_SENSE // MKK
} rtw_adaptivity_mode_t;
};
typedef unsigned long rtw_adaptivity_mode_t;
/**
* @brief The enumeration lists the supported operation mode by WIFI driver,
* including station and AP mode.
*/
typedef enum {
enum {
RTW_MODE_NONE = 0,
RTW_MODE_STA,
RTW_MODE_AP,
RTW_MODE_STA_AP,
RTW_MODE_PROMISC,
RTW_MODE_P2P
}rtw_mode_t;
};
typedef unsigned long rtw_mode_t;
typedef enum {
enum {
RTW_SCAN_FULL = 0,
RTW_SCAN_SOCIAL,
RTW_SCAN_ONE
}rtw_scan_mode_t;
};
typedef unsigned long rtw_scan_mode_t;
/**
* @brief The enumeration lists the status to describe the connection link.
*/
typedef enum {
enum {
RTW_LINK_DISCONNECTED = 0,
RTW_LINK_CONNECTED
} rtw_link_status_t;
};
typedef unsigned long rtw_link_status_t;
/**
* @brief The enumeration lists the scan types.
*/
typedef enum {
enum {
RTW_SCAN_TYPE_ACTIVE = 0x00, /**< Actively scan a network by sending 802.11 probe(s) */
RTW_SCAN_TYPE_PASSIVE = 0x01, /**< Passively scan a network by listening for beacons from APs */
RTW_SCAN_TYPE_PROHIBITED_CHANNELS = 0x04 /**< Passively scan on channels not enabled by the country code */
} rtw_scan_type_t;
};
typedef unsigned long rtw_scan_type_t;
/**
* @brief The enumeration lists the bss types.
*/
typedef enum {
enum {
RTW_BSS_TYPE_INFRASTRUCTURE = 0, /**< Denotes infrastructure network */
RTW_BSS_TYPE_ADHOC = 1, /**< Denotes an 802.11 ad-hoc IBSS network */
RTW_BSS_TYPE_ANY = 2, /**< Denotes either infrastructure or ad-hoc network */
RTW_BSS_TYPE_UNKNOWN = -1 /**< May be returned by scan function if BSS type is unknown. Do not pass this to the Join function */
} rtw_bss_type_t;
};
typedef unsigned long rtw_bss_type_t;
typedef enum {
enum {
RTW_SCAN_COMMAMD = 0x01
} rtw_scan_command_t;
};
typedef unsigned long rtw_scan_command_t;
typedef enum{
enum{
COMMAND1 = 0x01
}rtw_command_type;
};
typedef unsigned long rtw_command_type;
typedef enum {
enum {
RTW_WPS_TYPE_DEFAULT = 0x0000,
RTW_WPS_TYPE_USER_SPECIFIED = 0x0001,
RTW_WPS_TYPE_MACHINE_SPECIFIED = 0x0002,
@ -436,68 +450,75 @@ typedef enum {
RTW_WPS_TYPE_PUSHBUTTON = 0x0004,
RTW_WPS_TYPE_REGISTRAR_SPECIFIED = 0x0005,
RTW_WPS_TYPE_NONE = 0x0006
} rtw_wps_type_t;
};
typedef unsigned long rtw_wps_type_t;
/**
* @brief The enumeration lists all the network bgn mode.
*/
typedef enum {
enum {
RTW_NETWORK_B = 1,
RTW_NETWORK_BG = 3,
RTW_NETWORK_BGN = 11
} rtw_network_mode_t;
};
typedef unsigned long rtw_network_mode_t;
/**
* @brief The enumeration lists the interfaces.
*/
typedef enum {
enum {
RTW_STA_INTERFACE = 0, /**< STA or Client Interface */
RTW_AP_INTERFACE = 1, /**< SoftAP Interface */
} rtw_interface_t;
};
typedef unsigned long rtw_interface_t;
/**
* @brief The enumeration lists the packet filter rules.
*/
typedef enum {
enum {
RTW_POSITIVE_MATCHING = 0, /**< Receive the data matching with this pattern and discard the other data */
RTW_NEGATIVE_MATCHING = 1 /**< Discard the data matching with this pattern and receive the other data */
} rtw_packet_filter_rule_t;
};
typedef unsigned long rtw_packet_filter_rule_t;
/**
* @brief The enumeration lists the promisc levels.
*/
typedef enum {
enum {
RTW_PROMISC_DISABLE = 0, /**< Disable the promisc */
RTW_PROMISC_ENABLE = 1, /**< Fetch all ethernet packets */
RTW_PROMISC_ENABLE_1 = 2, /**< Fetch only B/M packets */
RTW_PROMISC_ENABLE_2 = 3, /**< Fetch all 802.11 packets*/
RTW_PROMISC_ENABLE_3 = 4, /**< Fetch only B/M 802.11 packets*/
} rtw_rcr_level_t;
};
typedef unsigned long rtw_rcr_level_t;
/**
* @brief The enumeration lists the disconnect reasons.
*/
typedef enum{
enum{
RTW_NO_ERROR = 0,
RTW_NONE_NETWORK = 1,
RTW_CONNECT_FAIL = 2,
RTW_WRONG_PASSWORD = 3 ,
RTW_DHCP_FAIL = 4,
RTW_UNKNOWN,
}rtw_connect_error_flag_t;
};
typedef unsigned long rtw_connect_error_flag_t;
typedef enum {
enum {
RTW_TX_PWR_PERCENTAGE_100 = 0, /* 100%, default target output power. */
RTW_TX_PWR_PERCENTAGE_75 = 1, /* 75% */
RTW_TX_PWR_PERCENTAGE_50 = 2, /* 50% */
RTW_TX_PWR_PERCENTAGE_25 = 3, /* 25% */
RTW_TX_PWR_PERCENTAGE_12_5 = 4, /* 12.5% */
}rtw_tx_pwr_percentage_t;
};
typedef unsigned long rtw_tx_pwr_percentage_t;
/**
* @brief The enumeration is event type indicated from wlan driver.
*/
typedef enum _WIFI_EVENT_INDICATE{
enum _WIFI_EVENT_INDICATE{
WIFI_EVENT_CONNECT = 0,
WIFI_EVENT_DISCONNECT = 1,
WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2,
@ -515,7 +536,8 @@ typedef enum _WIFI_EVENT_INDICATE{
WIFI_EVENT_NO_NETWORK = 14,
WIFI_EVENT_BEACON_AFTER_DHCP = 15,
WIFI_EVENT_MAX,
}rtw_event_indicate_t;
};
typedef unsigned long rtw_event_indicate_t;
#ifdef __cplusplus
}
#endif

78
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/wlan_bssdef.h
View File

@ -48,14 +48,16 @@ __attribute__((packed))
#endif
NDIS_802_11_SSID, *PNDIS_802_11_SSID;
typedef enum _NDIS_802_11_NETWORK_TYPE
enum _NDIS_802_11_NETWORK_TYPE
{
Ndis802_11FH,
Ndis802_11DS,
Ndis802_11OFDM5,
Ndis802_11OFDM24,
Ndis802_11NetworkTypeMax // not a real type, defined as an upper bound
} NDIS_802_11_NETWORK_TYPE, *PNDIS_802_11_NETWORK_TYPE;
};
typedef uint32_t NDIS_802_11_NETWORK_TYPE;
typedef uint32_t *PNDIS_802_11_NETWORK_TYPE;
typedef struct _NDIS_802_11_CONFIGURATION_FH
{
@ -89,14 +91,16 @@ NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION;
typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE
enum _NDIS_802_11_NETWORK_INFRASTRUCTURE
{
Ndis802_11IBSS,
Ndis802_11Infrastructure,
Ndis802_11AutoUnknown,
Ndis802_11InfrastructureMax, // Not a real value, defined as upper bound
Ndis802_11APMode
} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE;
};
typedef uint32_t NDIS_802_11_NETWORK_INFRASTRUCTURE;
typedef uint32_t *PNDIS_802_11_NETWORK_INFRASTRUCTURE;
@ -158,7 +162,7 @@ typedef struct _NDIS_802_11_BSSID_LIST_EX
} NDIS_802_11_BSSID_LIST_EX, *PNDIS_802_11_BSSID_LIST_EX;
#endif
typedef enum _NDIS_802_11_AUTHENTICATION_MODE
enum _NDIS_802_11_AUTHENTICATION_MODE
{
Ndis802_11AuthModeOpen,
Ndis802_11AuthModeShared,
@ -168,9 +172,11 @@ typedef enum _NDIS_802_11_AUTHENTICATION_MODE
Ndis802_11AuthModeWPANone,
Ndis802_11AuthModeWAPI,
Ndis802_11AuthModeMax // Not a real mode, defined as upper bound
} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE;
};
typedef uint32_t NDIS_802_11_AUTHENTICATION_MODE;
typedef uint32_t *PNDIS_802_11_AUTHENTICATION_MODE;
typedef enum _NDIS_802_11_WEP_STATUS
enum _NDIS_802_11_WEP_STATUS
{
Ndis802_11WEPEnabled,
Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled,
@ -185,8 +191,11 @@ typedef enum _NDIS_802_11_WEP_STATUS
Ndis802_11Encryption3Enabled,
Ndis802_11Encryption3KeyAbsent,
Ndis802_11_EncrypteionWAPI
} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS,
NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS;
};
typedef uint32_t NDIS_802_11_WEP_STATUS;
typedef uint32_t *PNDIS_802_11_WEP_STATUS;
typedef uint32_t NDIS_802_11_ENCRYPTION_STATUS;
typedef uint32_t *PNDIS_802_11_ENCRYPTION_STATUS;
#define NDIS_802_11_AI_REQFI_CAPABILITIES 1
@ -224,10 +233,12 @@ typedef struct _NDIS_802_11_ASSOCIATION_INFORMATION
u32 OffsetResponseIEs;
} NDIS_802_11_ASSOCIATION_INFORMATION, *PNDIS_802_11_ASSOCIATION_INFORMATION;
typedef enum _NDIS_802_11_RELOAD_DEFAULTS
enum _NDIS_802_11_RELOAD_DEFAULTS
{
Ndis802_11ReloadWEPKeys
} NDIS_802_11_RELOAD_DEFAULTS, *PNDIS_802_11_RELOAD_DEFAULTS;
};
typedef uint32_t NDIS_802_11_RELOAD_DEFAULTS;
typedef uint32_t *PNDIS_802_11_RELOAD_DEFAULTS;
// Key mapping keys require a BSSID
@ -263,13 +274,15 @@ typedef struct _NDIS_802_11_AUTHENTICATION_REQUEST
u32 Flags;
} NDIS_802_11_AUTHENTICATION_REQUEST, *PNDIS_802_11_AUTHENTICATION_REQUEST;
typedef enum _NDIS_802_11_STATUS_TYPE
enum _NDIS_802_11_STATUS_TYPE
{
Ndis802_11StatusType_Authentication,
Ndis802_11StatusType_MediaStreamMode,
Ndis802_11StatusType_PMKID_CandidateList,
Ndis802_11StatusTypeMax // not a real type, defined as an upper bound
} NDIS_802_11_STATUS_TYPE, *PNDIS_802_11_STATUS_TYPE;
};
typedef uint32_t NDIS_802_11_STATUS_TYPE;
typedef uint32_t *PNDIS_802_11_STATUS_TYPE;
typedef struct _NDIS_802_11_STATUS_INDICATION
{
@ -328,14 +341,16 @@ typedef struct _NDIS_802_11_SSID
u8 Ssid[32];
} NDIS_802_11_SSID, *PNDIS_802_11_SSID;
typedef enum _NDIS_802_11_NETWORK_TYPE
enum _NDIS_802_11_NETWORK_TYPE
{
Ndis802_11FH,
Ndis802_11DS,
Ndis802_11OFDM5,
Ndis802_11OFDM24,
Ndis802_11NetworkTypeMax // not a real type, defined as an upper bound
} NDIS_802_11_NETWORK_TYPE, *PNDIS_802_11_NETWORK_TYPE;
};
typedef uint32_t NDIS_802_11_NETWORK_TYPE;
typedef uint32_t *PNDIS_802_11_NETWORK_TYPE;
typedef struct _NDIS_802_11_CONFIGURATION_FH
{
@ -361,14 +376,16 @@ typedef struct _NDIS_802_11_CONFIGURATION
typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE
enum _NDIS_802_11_NETWORK_INFRASTRUCTURE
{
Ndis802_11IBSS,
Ndis802_11Infrastructure,
Ndis802_11AutoUnknown,
Ndis802_11InfrastructureMax, // Not a real value, defined as upper bound
Ndis802_11APMode
} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE;
};
typedef uint32_t NDIS_802_11_NETWORK_INFRASTRUCTURE;
typedef uint32_t *PNDIS_802_11_NETWORK_INFRASTRUCTURE;
@ -430,7 +447,7 @@ typedef struct _NDIS_802_11_BSSID_LIST_EX
} NDIS_802_11_BSSID_LIST_EX, *PNDIS_802_11_BSSID_LIST_EX;
#endif
typedef enum _NDIS_802_11_AUTHENTICATION_MODE
enum _NDIS_802_11_AUTHENTICATION_MODE
{
Ndis802_11AuthModeOpen,
Ndis802_11AuthModeShared,
@ -439,9 +456,11 @@ typedef enum _NDIS_802_11_AUTHENTICATION_MODE
Ndis802_11AuthModeWPAPSK,
Ndis802_11AuthModeWPANone,
Ndis802_11AuthModeMax // Not a real mode, defined as upper bound
} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE;
};
typedef uint32_t NDIS_802_11_AUTHENTICATION_MODE;
typedef uint32_t *PNDIS_802_11_AUTHENTICATION_MODE;
typedef enum _NDIS_802_11_WEP_STATUS
enum _NDIS_802_11_WEP_STATUS
{
Ndis802_11WEPEnabled,
Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled,
@ -455,8 +474,11 @@ typedef enum _NDIS_802_11_WEP_STATUS
Ndis802_11Encryption2KeyAbsent,
Ndis802_11Encryption3Enabled,
Ndis802_11Encryption3KeyAbsent
} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS,
NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS;
} ;
typedef uint32_t NDIS_802_11_WEP_STATUS;
typedef uint32_t *PNDIS_802_11_WEP_STATUS;
typedef uint32_t NDIS_802_11_ENCRYPTION_STATUS;
typedef uint32_t *PNDIS_802_11_ENCRYPTION_STATUS;
#define NDIS_802_11_AI_REQFI_CAPABILITIES 1
@ -494,10 +516,12 @@ typedef struct _NDIS_802_11_ASSOCIATION_INFORMATION
u32 OffsetResponseIEs;
} NDIS_802_11_ASSOCIATION_INFORMATION, *PNDIS_802_11_ASSOCIATION_INFORMATION;
typedef enum _NDIS_802_11_RELOAD_DEFAULTS
enum _NDIS_802_11_RELOAD_DEFAULTS
{
Ndis802_11ReloadWEPKeys
} NDIS_802_11_RELOAD_DEFAULTS, *PNDIS_802_11_RELOAD_DEFAULTS;
};
typedef uint32_t NDIS_802_11_RELOAD_DEFAULTS;
typedef uint32_t *PNDIS_802_11_RELOAD_DEFAULTS;
// Key mapping keys require a BSSID
@ -533,13 +557,15 @@ typedef struct _NDIS_802_11_AUTHENTICATION_REQUEST
u32 Flags;
} NDIS_802_11_AUTHENTICATION_REQUEST, *PNDIS_802_11_AUTHENTICATION_REQUEST;
typedef enum _NDIS_802_11_STATUS_TYPE
enum _NDIS_802_11_STATUS_TYPE
{
Ndis802_11StatusType_Authentication,
Ndis802_11StatusType_MediaStreamMode,
Ndis802_11StatusType_PMKID_CandidateList,
Ndis802_11StatusTypeMax // not a real type, defined as an upper bound
} NDIS_802_11_STATUS_TYPE, *PNDIS_802_11_STATUS_TYPE;
};
typedef uint32_t NDIS_802_11_STATUS_TYPE;
typedef uint32_t *PNDIS_802_11_STATUS_TYPE;
typedef struct _NDIS_802_11_STATUS_INDICATION
{

10
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/hal/OUTSRC/HalPhyRf.h
View File

@ -21,16 +21,18 @@
#ifndef __HAL_PHY_RF_H__
#define __HAL_PHY_RF_H__
typedef enum _SPUR_CAL_METHOD {
enum _SPUR_CAL_METHOD {
PLL_RESET,
AFE_PHASE_SEL
} SPUR_CAL_METHOD;
};
typedef uint32_t SPUR_CAL_METHOD;
typedef enum _PWRTRACK_CONTROL_METHOD {
enum _PWRTRACK_CONTROL_METHOD {
BBSWING,
TXAGC,
MIX_MODE
} PWRTRACK_METHOD;
};
typedef uint32_t PWRTRACK_METHOD;
typedef VOID (*FuncSetPwr)(PDM_ODM_T, PWRTRACK_METHOD, u1Byte, u1Byte);
typedef VOID (*FuncIQK)(PDM_ODM_T, u1Byte, u1Byte, u1Byte);

15
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/hal/OUTSRC/PhyDM_Adaptivity.h
View File

@ -27,30 +27,33 @@
#define DFIRloss 5
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
typedef enum _tag_PhyDM_REGULATION_Type {
enum _tag_PhyDM_REGULATION_Type {
REGULATION_FCC = 0,
REGULATION_MKK = 1,
REGULATION_ETSI = 2,
REGULATION_WW = 3,
MAX_REGULATION_NUM = 4
} PhyDM_REGULATION_TYPE;
};
typedef uint32_t PhyDM_REGULATION_TYPE;
#endif
typedef enum tag_PhyDM_TRx_MUX_Type
enum tag_PhyDM_TRx_MUX_Type
{
PhyDM_SHUTDOWN = 0,
PhyDM_STANDBY_MODE = 1,
PhyDM_TX_MODE = 2,
PhyDM_RX_MODE = 3
}PhyDM_Trx_MUX_Type;
};
typedef uint32_t PhyDM_Trx_MUX_Type;
typedef enum tag_PhyDM_MACEDCCA_Type
enum tag_PhyDM_MACEDCCA_Type
{
PhyDM_IGNORE_EDCCA = 0,
PhyDM_DONT_IGNORE_EDCCA = 1
}PhyDM_MACEDCCA_Type;
};
typedef uint32_t PhyDM_MACEDCCA_Type;
typedef struct _ADAPTIVITY_STATISTICS {
s1Byte TH_L2H_ini_mode2;

207
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm.h
View File

@ -344,7 +344,7 @@ typedef struct _SW_Antenna_Switch_
//
// Indicate different AP vendor for IOT issue.
//
typedef enum _HT_IOT_PEER
enum _HT_IOT_PEER
{
HT_IOT_PEER_UNKNOWN = 0,
HT_IOT_PEER_REALTEK = 1,
@ -363,7 +363,9 @@ typedef enum _HT_IOT_PEER
HT_IOT_PEER_REALTEK_81XX = 14,
HT_IOT_PEER_REALTEK_WOW = 15,
HT_IOT_PEER_MAX = 16
}HT_IOT_PEER_E, *PHTIOT_PEER_E;
};
typedef uint32_t HT_IOT_PEER_E;
typedef uint32_t *PHTIOT_PEER_E;
#endif//#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#define DM_Type_ByFW 0
@ -558,7 +560,7 @@ typedef struct _ODM_Mac_Status_Info_
}ODM_MAC_INFO;
typedef enum tag_Dynamic_ODM_Support_Ability_Type
enum tag_Dynamic_ODM_Support_Ability_Type
{
// BB Team
ODM_DIG = 0x00000001,
@ -573,7 +575,8 @@ typedef enum tag_Dynamic_ODM_Support_Ability_Type
ODM_2TPATHDIV = 0x00000200,
ODM_1TPATHDIV = 0x00000400,
ODM_PSD2AFH = 0x00000800
}ODM_Ability_E;
};
typedef uint32_t ODM_Ability_E;
//
// 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T
@ -643,7 +646,7 @@ typedef struct _ODM_STA_INFO{
//
// 2011/10/20 MH Define Common info enum for all team.
//
typedef enum _ODM_Common_Info_Definition
enum _ODM_Common_Info_Definition
{
//-------------REMOVED CASE-----------//
//ODM_CMNINFO_CCK_HP,
@ -752,12 +755,13 @@ typedef enum _ODM_Common_Info_Definition
ODM_CMNINFO_MAX,
}ODM_CMNINFO_E;
};
typedef uint32_t ODM_CMNINFO_E;
//
// 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY
//
typedef enum _ODM_Support_Ability_Definition
enum _ODM_Support_Ability_Definition
{
//
// BB ODM section BIT 0-19
@ -793,10 +797,11 @@ typedef enum _ODM_Support_Ability_Definition
ODM_RF_RX_GAIN_TRACK = BIT25,
ODM_RF_CALIBRATION = BIT26,
}ODM_ABILITY_E;
};
typedef uint32_t ODM_ABILITY_E;
// ODM_CMNINFO_INTERFACE
typedef enum tag_ODM_Support_Interface_Definition
enum tag_ODM_Support_Interface_Definition
{
ODM_ITRF_PCIE = 0x1,
ODM_ITRF_USB = 0x2,
@ -804,10 +809,11 @@ typedef enum tag_ODM_Support_Interface_Definition
ODM_ITRF_GSPI = 0x8,
ODM_ITRF_LXBUS = 0x10,
ODM_ITRF_ALL = 0xFF,
}ODM_INTERFACE_E;
};
typedef uint32_t ODM_INTERFACE_E;
// ODM_CMNINFO_IC_TYPE
typedef enum tag_ODM_Support_IC_Type_Definition
enum tag_ODM_Support_IC_Type_Definition
{
ODM_RTL8192S = BIT0,
ODM_RTL8192C = BIT1,
@ -824,13 +830,14 @@ typedef enum tag_ODM_Support_IC_Type_Definition
ODM_RTL8822B = BIT12,
ODM_RTL8195A = BIT13,
ODM_RTL8711B = BIT14
}ODM_IC_TYPE_E;
};
typedef uint32_t ODM_IC_TYPE_E;
#define ODM_IC_11N_SERIES (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8195A|ODM_RTL8711B)
#define ODM_IC_11AC_SERIES (ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8821B|ODM_RTL8822B)
//ODM_CMNINFO_CUT_VER
typedef enum tag_ODM_Cut_Version_Definition
enum tag_ODM_Cut_Version_Definition
{
ODM_CUT_A = 0,
ODM_CUT_B = 1,
@ -841,20 +848,22 @@ typedef enum tag_ODM_Cut_Version_Definition
ODM_CUT_I = 8,
ODM_CUT_TEST = 15,
}ODM_CUT_VERSION_E;
};
typedef uint32_t ODM_CUT_VERSION_E;
// ODM_CMNINFO_FAB_VER
typedef enum tag_ODM_Fab_Version_Definition
enum tag_ODM_Fab_Version_Definition
{
ODM_TSMC = 0,
ODM_UMC = 1,
}ODM_FAB_E;
};
typedef uint32_t ODM_FAB_E;
// ODM_CMNINFO_RF_TYPE
//
// For example 1T2R (A+AB = BIT0|BIT4|BIT5)
//
typedef enum tag_ODM_RF_Path_Bit_Definition
enum tag_ODM_RF_Path_Bit_Definition
{
ODM_RF_TX_A = BIT0,
ODM_RF_TX_B = BIT1,
@ -864,10 +873,11 @@ typedef enum tag_ODM_RF_Path_Bit_Definition
ODM_RF_RX_B = BIT5,
ODM_RF_RX_C = BIT6,
ODM_RF_RX_D = BIT7,
}ODM_RF_PATH_E;
};
typedef uint32_t ODM_RF_PATH_E;
typedef enum tag_ODM_RF_Type_Definition
enum tag_ODM_RF_Type_Definition
{
ODM_1T1R = 0,
ODM_1T2R = 1,
@ -877,7 +887,8 @@ typedef enum tag_ODM_RF_Type_Definition
ODM_3T3R = 5,
ODM_3T4R = 6,
ODM_4T4R = 7,
}ODM_RF_TYPE_E;
};
typedef uint32_t ODM_RF_TYPE_E;
//
@ -890,24 +901,26 @@ typedef enum tag_ODM_RF_Type_Definition
// DUALMAC_SINGLEPHY,
//}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D;
// Above is the original define in MP driver. Please use the same define. THX.
typedef enum tag_ODM_MAC_PHY_Mode_Definition
enum tag_ODM_MAC_PHY_Mode_Definition
{
ODM_SMSP = 0,
ODM_DMSP = 1,
ODM_DMDP = 2,
}ODM_MAC_PHY_MODE_E;
};
typedef uint32_t ODM_MAC_PHY_MODE_E;
typedef enum tag_BT_Coexist_Definition
enum tag_BT_Coexist_Definition
{
ODM_BT_BUSY = 1,
ODM_BT_ON = 2,
ODM_BT_OFF = 3,
ODM_BT_NONE = 4,
}ODM_BT_COEXIST_E;
};
typedef uint32_t ODM_BT_COEXIST_E;
// ODM_CMNINFO_OP_MODE
typedef enum tag_Operation_Mode_Definition
enum tag_Operation_Mode_Definition
{
ODM_NO_LINK = BIT0,
ODM_LINK = BIT1,
@ -918,11 +931,12 @@ typedef enum tag_Operation_Mode_Definition
ODM_AD_HOC = BIT6,
ODM_WIFI_DIRECT = BIT7,
ODM_WIFI_DISPLAY = BIT8,
}ODM_OPERATION_MODE_E;
};
typedef uint32_t ODM_OPERATION_MODE_E;
// ODM_CMNINFO_WM_MODE
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_CE|ODM_IOT))
typedef enum tag_Wireless_Mode_Definition
enum tag_Wireless_Mode_Definition
{
ODM_WM_UNKNOW = 0x0,
ODM_WM_B = BIT0,
@ -932,9 +946,10 @@ typedef enum tag_Wireless_Mode_Definition
ODM_WM_N5G = BIT4,
ODM_WM_AUTO = BIT5,
ODM_WM_AC = BIT6,
}ODM_WIRELESS_MODE_E;
};
typedef uint32_t ODM_WIRELESS_MODE_E;
#else
typedef enum tag_Wireless_Mode_Definition
enum tag_Wireless_Mode_Definition
{
ODM_WM_UNKNOWN = 0x00,
ODM_WM_A = BIT0,
@ -947,29 +962,32 @@ typedef enum tag_Wireless_Mode_Definition
ODM_WM_AC_24G = BIT7,
ODM_WM_AC_ONLY = BIT8,
ODM_WM_MAX = BIT9
}ODM_WIRELESS_MODE_E;
};
typedef uint32_t ODM_WIRELESS_MODE_E;
#endif
// ODM_CMNINFO_BAND
typedef enum tag_Band_Type_Definition
enum tag_Band_Type_Definition
{
ODM_BAND_2_4G = 0,
ODM_BAND_5G,
ODM_BAND_ON_BOTH,
ODM_BANDMAX
}ODM_BAND_TYPE_E;
};
typedef uint32_t ODM_BAND_TYPE_E;
// ODM_CMNINFO_SEC_CHNL_OFFSET
typedef enum tag_Secondary_Channel_Offset_Definition
enum tag_Secondary_Channel_Offset_Definition
{
ODM_DONT_CARE = 0,
ODM_BELOW = 1,
ODM_ABOVE = 2
}ODM_SEC_CHNL_OFFSET_E;
};
typedef uint32_t ODM_SEC_CHNL_OFFSET_E;
// ODM_CMNINFO_SEC_MODE
typedef enum tag_Security_Definition
enum tag_Security_Definition
{
ODM_SEC_OPEN = 0,
ODM_SEC_WEP40 = 1,
@ -979,23 +997,25 @@ typedef enum tag_Security_Definition
ODM_SEC_WEP104 = 5,
ODM_WEP_WPA_MIXED = 6, // WEP + WPA
ODM_SEC_SMS4 = 7,
}ODM_SECURITY_E;
};
typedef uint32_t ODM_SECURITY_E;
// ODM_CMNINFO_BW
typedef enum tag_Bandwidth_Definition
enum tag_Bandwidth_Definition
{
ODM_BW20M = 0,
ODM_BW40M = 1,
ODM_BW80M = 2,
ODM_BW160M = 3,
ODM_BW10M = 4,
}ODM_BW_E;
};
typedef uint32_t ODM_BW_E;
// ODM_CMNINFO_BOARD_TYPE
// For non-AC-series IC , ODM_BOARD_5G_EXT_PA and ODM_BOARD_5G_EXT_LNA are ignored
// For AC-series IC, external PA & LNA can be indivisuallly added on 2.4G and/or 5G
typedef enum tag_Board_Definition
enum tag_Board_Definition
{
ODM_BOARD_DEFAULT = 0, // The DEFAULT case.
ODM_BOARD_MINICARD = BIT(0), // 0 = non-mini card, 1= mini card.
@ -1006,51 +1026,58 @@ typedef enum tag_Board_Definition
ODM_BOARD_EXT_TRSW = BIT(5), // 0 = no ext-TRSW, 1 = existing ext-TRSW
ODM_BOARD_EXT_PA_5G = BIT(6), // 0 = no 5G ext-PA, 1 = existing 5G ext-PA
ODM_BOARD_EXT_LNA_5G= BIT(7), // 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA
}ODM_BOARD_TYPE_E;
};
typedef uint32_t ODM_BOARD_TYPE_E;
typedef enum tag_ODM_Package_Definition
enum tag_ODM_Package_Definition
{
ODM_PACKAGE_DEFAULT = 0,
ODM_PACKAGE_QFN68 = BIT(0),
ODM_PACKAGE_TFBGA90 = BIT(1),
ODM_PACKAGE_TFBGA79 = BIT(2),
}ODM_Package_TYPE_E;
};
typedef uint32_t ODM_Package_TYPE_E;
typedef enum tag_ODM_TYPE_GPA_Definition
enum tag_ODM_TYPE_GPA_Definition
{
TYPE_GPA0 = 0,
TYPE_GPA1 = BIT(1)|BIT(0)
}ODM_TYPE_GPA_E;
};
typedef uint32_t ODM_TYPE_GPA_E;
typedef enum tag_ODM_TYPE_APA_Definition
enum tag_ODM_TYPE_APA_Definition
{
TYPE_APA0 = 0,
TYPE_APA1 = BIT(1)|BIT(0)
}ODM_TYPE_APA_E;
};
typedef uint32_t ODM_TYPE_APA_E;
typedef enum tag_ODM_TYPE_GLNA_Definition
enum tag_ODM_TYPE_GLNA_Definition
{
TYPE_GLNA0 = 0,
TYPE_GLNA1 = BIT(2)|BIT(0),
TYPE_GLNA2 = BIT(3)|BIT(1),
TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)
}ODM_TYPE_GLNA_E;
};
typedef uint32_t ODM_TYPE_GLNA_E;
typedef enum tag_ODM_TYPE_ALNA_Definition
enum tag_ODM_TYPE_ALNA_Definition
{
TYPE_ALNA0 = 0,
TYPE_ALNA1 = BIT(2)|BIT(0),
TYPE_ALNA2 = BIT(3)|BIT(1),
TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)
}ODM_TYPE_ALNA_E;
};
typedef uint32_t ODM_TYPE_ALNA_E;
// ODM_CMNINFO_ONE_PATH_CCA
typedef enum tag_CCA_Path
enum tag_CCA_Path
{
ODM_CCA_2R = 0,
ODM_CCA_1R_A = 1,
ODM_CCA_1R_B = 2,
}ODM_CCA_PATH_E;
};
typedef uint32_t ODM_CCA_PATH_E;
typedef struct _ODM_RA_Info_
@ -1166,13 +1193,15 @@ typedef struct _ROM_INFO{
}ROM_INFO, *PROM_INFO;
#endif
typedef enum _FAT_STATE
enum _FAT_STATE
{
FAT_NORMAL_STATE = 0,
FAT_TRAINING_STATE = 1,
}FAT_STATE_E, *PFAT_STATE_E;
};
typedef uint32_t FAT_STATE_E;
typedef uint32_t *PFAT_STATE_E;
typedef enum _ANT_DIV_TYPE
enum _ANT_DIV_TYPE
{
NO_ANTDIV = 0xFF,
CG_TRX_HW_ANTDIV = 0x01,
@ -1181,7 +1210,9 @@ typedef enum _ANT_DIV_TYPE
CG_TRX_SMART_ANTDIV = 0x04,
CGCS_RX_SW_ANTDIV = 0x05,
S0S1_SW_ANTDIV = 0x06 //8723B intrnal switch S0 S1
}ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E;
};
typedef uint32_t ANT_DIV_TYPE_E;
typedef uint32_t *PANT_DIV_TYPE_E;
#if (RTL8812A_SUPPORT == 1)
typedef struct _ODM_PATH_DIVERSITY_
@ -1195,10 +1226,11 @@ typedef struct _ODM_PATH_DIVERSITY_
}PATHDIV_T, *pPATHDIV_T;
#endif
typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{
enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{
PHY_REG_PG_RELATIVE_VALUE = 0,
PHY_REG_PG_EXACT_VALUE = 1
} PHY_REG_PG_TYPE;
};
typedef uint32_t PHY_REG_PG_TYPE;
//
@ -1624,15 +1656,16 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure
#endif
typedef enum _PhyDM_Structure_Type{
enum _PhyDM_Structure_Type{
PhyDM_FalseAlmCnt,
PhyDM_CfoTrack,
PHYDM_ADAPTIVITY,
PhyDM_ROMInfo,
}PhyDM_Structure_Type;
};
typedef uint32_t PhyDM_Structure_Type;
typedef enum _ODM_RF_RADIO_PATH {
enum _ODM_RF_RADIO_PATH {
ODM_RF_PATH_A = 0, //Radio Path A
ODM_RF_PATH_B = 1, //Radio Path B
ODM_RF_PATH_C = 2, //Radio Path C
@ -1648,16 +1681,19 @@ typedef enum _ODM_RF_RADIO_PATH {
ODM_RF_PATH_BCD,
ODM_RF_PATH_ABCD,
// ODM_RF_PATH_MAX, //Max RF number 90 support
} ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E;
};
typedef uint32_t ODM_RF_RADIO_PATH_E;
typedef uint32_t *PODM_RF_RADIO_PATH_E;
typedef enum _ODM_RF_CONTENT{
enum _ODM_RF_CONTENT{
odm_radioa_txt = 0x1000,
odm_radiob_txt = 0x1001,
odm_radioc_txt = 0x1002,
odm_radiod_txt = 0x1003
} ODM_RF_CONTENT;
};
typedef uint32_t ODM_RF_CONTENT;
typedef enum _ODM_BB_Config_Type{
enum _ODM_BB_Config_Type{
CONFIG_BB_PHY_REG,
CONFIG_BB_AGC_TAB,
CONFIG_BB_AGC_TAB_2G,
@ -1665,14 +1701,18 @@ typedef enum _ODM_BB_Config_Type{
CONFIG_BB_PHY_REG_PG,
CONFIG_BB_PHY_REG_MP,
CONFIG_BB_AGC_TAB_DIFF,
} ODM_BB_Config_Type, *PODM_BB_Config_Type;
};
typedef uint32_t ODM_BB_Config_Type;
typedef uint32_t *PODM_BB_Config_Type;
typedef enum _ODM_RF_Config_Type{
enum _ODM_RF_Config_Type{
CONFIG_RF_RADIO,
CONFIG_RF_TXPWR_LMT,
} ODM_RF_Config_Type, *PODM_RF_Config_Type;
};
typedef uint32_t ODM_RF_Config_Type;
typedef uint32_t *PODM_RF_Config_Type;
typedef enum _ODM_FW_Config_Type{
enum _ODM_FW_Config_Type{
CONFIG_FW_NIC,
CONFIG_FW_NIC_2,
CONFIG_FW_AP,
@ -1682,11 +1722,12 @@ typedef enum _ODM_FW_Config_Type{
CONFIG_FW_AP_WoWLAN,
CONFIG_FW_BT,
CONFIG_FW_ROM,
} ODM_FW_Config_Type;
};
typedef uint32_t ODM_FW_Config_Type;
// Status code
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
typedef enum _RT_STATUS{
enum _RT_STATUS{
RT_STATUS_SUCCESS,
RT_STATUS_FAILURE,
RT_STATUS_PENDING,
@ -1695,7 +1736,9 @@ typedef enum _RT_STATUS{
RT_STATUS_INVALID_PARAMETER,
RT_STATUS_NOT_SUPPORT,
RT_STATUS_OS_API_FAILED,
}RT_STATUS,*PRT_STATUS;
};
typedef uint32_t RT_STATUS;
typedef uint32_t *PRT_STATUS;
#endif // end of RT_STATUS definition
#ifdef REMOVE_PACK
@ -1752,29 +1795,32 @@ typedef enum _RT_STATUS{
//3 BB Power Save
//3===========================================================
typedef enum tag_1R_CCA_Type_Definition
enum tag_1R_CCA_Type_Definition
{
CCA_1R =0,
CCA_2R = 1,
CCA_MAX = 2,
}DM_1R_CCA_E;
};
typedef uint32_t DM_1R_CCA_E;
typedef enum tag_RF_Type_Definition
enum tag_RF_Type_Definition
{
RF_Save =0,
RF_Normal = 1,
RF_MAX = 2,
}DM_RF_E;
};
typedef uint32_t DM_RF_E;
//3===========================================================
//3 Antenna Diversity
//3===========================================================
typedef enum tag_SW_Antenna_Switch_Definition
enum tag_SW_Antenna_Switch_Definition
{
Antenna_A = 1,
Antenna_B = 2,
Antenna_MAX = 3,
}DM_SWAS_E;
};
typedef uint32_t DM_SWAS_E;
// Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28.
@ -2004,7 +2050,7 @@ PlatformDivision64(
//
typedef enum tag_DIG_Connect_Definition
enum tag_DIG_Connect_Definition
{
DIG_STA_DISCONNECT = 0,
DIG_STA_CONNECT = 1,
@ -2012,7 +2058,8 @@ typedef enum tag_DIG_Connect_Definition
DIG_MultiSTA_DISCONNECT = 3,
DIG_MultiSTA_CONNECT = 4,
DIG_CONNECT_MAX
}DM_DIG_CONNECT_E;
};
typedef uint32_t DM_DIG_CONNECT_E;

25
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_DIG.h
View File

@ -104,7 +104,7 @@ typedef struct _FALSE_ALARM_STATISTICS{
}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
#endif
typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
enum tag_Dynamic_Init_Gain_Operation_Type_Definition
{
DIG_TYPE_THRESH_HIGH = 0,
DIG_TYPE_THRESH_LOW = 1,
@ -114,31 +114,36 @@ typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
DIG_TYPE_ENABLE = 5,
DIG_TYPE_DISABLE = 6,
DIG_OP_TYPE_MAX
}DM_DIG_OP_E;
};
typedef uint32_t DM_DIG_OP_E;
typedef enum tag_ODM_PauseDIG_Type {
enum tag_ODM_PauseDIG_Type {
ODM_PAUSE_DIG = BIT0,
ODM_RESUME_DIG = BIT1
} ODM_Pause_DIG_TYPE;
};
typedef uint32_t ODM_Pause_DIG_TYPE;
typedef enum tag_ODM_PauseCCKPD_Type {
enum tag_ODM_PauseCCKPD_Type {
ODM_PAUSE_CCKPD = BIT0,
ODM_RESUME_CCKPD = BIT1
} ODM_Pause_CCKPD_TYPE;
};
typedef uint32_t ODM_Pause_CCKPD_TYPE;
typedef enum tag_ODM_TRx_MUX_Type
enum tag_ODM_TRx_MUX_Type
{
ODM_SHUTDOWN = 0,
ODM_STANDBY_MODE = 1,
ODM_TX_MODE = 2,
ODM_RX_MODE = 3
}ODM_Trx_MUX_Type;
};
typedef uint32_t ODM_Trx_MUX_Type;
typedef enum tag_ODM_MACEDCCA_Type
enum tag_ODM_MACEDCCA_Type
{
ODM_IGNORE_EDCCA = 0,
ODM_DONT_IGNORE_EDCCA = 1
}ODM_MACEDCCA_Type;
};
typedef uint32_t ODM_MACEDCCA_Type;
/*
typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition

5
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_interface.h
View File

@ -97,7 +97,7 @@ ODM_REG(DIG,_pDM_Odm)
#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg)
#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit)
#endif
typedef enum _ODM_H2C_CMD
enum _ODM_H2C_CMD
{
/*ODM_H2C_RSSI_REPORT = 0,
ODM_H2C_PSD_RESULT=1,
@ -115,7 +115,8 @@ typedef enum _ODM_H2C_CMD
ODM_H2C_WIFI_CALIBRATION = 0x6d,
PHYDM_H2C_MU = 0x4a,
ODM_MAX_H2CCMD
}ODM_H2C_CMD;
};
typedef uint32_t ODM_H2C_CMD;
//

36
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_types.h
View File

@ -141,7 +141,7 @@
#define RT_LXBUS_INTERFACE 4
#endif
typedef enum _HAL_STATUS{
enum _HAL_STATUS{
HAL_STATUS_SUCCESS,
HAL_STATUS_FAILURE,
/*RT_STATUS_PENDING,
@ -150,7 +150,9 @@ typedef enum _HAL_STATUS{
RT_STATUS_INVALID_PARAMETER,
RT_STATUS_NOT_SUPPORT,
RT_STATUS_OS_API_FAILED,*/
}HAL_STATUS,*PHAL_STATUS;
};
typedef unsigned long HAL_STATUS;
typedef unsigned long *PHAL_STATUS;
#if( (DM_ODM_SUPPORT_TYPE == ODM_AP) ||(DM_ODM_SUPPORT_TYPE == ODM_ADSL) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
@ -160,7 +162,7 @@ typedef enum _HAL_STATUS{
//
// Declare for ODM spin lock defintion temporarily fro compile pass.
//
typedef enum _RT_SPINLOCK_TYPE{
enum _RT_SPINLOCK_TYPE{
RT_TX_SPINLOCK = 1,
RT_RX_SPINLOCK = 2,
RT_RM_SPINLOCK = 3,
@ -200,7 +202,8 @@ typedef enum _RT_SPINLOCK_TYPE{
RT_PENDED_OID_SPINLOCK = 39,
RT_CHNLLIST_SPINLOCK = 40,
RT_INDIC_SPINLOCK = 41, //protect indication
}RT_SPINLOCK_TYPE;
};
typedef unsigned long RT_SPINLOCK_TYPE;
#endif
@ -389,42 +392,47 @@ typedef enum _RT_SPINLOCK_TYPE{
#endif
// Array_MP_8195A_TXPWR_LMT[]
typedef enum _ODM_PW_LMT_REGULATION_TYPE{
enum _ODM_PW_LMT_REGULATION_TYPE{
PW_LMT_REGU_NULL = 0,
PW_LMT_REGU_FCC = 1,
PW_LMT_REGU_ETSI = 2,
PW_LMT_REGU_MKK = 3,
PW_LMT_REGU_WW13 = 4
}ODM_PW_LMT_REGULATION_TYPE;
};
typedef unsigned long ODM_PW_LMT_REGULATION_TYPE;
typedef enum _ODM_PW_LMT_BAND_TYPE{
enum _ODM_PW_LMT_BAND_TYPE{
PW_LMT_BAND_NULL = 0,
PW_LMT_BAND_2_4G = 1,
PW_LMT_BAND_5G = 2
}ODM_PW_LMT_BAND_TYPE;
};
typedef unsigned long ODM_PW_LMT_BAND_TYPE;
typedef enum _ODM_PW_LMT_BANDWIDTH_TYPE{
enum _ODM_PW_LMT_BANDWIDTH_TYPE{
PW_LMT_BW_NULL = 0,
PW_LMT_BW_20M = 1,
PW_LMT_BW_40M = 2,
PW_LMT_BW_80M = 3
}ODM_PW_LMT_BANDWIDTH_TYPE;
};
typedef unsigned long ODM_PW_LMT_BANDWIDTH_TYPE;
typedef enum _ODM_PW_LMT_RATESECTION_TYPE{
enum _ODM_PW_LMT_RATESECTION_TYPE{
PW_LMT_RS_NULL = 0,
PW_LMT_RS_CCK = 1,
PW_LMT_RS_OFDM = 2,
PW_LMT_RS_HT = 3,
PW_LMT_RS_VHT = 4
}ODM_PW_LMT_RATESECTION_TYPE;
};
typedef unsigned long ODM_PW_LMT_RATESECTION_TYPE;
typedef enum _ODM_PW_LMT_RFPATH_TYPE{
enum _ODM_PW_LMT_RFPATH_TYPE{
PW_LMT_PH_NULL = 0,
PW_LMT_PH_1T = 1,
PW_LMT_PH_2T = 2,
PW_LMT_PH_3T = 3,
PW_LMT_PH_4T = 4
}ODM_PW_LMT_RFPATH_TYPE;
};
typedef unsigned long ODM_PW_LMT_RFPATH_TYPE;
#if defined(CONFIG_LITTLE_ENDIAN)
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE

12
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/Hal8195ARateAdaptive.h
View File

@ -106,7 +106,7 @@
#define TRY_NESS_CNT_IDX_SIZE 16
/*------------------------------Define Enum-----------------------------------*/
typedef enum _RTL8195_RATEID_IDX_ {
enum _RTL8195_RATEID_IDX_ {
MODE_BGN_40M_2SS = 0,
MODE_BGN_40M_1SS = 1,
MODE_BGN_20M_2SS_BN = 2,
@ -116,14 +116,18 @@ typedef enum _RTL8195_RATEID_IDX_ {
MODE_BG = 6,
MODE_G = 7,
MODE_B = 8
} RTL8195_RATEID_IDX, *PRTL8195_RATEID_IDX;
};
typedef uint32_t RTL8195_RATEID_IDX;
typedef uint32_t * PRTL8195_RATEID_IDX;
typedef enum _VHT_HT_SWITCH_ {
enum _VHT_HT_SWITCH_ {
TYPE_HT = 0,
TYPE_VHT = 1,
TYPE_MIX1 = 2,
TYPE_MIX2 = 3
} VHT_SEL_SWITCH, *PVHT_SEL_SWITCH;
};
typedef uint32_t VHT_SEL_SWITCH;
typedef uint32_t * PVHT_SEL_SWITCH;
/*--------------------------Define MACRO--------------------------------------*/
#define TRYING_DISABLE 0

18
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/hal/hal_data.h
View File

@ -42,25 +42,31 @@
//
// <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
//
typedef enum _RT_MULTI_FUNC{
enum _RT_MULTI_FUNC{
RT_MULTI_FUNC_NONE = 0x00,
RT_MULTI_FUNC_WIFI = 0x01,
RT_MULTI_FUNC_BT = 0x02,
RT_MULTI_FUNC_GPS = 0x04,
}RT_MULTI_FUNC,*PRT_MULTI_FUNC;
};
typedef uint32_t RT_MULTI_FUNC;
typedef uint32_t * PRT_MULTI_FUNC;
//
// <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08.
//
typedef enum _RT_POLARITY_CTL {
enum _RT_POLARITY_CTL {
RT_POLARITY_LOW_ACT = 0,
RT_POLARITY_HIGH_ACT = 1,
} RT_POLARITY_CTL, *PRT_POLARITY_CTL;
};
typedef uint32_t RT_POLARITY_CTL;
typedef uint32_t *PRT_POLARITY_CTL;
// For RTL8723 regulator mode. by tynli. 2011.01.14.
typedef enum _RT_REGULATOR_MODE {
enum _RT_REGULATOR_MODE {
RT_SWITCHING_REGULATOR = 0,
RT_LDO_REGULATOR = 1,
} RT_REGULATOR_MODE, *PRT_REGULATOR_MODE;
};
typedef uint32_t RT_REGULATOR_MODE;
typedef uint32_t *PRT_REGULATOR_MODE;
#define CHANNEL_MAX_NUMBER 14 // 14 is the max channel number
#define CHANNEL_MAX_NUMBER_2G 14

11
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_pmu_cmd.h
View File

@ -20,12 +20,13 @@
#ifndef __RTL8195A_PMU_CMD_H__
#define __RTL8195A_PMU_CMD_H__
typedef enum _RT_MEDIA_STATUS{
enum _RT_MEDIA_STATUS{
RT_MEDIA_DISCONNECT = 0,
RT_MEDIA_CONNECT = 1
}RT_MEDIA_STATUS;
};
typedef uint32_t RT_MEDIA_STATUS;
typedef enum _H2C_CMD_ {
enum _H2C_CMD_ {
//1 Class1: Common
H2CID_RSVDPAGE = 0x00,
H2CID_JOININFO = 0x01,
@ -109,7 +110,9 @@ typedef enum _H2C_CMD_ {
//1 Class8: Testing
H2CID_H2C2HLB = 0xE0
} H2C_CMD, *PH2C_CMD;
};
typedef uint32_t H2C_CMD;
typedef uint32_t *PH2C_CMD;
typedef struct _H2CParam_JoinInfo_ {
BOOLEAN bConnected:1;

30
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_pmu_task.h
View File

@ -63,7 +63,7 @@
#ifdef CONFIG_POWER_SAVING
//REGDUMP_FW_ERR0
typedef enum _FW_ERR0_STATUS_
enum _FW_ERR0_STATUS_
{
FES0_H2C_CMDID = BIT0,
FES0_H2C_PTR = BIT1,
@ -74,11 +74,13 @@ typedef enum _FW_ERR0_STATUS_
FES0_RPWM_STABLE = BIT6,
FES0_C2H_TIMEOUT_ERR = BIT7,
}FW_ERR0_STATUS, *PFW_ERR0_STATUS;
};
typedef uint32_t FW_ERR0_STATUS;
typedef uint32_t *PFW_ERR0_STATUS;
//TxPauseReasonCode
typedef enum _TRPC_ {
enum _TRPC_ {
TPRC_ISSUENULLDATA_1 = 0x26,
TPRC_ISSUENULLDATA_2 = 0x27,
TPRC_PSS2TS3 = 0x2B,
@ -86,10 +88,12 @@ typedef enum _TRPC_ {
TPRC_PSS2TS4 = 0x2D,
TPRC_PSS2TS5 = 0x2E,
TPRC_PSS0TS6 = 0x2F,
} TRPC, *PTRPC;
} ;
typedef uint32_t TRPC;
typedef uint32_t *PTRPC;
typedef enum _PS_MODE_SETTING_SELECTION_
enum _PS_MODE_SETTING_SELECTION_
{
MODE_SETTING_ACTIVE = 0,
MODE_SETTING_LEGACY = 1,
@ -97,22 +101,28 @@ typedef enum _PS_MODE_SETTING_SELECTION_
#ifdef TDMA_POWER_SAVING
MODE_SETTING_TDMA = 3
#endif //#ifdef TDMA_POWER_SAVING
}PS_MODE_SETTING_SELECTION, *PPS_MODE_SETTING_SELECTION;
};
typedef uint32_t PS_MODE_SETTING_SELECTION;
typedef uint32_t *PPS_MODE_SETTING_SELECTION;
typedef enum _RxListenBeaconMode_
enum _RxListenBeaconMode_
{
RLBM_MIN = 0,
RLBM_MAX = 1,
RLBM_SELF_DEFINED = 2
}RxListenBeaconMode, *PRxListenBeaconMode;
};
typedef uint32_t RxListenBeaconMode;
typedef uint32_t *PRxListenBeaconMode;
typedef enum _SMART_PS_MODE_FOR_LEGACY_
enum _SMART_PS_MODE_FOR_LEGACY_
{
SMART_PS_MODE_LEGACY_PWR1 = 0, // TRX all use PS_POLL
SMART_PS_MODE_TX_PWR0 = 1, // TX: pwr bit = 0, RX: PS_POLL
SMART_PS_MODE_TRX_PWR0 = 2 // TX: pwr bit = 0, RX: NULL(0)
}SMART_PS_MODE_FOR_LEGACY, *PSMART_PS_MODE_FOR_LEGACY;
};
typedef uint32_t SMART_PS_MODE_FOR_LEGACY;
typedef uint32_t *PSMART_PS_MODE_FOR_LEGACY;
#endif //#ifdef CONFIG_POWER_SAVING

6
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_spec.h
View File

@ -329,13 +329,15 @@
#ifdef CONFIG_USB_HCI
//should be renamed and moved to another file
typedef enum _BOARD_TYPE_8192CUSB{
enum _BOARD_TYPE_8192CUSB{
BOARD_USB_DONGLE = 0, // USB dongle
BOARD_USB_High_PA = 1, // USB dongle with high power PA
BOARD_MINICARD = 2, // Minicard
BOARD_USB_SOLO = 3, // USB solo-Slim module
BOARD_USB_COMBO = 4, // USB Combo-Slim module
} BOARD_TYPE_8723BUSB, *PBOARD_TYPE_8723BUSB;
};
typedef uint32_t BOARD_TYPE_8723BUSB;
typedef uint32_t *PBOARD_TYPE_8723BUSB;
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/sdk/lib_peripheral_mbed.a
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targets/TARGET_Realtek/TARGET_AMEBA/sdk/lib_peripheral_mbed.ar
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targets/TARGET_Realtek/TARGET_AMEBA/sdk/lib_wlan_mbed.a
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targets/TARGET_Realtek/TARGET_AMEBA/sdk/lib_wlan_mbed.ar
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5
targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/include/device_lock.h
View File

@ -10,13 +10,14 @@
#ifndef _DEVICE_LOCK_H_
#define _DEVICE_LOCK_H_
typedef enum _RT_DEV_LOCK_E
enum _RT_DEV_LOCK_E
{
RT_DEV_LOCK_EFUSE = 0,
RT_DEV_LOCK_FLASH = 1,
RT_DEV_LOCK_CRYPTO = 2,
RT_DEV_LOCK_MAX = 3
}RT_DEV_LOCK_E;
};
typedef uint32_t RT_DEV_LOCK_E;
void device_mutex_lock(RT_DEV_LOCK_E device);
void device_mutex_unlock(RT_DEV_LOCK_E device);

66
targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_adc.h
View File

@ -37,11 +37,13 @@
#define ADC_PREFIX "RTL8195A[adc]: "
#define ADC_PREFIX_LVL " [ADC_DBG]: "
typedef enum _ADC_DBG_LVL_ {
enum _ADC_DBG_LVL_ {
HAL_ADC_LVL = 0x01,
SAL_ADC_LVL = 0x02,
VERI_ADC_LVL = 0x04,
}ADC_DBG_LVL,*PADC_DBG_LVL;
};
typedef uint32_t ADC_DBG_LVL;
typedef uint32_t * PADC_DBG_LVL;
#ifdef CONFIG_DEBUG_LOG
#ifdef CONFIG_DEBUG_LOG_ADC_HAL
@ -67,51 +69,65 @@ typedef enum _ADC_DBG_LVL_ {
//================ ADC HAL Related Enumeration ==================
// ADC Module Selection
typedef enum _ADC_MODULE_SEL_ {
enum _ADC_MODULE_SEL_ {
ADC0_SEL = 0x0,
ADC1_SEL = 0x1,
ADC2_SEL = 0x2,
ADC3_SEL = 0x3,
}ADC_MODULE_SEL,*PADC_MODULE_SEL;
};
typedef uint32_t ADC_MODULE_SEL;
typedef uint32_t * PADC_MODULE_SEL;
// ADC module status
typedef enum _ADC_MODULE_STATUS_ {
enum _ADC_MODULE_STATUS_ {
ADC_DISABLE = 0x0,
ADC_ENABLE = 0x1,
}ADC_MODULE_STATUS, *PADC_MODULE_STATUS;
};
typedef uint32_t ADC_MODULE_STATUS;
typedef uint32_t * PADC_MODULE_STATUS;
// ADC Data Endian
typedef enum _ADC_DATA_ENDIAN_ {
enum _ADC_DATA_ENDIAN_ {
ADC_DATA_ENDIAN_LITTLE = 0x0,
ADC_DATA_ENDIAN_BIG = 0x1,
}ADC_DATA_ENDIAN,*PADC_DATA_ENDIAN;
};
typedef uint32_t ADC_DATA_ENDIAN;
typedef uint32_t * PADC_DATA_ENDIAN;
// ADC Debug Select
typedef enum _ADC_DEBUG_SEL_ {
enum _ADC_DEBUG_SEL_ {
ADC_DBG_SEL_DISABLE = 0x0,
ADC_DBG_SEL_ENABLE = 0x1,
}ADC_DEBUG_SEL,*PADC_DEBUG_SEL;
};
typedef uint32_t ADC_DEBUG_SEL;
typedef uint32_t * PADC_DEBUG_SEL;
typedef enum _ADC_COMPARE_SET_ {
enum _ADC_COMPARE_SET_ {
ADC_COMP_SMALLER_THAN = 0x0,
ADC_COMP_GREATER_THAN = 0x1,
}ADC_COMPARE_SET, *PADC_COMPARE_SET;
};
typedef uint32_t ADC_COMPARE_SET;
typedef uint32_t * PADC_COMPARE_SET;
// ADC feature status
typedef enum _ADC_FEATURE_STATUS_{
enum _ADC_FEATURE_STATUS_{
ADC_FEATURE_DISABLED = 0,
ADC_FEATURE_ENABLED = 1,
}ADC_FEATURE_STATUS,*PADC_FEATURE_STATUS;
};
typedef uint32_t ADC_FEATURE_STATUS;
typedef uint32_t * PADC_FEATURE_STATUS;
// ADC operation type
typedef enum _ADC_OP_TYPE_ {
enum _ADC_OP_TYPE_ {
ADC_RDREG_TYPE = 0x0,
ADC_DMA_TYPE = 0x1,
ADC_INTR_TYPE = 0x2,
}ADC_OP_TYPE, *PADC_OP_TYPE;
};
typedef uint32_t ADC_OP_TYPE;
typedef uint32_t * PADC_OP_TYPE;
// ADC device status
typedef enum _ADC_DEVICE_STATUS_ {
enum _ADC_DEVICE_STATUS_ {
ADC_STS_UNINITIAL = 0x00,
ADC_STS_INITIALIZED = 0x01,
ADC_STS_IDLE = 0x02,
@ -124,20 +140,26 @@ typedef enum _ADC_DEVICE_STATUS_ {
ADC_STS_ERROR = 0x07,
ADC_STS_FULL = 0x08,
}ADC_DEVICE_STATUS, *PADC_DEVICE_STATUS;
};
typedef uint32_t ADC_DEVICE_STATUS;
typedef uint32_t * PADC_DEVICE_STATUS;
// ADC error type
typedef enum _ADC_ERR_TYPE_ {
enum _ADC_ERR_TYPE_ {
ADC_ERR_FIFO_RD_ERROR = 0x40, //ADC FIFO read error
}ADC_ERR_TYPE, *PADC_ERR_TYPE;
};
typedef uint32_t ADC_ERR_TYPE;
typedef uint32_t * PADC_ERR_TYPE;
// ADC initial status
typedef enum _ADC_INITAIL_STATUS_ {
enum _ADC_INITAIL_STATUS_ {
ADC0_INITED = 0x1,
ADC1_INITED = 0x2,
ADC2_INITED = 0x4,
ADC3_INITED = 0x8,
}ADC_INITAIL_STATUS, *PADC_INITAIL_STATUS;
};
typedef uint32_t ADC_INITAIL_STATUS;
typedef uint32_t * PADC_INITAIL_STATUS;
//================ ADC HAL Data Structure ======================

5
targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_api.h
View File

@ -113,7 +113,7 @@ extern VOID InitWDGIRQ(VOID);
#define Calibration32k En32KCalibration
#define WDGInit InitWDGIRQ
typedef enum _HAL_Status
enum _HAL_Status
{
HAL_OK = 0x00,
HAL_BUSY = 0x01,
@ -124,7 +124,8 @@ typedef enum _HAL_Status
HAL_ERR_UNKNOWN = 0xee // unknown error
} HAL_Status;
};
typedef uint32_t HAL_Status;
#endif //_HAL_API_H_

78
targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_dac.h
View File

@ -35,11 +35,13 @@
#define DAC_PREFIX "RTL8195A[dac]: "
#define DAC_PREFIX_LVL " [DAC_DBG]: "
typedef enum _DAC_DBG_LVL_ {
enum _DAC_DBG_LVL_ {
HAL_DAC_LVL = 0x00,
SAL_DAC_LVL = 0x02,
VERI_DAC_LVL = 0x04,
}DAC_DBG_LVL,*PDAC_DBG_LVL;
};
typedef uint32_t DAC_DBG_LVL;
typedef uint32_t * PDAC_DBG_LVL;
#ifdef CONFIG_DEBUG_LOG
#ifdef CONFIG_DEBUG_LOG_DAC_HAL
@ -65,63 +67,81 @@ typedef enum _DAC_DBG_LVL_ {
//================ DAC HAL Related Enumeration ==================
// DAC Module Selection
typedef enum _DAC_MODULE_SEL_ {
enum _DAC_MODULE_SEL_ {
DAC0_SEL = 0x0,
DAC1_SEL = 0x1,
}DAC_MODULE_SEL,*PDAC_MODULE_SEL;
};
typedef uint32_t DAC_MODULE_SEL;
typedef uint32_t * PDAC_MODULE_SEL;
// DAC module status
typedef enum _DAC_MODULE_STATUS_ {
enum _DAC_MODULE_STATUS_ {
DAC_DISABLE = 0x0,
DAC_ENABLE = 0x1,
}DAC_MODULE_STATUS, *PDAC_MODULE_STATUS;
};
typedef uint32_t DAC_MODULE_STATUS;
typedef uint32_t * PDAC_MODULE_STATUS;
// DAC Data Rate
typedef enum _DAC_DATA_RATE_ {
enum _DAC_DATA_RATE_ {
DAC_DATA_RATE_10K = 0x0,
DAC_DATA_RATE_250K = 0x1,
}DAC_DATA_RATE,*PDAC_DATA_RATE;
};
typedef uint32_t DAC_DATA_RATE;
typedef uint32_t * PDAC_DATA_RATE;
// DAC Data Endian
typedef enum _DAC_DATA_ENDIAN_ {
enum _DAC_DATA_ENDIAN_ {
DAC_DATA_ENDIAN_LITTLE = 0x0,
DAC_DATA_ENDIAN_BIG = 0x1,
}DAC_DATA_ENDIAN,*PDAC_DATA_ENDIAN;
};
typedef uint32_t DAC_DATA_ENDIAN;
typedef uint32_t * PDAC_DATA_ENDIAN;
// DAC Debug Select
typedef enum _DAC_DEBUG_SEL_ {
enum _DAC_DEBUG_SEL_ {
DAC_DBG_SEL_DISABLE = 0x0,
DAC_DBG_SEL_ENABLE = 0x1,
}DAC_DEBUG_SEL,*PDAC_DEBUG_SEL;
};
typedef uint32_t DAC_DEBUG_SEL;
typedef uint32_t *PDAC_DEBUG_SEL;
// DAC Dsc Debug Select
typedef enum _DAC_DSC_DEBUG_SEL_ {
enum _DAC_DSC_DEBUG_SEL_ {
DAC_DSC_DBG_SEL_DISABLE = 0x0,
DAC_DSC_DBG_SEL_ENABLE = 0x1,
}DAC_DSC_DEBUG_SEL,*PDAC_DSC_DEBUG_SEL;
};
typedef uint32_t DAC_DSC_DEBUG_SEL;
typedef uint32_t * PDAC_DSC_DEBUG_SEL;
// DAC Bypass Dsc Debug Select
typedef enum _DAC_BYPASS_DSC_SEL_ {
enum _DAC_BYPASS_DSC_SEL_ {
DAC_BYPASS_DSC_SEL_DISABLE = 0x0,
DAC_BYPASS_DSC_SEL_ENABLE = 0x1,
}DAC_BYPASS_DSC_SEL,*PDAC_BYPASS_DSC_SEL;
};
typedef uint32_t DAC_BYPASS_DSC_SEL;
typedef uint32_t * PDAC_BYPASS_DSC_SEL;
// DAC feature status
typedef enum _DAC_FEATURE_STATUS_{
enum _DAC_FEATURE_STATUS_{
DAC_FEATURE_DISABLED = 0,
DAC_FEATURE_ENABLED = 1,
}DAC_FEATURE_STATUS,*PDAC_FEATURE_STATUS;
};
typedef uint32_t DAC_FEATURE_STATUS;
typedef uint32_t * PDAC_FEATURE_STATUS;
// DAC operation type
typedef enum _DAC_OP_TYPE_ {
enum _DAC_OP_TYPE_ {
DAC_POLL_TYPE = 0x0,
DAC_DMA_TYPE = 0x1,
DAC_INTR_TYPE = 0x2,
}DAC_OP_TYPE, *PDAC_OP_TYPE;
};
typedef uint32_t DAC_OP_TYPE;
typedef uint32_t * PDAC_OP_TYPE;
// DAC device status
typedef enum _DAC_Device_STATUS_ {
enum _DAC_Device_STATUS_ {
DAC_STS_UNINITIAL = 0x00,
DAC_STS_INITIALIZED = 0x01,
DAC_STS_IDLE = 0x02,
@ -133,23 +153,29 @@ typedef enum _DAC_Device_STATUS_ {
DAC_STS_RX_ING = 0x06,
DAC_STS_ERROR = 0x07,
}DAC_Device_STATUS, *PDAC_Device_STATUS;
};
typedef uint32_t DAC_Device_STATUS;
typedef uint32_t * PDAC_Device_STATUS;
//DAC device error type
typedef enum _DAC_ERR_TYPE_ {
enum _DAC_ERR_TYPE_ {
DAC_ERR_FIFO_OVER = 0x04, //DAC FIFO overflow.
DAC_ERR_FIFO_STOP = 0x08, //DAC FIFO is completely empty, and it will be stopped automatically.
DAC_ERR_FIFO_WRFAIL = 0x10, //When DAC is NOT enabled, a write operation attempts to access DAC register.
DAC_ERR_FIFO_DSC_OVER0 = 0x20,
DAC_ERR_FIFO_DSC_OVER1 = 0x40,
}DAC_ERR_TYPE, *PDAC_ERR_TYPE;
};
typedef uint32_t DAC_ERR_TYPE;
typedef uint32_t * PDAC_ERR_TYPE;
// DAC data input method
typedef enum _DAC_INPUT_TYPE_{
enum _DAC_INPUT_TYPE_{
DAC_INPUT_SINGLE_WR = 0x1, //DAC input by using single register write
DAC_INPUT_DMA_ONEBLK = 0x2, //DAC input by using single DMA block
DAC_INPUT_DMA_LLP = 0x3, //DAC input by using DMA linked list mode
}DAC_INPUT_TYPE,*PDAC_INPUT_TYPE;
};
typedef uint32_t DAC_INPUT_TYPE;
typedef uint32_t * PDAC_INPUT_TYPE;

25
targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_gpio.h
View File

@ -16,7 +16,7 @@
#define HAL_GPIO_PIN_INT_MODE 0x80
typedef enum {
enum {
_PORT_A = 0,
_PORT_B = 1,
_PORT_C = 2,
@ -30,9 +30,10 @@ typedef enum {
_PORT_K = 10,
_PORT_MAX
} HAL_GPIO_PORT_NAME;
};
typedef uint32_t HAL_GPIO_PORT_NAME;
typedef enum {
enum {
_PA_0 = (_PORT_A<<4|0),
_PA_1 = (_PORT_A<<4|1),
_PA_2 = (_PORT_A<<4|2),
@ -141,16 +142,18 @@ typedef enum {
// Not connected
_PIN_NC = (int)0xFFFFFFFF
} HAL_PIN_NAME;
};
typedef uint32_t HAL_PIN_NAME;
typedef enum
enum
{
GPIO_PIN_LOW = 0,
GPIO_PIN_HIGH = 1,
GPIO_PIN_ERR = 2 // read Pin error
} HAL_GPIO_PIN_STATE;
};
typedef uint32_t HAL_GPIO_PIN_STATE;
typedef enum {
enum {
DIN_PULL_NONE = 0, //floating or high impedance ?
DIN_PULL_LOW = 1,
DIN_PULL_HIGH = 2,
@ -162,7 +165,8 @@ typedef enum {
INT_HIGH = (6|HAL_GPIO_PIN_INT_MODE), // Interrupt High level trigger
INT_FALLING = (7|HAL_GPIO_PIN_INT_MODE), // Interrupt Falling edge trigger
INT_RISING = (8|HAL_GPIO_PIN_INT_MODE) // Interrupt Rising edge trigger
} HAL_GPIO_PIN_MODE;
};
typedef uint32_t HAL_GPIO_PIN_MODE;
enum {
GPIO_PORT_A = 0,
@ -171,13 +175,14 @@ enum {
GPIO_PORT_D = 3
};
typedef enum {
enum {
hal_PullNone = 0,
hal_PullUp = 1,
hal_PullDown = 2,
hal_OpenDrain = 3,
hal_PullDefault = hal_PullNone
} HAL_PinMode;
};
typedef uint32_t HAL_PinMode;
typedef struct _HAL_GPIO_PORT_ {
u32 out_data; // to write the GPIO port

108
targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_i2c.h
View File

@ -79,12 +79,14 @@ typedef enum _I2C_DBG_LVL_ {
//======================================================
// I2C HAL related enumeration
// I2C Module Selection
typedef enum _I2C_MODULE_SEL_ {
enum _I2C_MODULE_SEL_ {
I2C0_SEL = 0x0,
I2C1_SEL = 0x1,
I2C2_SEL = 0x2,
I2C3_SEL = 0x3,
}I2C_MODULE_SEL,*PI2C_MODULE_SEL;
};
typedef uint32_t I2C_MODULE_SEL;
typedef uint32_t *PI2C_MODULE_SEL;
// I2C HAL initial data structure
typedef struct _HAL_I2C_INIT_DAT_ {
@ -154,7 +156,7 @@ typedef struct _HAL_I2C_OP_ {
//======================================================
// I2C SAL related enumerations
// I2C Extend Features
typedef enum _I2C_EXD_SUPPORT_{
enum _I2C_EXD_SUPPORT_{
I2C_EXD_RESTART = 0x1, //BIT_0, RESTART bit
I2C_EXD_GENCALL = 0x2, //BIT_1, Master generates General Call. All "send" operations generate General Call addresss
I2C_EXD_STARTB = 0x4, //BIT_2, Using START BYTE, instead of START Bit
@ -168,31 +170,39 @@ typedef enum _I2C_EXD_SUPPORT_{
I2C_EXD_MTR_ADDR_UPD= 0x200, //BIT_9, Master dynamically updates slave address
I2C_EXD_MTR_HOLD_BUS= 0x400, //BIT_10, Master doesn't generate STOP when the FIFO is empty. This would make Master hold
// the bus.
}I2C_EXD_SUPPORT,*PI2C_EXD_SUPPORT;
};
typedef uint32_t I2C_EXD_SUPPORT;
typedef uint32_t *PI2C_EXD_SUPPORT;
// I2C operation type
typedef enum _I2C_OP_TYPE_ {
enum _I2C_OP_TYPE_ {
I2C_POLL_TYPE = 0x0,
I2C_DMA_TYPE = 0x1,
I2C_INTR_TYPE = 0x2,
}I2C_OP_TYPE, *PI2C_OP_TYPE;
};
typedef uint32_t I2C_OP_TYPE;
typedef uint32_t *PI2C_OP_TYPE;
// I2C pinmux selection
typedef enum _I2C_PINMUX_ {
enum _I2C_PINMUX_ {
I2C_PIN_S0 = 0x0,
I2C_PIN_S1 = 0x1,
I2C_PIN_S2 = 0x2,
I2C_PIN_S3 = 0x3, //Only valid for I2C0 and I2C3
}I2C_PINMUX, *PI2C_PINMUX;
};
typedef uint32_t I2C_PINMUX;
typedef uint32_t *PI2C_PINMUX;
// I2C module status
typedef enum _I2C_MODULE_STATUS_ {
enum _I2C_MODULE_STATUS_ {
I2C_DISABLE = 0x0,
I2C_ENABLE = 0x1,
}I2C_MODULE_STATUS, *PI2C_MODULE_STATUS;
};
typedef uint32_t I2C_MODULE_STATUS;
typedef uint32_t *PI2C_MODULE_STATUS;
// I2C device status
typedef enum _I2C_Device_STATUS_ {
enum _I2C_Device_STATUS_ {
I2C_STS_UNINITIAL = 0x00,
I2C_STS_INITIALIZED = 0x01,
I2C_STS_IDLE = 0x02,
@ -205,71 +215,93 @@ typedef enum _I2C_Device_STATUS_ {
I2C_STS_ERROR = 0x10,
I2C_STS_TIMEOUT = 0x11,
}I2C_Device_STATUS, *PI2C_Device_STATUS;
};
typedef uint32_t I2C_Device_STATUS;
typedef uint32_t *PI2C_Device_STATUS;
// I2C feature status
typedef enum _I2C_FEATURE_STATUS_{
enum _I2C_FEATURE_STATUS_{
I2C_FEATURE_DISABLED = 0,
I2C_FEATURE_ENABLED = 1,
}I2C_FEATURE_STATUS,*PI2C_FEATURE_STATUS;
};
typedef uint32_t I2C_FEATURE_STATUS;
typedef uint32_t *PI2C_FEATURE_STATUS;
// I2C device mode
typedef enum _I2C_DEV_MODE_ {
enum _I2C_DEV_MODE_ {
I2C_SLAVE_MODE = 0x0,
I2C_MASTER_MODE = 0x1,
}I2C_DEV_MODE, *PI2C_DEV_MODE;
};
typedef uint32_t I2C_DEV_MODE;
typedef uint32_t *PI2C_DEV_MODE;
// I2C Bus Transmit/Receive
typedef enum _I2C_DIRECTION_ {
enum _I2C_DIRECTION_ {
I2C_ONLY_TX = 0x1,
I2C_ONLY_RX = 0x2,
I2C_TXRX = 0x3,
}I2C_DIRECTION, *PI2C_DIRECTION;
};
typedef uint32_t I2C_DIRECTION;
typedef uint32_t *PI2C_DIRECTION;
//I2C DMA module number
typedef enum _I2C_DMA_MODULE_SEL_ {
enum _I2C_DMA_MODULE_SEL_ {
I2C_DMA_MODULE_0 = 0x0,
I2C_DMA_MODULE_1 = 0x1
}I2C_DMA_MODULE_SEL, *PI2C_DMA_MODULE_SEL;
};
typedef uint32_t I2C_DMA_MODULE_SEL;
typedef uint32_t *PI2C_DMA_MODULE_SEL;
// I2C0 DMA peripheral number
typedef enum _I2C0_DMA_PERI_NUM_ {
enum _I2C0_DMA_PERI_NUM_ {
I2C0_DMA_TX_NUM = 0x8,
I2C0_DMA_RX_NUM = 0x9,
}I2C0_DMA_PERI_NUM,*PI2C0_DMA_PERI_NUM;
};
typedef uint32_t I2C0_DMA_PERI_NUM;
typedef uint32_t *PI2C0_DMA_PERI_NUM;
// I2C1 DMA peripheral number
typedef enum _I2C1_DMA_PERI_NUM_ {
enum _I2C1_DMA_PERI_NUM_ {
I2C1_DMA_TX_NUM = 0xA,
I2C1_DMA_RX_NUM = 0xB,
}I2C1_DMA_PERI_NUM,*PI2C1_DMA_PERI_NUM;
};
typedef uint32_t I2C1_DMA_PERI_NUM;
typedef uint32_t *PI2C1_DMA_PERI_NUM;
// I2C0 DMA module used
typedef enum _I2C0_DMA_MODULE_ {
enum _I2C0_DMA_MODULE_ {
I2C0_DMA0 = 0x0,
I2C0_DMA1 = 0x1,
}I2C0_DMA_MODULE,*PI2C0_DMA_MODULE;
};
typedef uint32_t I2C0_DMA_MODULE;
typedef uint32_t *PI2C0_DMA_MODULE;
// I2C0 DMA module used
typedef enum _I2C1_DMA_MODULE_ {
enum _I2C1_DMA_MODULE_ {
I2C1_DMA0 = 0x0,
I2C1_DMA1 = 0x1,
}I2C1_DMA_MODULE,*PI2C1_DMA_MODULE;
};
typedef uint32_t I2C1_DMA_MODULE;
typedef uint32_t *PI2C1_DMA_MODULE;
// I2C command type
typedef enum _I2C_COMMAND_TYPE_ {
enum _I2C_COMMAND_TYPE_ {
I2C_WRITE_CMD = 0x0,
I2C_READ_CMD = 0x1,
}I2C_COMMAND_TYPE,*PI2C_COMMAND_TYPE;
};
typedef uint32_t I2C_COMMAND_TYPE;
typedef uint32_t *PI2C_COMMAND_TYPE;
// I2C STOP BIT
typedef enum _I2C_STOP_TYPE_ {
enum _I2C_STOP_TYPE_ {
I2C_STOP_DIS = 0x0,
I2C_STOP_EN = 0x1,
}I2C_STOP_TYPE, *PI2C_STOP_TYPE;
};
typedef uint32_t I2C_STOP_TYPE;
typedef uint32_t *PI2C_STOP_TYPE;
// I2C error type
typedef enum _I2C_ERR_TYPE_ {
enum _I2C_ERR_TYPE_ {
I2C_ERR_RX_UNDER = 0x01, //I2C RX FIFO Underflow
I2C_ERR_RX_OVER = 0x02, //I2C RX FIFO Overflow
I2C_ERR_TX_OVER = 0x04, //I2C TX FIFO Overflow
@ -287,13 +319,17 @@ typedef enum _I2C_ERR_TYPE_ {
I2C_ERR_TX_ADD_TO = 0x25,
I2C_ERR_RX_ADD_TO = 0x26,
}I2C_ERR_TYPE, *PI2C_ERR_TYPE;
};
typedef uint32_t I2C_ERR_TYPE;
typedef uint32_t *PI2C_ERR_TYPE;
// I2C Time Out type
typedef enum _I2C_TIMEOUT_TYPE_ {
enum _I2C_TIMEOUT_TYPE_ {
I2C_TIMEOOUT_DISABLE = 0x00,
I2C_TIMEOOUT_ENDLESS = 0xFFFFFFFF,
}I2C_TIMEOUT_TYPE, *PI2C_TIMEOUT_TYPE;
};
typedef uint32_t I2C_TIMEOUT_TYPE;
typedef uint32_t *PI2C_TIMEOUT_TYPE;
//======================================================
// SAL I2C related data structures

12
targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_irqn.h
View File

@ -16,7 +16,7 @@
#define PERIPHERAL_IRQ_BASE_NUM 64
typedef enum _IRQn_Type_ {
enum _IRQn_Type_ {
#if 0
/****** Cortex-M3 Processor Exceptions Numbers ********/
NON_MASKABLE_INT_IRQ = -14,
@ -92,15 +92,19 @@ typedef enum _IRQn_Type_ {
PTA_TRX_IRQ = 95,// 31+64
RXI300_IRQ = 96,// 0+32 + 64
NFC_IRQ = 97// 1+32+64
} IRQn_Type, *PIRQn_Type;
};
typedef uint32_t IRQn_Type;
typedef uint32_t *PIRQn_Type;
typedef VOID (*HAL_VECTOR_FUN) (VOID);
typedef enum _VECTOR_TABLE_TYPE_{
enum _VECTOR_TABLE_TYPE_{
DEDECATED_VECTRO_TABLE,
PERIPHERAL_VECTOR_TABLE
}VECTOR_TABLE_TYPE, *PVECTOR_TABLE_TYPE;
};
typedef uint32_t VECTOR_TABLE_TYPE;
typedef uint32_t *PVECTOR_TABLE_TYPE;
typedef void (*IRQ_FUN)(VOID *Data);

25
targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_log_uart.h
View File

@ -19,7 +19,7 @@
#define LOG_UART_WAIT_FOREVER 0xffffffff
// Define Line Control Register Bits
typedef enum {
enum {
LCR_DLS_5B = 0, // Data Length: 5 bits
LCR_DLS_6B = BIT(0), // Data Length: 6 bits
LCR_DLS_7B = BIT(1), // Data Length: 7 bits
@ -34,7 +34,8 @@ typedef enum {
LCR_BC = BIT(6), // Break Control Bit
LCR_DLAB = BIT(7) // Divisor Latch Access Bit
} LOG_UART_LINE_CTRL;
};
typedef uint32_t LOG_UART_LINE_CTRL;
// define Log UART Interrupt Indication ID
/*
@ -47,7 +48,7 @@ IIR[3:0]:
0111 = busy detect
1100 = character timeout
*/
typedef enum {
enum {
IIR_MODEM_STATUS = 0, //Clear to send or data set ready or ring indicator or data carrier detect.
IIR_NO_PENDING = 1,
IIR_THR_EMPTY = 2, // TX FIFO level lower than threshold or FIFO empty
@ -55,19 +56,21 @@ typedef enum {
IIR_RX_LINE_STATUS = 6, // Overrun/parity/framing errors or break interrupt
IIR_BUSY = 7,
IIR_CHAR_TIMEOUT = 12 // timeout: Rx dara ready but no read
} LOG_UART_INT_ID;
};
typedef uint32_t LOG_UART_INT_ID;
// Define Interrupt Enable Bit
typedef enum {
enum {
IER_ERBFI = BIT(0), // Enable Received Data Available Interrupt
IER_ETBEI = BIT(1), // Enable Transmit Holding Register Empty Interrupt
IER_ELSI = BIT(2), // Enable Receiver Line Status Interrupt
IER_EDSSI = BIT(3), // Enable Modem Status Interrupt
IER_PTIME = BIT(7) // Programmable THRE Interrupt Mode Enable
} LOG_UART_INT_EN;
};
typedef uint32_t LOG_UART_INT_EN;
// Define Line Status Bit
typedef enum {
enum {
LSR_DR = BIT(0), // Data Ready bit
LSR_OE = BIT(1), // Overrun error bit
LSR_PE = BIT(2), // Parity Error bit
@ -77,7 +80,8 @@ typedef enum {
LSR_FIFOF = BIT(5), // Transmit FIFO Full bit(IER_PTIME=1)
LSR_TEMT = BIT(6), // Transmitter Empty bit
LSR_RFE = BIT(7) // Receiver FIFO Error bit
} LOG_UART_LINE_STATUS;
};
typedef uint32_t LOG_UART_LINE_STATUS;
enum {
LOG_UART_RST_TX_FIFO = 0x01,
@ -88,7 +92,7 @@ enum {
#define LOG_UART_RX_FIFO_DEPTH 16
// Define FIFO Control Register Bits
typedef enum {
enum {
FCR_FIFO_EN = BIT(0), // FIFO Enable.
FCR_RST_RX = BIT(1), // RCVR FIFO Reset, self clear
FCR_RST_TX = BIT(2), // XMIT FIFO Reset, self clear
@ -102,7 +106,8 @@ typedef enum {
FCR_RX_TRIG_HF = BIT(7), // RCVR Trigger: FIFO 1/2 full
FCR_RX_TRIG_AF = (BIT(7)|BIT(6)), // RCVR Trigger: FIFO 2 less than full
FCR_RX_TRIG_MASK = (BIT(7)|BIT(6)) // RCVR Trigger bits Mask
} LOG_UART_FIFO_CTRL;
};
typedef uint32_t LOG_UART_FIFO_CTRL;
typedef struct _HAL_LOG_UART_ADAPTER_ {
u32 BaudRate;

6
targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_ssi.h
View File

@ -104,7 +104,7 @@ extern uint8_t SPI0_IS_AS_SLAVE;
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
typedef enum _SSI_DBG_TYPE_LIST_ {
enum _SSI_DBG_TYPE_LIST_ {
DBG_TYPE_ENTRANCE = 1 << 0,
DBG_TYPE_INIT = 1 << 1,
DBG_TYPE_INIT_V = 1 << 2,
@ -121,7 +121,9 @@ typedef enum _SSI_DBG_TYPE_LIST_ {
DBG_TYPE_READ = 1 << 13,
DBG_TYPE_WRITE = 1 << 14,
DBG_TYPE_SLV_CTRL = 1 << 15
} SSI_DBG_TYPE_LIST, *PSSI_DBG_TYPE_LIST;
};
typedef uint32_t SSI_DBG_TYPE_LIST;
typedef uint32_t *PSSI_DBG_TYPE_LIST;
typedef struct _SSI_DMA_CONFIG_ {
VOID *pHalGdmaOp;

6
targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_timer.h
View File

@ -20,10 +20,12 @@
#define GTIMER_CLK_HZ (32768)
#define GTIMER_TICK_US (1000000/GTIMER_CLK_HZ)
typedef enum _TIMER_MODE_ {
enum _TIMER_MODE_ {
FREE_RUN_MODE = 0,
USER_DEFINED = 1
}TIMER_MODE, *PTIMER_MODE;
};
typedef uint32_t TIMER_MODE;
typedef uint32_t *PTIMER_MODE;
typedef struct _TIMER_ADAPTER_ {

6
targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/common/bsp/basic_types.h
View File

@ -102,10 +102,12 @@ typedef unsigned char bool;
typedef struct { volatile int counter; } atomic_t;
typedef enum _RTK_STATUS_ {
enum _RTK_STATUS_ {
_EXIT_SUCCESS = 0,
_EXIT_FAILURE = 1
}RTK_STATUS, *PRTK_STATUS;
};
typedef uint32_t RTK_STATUS;
typedef uint32_t * PRTK_STATUS;
#define IN
#define OUT

3
tools/toolchains/arm.py
View File

@ -68,9 +68,6 @@ class ARM(mbedToolchain):
self.asm = [main_cc] + self.flags['common'] + self.flags['asm']
self.cc = [main_cc] + self.flags['common'] + self.flags['c']
self.cppc = [main_cc] + self.flags['common'] + self.flags['c'] + self.flags['cxx']
if target.name in ["REALTEK_RTL8195AM"]:
self.cc += ["--enum_is_int"]
self.cppc += ["--enum_is_int"]
self.ld = [join(ARM_BIN, "armlink")]

3
tools/toolchains/gcc.py
View File

@ -91,9 +91,6 @@ class GCC(mbedToolchain):
self.cppc =[main_cppc]
self.cc += self.flags['c'] + self.flags['common']
self.cppc += self.flags['cxx'] + self.flags['common']
if target.name in ["REALTEK_RTL8195AM"]:
self.cc += ["-fno-short-enums"]
self.cppc += ["-fno-short-enums"]
self.flags['ld'] += self.cpu
self.ld = [join(tool_path, "arm-none-eabi-gcc")] + self.flags['ld']

3
tools/toolchains/iar.py
View File

@ -91,9 +91,6 @@ class IAR(mbedToolchain):
self.cppc = [main_cc]
self.cc += self.flags["common"] + c_flags_cmd + self.flags["c"]
self.cppc += self.flags["common"] + c_flags_cmd + cxx_flags_cmd + self.flags["cxx"]
if target.name in ["REALTEK_RTL8195AM"]:
self.cc += ["--enum_is_int"]
self.cppc += ["--enum_is_int"]
self.ld = [join(IAR_BIN, "ilinkarm")]
self.ar = join(IAR_BIN, "iarchive")