From 020b4e7860744e890ff20fc98bc0808fc88eff87 Mon Sep 17 00:00:00 2001 From: Martin Olejar Date: Sat, 11 Oct 2014 20:09:27 +0200 Subject: [PATCH] Revert "Added CMSIS files for Freescale KL43Z ARM" This reverts commit 94581919bde26c093ad791025324af1471f89bd5. --- .gitignore | 3 - .../TARGET_KLXX/TARGET_KL43Z/MKL43Z4.h | 8889 ----------------- .../TOOLCHAIN_ARM_STD/MKL43Z4.sct | 14 - .../TOOLCHAIN_ARM_STD/startup_MKL43Z4.s | 362 - .../TARGET_KL43Z/TOOLCHAIN_ARM_STD/sys.cpp | 31 - .../TARGET_KL43Z/TOOLCHAIN_GCC_ARM/MKL43Z4.ld | 163 - .../TOOLCHAIN_GCC_ARM/startup_MKL43Z4.s | 243 - .../TARGET_KLXX/TARGET_KL43Z/cmsis.h | 13 - .../TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.c | 30 - .../TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.h | 26 - .../TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.c | 224 - .../TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.h | 335 - 12 files changed, 10333 deletions(-) delete mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/MKL43Z4.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/MKL43Z4.sct delete mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/startup_MKL43Z4.s delete mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/sys.cpp delete mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/MKL43Z4.ld delete mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/startup_MKL43Z4.s delete mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.h diff --git a/.gitignore b/.gitignore index 5535e8caae..75da3674af 100644 --- a/.gitignore +++ b/.gitignore @@ -63,6 +63,3 @@ debug.log # Orig diff files *.orig - -# PyCharm project files -.idea diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/MKL43Z4.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/MKL43Z4.h deleted file mode 100644 index 88de20bea9..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/MKL43Z4.h +++ /dev/null @@ -1,8889 +0,0 @@ -/* -** ################################################################### -** Processors: MKL43Z256VLH4 -** MKL43Z128VLH4 -** MKL43Z64VLH4 -** MKL43Z256VMP4 -** MKL43Z128VMP4 -** MKL43Z64VMP4 -** -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014 -** Version: rev. 1.5, 2014-09-05 -** Build: b140905 -** -** Abstract: -** CMSIS Peripheral Access Layer for MKL43Z4 -** -** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-03-27) -** Initial version. -** - rev. 1.1 (2014-05-26) -** I2S registers TCR2/RCR2 and others were changed. -** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR. -** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS. -** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS. -** Clock configuration for high range external oscillator has been added. -** RFSYS module access has been added. -** - rev. 1.2 (2014-07-10) -** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE. -** UART0 - UART0 module renamed to UART2. -** I2S - removed MDR register. -** - rev. 1.3 (2014-08-21) -** UART2 - Removed ED register. -** UART2 - Removed MODEM register. -** UART2 - Removed IR register. -** UART2 - Removed PFIFO register. -** UART2 - Removed CFIFO register. -** UART2 - Removed SFIFO register. -** UART2 - Removed TWFIFO register. -** UART2 - Removed TCFIFO register. -** UART2 - Removed RWFIFO register. -** UART2 - Removed RCFIFO register. -** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register. -** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register. -** SIM - Removed bitfield DIEID in SDID register. -** - rev. 1.4 (2014-09-01) -** USB - USB0_CTL0 was renamed to USB0_OTGCTL register. -** USB - USB0_CTL1 was renamed to USB0_CTL register. -** - rev. 1.5 (2014-09-05) -** USB - USBEN bitfield of the USB0_CTL renamed to USBENSOFEN. -** -** ################################################################### -*/ - -/*! - * @file MKL43Z4.h - * @version 1.5 - * @date 2014-09-05 - * @brief CMSIS Peripheral Access Layer for MKL43Z4 - * - * CMSIS Peripheral Access Layer for MKL43Z4 - */ - - -/* ---------------------------------------------------------------------------- - -- MCU activation - ---------------------------------------------------------------------------- */ - -/* Prevention from multiple including the same memory map */ -#if !defined(MKL43Z4_H_) /* Check if memory map has not been already included */ -#define MKL43Z4_H_ -#define MCU_MKL43Z4 - -/* Check if another memory map has not been also included */ -#if (defined(MCU_ACTIVE)) - #error MKL43Z4 memory map: There is already included another memory map. Only one memory map can be included. -#endif /* (defined(MCU_ACTIVE)) */ -#define MCU_ACTIVE - -#include - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100u -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0005u - - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Auxiliary constants */ - NotAvail_IRQn = -128, /**< Not available device specific interrupt */ - - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ - - /* Device specific interrupts */ - DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */ - DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ - DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ - DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */ - Reserved20_IRQn = 4, /**< Reserved interrupt */ - FTFA_IRQn = 5, /**< Command complete and read collision */ - PMC_IRQn = 6, /**< Low-voltage detect, low-voltage warning */ - LLWU_IRQn = 7, /**< Low leakage wakeup */ - I2C0_IRQn = 8, /**< I2C0 interrupt */ - I2C1_IRQn = 9, /**< I2C1 interrupt */ - SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */ - SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */ - LPUART0_IRQn = 12, /**< LPUART0 status and error */ - LPUART1_IRQn = 13, /**< LPUART1 status and error */ - UART2_FLEXIO_IRQn = 14, /**< UART2 or FLEXIO */ - ADC0_IRQn = 15, /**< ADC0 interrupt */ - CMP0_IRQn = 16, /**< CMP0 interrupt */ - TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */ - TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */ - TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */ - RTC_IRQn = 20, /**< RTC alarm */ - RTC_Seconds_IRQn = 21, /**< RTC seconds */ - PIT_IRQn = 22, /**< PIT interrupt */ - I2S0_IRQn = 23, /**< I2S0 interrupt */ - USB0_IRQn = 24, /**< USB0 interrupt */ - DAC0_IRQn = 25, /**< DAC0 interrupt */ - Reserved42_IRQn = 26, /**< Reserved interrupt */ - Reserved43_IRQn = 27, /**< Reserved interrupt */ - LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */ - LCD_IRQn = 29, /**< LCD interrupt */ - PORTA_IRQn = 30, /**< PORTA Pin detect */ - PORTCD_IRQn = 31 /**< Single interrupt vector for PORTC; PORTD Pin detect */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M0 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration - * @{ - */ - -#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ -#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ -#define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ - -#include "core_cm0plus.h" /* Core Peripheral Access Layer */ -#include "system_MKL43Z4.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ - __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ - __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ - __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ - __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ - __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ - __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ - __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ - __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ - __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ - __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ - __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ - __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ - __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ - __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ - __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ - __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ - __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ - uint8_t RESERVED_0[4]; - __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ - __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ - __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ - __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ - __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ - __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ - __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ -} ADC_Type, *ADC_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- ADC - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros - * @{ - */ - - -/* ADC - Register accessors */ -#define ADC_SC1_REG(base,index) ((base)->SC1[index]) -#define ADC_CFG1_REG(base) ((base)->CFG1) -#define ADC_CFG2_REG(base) ((base)->CFG2) -#define ADC_R_REG(base,index) ((base)->R[index]) -#define ADC_CV1_REG(base) ((base)->CV1) -#define ADC_CV2_REG(base) ((base)->CV2) -#define ADC_SC2_REG(base) ((base)->SC2) -#define ADC_SC3_REG(base) ((base)->SC3) -#define ADC_OFS_REG(base) ((base)->OFS) -#define ADC_PG_REG(base) ((base)->PG) -#define ADC_MG_REG(base) ((base)->MG) -#define ADC_CLPD_REG(base) ((base)->CLPD) -#define ADC_CLPS_REG(base) ((base)->CLPS) -#define ADC_CLP4_REG(base) ((base)->CLP4) -#define ADC_CLP3_REG(base) ((base)->CLP3) -#define ADC_CLP2_REG(base) ((base)->CLP2) -#define ADC_CLP1_REG(base) ((base)->CLP1) -#define ADC_CLP0_REG(base) ((base)->CLP0) -#define ADC_CLMD_REG(base) ((base)->CLMD) -#define ADC_CLMS_REG(base) ((base)->CLMS) -#define ADC_CLM4_REG(base) ((base)->CLM4) -#define ADC_CLM3_REG(base) ((base)->CLM3) -#define ADC_CLM2_REG(base) ((base)->CLM2) -#define ADC_CLM1_REG(base) ((base)->CLM1) -#define ADC_CLM0_REG(base) ((base)->CLM0) - -/*! - * @} - */ /* end of group ADC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/* SC1 Bit Fields */ -#define ADC_SC1_ADCH_MASK 0x1Fu -#define ADC_SC1_ADCH_SHIFT 0 -#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<CR0) -#define CMP_CR1_REG(base) ((base)->CR1) -#define CMP_FPR_REG(base) ((base)->FPR) -#define CMP_SCR_REG(base) ((base)->SCR) -#define CMP_DACCR_REG(base) ((base)->DACCR) -#define CMP_MUXCR_REG(base) ((base)->MUXCR) - -/*! - * @} - */ /* end of group CMP_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- CMP Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CMP_Register_Masks CMP Register Masks - * @{ - */ - -/* CR0 Bit Fields */ -#define CMP_CR0_HYSTCTR_MASK 0x3u -#define CMP_CR0_HYSTCTR_SHIFT 0 -#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<DAT[index].DATL) -#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH) -#define DAC_SR_REG(base) ((base)->SR) -#define DAC_C0_REG(base) ((base)->C0) -#define DAC_C1_REG(base) ((base)->C1) -#define DAC_C2_REG(base) ((base)->C2) - -/*! - * @} - */ /* end of group DAC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- DAC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DAC_Register_Masks DAC Register Masks - * @{ - */ - -/* DATL Bit Fields */ -#define DAC_DATL_DATA0_MASK 0xFFu -#define DAC_DATL_DATA0_SHIFT 0 -#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<DMA[index].SAR) -#define DMA_DAR_REG(base,index) ((base)->DMA[index].DAR) -#define DMA_DSR_BCR_REG(base,index) ((base)->DMA[index].DSR_BCR) -#define DMA_DSR_REG(base,index) ((base)->DMA[index].DMA_DSR_ACCESS8BIT.DSR) -#define DMA_DCR_REG(base,index) ((base)->DMA[index].DCR) - -/*! - * @} - */ /* end of group DMA_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/* SAR Bit Fields */ -#define DMA_SAR_SAR_MASK 0xFFFFFFFFu -#define DMA_SAR_SAR_SHIFT 0 -#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<CHCFG[index]) - -/*! - * @} - */ /* end of group DMAMUX_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- DMAMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks - * @{ - */ - -/* CHCFG Bit Fields */ -#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu -#define DMAMUX_CHCFG_SOURCE_SHIFT 0 -#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<VERID) -#define FLEXIO_PARAM_REG(base) ((base)->PARAM) -#define FLEXIO_CTRL_REG(base) ((base)->CTRL) -#define FLEXIO_SHIFTSTAT_REG(base) ((base)->SHIFTSTAT) -#define FLEXIO_SHIFTERR_REG(base) ((base)->SHIFTERR) -#define FLEXIO_TIMSTAT_REG(base) ((base)->TIMSTAT) -#define FLEXIO_SHIFTSIEN_REG(base) ((base)->SHIFTSIEN) -#define FLEXIO_SHIFTEIEN_REG(base) ((base)->SHIFTEIEN) -#define FLEXIO_TIMIEN_REG(base) ((base)->TIMIEN) -#define FLEXIO_SHIFTSDEN_REG(base) ((base)->SHIFTSDEN) -#define FLEXIO_SHIFTCTL_REG(base,index) ((base)->SHIFTCTL[index]) -#define FLEXIO_SHIFTCFG_REG(base,index) ((base)->SHIFTCFG[index]) -#define FLEXIO_SHIFTBUF_REG(base,index) ((base)->SHIFTBUF[index]) -#define FLEXIO_SHIFTBUFBBS_REG(base,index) ((base)->SHIFTBUFBBS[index]) -#define FLEXIO_SHIFTBUFBYS_REG(base,index) ((base)->SHIFTBUFBYS[index]) -#define FLEXIO_SHIFTBUFBIS_REG(base,index) ((base)->SHIFTBUFBIS[index]) -#define FLEXIO_TIMCTL_REG(base,index) ((base)->TIMCTL[index]) -#define FLEXIO_TIMCFG_REG(base,index) ((base)->TIMCFG[index]) -#define FLEXIO_TIMCMP_REG(base,index) ((base)->TIMCMP[index]) - -/*! - * @} - */ /* end of group FLEXIO_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- FLEXIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks - * @{ - */ - -/* VERID Bit Fields */ -#define FLEXIO_VERID_FEATURE_MASK 0xFFFFu -#define FLEXIO_VERID_FEATURE_SHIFT 0 -#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<FSTAT) -#define FTFA_FCNFG_REG(base) ((base)->FCNFG) -#define FTFA_FSEC_REG(base) ((base)->FSEC) -#define FTFA_FOPT_REG(base) ((base)->FOPT) -#define FTFA_FCCOB3_REG(base) ((base)->FCCOB3) -#define FTFA_FCCOB2_REG(base) ((base)->FCCOB2) -#define FTFA_FCCOB1_REG(base) ((base)->FCCOB1) -#define FTFA_FCCOB0_REG(base) ((base)->FCCOB0) -#define FTFA_FCCOB7_REG(base) ((base)->FCCOB7) -#define FTFA_FCCOB6_REG(base) ((base)->FCCOB6) -#define FTFA_FCCOB5_REG(base) ((base)->FCCOB5) -#define FTFA_FCCOB4_REG(base) ((base)->FCCOB4) -#define FTFA_FCCOBB_REG(base) ((base)->FCCOBB) -#define FTFA_FCCOBA_REG(base) ((base)->FCCOBA) -#define FTFA_FCCOB9_REG(base) ((base)->FCCOB9) -#define FTFA_FCCOB8_REG(base) ((base)->FCCOB8) -#define FTFA_FPROT3_REG(base) ((base)->FPROT3) -#define FTFA_FPROT2_REG(base) ((base)->FPROT2) -#define FTFA_FPROT1_REG(base) ((base)->FPROT1) -#define FTFA_FPROT0_REG(base) ((base)->FPROT0) - -/*! - * @} - */ /* end of group FTFA_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- FTFA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FTFA_Register_Masks FTFA Register Masks - * @{ - */ - -/* FSTAT Bit Fields */ -#define FTFA_FSTAT_MGSTAT0_MASK 0x1u -#define FTFA_FSTAT_MGSTAT0_SHIFT 0 -#define FTFA_FSTAT_FPVIOL_MASK 0x10u -#define FTFA_FSTAT_FPVIOL_SHIFT 4 -#define FTFA_FSTAT_ACCERR_MASK 0x20u -#define FTFA_FSTAT_ACCERR_SHIFT 5 -#define FTFA_FSTAT_RDCOLERR_MASK 0x40u -#define FTFA_FSTAT_RDCOLERR_SHIFT 6 -#define FTFA_FSTAT_CCIF_MASK 0x80u -#define FTFA_FSTAT_CCIF_SHIFT 7 -/* FCNFG Bit Fields */ -#define FTFA_FCNFG_ERSSUSP_MASK 0x10u -#define FTFA_FCNFG_ERSSUSP_SHIFT 4 -#define FTFA_FCNFG_ERSAREQ_MASK 0x20u -#define FTFA_FCNFG_ERSAREQ_SHIFT 5 -#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u -#define FTFA_FCNFG_RDCOLLIE_SHIFT 6 -#define FTFA_FCNFG_CCIE_MASK 0x80u -#define FTFA_FCNFG_CCIE_SHIFT 7 -/* FSEC Bit Fields */ -#define FTFA_FSEC_SEC_MASK 0x3u -#define FTFA_FSEC_SEC_SHIFT 0 -#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<PDOR) -#define GPIO_PSOR_REG(base) ((base)->PSOR) -#define GPIO_PCOR_REG(base) ((base)->PCOR) -#define GPIO_PTOR_REG(base) ((base)->PTOR) -#define GPIO_PDIR_REG(base) ((base)->PDIR) -#define GPIO_PDDR_REG(base) ((base)->PDDR) - -/*! - * @} - */ /* end of group GPIO_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/* PDOR Bit Fields */ -#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu -#define GPIO_PDOR_PDO_SHIFT 0 -#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<A1) -#define I2C_F_REG(base) ((base)->F) -#define I2C_C1_REG(base) ((base)->C1) -#define I2C_S_REG(base) ((base)->S) -#define I2C_D_REG(base) ((base)->D) -#define I2C_C2_REG(base) ((base)->C2) -#define I2C_FLT_REG(base) ((base)->FLT) -#define I2C_RA_REG(base) ((base)->RA) -#define I2C_SMB_REG(base) ((base)->SMB) -#define I2C_A2_REG(base) ((base)->A2) -#define I2C_SLTH_REG(base) ((base)->SLTH) -#define I2C_SLTL_REG(base) ((base)->SLTL) -#define I2C_S2_REG(base) ((base)->S2) - -/*! - * @} - */ /* end of group I2C_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- I2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Register_Masks I2C Register Masks - * @{ - */ - -/* A1 Bit Fields */ -#define I2C_A1_AD_MASK 0xFEu -#define I2C_A1_AD_SHIFT 1 -#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<TCSR) -#define I2S_TCR2_REG(base) ((base)->TCR2) -#define I2S_TCR3_REG(base) ((base)->TCR3) -#define I2S_TCR4_REG(base) ((base)->TCR4) -#define I2S_TCR5_REG(base) ((base)->TCR5) -#define I2S_TDR_REG(base,index) ((base)->TDR[index]) -#define I2S_TMR_REG(base) ((base)->TMR) -#define I2S_RCSR_REG(base) ((base)->RCSR) -#define I2S_RCR2_REG(base) ((base)->RCR2) -#define I2S_RCR3_REG(base) ((base)->RCR3) -#define I2S_RCR4_REG(base) ((base)->RCR4) -#define I2S_RCR5_REG(base) ((base)->RCR5) -#define I2S_RDR_REG(base,index) ((base)->RDR[index]) -#define I2S_RMR_REG(base) ((base)->RMR) -#define I2S_MCR_REG(base) ((base)->MCR) - -/*! - * @} - */ /* end of group I2S_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/* TCSR Bit Fields */ -#define I2S_TCSR_FWDE_MASK 0x2u -#define I2S_TCSR_FWDE_SHIFT 1 -#define I2S_TCSR_FWIE_MASK 0x200u -#define I2S_TCSR_FWIE_SHIFT 9 -#define I2S_TCSR_FEIE_MASK 0x400u -#define I2S_TCSR_FEIE_SHIFT 10 -#define I2S_TCSR_SEIE_MASK 0x800u -#define I2S_TCSR_SEIE_SHIFT 11 -#define I2S_TCSR_WSIE_MASK 0x1000u -#define I2S_TCSR_WSIE_SHIFT 12 -#define I2S_TCSR_FWF_MASK 0x20000u -#define I2S_TCSR_FWF_SHIFT 17 -#define I2S_TCSR_FEF_MASK 0x40000u -#define I2S_TCSR_FEF_SHIFT 18 -#define I2S_TCSR_SEF_MASK 0x80000u -#define I2S_TCSR_SEF_SHIFT 19 -#define I2S_TCSR_WSF_MASK 0x100000u -#define I2S_TCSR_WSF_SHIFT 20 -#define I2S_TCSR_SR_MASK 0x1000000u -#define I2S_TCSR_SR_SHIFT 24 -#define I2S_TCSR_FR_MASK 0x2000000u -#define I2S_TCSR_FR_SHIFT 25 -#define I2S_TCSR_BCE_MASK 0x10000000u -#define I2S_TCSR_BCE_SHIFT 28 -#define I2S_TCSR_DBGE_MASK 0x20000000u -#define I2S_TCSR_DBGE_SHIFT 29 -#define I2S_TCSR_STOPE_MASK 0x40000000u -#define I2S_TCSR_STOPE_SHIFT 30 -#define I2S_TCSR_TE_MASK 0x80000000u -#define I2S_TCSR_TE_SHIFT 31 -/* TCR2 Bit Fields */ -#define I2S_TCR2_DIV_MASK 0xFFu -#define I2S_TCR2_DIV_SHIFT 0 -#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<GCR) -#define LCD_AR_REG(base) ((base)->AR) -#define LCD_FDCR_REG(base) ((base)->FDCR) -#define LCD_FDSR_REG(base) ((base)->FDSR) -#define LCD_PEN_REG(base,index) ((base)->PEN[index]) -#define LCD_BPEN_REG(base,index) ((base)->BPEN[index]) -#define LCD_WF_REG(base,index2) ((base)->WF[index2]) -#define LCD_WF8B_REG(base,index2) ((base)->WF8B[index2]) - -/*! - * @} - */ /* end of group LCD_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- LCD Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LCD_Register_Masks LCD Register Masks - * @{ - */ - -/* GCR Bit Fields */ -#define LCD_GCR_DUTY_MASK 0x7u -#define LCD_GCR_DUTY_SHIFT 0 -#define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x))<PE1) -#define LLWU_PE2_REG(base) ((base)->PE2) -#define LLWU_PE3_REG(base) ((base)->PE3) -#define LLWU_PE4_REG(base) ((base)->PE4) -#define LLWU_ME_REG(base) ((base)->ME) -#define LLWU_F1_REG(base) ((base)->F1) -#define LLWU_F2_REG(base) ((base)->F2) -#define LLWU_F3_REG(base) ((base)->F3) -#define LLWU_FILT1_REG(base) ((base)->FILT1) -#define LLWU_FILT2_REG(base) ((base)->FILT2) - -/*! - * @} - */ /* end of group LLWU_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- LLWU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LLWU_Register_Masks LLWU Register Masks - * @{ - */ - -/* PE1 Bit Fields */ -#define LLWU_PE1_WUPE0_MASK 0x3u -#define LLWU_PE1_WUPE0_SHIFT 0 -#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<CSR) -#define LPTMR_PSR_REG(base) ((base)->PSR) -#define LPTMR_CMR_REG(base) ((base)->CMR) -#define LPTMR_CNR_REG(base) ((base)->CNR) - -/*! - * @} - */ /* end of group LPTMR_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- LPTMR Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPTMR_Register_Masks LPTMR Register Masks - * @{ - */ - -/* CSR Bit Fields */ -#define LPTMR_CSR_TEN_MASK 0x1u -#define LPTMR_CSR_TEN_SHIFT 0 -#define LPTMR_CSR_TMS_MASK 0x2u -#define LPTMR_CSR_TMS_SHIFT 1 -#define LPTMR_CSR_TFC_MASK 0x4u -#define LPTMR_CSR_TFC_SHIFT 2 -#define LPTMR_CSR_TPP_MASK 0x8u -#define LPTMR_CSR_TPP_SHIFT 3 -#define LPTMR_CSR_TPS_MASK 0x30u -#define LPTMR_CSR_TPS_SHIFT 4 -#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<BAUD) -#define LPUART_STAT_REG(base) ((base)->STAT) -#define LPUART_CTRL_REG(base) ((base)->CTRL) -#define LPUART_DATA_REG(base) ((base)->DATA) -#define LPUART_MATCH_REG(base) ((base)->MATCH) - -/*! - * @} - */ /* end of group LPUART_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- LPUART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPUART_Register_Masks LPUART Register Masks - * @{ - */ - -/* BAUD Bit Fields */ -#define LPUART_BAUD_SBR_MASK 0x1FFFu -#define LPUART_BAUD_SBR_SHIFT 0 -#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<C1) -#define MCG_C2_REG(base) ((base)->C2) -#define MCG_S_REG(base) ((base)->S) -#define MCG_SC_REG(base) ((base)->SC) -#define MCG_HCTRIM_REG(base) ((base)->HCTRIM) -#define MCG_HTTRIM_REG(base) ((base)->HTTRIM) -#define MCG_HFTRIM_REG(base) ((base)->HFTRIM) -#define MCG_MC_REG(base) ((base)->MC) -#define MCG_LTRIMRNG_REG(base) ((base)->LTRIMRNG) -#define MCG_LFTRIM_REG(base) ((base)->LFTRIM) -#define MCG_LSTRIM_REG(base) ((base)->LSTRIM) - -/*! - * @} - */ /* end of group MCG_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- MCG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCG_Register_Masks MCG Register Masks - * @{ - */ - -/* C1 Bit Fields */ -#define MCG_C1_IREFSTEN_MASK 0x1u -#define MCG_C1_IREFSTEN_SHIFT 0 -#define MCG_C1_IRCLKEN_MASK 0x2u -#define MCG_C1_IRCLKEN_SHIFT 1 -#define MCG_C1_CLKS_MASK 0xC0u -#define MCG_C1_CLKS_SHIFT 6 -#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<PLASC) -#define MCM_PLAMC_REG(base) ((base)->PLAMC) -#define MCM_PLACR_REG(base) ((base)->PLACR) -#define MCM_CPO_REG(base) ((base)->CPO) - -/*! - * @} - */ /* end of group MCM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- MCM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCM_Register_Masks MCM Register Masks - * @{ - */ - -/* PLASC Bit Fields */ -#define MCM_PLASC_ASC_MASK 0xFFu -#define MCM_PLASC_ASC_SHIFT 0 -#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<POSITION) -#define MTB_MASTER_REG(base) ((base)->MASTER) -#define MTB_FLOW_REG(base) ((base)->FLOW) -#define MTB_BASE_REG(base) ((base)->BASE) -#define MTB_MODECTRL_REG(base) ((base)->MODECTRL) -#define MTB_TAGSET_REG(base) ((base)->TAGSET) -#define MTB_TAGCLEAR_REG(base) ((base)->TAGCLEAR) -#define MTB_LOCKACCESS_REG(base) ((base)->LOCKACCESS) -#define MTB_LOCKSTAT_REG(base) ((base)->LOCKSTAT) -#define MTB_AUTHSTAT_REG(base) ((base)->AUTHSTAT) -#define MTB_DEVICEARCH_REG(base) ((base)->DEVICEARCH) -#define MTB_DEVICECFG_REG(base) ((base)->DEVICECFG) -#define MTB_DEVICETYPID_REG(base) ((base)->DEVICETYPID) -#define MTB_PERIPHID_REG(base,index) ((base)->PERIPHID[index]) -#define MTB_COMPID_REG(base,index) ((base)->COMPID[index]) - -/*! - * @} - */ /* end of group MTB_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- MTB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MTB_Register_Masks MTB Register Masks - * @{ - */ - -/* POSITION Bit Fields */ -#define MTB_POSITION_WRAP_MASK 0x4u -#define MTB_POSITION_WRAP_SHIFT 2 -#define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u -#define MTB_POSITION_POINTER_SHIFT 3 -#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<CTRL) -#define MTBDWT_COMP_REG(base,index) ((base)->COMPARATOR[index].COMP) -#define MTBDWT_MASK_REG(base,index) ((base)->COMPARATOR[index].MASK) -#define MTBDWT_FCT_REG(base,index) ((base)->COMPARATOR[index].FCT) -#define MTBDWT_TBCTRL_REG(base) ((base)->TBCTRL) -#define MTBDWT_DEVICECFG_REG(base) ((base)->DEVICECFG) -#define MTBDWT_DEVICETYPID_REG(base) ((base)->DEVICETYPID) -#define MTBDWT_PERIPHID_REG(base,index) ((base)->PERIPHID[index]) -#define MTBDWT_COMPID_REG(base,index) ((base)->COMPID[index]) - -/*! - * @} - */ /* end of group MTBDWT_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- MTBDWT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks - * @{ - */ - -/* CTRL Bit Fields */ -#define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu -#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0 -#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<BACKKEY3) -#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2) -#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1) -#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0) -#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7) -#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6) -#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5) -#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4) -#define NV_FPROT3_REG(base) ((base)->FPROT3) -#define NV_FPROT2_REG(base) ((base)->FPROT2) -#define NV_FPROT1_REG(base) ((base)->FPROT1) -#define NV_FPROT0_REG(base) ((base)->FPROT0) -#define NV_FSEC_REG(base) ((base)->FSEC) -#define NV_FOPT_REG(base) ((base)->FOPT) - -/*! - * @} - */ /* end of group NV_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- NV Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup NV_Register_Masks NV Register Masks - * @{ - */ - -/* BACKKEY3 Bit Fields */ -#define NV_BACKKEY3_KEY_MASK 0xFFu -#define NV_BACKKEY3_KEY_SHIFT 0 -#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<CR) - -/*! - * @} - */ /* end of group OSC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- OSC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSC_Register_Masks OSC Register Masks - * @{ - */ - -/* CR Bit Fields */ -#define OSC_CR_SC16P_MASK 0x1u -#define OSC_CR_SC16P_SHIFT 0 -#define OSC_CR_SC8P_MASK 0x2u -#define OSC_CR_SC8P_SHIFT 1 -#define OSC_CR_SC4P_MASK 0x4u -#define OSC_CR_SC4P_SHIFT 2 -#define OSC_CR_SC2P_MASK 0x8u -#define OSC_CR_SC2P_SHIFT 3 -#define OSC_CR_EREFSTEN_MASK 0x20u -#define OSC_CR_EREFSTEN_SHIFT 5 -#define OSC_CR_ERCLKEN_MASK 0x80u -#define OSC_CR_ERCLKEN_SHIFT 7 - -/*! - * @} - */ /* end of group OSC_Register_Masks */ - - -/* OSC - Peripheral instance base addresses */ -/** Peripheral OSC0 base address */ -#define OSC0_BASE (0x40065000u) -/** Peripheral OSC0 base pointer */ -#define OSC0 ((OSC_Type *)OSC0_BASE) -#define OSC0_BASE_PTR (OSC0) -/** Array initializer of OSC peripheral base addresses */ -#define OSC_BASE_ADDRS { OSC0_BASE } -/** Array initializer of OSC peripheral base pointers */ -#define OSC_BASE_PTRS { OSC0 } -#define OSC_BASES { OSC0 } - -/* ---------------------------------------------------------------------------- - -- OSC - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros - * @{ - */ - - -/* OSC - Register instance definitions */ -/* OSC0 */ -#define OSC0_CR OSC_CR_REG(OSC0) - -/*! - * @} - */ /* end of group OSC_Register_Accessor_Macros */ - - -/*! - * @} - */ /* end of group OSC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PIT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer - * @{ - */ - -/** PIT - Register Layout Typedef */ -typedef struct { - __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ - uint8_t RESERVED_0[220]; - __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */ - __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */ - uint8_t RESERVED_1[24]; - struct { /* offset: 0x100, array step: 0x10 */ - __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ - __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ - __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ - __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ - } CHANNEL[2]; -} PIT_Type, *PIT_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- PIT - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros - * @{ - */ - - -/* PIT - Register accessors */ -#define PIT_MCR_REG(base) ((base)->MCR) -#define PIT_LTMR64H_REG(base) ((base)->LTMR64H) -#define PIT_LTMR64L_REG(base) ((base)->LTMR64L) -#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL) -#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL) -#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL) -#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG) - -/*! - * @} - */ /* end of group PIT_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- PIT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PIT_Register_Masks PIT Register Masks - * @{ - */ - -/* MCR Bit Fields */ -#define PIT_MCR_FRZ_MASK 0x1u -#define PIT_MCR_FRZ_SHIFT 0 -#define PIT_MCR_MDIS_MASK 0x2u -#define PIT_MCR_MDIS_SHIFT 1 -/* LTMR64H Bit Fields */ -#define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu -#define PIT_LTMR64H_LTH_SHIFT 0 -#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<LVDSC1) -#define PMC_LVDSC2_REG(base) ((base)->LVDSC2) -#define PMC_REGSC_REG(base) ((base)->REGSC) - -/*! - * @} - */ /* end of group PMC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- PMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMC_Register_Masks PMC Register Masks - * @{ - */ - -/* LVDSC1 Bit Fields */ -#define PMC_LVDSC1_LVDV_MASK 0x3u -#define PMC_LVDSC1_LVDV_SHIFT 0 -#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<PCR[index]) -#define PORT_GPCLR_REG(base) ((base)->GPCLR) -#define PORT_GPCHR_REG(base) ((base)->GPCHR) -#define PORT_ISFR_REG(base) ((base)->ISFR) - -/*! - * @} - */ /* end of group PORT_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- PORT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PORT_Register_Masks PORT Register Masks - * @{ - */ - -/* PCR Bit Fields */ -#define PORT_PCR_PS_MASK 0x1u -#define PORT_PCR_PS_SHIFT 0 -#define PORT_PCR_PE_MASK 0x2u -#define PORT_PCR_PE_SHIFT 1 -#define PORT_PCR_SRE_MASK 0x4u -#define PORT_PCR_SRE_SHIFT 2 -#define PORT_PCR_PFE_MASK 0x10u -#define PORT_PCR_PFE_SHIFT 4 -#define PORT_PCR_DSE_MASK 0x40u -#define PORT_PCR_DSE_SHIFT 6 -#define PORT_PCR_MUX_MASK 0x700u -#define PORT_PCR_MUX_SHIFT 8 -#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<SRS0) -#define RCM_SRS1_REG(base) ((base)->SRS1) -#define RCM_RPFC_REG(base) ((base)->RPFC) -#define RCM_RPFW_REG(base) ((base)->RPFW) -#define RCM_FM_REG(base) ((base)->FM) -#define RCM_MR_REG(base) ((base)->MR) -#define RCM_SSRS0_REG(base) ((base)->SSRS0) -#define RCM_SSRS1_REG(base) ((base)->SSRS1) - -/*! - * @} - */ /* end of group RCM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RCM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RCM_Register_Masks RCM Register Masks - * @{ - */ - -/* SRS0 Bit Fields */ -#define RCM_SRS0_WAKEUP_MASK 0x1u -#define RCM_SRS0_WAKEUP_SHIFT 0 -#define RCM_SRS0_LVD_MASK 0x2u -#define RCM_SRS0_LVD_SHIFT 1 -#define RCM_SRS0_WDOG_MASK 0x20u -#define RCM_SRS0_WDOG_SHIFT 5 -#define RCM_SRS0_PIN_MASK 0x40u -#define RCM_SRS0_PIN_SHIFT 6 -#define RCM_SRS0_POR_MASK 0x80u -#define RCM_SRS0_POR_SHIFT 7 -/* SRS1 Bit Fields */ -#define RCM_SRS1_LOCKUP_MASK 0x2u -#define RCM_SRS1_LOCKUP_SHIFT 1 -#define RCM_SRS1_SW_MASK 0x4u -#define RCM_SRS1_SW_SHIFT 2 -#define RCM_SRS1_MDM_AP_MASK 0x8u -#define RCM_SRS1_MDM_AP_SHIFT 3 -#define RCM_SRS1_SACKERR_MASK 0x20u -#define RCM_SRS1_SACKERR_SHIFT 5 -/* RPFC Bit Fields */ -#define RCM_RPFC_RSTFLTSRW_MASK 0x3u -#define RCM_RPFC_RSTFLTSRW_SHIFT 0 -#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<REG[index]) - -/*! - * @} - */ /* end of group RFSYS_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RFSYS Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RFSYS_Register_Masks RFSYS Register Masks - * @{ - */ - -/* REG Bit Fields */ -#define RFSYS_REG_LL_MASK 0xFFu -#define RFSYS_REG_LL_SHIFT 0 -#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<ENTRY[index]) -#define ROM_TABLEMARK_REG(base) ((base)->TABLEMARK) -#define ROM_SYSACCESS_REG(base) ((base)->SYSACCESS) -#define ROM_PERIPHID4_REG(base) ((base)->PERIPHID4) -#define ROM_PERIPHID5_REG(base) ((base)->PERIPHID5) -#define ROM_PERIPHID6_REG(base) ((base)->PERIPHID6) -#define ROM_PERIPHID7_REG(base) ((base)->PERIPHID7) -#define ROM_PERIPHID0_REG(base) ((base)->PERIPHID0) -#define ROM_PERIPHID1_REG(base) ((base)->PERIPHID1) -#define ROM_PERIPHID2_REG(base) ((base)->PERIPHID2) -#define ROM_PERIPHID3_REG(base) ((base)->PERIPHID3) -#define ROM_COMPID_REG(base,index) ((base)->COMPID[index]) - -/*! - * @} - */ /* end of group ROM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- ROM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ROM_Register_Masks ROM Register Masks - * @{ - */ - -/* ENTRY Bit Fields */ -#define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu -#define ROM_ENTRY_ENTRY_SHIFT 0 -#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<TSR) -#define RTC_TPR_REG(base) ((base)->TPR) -#define RTC_TAR_REG(base) ((base)->TAR) -#define RTC_TCR_REG(base) ((base)->TCR) -#define RTC_CR_REG(base) ((base)->CR) -#define RTC_SR_REG(base) ((base)->SR) -#define RTC_LR_REG(base) ((base)->LR) -#define RTC_IER_REG(base) ((base)->IER) - -/*! - * @} - */ /* end of group RTC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/* TSR Bit Fields */ -#define RTC_TSR_TSR_MASK 0xFFFFFFFFu -#define RTC_TSR_TSR_SHIFT 0 -#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<SOPT1) -#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG) -#define SIM_SOPT2_REG(base) ((base)->SOPT2) -#define SIM_SOPT4_REG(base) ((base)->SOPT4) -#define SIM_SOPT5_REG(base) ((base)->SOPT5) -#define SIM_SOPT7_REG(base) ((base)->SOPT7) -#define SIM_SDID_REG(base) ((base)->SDID) -#define SIM_SCGC4_REG(base) ((base)->SCGC4) -#define SIM_SCGC5_REG(base) ((base)->SCGC5) -#define SIM_SCGC6_REG(base) ((base)->SCGC6) -#define SIM_SCGC7_REG(base) ((base)->SCGC7) -#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1) -#define SIM_FCFG1_REG(base) ((base)->FCFG1) -#define SIM_FCFG2_REG(base) ((base)->FCFG2) -#define SIM_UIDMH_REG(base) ((base)->UIDMH) -#define SIM_UIDML_REG(base) ((base)->UIDML) -#define SIM_UIDL_REG(base) ((base)->UIDL) -#define SIM_COPC_REG(base) ((base)->COPC) -#define SIM_SRVCOP_REG(base) ((base)->SRVCOP) - -/*! - * @} - */ /* end of group SIM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SIM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SIM_Register_Masks SIM Register Masks - * @{ - */ - -/* SOPT1 Bit Fields */ -#define SIM_SOPT1_OSC32KOUT_MASK 0x30000u -#define SIM_SOPT1_OSC32KOUT_SHIFT 16 -#define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x))<PMPROT) -#define SMC_PMCTRL_REG(base) ((base)->PMCTRL) -#define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL) -#define SMC_PMSTAT_REG(base) ((base)->PMSTAT) - -/*! - * @} - */ /* end of group SMC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SMC_Register_Masks SMC Register Masks - * @{ - */ - -/* PMPROT Bit Fields */ -#define SMC_PMPROT_AVLLS_MASK 0x2u -#define SMC_PMPROT_AVLLS_SHIFT 1 -#define SMC_PMPROT_ALLS_MASK 0x8u -#define SMC_PMPROT_ALLS_SHIFT 3 -#define SMC_PMPROT_AVLP_MASK 0x20u -#define SMC_PMPROT_AVLP_SHIFT 5 -/* PMCTRL Bit Fields */ -#define SMC_PMCTRL_STOPM_MASK 0x7u -#define SMC_PMCTRL_STOPM_SHIFT 0 -#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<S) -#define SPI_BR_REG(base) ((base)->BR) -#define SPI_C2_REG(base) ((base)->C2) -#define SPI_C1_REG(base) ((base)->C1) -#define SPI_ML_REG(base) ((base)->ML) -#define SPI_MH_REG(base) ((base)->MH) -#define SPI_DL_REG(base) ((base)->DL) -#define SPI_DH_REG(base) ((base)->DH) -#define SPI_CI_REG(base) ((base)->CI) -#define SPI_C3_REG(base) ((base)->C3) - -/*! - * @} - */ /* end of group SPI_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Register_Masks SPI Register Masks - * @{ - */ - -/* S Bit Fields */ -#define SPI_S_RFIFOEF_MASK 0x1u -#define SPI_S_RFIFOEF_SHIFT 0 -#define SPI_S_TXFULLF_MASK 0x2u -#define SPI_S_TXFULLF_SHIFT 1 -#define SPI_S_TNEAREF_MASK 0x4u -#define SPI_S_TNEAREF_SHIFT 2 -#define SPI_S_RNFULLF_MASK 0x8u -#define SPI_S_RNFULLF_SHIFT 3 -#define SPI_S_MODF_MASK 0x10u -#define SPI_S_MODF_SHIFT 4 -#define SPI_S_SPTEF_MASK 0x20u -#define SPI_S_SPTEF_SHIFT 5 -#define SPI_S_SPMF_MASK 0x40u -#define SPI_S_SPMF_SHIFT 6 -#define SPI_S_SPRF_MASK 0x80u -#define SPI_S_SPRF_SHIFT 7 -/* BR Bit Fields */ -#define SPI_BR_SPR_MASK 0xFu -#define SPI_BR_SPR_SHIFT 0 -#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<SC) -#define TPM_CNT_REG(base) ((base)->CNT) -#define TPM_MOD_REG(base) ((base)->MOD) -#define TPM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC) -#define TPM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV) -#define TPM_STATUS_REG(base) ((base)->STATUS) -#define TPM_POL_REG(base) ((base)->POL) -#define TPM_CONF_REG(base) ((base)->CONF) - -/*! - * @} - */ /* end of group TPM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- TPM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TPM_Register_Masks TPM Register Masks - * @{ - */ - -/* SC Bit Fields */ -#define TPM_SC_PS_MASK 0x7u -#define TPM_SC_PS_SHIFT 0 -#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<BDH) -#define UART_BDL_REG(base) ((base)->BDL) -#define UART_C1_REG(base) ((base)->C1) -#define UART_C2_REG(base) ((base)->C2) -#define UART_S1_REG(base) ((base)->S1) -#define UART_S2_REG(base) ((base)->S2) -#define UART_C3_REG(base) ((base)->C3) -#define UART_D_REG(base) ((base)->D) -#define UART_MA1_REG(base) ((base)->MA1) -#define UART_MA2_REG(base) ((base)->MA2) -#define UART_C4_REG(base) ((base)->C4) -#define UART_C5_REG(base) ((base)->C5) -#define UART_C7816_REG(base) ((base)->C7816) -#define UART_IE7816_REG(base) ((base)->IE7816) -#define UART_IS7816_REG(base) ((base)->IS7816) -#define UART_WP7816_REG(base) ((base)->WP7816) -#define UART_WN7816_REG(base) ((base)->WN7816) -#define UART_WF7816_REG(base) ((base)->WF7816) -#define UART_ET7816_REG(base) ((base)->ET7816) -#define UART_TL7816_REG(base) ((base)->TL7816) -#define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0) -#define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0) -#define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0) -#define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0) -#define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1) -#define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1) -#define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1) -#define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1) - -/*! - * @} - */ /* end of group UART_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- UART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UART_Register_Masks UART Register Masks - * @{ - */ - -/* BDH Bit Fields */ -#define UART_BDH_SBR_MASK 0x1Fu -#define UART_BDH_SBR_SHIFT 0 -#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<PERID) -#define USB_IDCOMP_REG(base) ((base)->IDCOMP) -#define USB_REV_REG(base) ((base)->REV) -#define USB_ADDINFO_REG(base) ((base)->ADDINFO) -#define USB_OTGCTL_REG(base) ((base)->OTGCTL) -#define USB_ISTAT_REG(base) ((base)->ISTAT) -#define USB_INTEN_REG(base) ((base)->INTEN) -#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT) -#define USB_ERREN_REG(base) ((base)->ERREN) -#define USB_STAT_REG(base) ((base)->STAT) -#define USB_CTL_REG(base) ((base)->CTL) -#define USB_ADDR_REG(base) ((base)->ADDR) -#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1) -#define USB_FRMNUML_REG(base) ((base)->FRMNUML) -#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH) -#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2) -#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3) -#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT) -#define USB_USBCTRL_REG(base) ((base)->USBCTRL) -#define USB_OBSERVE_REG(base) ((base)->OBSERVE) -#define USB_CONTROL_REG(base) ((base)->CONTROL) -#define USB_USBTRC0_REG(base) ((base)->USBTRC0) -#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST) -#define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL) -#define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN) -#define USB_CLK_RECOVER_INT_EN_REG(base) ((base)->CLK_RECOVER_INT_EN) -#define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS) - -/*! - * @} - */ /* end of group USB_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/* PERID Bit Fields */ -#define USB_PERID_ID_MASK 0x3Fu -#define USB_PERID_ID_SHIFT 0 -#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<TRM) -#define VREF_SC_REG(base) ((base)->SC) - -/*! - * @} - */ /* end of group VREF_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- VREF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup VREF_Register_Masks VREF Register Masks - * @{ - */ - -/* TRM Bit Fields */ -#define VREF_TRM_TRIM_MASK 0x3Fu -#define VREF_TRM_TRIM_SHIFT 0 -#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<>> ------------------ -; * -; *****************************************************************************/ - - -__initial_sp EQU 0x20006000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_IRQHandler ;DMA channel 0 transfer complete - DCD DMA1_IRQHandler ;DMA channel 1 transfer complete - DCD DMA2_IRQHandler ;DMA channel 2 transfer complete - DCD DMA3_IRQHandler ;DMA channel 3 transfer complete - DCD Reserved20_IRQHandler ;Reserved interrupt - DCD FTFA_IRQHandler ;Command complete and read collision - DCD PMC_IRQHandler ;Low-voltage detect, low-voltage warning - DCD LLWU_IRQHandler ;Low leakage wakeup - DCD I2C0_IRQHandler ;I2C0 interrupt - DCD I2C1_IRQHandler ;I2C1 interrupt - DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources - DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources - DCD LPUART0_IRQHandler ;LPUART0 status and error - DCD LPUART1_IRQHandler ;LPUART1 status and error - DCD UART2_FLEXIO_IRQHandler ;UART2 or FLEXIO - DCD ADC0_IRQHandler ;ADC0 interrupt - DCD CMP0_IRQHandler ;CMP0 interrupt - DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources - DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources - DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources - DCD RTC_IRQHandler ;RTC alarm - DCD RTC_Seconds_IRQHandler ;RTC seconds - DCD PIT_IRQHandler ;PIT interrupt - DCD I2S0_IRQHandler ;I2S0 interrupt - DCD USB0_IRQHandler ;USB0 interrupt - DCD DAC0_IRQHandler ;DAC0 interrupt - DCD Reserved42_IRQHandler ;Reserved interrupt - DCD Reserved43_IRQHandler ;Reserved interrupt - DCD LPTMR0_IRQHandler ;LPTMR0 interrupt - DCD LCD_IRQHandler ;LCD interrupt - DCD PORTA_IRQHandler ;PORTA Pin detect - DCD PORTCD_IRQHandler ;Single interrupt vector for PORTC; PORTD Pin detect -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -; Flash Configuration -; 16-byte flash configuration field that stores default protection settings (loaded on reset) -; and security information that allows the MCU to restrict access to the FTFL module. -; Backdoor Comparison Key -; Backdoor Comparison Key 0. <0x0-0xFF:2> -; Backdoor Comparison Key 1. <0x0-0xFF:2> -; Backdoor Comparison Key 2. <0x0-0xFF:2> -; Backdoor Comparison Key 3. <0x0-0xFF:2> -; Backdoor Comparison Key 4. <0x0-0xFF:2> -; Backdoor Comparison Key 5. <0x0-0xFF:2> -; Backdoor Comparison Key 6. <0x0-0xFF:2> -; Backdoor Comparison Key 7. <0x0-0xFF:2> -BackDoorK0 EQU 0xFF -BackDoorK1 EQU 0xFF -BackDoorK2 EQU 0xFF -BackDoorK3 EQU 0xFF -BackDoorK4 EQU 0xFF -BackDoorK5 EQU 0xFF -BackDoorK6 EQU 0xFF -BackDoorK7 EQU 0xFF -; -; Program flash protection bytes (FPROT) -; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. -; Each bit protects a 1/32 region of the program flash memory. -; FPROT0 -; Program Flash Region Protect Register 0 -; 1/32 - 8/32 region -; FPROT0.0 -; FPROT0.1 -; FPROT0.2 -; FPROT0.3 -; FPROT0.4 -; FPROT0.5 -; FPROT0.6 -; FPROT0.7 -nFPROT0 EQU 0x00 -FPROT0 EQU nFPROT0:EOR:0xFF -; -; FPROT1 -; Program Flash Region Protect Register 1 -; 9/32 - 16/32 region -; FPROT1.0 -; FPROT1.1 -; FPROT1.2 -; FPROT1.3 -; FPROT1.4 -; FPROT1.5 -; FPROT1.6 -; FPROT1.7 -nFPROT1 EQU 0x00 -FPROT1 EQU nFPROT1:EOR:0xFF -; -; FPROT2 -; Program Flash Region Protect Register 2 -; 17/32 - 24/32 region -; FPROT2.0 -; FPROT2.1 -; FPROT2.2 -; FPROT2.3 -; FPROT2.4 -; FPROT2.5 -; FPROT2.6 -; FPROT2.7 -nFPROT2 EQU 0x00 -FPROT2 EQU nFPROT2:EOR:0xFF -; -; FPROT3 -; Program Flash Region Protect Register 3 -; 25/32 - 32/32 region -; FPROT3.0 -; FPROT3.1 -; FPROT3.2 -; FPROT3.3 -; FPROT3.4 -; FPROT3.5 -; FPROT3.6 -; FPROT3.7 -nFPROT3 EQU 0x00 -FPROT3 EQU nFPROT3:EOR:0xFF -; -; -; Flash nonvolatile option byte (FOPT) -; Allows the user to customize the operation of the MCU at boot time. -; LPBOOT0 -; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. -; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. -; BOOTPIN_OPT -; <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin -; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits -; NMI_DIS -; <0=> NMI interrupts are always blocked -; <1=> NMI_b pin/interrupts reset default to enabled -; RESET_PIN_CFG -; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function -; <1=> RESET_b pin is dedicated -; LPBOOT1 -; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. -; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. -; FAST_INIT -; <0=> Slower initialization -; <1=> Fast Initialization -; BOOTSRC_SEL -; <0=> Boot from Flash -; <2=> Boot from ROM -; <3=> Boot from ROM -; Boot source selection -FOPT EQU 0x3F -; -; Flash security byte (FSEC) -; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", -; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! -; SEC -; <2=> MCU security status is unsecure -; <3=> MCU security status is secure -; Flash Security -; FSLACC -; <2=> Freescale factory access denied -; <3=> Freescale factory access granted -; Freescale Failure Analysis Access Code -; MEEN -; <2=> Mass erase is disabled -; <3=> Mass erase is enabled -; KEYEN -; <2=> Backdoor key access enabled -; <3=> Backdoor key access disabled -; Backdoor Key Security Enable -FSEC EQU 0xFE -; -; - IF :LNOT::DEF:RAM_TARGET - AREA |.ARM.__at_0x400|, DATA, READONLY -__FlashConfig - DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 - DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 - DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 - DCB FSEC , FOPT , 0xFF , 0xFF - ENDIF - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler\ - PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Default_Handler\ - PROC - EXPORT DMA0_IRQHandler [WEAK] - EXPORT DMA1_IRQHandler [WEAK] - EXPORT DMA2_IRQHandler [WEAK] - EXPORT DMA3_IRQHandler [WEAK] - EXPORT Reserved20_IRQHandler [WEAK] - EXPORT FTFA_IRQHandler [WEAK] - EXPORT PMC_IRQHandler [WEAK] - EXPORT LLWU_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT LPUART0_IRQHandler [WEAK] - EXPORT LPUART1_IRQHandler [WEAK] - EXPORT UART2_FLEXIO_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT CMP0_IRQHandler [WEAK] - EXPORT TPM0_IRQHandler [WEAK] - EXPORT TPM1_IRQHandler [WEAK] - EXPORT TPM2_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT RTC_Seconds_IRQHandler [WEAK] - EXPORT PIT_IRQHandler [WEAK] - EXPORT I2S0_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT DAC0_IRQHandler [WEAK] - EXPORT Reserved42_IRQHandler [WEAK] - EXPORT Reserved43_IRQHandler [WEAK] - EXPORT LPTMR0_IRQHandler [WEAK] - EXPORT LCD_IRQHandler [WEAK] - EXPORT PORTA_IRQHandler [WEAK] - EXPORT PORTCD_IRQHandler [WEAK] - EXPORT DefaultISR [WEAK] -DMA0_IRQHandler -DMA1_IRQHandler -DMA2_IRQHandler -DMA3_IRQHandler -Reserved20_IRQHandler -FTFA_IRQHandler -PMC_IRQHandler -LLWU_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -LPUART0_IRQHandler -LPUART1_IRQHandler -UART2_FLEXIO_IRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -TPM0_IRQHandler -TPM1_IRQHandler -TPM2_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT_IRQHandler -I2S0_IRQHandler -USB0_IRQHandler -DAC0_IRQHandler -Reserved42_IRQHandler -Reserved43_IRQHandler -LPTMR0_IRQHandler -LCD_IRQHandler -PORTA_IRQHandler -PORTCD_IRQHandler -DefaultISR - B . - ENDP - ALIGN - - - END diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/sys.cpp deleted file mode 100644 index 2f1024ace8..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/sys.cpp +++ /dev/null @@ -1,31 +0,0 @@ -/* mbed Microcontroller Library - stackheap - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * Setup a fixed single stack/heap memory model, - * between the top of the RW/ZI region and the stackpointer - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -extern char Image$$RW_IRAM1$$ZI$$Limit[]; - -extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { - uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; - uint32_t sp_limit = __current_sp(); - - zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned - - struct __initial_stackheap r; - r.heap_base = zi_limit; - r.heap_limit = sp_limit; - return r; -} - -#ifdef __cplusplus -} -#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/MKL43Z4.ld b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/MKL43Z4.ld deleted file mode 100644 index 80cc231e58..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/MKL43Z4.ld +++ /dev/null @@ -1,163 +0,0 @@ -/* - * KL43Z ARM GCC linker script file - */ - -MEMORY -{ - VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 - FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010 - FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 256K - 0x00000410 - RAM (rwx) : ORIGIN = 0x1FFFE0C0, LENGTH = 32K - 0xC0 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * _reset_init : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .isr_vector : - { - __vector_table = .; - KEEP(*(.vector_table)) - *(.text.Reset_Handler) - *(.text.System_Init) - . = ALIGN(4); - } > VECTORS - - .flash_protect : - { - KEEP(*(.kinetis_flash_config_field)) - . = ALIGN(4); - } > FLASH_PROTECTION - - .text : - { - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/startup_MKL43Z4.s b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/startup_MKL43Z4.s deleted file mode 100644 index 7f1b04ccfe..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/startup_MKL43Z4.s +++ /dev/null @@ -1,243 +0,0 @@ -/* KL43Z startup ARM GCC - * Purpose: startup file for Cortex-M0 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V1.3 - * Date: 10 Nov 2014 - * - * Copyright (c) 2011, ARM Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of the ARM Limited nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - .syntax unified - .arch armv6-m - -/* Memory Model - The HEAP starts at the end of the DATA section and grows upward. - - The STACK starts at the end of the RAM and grows downward. - - The HEAP and stack STACK are only checked at compile time: - (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE - - This is just a check for the bare minimum for the Heap+Stack area before - aborting compilation, it is not the run time limit: - Heap_Size + Stack_Size = 0x200 + 0x400 = 0x600 - */ - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x400 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x200 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .space Heap_Size - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .vector_table,"a",%progbits - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts */ - .long DMA0_IRQHandler /* DMA channel 0 transfer complete interrupt */ - .long DMA1_IRQHandler /* DMA channel 1 transfer complete interrupt */ - .long DMA2_IRQHandler /* DMA channel 2 transfer complete interrupt */ - .long DMA3_IRQHandler /* DMA channel 3 transfer complete interrupt */ - .long Default_Handler /* Reserved interrupt 20 */ - .long FTFA_IRQHandler /* FTFA interrupt */ - .long PMC_IRQHandler /* Low-voltage detect, low-voltage warning*/ - .long LLWU_IRQHandler /* Low leakage wakeup*/ - .long I2C0_IRQHandler /* I2C0 interrupt*/ - .long I2C1_IRQHandler /* I2C1 interrupt*/ - .long SPI0_IRQHandler /* SPI0 single interrupt vector for all sources*/ - .long SPI1_IRQHandler /* SPI1 single interrupt vector for all sources*/ - .long LPUART0_IRQHandler /* LPUART0 status and error*/ - .long LPUART1_IRQHandler /* LPUART1 status and error*/ - .long UART2_FLEXIO_IRQHandler /* UART2 or FLEXIO*/ - .long ADC0_IRQHandler /* ADC0 interrupt*/ - .long CMP0_IRQHandler /* CMP0 interrupt*/ - .long TPM0_IRQHandler /* TPM0 single interrupt vector for all sources*/ - .long TPM1_IRQHandler /* TPM1 single interrupt vector for all sources*/ - .long TPM2_IRQHandler /* TPM2 single interrupt vector for all sources*/ - .long RTC_IRQHandler /* RTC alarm*/ - .long RTC_Seconds_IRQHandler /* RTC seconds*/ - .long PIT_IRQHandler /* PIT interrupt*/ - .long I2S0_IRQHandler /* I2S0 interrupt*/ - .long USB0_IRQHandler /* USB0 interrupt*/ - .long DAC0_IRQHandler /* DAC0 interrupt*/ - .long Reserved42_IRQHandler /* Reserved interrupt*/ - .long Reserved43_IRQHandler /* Reserved interrupt*/ - .long LPTMR0_IRQHandler /* LPTMR0 interrupt*/ - .long LCD_IRQHandler /* LCD interrupt*/ - .long PORTA_IRQHandler /* PORTA Pin detect*/ - .long PORTCD_IRQHandler /* Single interrupt vector for PORTC; PORTD Pin detect*/ - - .size __isr_vector, . - __isr_vector - - /* Reset Handler */ - .section .text.Reset_Handler - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - /* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .Lflash_to_ram_loop_end - - movs r4, 0 -.Lflash_to_ram_loop: - ldr r0, [r1,r4] - str r0, [r2,r4] - adds r4, 4 - cmp r4, r3 - blt .Lflash_to_ram_loop -.Lflash_to_ram_loop_end: - - ldr r0, =SystemInit - blx r0 - ldr r0, =_start - bx r0 - .pool - .size Reset_Handler, . - Reset_Handler - - - .text -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler SVC_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - def_default_handler Default_Handler - - .macro def_irq_default_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_default_handler DMA0_IRQHandler - def_irq_default_handler DMA1_IRQHandler - def_irq_default_handler DMA2_IRQHandler - def_irq_default_handler DMA3_IRQHandler - def_irq_default_handler Reserved20_IRQHandler - def_irq_default_handler FTFA_IRQHandler - def_irq_default_handler PMC_IRQHandler - def_irq_default_handler LLWU_IRQHandler - def_irq_default_handler I2C0_IRQHandler - def_irq_default_handler I2C1_IRQHandler - def_irq_default_handler SPI0_IRQHandler - def_irq_default_handler SPI1_IRQHandler - def_irq_default_handler LPUART0_IRQHandler - def_irq_default_handler LPUART1_IRQHandler - def_irq_default_handler UART2_FLEXIO_IRQHandler - def_irq_default_handler ADC0_IRQHandler - def_irq_default_handler CMP0_IRQHandler - def_irq_default_handler TPM0_IRQHandler - def_irq_default_handler TPM1_IRQHandler - def_irq_default_handler TPM2_IRQHandler - def_irq_default_handler RTC_IRQHandler - def_irq_default_handler RTC_Seconds_IRQHandler - def_irq_default_handler PIT_IRQHandler - def_irq_default_handler I2S0_IRQHandler - def_irq_default_handler USB0_IRQHandler - def_irq_default_handler DAC0_IRQHandler - def_irq_default_handler Reserved42_IRQHandler - def_irq_default_handler Reserved43_IRQHandler - def_irq_default_handler LPTMR0_IRQHandler - def_irq_default_handler LCD_IRQHandler - def_irq_default_handler PORTA_IRQHandler - def_irq_default_handler PORTCD_IRQHandler - def_irq_default_handler DefaultISR - - /* Flash protection region, placed at 0x400 */ - .text - .thumb - .align 2 - .section .kinetis_flash_config_field,"a",%progbits -kinetis_flash_config: - .long 0xFFFFFFFF - .long 0xFFFFFFFF - .long 0xFFFFFFFF - .long 0xFFFF3FFE - - .end diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis.h deleted file mode 100644 index c7bc71154e..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC11U24 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "MKL43Z4.h" -#include "cmsis_nvic.h" - -#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.c deleted file mode 100644 index 8d64306859..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.c +++ /dev/null @@ -1,30 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic for LPC11U24 - * Copyright (c) 2011 ARM Limited. All rights reserved. - * - * CMSIS-style functionality to support dynamic vectors - */ -#include "cmsis_nvic.h" - -#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFE000) // Vectors positioned at start of RAM -#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - uint32_t *vectors = (uint32_t*)SCB->VTOR; - uint32_t i; - - // Copy and switch to dynamic vectors if the first time called - if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { - uint32_t *old_vectors = vectors; - vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; - for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; - } - vectors[IRQn + 16] = vector; -} - -uint32_t NVIC_GetVector(IRQn_Type IRQn) { - uint32_t *vectors = (uint32_t*)SCB->VTOR; - return vectors[IRQn + 16]; -} diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.h deleted file mode 100644 index 6acdca9efd..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.h +++ /dev/null @@ -1,26 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic - * Copyright (c) 2009-2011 ARM Limited. All rights reserved. - * - * CMSIS-style functionality to support dynamic vectors - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals -#define NVIC_USER_IRQ_OFFSET 16 - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); -uint32_t NVIC_GetVector(IRQn_Type IRQn); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.c deleted file mode 100644 index 2d1e6b5fbe..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.c +++ /dev/null @@ -1,224 +0,0 @@ -/* -** ################################################################### -** Processors: MKL43Z256VLH4 -** MKL43Z128VLH4 -** MKL43Z64VLH4 -** MKL43Z256VMP4 -** MKL43Z128VMP4 -** MKL43Z64VMP4 -** -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014 -** Version: rev. 1.4, 2014-09-01 -** Build: b140904 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-03-27) -** Initial version. -** - rev. 1.1 (2014-05-26) -** I2S registers TCR2/RCR2 and others were changed. -** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR. -** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS. -** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS. -** Clock configuration for high range external oscillator has been added. -** RFSYS module access has been added. -** - rev. 1.2 (2014-07-10) -** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE. -** UART0 - UART0 module renamed to UART2. -** I2S - removed MDR register. -** - rev. 1.3 (2014-08-21) -** UART2 - Removed ED register. -** UART2 - Removed MODEM register. -** UART2 - Removed IR register. -** UART2 - Removed PFIFO register. -** UART2 - Removed CFIFO register. -** UART2 - Removed SFIFO register. -** UART2 - Removed TWFIFO register. -** UART2 - Removed TCFIFO register. -** UART2 - Removed RWFIFO register. -** UART2 - Removed RCFIFO register. -** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register. -** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register. -** SIM - Removed bitfield DIEID in SDID register. -** - rev. 1.4 (2014-09-01) -** USB - USB0_CTL0 was renamed to USB0_OTGCTL register. -** USB - USB0_CTL1 was renamed to USB0_CTL register. -** -** ################################################################### -*/ - -/*! - * @file MKL43Z4 - * @version 1.4 - * @date 2014-09-01 - * @brief Device specific configuration file for MKL43Z4 (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "device/fsl_device_registers.h" - - - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -void SystemInit (void) { - -#if (ACK_ISOLATION) - if(PMC->REGSC & PMC_REGSC_ACKISO_MASK) { - PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* VLLSx recovery */ - } -#endif - -#if (DISABLE_WDOG) - /* SIM->COPC: ?=0,COPCLKSEL=0,COPDBGEN=0,COPSTPEN=0,COPT=0,COPCLKS=0,COPW=0 */ - SIM->COPC = (uint32_t)0x00u; -#endif /* (DISABLE_WDOG) */ - - /* Power mode protection initialization */ -#ifdef SMC_PMPROT_VALUE - SMC->PMPROT = SMC_PMPROT_VALUE; -#endif - - /* System clock initialization */ - - /* Set system prescalers and clock sources */ - SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */ - SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */ -#define SOPT2_WRITE_MASK ((SIM_SOPT2_USBSRC_MASK) | (SIM_SOPT2_TPMSRC_MASK) | (SIM_SOPT2_LPUART0SRC_MASK) | (SIM_SOPT2_LPUART1SRC_MASK)) /* define mask of written bits. */ - SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~SOPT2_WRITE_MASK)) | ((SYSTEM_SIM_SOPT2_VALUE) & SOPT2_WRITE_MASK); /* Selects the clock source for the TPM counter clock. */ -#if (MCG_MODE == MCG_MODE_LIRC_2M || MCG_MODE == MCG_MODE_LIRC_8M || MCG_MODE == MCG_MODE_HIRC) - /* Set MCG and OSC0 */ -#if (((OSC0_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) - /* SIM_SCGC5: PORTA=1 */ - SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; - /* PORTA_PCR3: ISF=0,MUX=0 */ - PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); - if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) { - PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); - } -#endif - MCG->SC = MCG_SC_VALUE; /* Set SC (internal reference clock divider) */ - MCG->MC = MCG_MC_VALUE; /* Set MC (high-frequency IRC enable, second LIRC divider) */ - MCG->C1 = MCG_C1_VALUE; /* Set C1 (clock source selection, int. reference enable etc.) */ - MCG->C2 = MCG_C2_VALUE; /* Set C2 (ext. and int. reference clock selection) */ - OSC0->CR = OSC0_CR_VALUE; /* Set OSC0_CR (OSCERCLK enable, oscillator capacitor load) */ - -#else /* MCG_MODE */ - /* Set MCG and OSC0 */ - /* SIM_SCGC5: PORTA=1 */ - SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; - /* PORTA_PCR3: ISF=0,MUX=0 */ - PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); - if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) { - PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); - } - MCG->SC = MCG_SC_VALUE; /* Set SC (internal reference clock divider) */ - MCG->C2 = MCG_C2_VALUE; /* Set C2 (ext. and int. reference clock selection) */ - OSC0->CR = OSC0_CR_VALUE; /* Set OSC0_CR (OSCERCLK enable, oscillator capacitor load) */ - MCG->C1 = MCG_C1_VALUE; /* Set C1 (clock source selection, int. reference enable etc.) */ - MCG->MC = MCG_MC_VALUE; /* Set MC (high-frequency IRC enable, second LIRC divider) */ - if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0U) { - while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */ - } - } -#endif /* MCG_MODE */ - - /* Common for all MCG modes */ - -#if (MCG_MODE == MCG_MODE_HIRC) - while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until high internal reference clock is selected as MCG_Lite output */ - } -#elif (MCG_MODE == MCG_MODE_LIRC_2M || MCG_MODE == MCG_MODE_LIRC_8M) - while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until low internal reference clock is selected as MCG_Lite output */ - } -#elif (MCG_MODE == MCG_MODE_EXT) - while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG_Lite output */ - } -#endif - if (((SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == SMC_PMCTRL_RUNM(0x02U)) { - SMC->PMCTRL = (uint8_t)((SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */ - while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */ - } - } - -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate (void) { - - uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ - uint16_t Divider; - - if ((MCG->S & MCG_S_CLKST_MASK) == 0x00U) { - /* High internal reference clock is selected */ - MCGOUTClock = CPU_INT_FAST_CLK_HZ; /* Fast internal reference clock selected */ - } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x04U) { - /* Internal reference clock is selected */ - Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); - MCGOUTClock = (uint32_t) (CPU_INT_SLOW_CLK_HZ / Divider); /* Slow internal reference clock 8MHz selected */ - } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x08U) { - /* External reference clock is selected */ - MCGOUTClock = CPU_XTAL_CLK_HZ; - } else { - /* Reserved value */ - return; - } /* (!((MCG->S & MCG_S_CLKST_MASK) == 0x08U)) */ - SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); - -} diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.h deleted file mode 100644 index 4b07fde834..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.h +++ /dev/null @@ -1,335 +0,0 @@ -/* -** ################################################################### -** Processors: MKL43Z256VLH4 -** MKL43Z128VLH4 -** MKL43Z64VLH4 -** MKL43Z256VMP4 -** MKL43Z128VMP4 -** MKL43Z64VMP4 -** -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014 -** Version: rev. 1.4, 2014-09-01 -** Build: b140904 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2014-03-27) -** Initial version. -** - rev. 1.1 (2014-05-26) -** I2S registers TCR2/RCR2 and others were changed. -** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR. -** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS. -** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS. -** Clock configuration for high range external oscillator has been added. -** RFSYS module access has been added. -** - rev. 1.2 (2014-07-10) -** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE. -** UART0 - UART0 module renamed to UART2. -** I2S - removed MDR register. -** - rev. 1.3 (2014-08-21) -** UART2 - Removed ED register. -** UART2 - Removed MODEM register. -** UART2 - Removed IR register. -** UART2 - Removed PFIFO register. -** UART2 - Removed CFIFO register. -** UART2 - Removed SFIFO register. -** UART2 - Removed TWFIFO register. -** UART2 - Removed TCFIFO register. -** UART2 - Removed RWFIFO register. -** UART2 - Removed RCFIFO register. -** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register. -** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register. -** SIM - Removed bitfield DIEID in SDID register. -** - rev. 1.4 (2014-09-01) -** USB - USB0_CTL0 was renamed to USB0_OTGCTL register. -** USB - USB0_CTL1 was renamed to USB0_CTL register. -** -** ################################################################### -*/ - -/*! - * @file MKL43Z4 - * @version 1.4 - * @date 2014-09-01 - * @brief Device specific configuration file for MKL43Z4 (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef SYSTEM_MKL43Z4_H_ -#define SYSTEM_MKL43Z4_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - - -#ifndef DISABLE_WDOG - #define DISABLE_WDOG 1 -#endif - -#define ACK_ISOLATION 1 - -#ifndef CLOCK_SETUP - #define CLOCK_SETUP 1 -#endif - -/* MCG_Lite mode constants */ - -#define MCG_MODE_LIRC_8M 0U -#define MCG_MODE_HIRC 1U -#define MCG_MODE_LIRC_2M 2U -#define MCG_MODE_EXT 3U - -/* Predefined clock setups - 0 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 8 MHz (LIRC 8 MHz) mode - Default part configuration. - Core clock/Bus clock derived from the internal clock source 8 MHz - Core clock = 4MHz, BusClock = 2MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB) - 1 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode - Maximum achievable clock frequency configuration using internal clock. - Core clock/Bus clock derived from the internal clock source 48MHz - Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB) - 2 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode - Core clock/Bus clock derived directly from the external crystal 32.768kHz - The clock settings is ready for Very Low Power Run mode. - Core clock = 32.768kHz, BusClock = 32.768kHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB) - 3 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 2 MHz (LIRC 2 MHz) mode - Core clock/Bus clock derived from the internal clock source 2 MHz - The clock settings is ready for Very Low Power Run mode. - Core clock = 2MHz, BusClock = 1MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB) - 4 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode - USB clock setup - for USB to receive internal 48MHz clock derived from HIRC. - Core clock/Bus clock derived from the internal clock source 48MHz - Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from HIRC (MCGPCLK) - 5 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode - Core clock/Bus clock derived directly from the external crystal 8 MHz - Core clock = 8MHz, BusClock = 4MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB) -*/ - -/* Define clock source values */ - -#define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */ -#define CPU_INT_FAST_CLK_HZ 48000000u /* Value of the fast internal oscillator clock frequency in Hz */ -#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */ - -/* Low power mode enable */ -/* SMC_PMPROT: AVLP=1,AVLLS=1 */ -#define SMC_PMPROT_VALUE 0x22u /* SMC_PMPROT */ - -#if (CLOCK_SETUP == 0) - #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */ - #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */ - #define MCG_MODE MCG_MODE_LIRC_8M /* Clock generator mode */ - /* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */ - #define MCG_C1_VALUE 0x42u /* MCG_C1 */ - /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */ - #define MCG_C2_VALUE 0x01u /* MCG_C2 */ - /* MCG_SC: FCRDIV=0 */ - #define MCG_SC_VALUE 0x00u /* MCG_SC */ - /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */ - #define MCG_MC_VALUE 0x00u /* MCG_MC */ - /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define OSC0_CR_VALUE 0x00u /* OSC0_CR */ - /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ - #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */ - /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x10010000u /* SIM_CLKDIV1 */ - /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */ - /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 1) - #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ - #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */ - #define MCG_MODE MCG_MODE_HIRC /* Clock generator mode */ - /* MCG_C1: CLKS=0,IRCLKEN=0,IREFSTEN=0 */ - #define MCG_C1_VALUE 0x00u /* MCG_C1 */ - /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */ - #define MCG_C2_VALUE 0x01u /* MCG_C2 */ - /* MCG_SC: FCRDIV=0 */ - #define MCG_SC_VALUE 0x00u /* MCG_SC */ - /* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */ - #define MCG_MC_VALUE 0x80u /* MCG_MC */ - /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define OSC0_CR_VALUE 0x00u /* OSC0_CR */ - /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ - #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */ - /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */ - /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */ - /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x03000000U /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 2) - #define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */ - #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */ - #define MCG_MODE MCG_MODE_EXT /* Clock generator mode */ - /* MCG_C1: CLKS=2,IRCLKEN=1,IREFSTEN=0 */ - #define MCG_C1_VALUE 0x82u /* MCG_C1 */ - /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=1,IRCS=1 */ - #define MCG_C2_VALUE 0x05u /* MCG_C2 */ - /* MCG_SC: FCRDIV=0 */ - #define MCG_SC_VALUE 0x00u /* MCG_SC */ - /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */ - #define MCG_MC_VALUE 0x00u /* MCG_MC */ - /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define OSC0_CR_VALUE 0x80u /* OSC0_CR */ - /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ - #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */ - /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x00u /* SIM_CLKDIV1 */ - /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */ - /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=2,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x02000000u /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 3) - #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */ - #define CPU_INT_SLOW_CLK_HZ 2000000u /* Value of the slow internal oscillator clock frequency in Hz */ - #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */ - /* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */ - #define MCG_C1_VALUE 0x42u /* MCG_C1 */ - /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=0 */ - #define MCG_C2_VALUE 0x00u /* MCG_C2 */ - /* MCG_SC: FCRDIV=0 */ - #define MCG_SC_VALUE 0x00u /* MCG_SC */ - /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */ - #define MCG_MC_VALUE 0x00u /* MCG_MC */ - /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define OSC0_CR_VALUE 0x00u /* OSC0_CR */ - /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ - #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */ - /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */ - /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */ - /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 4) - #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */ - #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */ - #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */ - /* MCG_C1: CLKS=0,IRCLKEN=1,IREFSTEN=0 */ - #define MCG_C1_VALUE 0x02u /* MCG_C1 */ - /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */ - #define MCG_C2_VALUE 0x01u /* MCG_C2 */ - /* MCG_SC: FCRDIV=0 */ - #define MCG_SC_VALUE 0x00u /* MCG_SC */ - /* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */ - #define MCG_MC_VALUE 0x80u /* MCG_MC */ - /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define OSC0_CR_VALUE 0x00u /* OSC0_CR */ - /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ - #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */ - /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */ - /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */ - /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x03040000u /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 5) - #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */ - #define CPU_INT_SLOW_CLK_HZ 2000000u /* Value of the slow internal oscillator clock frequency in Hz */ - #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */ - /* MCG_C1: CLKS=2,IRCLKEN=0,IREFSTEN=0 */ - #define MCG_C1_VALUE 0x80u /* MCG_C1 */ - /* MCG_C2: RANGE0=1,HGO0=0,EREFS0=1,IRCS=1 */ - #define MCG_C2_VALUE 0x15u /* MCG_C2 */ - /* MCG_SC: FCRDIV=0 */ - #define MCG_SC_VALUE 0x00u /* MCG_SC */ - /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */ - #define MCG_MC_VALUE 0x00u /* MCG_MC */ - /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define OSC0_CR_VALUE 0x80u /* OSC0_CR */ - /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ - #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */ - /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */ - /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */ - /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */ -#else - #error The selected clock setup is not supported. -#endif /* (CLOCK_SETUP == 5) */ - - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* #if !defined(SYSTEM_MKL43Z4_H_) */