From 01e798fd6a440d2ffc08dbf14ff2d526390b9e8d Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Fri, 6 Sep 2019 17:19:42 +0200 Subject: [PATCH] STM32 clock configuration depending on USB --- .../TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c | 6 ++++-- .../TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c | 6 ++++-- .../TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c | 4 ++++ .../TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/system_clock.c | 4 ++++ .../TARGET_STM32F469xI/TARGET_DISCO_F469NI/system_clock.c | 4 ++++ .../TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI/system_clock.c | 7 +++++-- .../TARGET_NUCLEO_H743ZI2/system_clock.c | 7 +++++-- .../TARGET_NUCLEO_L073RZ/device/system_clock.c | 4 ++++ .../TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c | 7 +++++++ .../TARGET_NUCLEO_L433RC_P/system_clock.c | 7 +++++++ .../TARGET_DISCO_L475VG_IOT01A/system_clock.c | 7 +++++++ .../TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_clock.c | 7 +++++++ .../TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c | 7 +++++++ .../TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c | 7 +++++++ .../TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c | 6 ++++++ .../TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c | 6 ++++++ .../TARGET_STM32L4R5xI/TARGET_NUCLEO_L4R5ZI/system_clock.c | 7 +++++++ .../TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/system_clock.c | 7 +++++++ 18 files changed, 102 insertions(+), 8 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c index 259f9afd0b..3d85e811fb 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c @@ -187,6 +187,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } +#if DEVICE_USBDEVICE /* Select PLLSAI output as USB clock source */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.PLLI2S.PLLI2SM = 8; @@ -195,8 +196,8 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); @@ -254,6 +255,7 @@ uint8_t SetSysClock_PLL_HSI(void) return 0; // FAIL } +#if DEVICE_USBDEVICE /* Select PLLI2S output as USB clock source */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.PLLI2S.PLLI2SM = 16; @@ -262,8 +264,8 @@ uint8_t SetSysClock_PLL_HSI(void) PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c index c7f64e5ff2..d57a91fccf 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c @@ -176,14 +176,15 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } +#if DEVICE_USBDEVICE /* Select PLLSAI output as USB clock source */ PeriphClkInitStruct.PLLI2S.PLLI2SM = 8; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); @@ -241,14 +242,15 @@ uint8_t SetSysClock_PLL_HSI(void) return 0; // FAIL } +#if DEVICE_USBDEVICE /* Select PLLI2S output as USB clock source */ PeriphClkInitStruct.PLLI2S.PLLI2SM = 16; PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c index ffac286622..8ec02c6686 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c @@ -172,6 +172,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } +#if DEVICE_USBDEVICE // Select PLLSAI output as USB clock source PeriphClkInitStruct.PLLSAI.PLLSAIM = 8; PeriphClkInitStruct.PLLSAI.PLLSAIN = 384; @@ -179,6 +180,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; @@ -240,6 +242,7 @@ uint8_t SetSysClock_PLL_HSI(void) return 0; // FAIL } +#if DEVICE_USBDEVICE // Select PLLSAI output as USB clock source PeriphClkInitStruct.PLLSAI.PLLSAIM = 8; PeriphClkInitStruct.PLLSAI.PLLSAIN = 192; @@ -247,6 +250,7 @@ uint8_t SetSysClock_PLL_HSI(void) PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/system_clock.c index fbd2f0e304..4df8d0fce6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/system_clock.c @@ -183,6 +183,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } +#if DEVICE_USBDEVICE // Select PLLSAI output as USB clock source PeriphClkInitStruct.PLLSAI.PLLSAIM = 8; PeriphClkInitStruct.PLLSAI.PLLSAIN = 384; @@ -190,6 +191,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); @@ -248,6 +250,7 @@ uint8_t SetSysClock_PLL_HSI(void) return 0; // FAIL } +#if DEVICE_USBDEVICE /* Select PLLSAI output as USB clock source */ PeriphClkInitStruct.PLLSAI.PLLSAIM = 8; PeriphClkInitStruct.PLLSAI.PLLSAIN = 192; @@ -255,6 +258,7 @@ uint8_t SetSysClock_PLL_HSI(void) PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/system_clock.c index b441aa3708..ea0656934b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/system_clock.c @@ -184,12 +184,14 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } +#if DEVICE_USBDEVICE // Select PLLSAI output as USB clock source PeriphClkInitStruct.PLLSAI.PLLSAIN = 192; PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4; PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); @@ -248,12 +250,14 @@ uint8_t SetSysClock_PLL_HSI(void) return 0; // FAIL } +#if DEVICE_USBDEVICE /* Select PLLSAI output as USB clock source */ PeriphClkInitStruct.PLLSAI.PLLSAIN = 192; PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4; PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI/system_clock.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI/system_clock.c index d3d9922434..0c276b767b 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI/system_clock.c @@ -140,13 +140,16 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_USB; - PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; +#if DEVICE_USBDEVICE + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { return 0; // FAIL } + HAL_PWREx_EnableUSBVoltageDetector(); +#endif /* DEVICE_USBDEVICE */ + return 1; // OK } #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/system_clock.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/system_clock.c index c6d77990ac..53e9efa5d0 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/system_clock.c @@ -140,13 +140,16 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_USB; - PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; +#if DEVICE_USBDEVICE + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { return 0; // FAIL } + HAL_PWREx_EnableUSBVoltageDetector(); +#endif /* DEVICE_USBDEVICE */ + return 1; // OK } #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/system_clock.c index 14cdda5ca5..617760c055 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/system_clock.c @@ -177,11 +177,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ /* Output clock on MCO1 pin(PA8) for debugging purpose */ //if (bypass == 0) @@ -234,11 +236,13 @@ uint8_t SetSysClock_PLL_HSI(void) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ /* Output clock on MCO1 pin(PA8) for debugging purpose */ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c index 94946fb792..b4e6e820aa 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c @@ -169,6 +169,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; @@ -181,6 +182,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ // Disable MSI Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; @@ -242,6 +244,7 @@ uint8_t SetSysClock_PLL_HSI(void) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; @@ -254,6 +257,7 @@ uint8_t SetSysClock_PLL_HSI(void) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ // Disable MSI Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; @@ -317,10 +321,13 @@ uint8_t SetSysClock_PLL_MSI(void) HAL_RCCEx_EnableMSIPLLMode(); #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ +#if DEVICE_USBDEVICE /* Select MSI output as USB clock source */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/system_clock.c index 94946fb792..b4e6e820aa 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/system_clock.c @@ -169,6 +169,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; @@ -181,6 +182,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ // Disable MSI Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; @@ -242,6 +244,7 @@ uint8_t SetSysClock_PLL_HSI(void) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; @@ -254,6 +257,7 @@ uint8_t SetSysClock_PLL_HSI(void) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ // Disable MSI Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; @@ -317,10 +321,13 @@ uint8_t SetSysClock_PLL_MSI(void) HAL_RCCEx_EnableMSIPLLMode(); #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ +#if DEVICE_USBDEVICE /* Select MSI output as USB clock source */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_clock.c index 7dac0c38b3..bcb449c1db 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_clock.c @@ -156,6 +156,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; @@ -168,6 +169,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ // Disable MSI Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; @@ -229,6 +231,7 @@ uint8_t SetSysClock_PLL_HSI(void) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; @@ -241,6 +244,7 @@ uint8_t SetSysClock_PLL_HSI(void) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ // Disable MSI Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; @@ -304,10 +308,13 @@ uint8_t SetSysClock_PLL_MSI(void) HAL_RCCEx_EnableMSIPLLMode(); #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ +#if DEVICE_USBDEVICE /* Select MSI output as USB clock source */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_clock.c index 7dac0c38b3..bcb449c1db 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_clock.c @@ -156,6 +156,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; @@ -168,6 +169,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ // Disable MSI Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; @@ -229,6 +231,7 @@ uint8_t SetSysClock_PLL_HSI(void) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; @@ -241,6 +244,7 @@ uint8_t SetSysClock_PLL_HSI(void) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ // Disable MSI Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; @@ -304,10 +308,13 @@ uint8_t SetSysClock_PLL_MSI(void) HAL_RCCEx_EnableMSIPLLMode(); #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ +#if DEVICE_USBDEVICE /* Select MSI output as USB clock source */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c index 7dac0c38b3..bcb449c1db 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c @@ -156,6 +156,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; @@ -168,6 +169,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ // Disable MSI Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; @@ -229,6 +231,7 @@ uint8_t SetSysClock_PLL_HSI(void) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; @@ -241,6 +244,7 @@ uint8_t SetSysClock_PLL_HSI(void) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ // Disable MSI Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; @@ -304,10 +308,13 @@ uint8_t SetSysClock_PLL_MSI(void) HAL_RCCEx_EnableMSIPLLMode(); #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ +#if DEVICE_USBDEVICE /* Select MSI output as USB clock source */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c index 7dac0c38b3..bcb449c1db 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c @@ -156,6 +156,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; @@ -168,6 +169,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ // Disable MSI Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; @@ -229,6 +231,7 @@ uint8_t SetSysClock_PLL_HSI(void) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; @@ -241,6 +244,7 @@ uint8_t SetSysClock_PLL_HSI(void) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ // Disable MSI Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; @@ -304,10 +308,13 @@ uint8_t SetSysClock_PLL_MSI(void) HAL_RCCEx_EnableMSIPLLMode(); #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ +#if DEVICE_USBDEVICE /* Select MSI output as USB clock source */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c index 736a6e4f42..3dd8ece280 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c @@ -156,6 +156,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; @@ -168,6 +169,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ // Disable MSI Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; @@ -236,6 +238,7 @@ uint8_t SetSysClock_PLL_HSI(void) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; @@ -248,6 +251,7 @@ uint8_t SetSysClock_PLL_HSI(void) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ // Disable MSI Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; @@ -317,10 +321,12 @@ uint8_t SetSysClock_PLL_MSI(void) HAL_RCCEx_EnableMSIPLLMode(); #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ +#if DEVICE_USBDEVICE /* Select MSI output as USB clock source */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c index 736a6e4f42..3dd8ece280 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c @@ -156,6 +156,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; @@ -168,6 +169,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ // Disable MSI Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; @@ -236,6 +238,7 @@ uint8_t SetSysClock_PLL_HSI(void) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; @@ -248,6 +251,7 @@ uint8_t SetSysClock_PLL_HSI(void) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ // Disable MSI Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; @@ -317,10 +321,12 @@ uint8_t SetSysClock_PLL_MSI(void) HAL_RCCEx_EnableMSIPLLMode(); #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ +#if DEVICE_USBDEVICE /* Select MSI output as USB clock source */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/TARGET_NUCLEO_L4R5ZI/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/TARGET_NUCLEO_L4R5ZI/system_clock.c index 858fdc309b..9066453856 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/TARGET_NUCLEO_L4R5ZI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/TARGET_NUCLEO_L4R5ZI/system_clock.c @@ -156,6 +156,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; @@ -168,6 +169,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ // Disable MSI Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; @@ -236,6 +238,7 @@ uint8_t SetSysClock_PLL_HSI(void) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; @@ -248,6 +251,7 @@ uint8_t SetSysClock_PLL_HSI(void) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ // Disable MSI Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; @@ -309,10 +313,13 @@ uint8_t SetSysClock_PLL_MSI(void) } /* Enable MSI Auto-calibration through LSE */ HAL_RCCEx_EnableMSIPLLMode(); + +#if DEVICE_USBDEVICE /* Select MSI output as USB clock source */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/system_clock.c index 858fdc309b..9066453856 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/system_clock.c @@ -156,6 +156,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; @@ -168,6 +169,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ // Disable MSI Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; @@ -236,6 +238,7 @@ uint8_t SetSysClock_PLL_HSI(void) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; @@ -248,6 +251,7 @@ uint8_t SetSysClock_PLL_HSI(void) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* DEVICE_USBDEVICE */ // Disable MSI Oscillator RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; @@ -309,10 +313,13 @@ uint8_t SetSysClock_PLL_MSI(void) } /* Enable MSI Auto-calibration through LSE */ HAL_RCCEx_EnableMSIPLLMode(); + +#if DEVICE_USBDEVICE /* Select MSI output as USB clock source */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);