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CMake: Fix NRF52840_DK build failure 

* Remove duplicated ARM toolchain directory
* Link with archived cryptocell 310 libraries instead
  of adding them as source files
* Provide default MBED_BOOT_STACK_SIZE definition
  in scatter file as is done for GCC_ARM linker file
pull/13566/head
Hugues Kamba 2020-08-17 17:36:36 +01:00
parent f856d6b0a3
commit 01ddb7d471
6 changed files with 16 additions and 323 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
connectivity/drivers/mbedtls/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/CMakeLists.txt
View File

@ -9,7 +9,10 @@ function(_mbed_get_libcc_310_ext)
elseif(${MBED_TOOLCHAIN} STREQUAL "IAR")
set(LIBCC_310_EXT TOOLCHAIN_IAR/lib_cc310_ext.a)
endif()
target_sources(mbed-os PRIVATE ${LIBCC_310_EXT})
target_link_libraries(mbed-os
PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/${LIBCC_310_EXT}
)
endfunction()
function(_mbed_get_libcc_310_trng)
@ -20,7 +23,10 @@ function(_mbed_get_libcc_310_trng)
elseif(${MBED_TOOLCHAIN} STREQUAL "IAR")
set(LIBCC_310_TRNG TOOLCHAIN_IAR/lib_cc310_trng.a)
endif()
target_sources(mbed-os PRIVATE ${LIBCC_310_TRNG})
target_link_libraries(mbed-os
PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/${LIBCC_310_TRNG}
)
endfunction()
_mbed_get_libcc_310_ext()

5
connectivity/drivers/mbedtls/FEATURE_CRYPTOCELL310/binaries/CMakeLists.txt
View File

@ -9,7 +9,10 @@ function(_mbed_get_libcc_310_core)
elseif(${MBED_TOOLCHAIN} STREQUAL "IAR")
set(LIBCC_310_CORE TOOLCHAIN_IAR/lib_cc310_ext.a)
endif()
target_sources(mbed-os PRIVATE ${LIBCC_310_CORE})
target_link_libraries(mbed-os
PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/${LIBCC_310_CORE}
)
endfunction()
_mbed_get_libcc_310_core()

4
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/CMakeLists.txt
View File

@ -5,7 +5,7 @@ function(_mbed_get_assembly_nrf52840_dk)
if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_NRF52840.S)
elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
set(STARTUP_FILE TOOLCHAIN_ARM/startup_nrf52840.S)
set(STARTUP_FILE TOOLCHAIN_ARM_STD/startup_nrf52840.S)
elseif(${MBED_TOOLCHAIN} STREQUAL "IAR")
set(STARTUP_FILE TOOLCHAIN_IAR/startup_NRF52840_IAR.S)
endif()
@ -16,7 +16,7 @@ function(_mbed_set_linker_file)
if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
set(LINKER_FILE ${CMAKE_CURRENT_SOURCE_DIR}/TOOLCHAIN_GCC_ARM/NRF52840.ld)
elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
set(LINKER_FILE ${CMAKE_CURRENT_SOURCE_DIR}/TOOLCHAIN_ARM/nRF52840.sct)
set(LINKER_FILE ${CMAKE_CURRENT_SOURCE_DIR}/TOOLCHAIN_ARM_STD/nRF52840.sct)
elseif(${MBED_TOOLCHAIN} STREQUAL "IAR")
set(LINKER_FILE ${CMAKE_CURRENT_SOURCE_DIR}/TOOLCHAIN_IAR/nRF52840.icf)
endif()

49
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM/nRF52840.sct
View File

@ -1,49 +0,0 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
/* Default to no softdevice */
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x0
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x100000
#endif
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#define MBED_RAM_SIZE 0x40000
#endif
#define Stack_Size MBED_BOOT_STACK_SIZE
#define MBED_RAM0_START MBED_RAM_START
#define MBED_RAM0_SIZE 0x100
#define MBED_CRASH_REPORT_RAM_START (MBED_RAM0_START + MBED_RAM0_SIZE)
#define MBED_CRASH_REPORT_RAM_SIZE 0x100
#define MBED_RAM1_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - (MBED_RAM0_SIZE + MBED_CRASH_REPORT_RAM_SIZE))
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+MBED_RAM0_SIZE+MBED_CRASH_REPORT_RAM_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE {
ER_IROM1 MBED_APP_START MBED_APP_SIZE {
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM0 MBED_RAM0_START UNINIT MBED_RAM0_SIZE { ;no init section
*(*nvictable)
}
RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
}
RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE {
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK MBED_RAM1_START+MBED_RAM1_SIZE EMPTY -Stack_Size { ; Stack region growing down
}
}

267
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM/startup_nrf52840.S
View File

@ -1,267 +0,0 @@
;/* Copyright (c) 2012 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemoryManagement_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler
DCD DebugMonitor_Handler
DCD 0 ; Reserved
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD POWER_CLOCK_IRQHandler
DCD RADIO_IRQHandler
DCD UARTE0_UART0_IRQHandler_v
DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v
DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v
DCD NFCT_IRQHandler_v
DCD GPIOTE_IRQHandler_v
DCD SAADC_IRQHandler_v
DCD TIMER0_IRQHandler_v
DCD TIMER1_IRQHandler_v
DCD TIMER2_IRQHandler_v
DCD RTC0_IRQHandler
DCD TEMP_IRQHandler_v
DCD RNG_IRQHandler
DCD ECB_IRQHandler
DCD CCM_AAR_IRQHandler
DCD WDT_IRQHandler_v
DCD RTC1_IRQHandler_v
DCD QDEC_IRQHandler_v
DCD COMP_LPCOMP_IRQHandler_v
DCD SWI0_EGU0_IRQHandler_v
DCD SWI1_EGU1_IRQHandler_v
DCD SWI2_EGU2_IRQHandler_v
DCD SWI3_EGU3_IRQHandler_v
DCD SWI4_EGU4_IRQHandler
DCD SWI5_EGU5_IRQHandler
DCD TIMER3_IRQHandler_v
DCD TIMER4_IRQHandler_v
DCD PWM0_IRQHandler_v
DCD PDM_IRQHandler_v
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD MWU_IRQHandler
DCD PWM1_IRQHandler_v
DCD PWM2_IRQHandler_v
DCD SPIM2_SPIS2_SPI2_IRQHandler_v
DCD RTC2_IRQHandler_v
DCD I2S_IRQHandler_v
DCD FPU_IRQHandler_v
DCD USBD_IRQHandler_v
DCD UARTE1_IRQHandler_v
DCD QSPI_IRQHandler_v
DCD CRYPTOCELL_IRQHandler_v
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PWM3_IRQHandler_v
DCD 0 ; Reserved
DCD SPIM3_IRQHandler_v
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
IMPORT nrf_reloc_vector_table
LDR R0, =SystemInit
BLX R0
LDR R0, =nrf_reloc_vector_table
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemoryManagement_Handler\
PROC
EXPORT MemoryManagement_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMonitor_Handler\
PROC
EXPORT DebugMonitor_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT POWER_CLOCK_IRQHandler [WEAK]
EXPORT RADIO_IRQHandler [WEAK]
EXPORT UARTE0_UART0_IRQHandler_v [WEAK]
EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v [WEAK]
EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v [WEAK]
EXPORT NFCT_IRQHandler_v [WEAK]
EXPORT GPIOTE_IRQHandler_v [WEAK]
EXPORT SAADC_IRQHandler_v [WEAK]
EXPORT TIMER0_IRQHandler_v [WEAK]
EXPORT TIMER1_IRQHandler_v [WEAK]
EXPORT TIMER2_IRQHandler_v [WEAK]
EXPORT RTC0_IRQHandler [WEAK]
EXPORT TEMP_IRQHandler_v [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT ECB_IRQHandler [WEAK]
EXPORT CCM_AAR_IRQHandler [WEAK]
EXPORT WDT_IRQHandler_v [WEAK]
EXPORT RTC1_IRQHandler_v [WEAK]
EXPORT QDEC_IRQHandler_v [WEAK]
EXPORT COMP_LPCOMP_IRQHandler_v [WEAK]
EXPORT SWI0_EGU0_IRQHandler_v [WEAK]
EXPORT SWI1_EGU1_IRQHandler_v [WEAK]
EXPORT SWI2_EGU2_IRQHandler_v [WEAK]
EXPORT SWI3_EGU3_IRQHandler_v [WEAK]
EXPORT SWI4_EGU4_IRQHandler [WEAK]
EXPORT SWI5_EGU5_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler_v [WEAK]
EXPORT TIMER4_IRQHandler_v [WEAK]
EXPORT PWM0_IRQHandler_v [WEAK]
EXPORT PDM_IRQHandler_v [WEAK]
EXPORT MWU_IRQHandler [WEAK]
EXPORT PWM1_IRQHandler_v [WEAK]
EXPORT PWM2_IRQHandler_v [WEAK]
EXPORT SPIM2_SPIS2_SPI2_IRQHandler_v [WEAK]
EXPORT RTC2_IRQHandler_v [WEAK]
EXPORT I2S_IRQHandler_v [WEAK]
EXPORT FPU_IRQHandler_v [WEAK]
EXPORT USBD_IRQHandler_v [WEAK]
EXPORT UARTE1_IRQHandler_v [WEAK]
EXPORT QSPI_IRQHandler_v [WEAK]
EXPORT CRYPTOCELL_IRQHandler_v [WEAK]
EXPORT SPIM3_IRQHandler_v [WEAK]
EXPORT PWM3_IRQHandler_v [WEAK]
POWER_CLOCK_IRQHandler
RADIO_IRQHandler
UARTE0_UART0_IRQHandler_v
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v
NFCT_IRQHandler_v
GPIOTE_IRQHandler_v
SAADC_IRQHandler_v
TIMER0_IRQHandler_v
TIMER1_IRQHandler_v
TIMER2_IRQHandler_v
RTC0_IRQHandler
TEMP_IRQHandler_v
RNG_IRQHandler
ECB_IRQHandler
CCM_AAR_IRQHandler
WDT_IRQHandler_v
RTC1_IRQHandler_v
QDEC_IRQHandler_v
COMP_LPCOMP_IRQHandler_v
SWI0_EGU0_IRQHandler_v
SWI1_EGU1_IRQHandler_v
SWI2_EGU2_IRQHandler_v
SWI3_EGU3_IRQHandler_v
SWI4_EGU4_IRQHandler
SWI5_EGU5_IRQHandler
TIMER3_IRQHandler_v
TIMER4_IRQHandler_v
PWM0_IRQHandler_v
PDM_IRQHandler_v
MWU_IRQHandler
PWM1_IRQHandler_v
PWM2_IRQHandler_v
SPIM2_SPIS2_SPI2_IRQHandler_v
RTC2_IRQHandler_v
I2S_IRQHandler_v
FPU_IRQHandler_v
USBD_IRQHandler_v
UARTE1_IRQHandler_v
QSPI_IRQHandler_v
CRYPTOCELL_IRQHandler_v
PWM3_IRQHandler_v
SPIM3_IRQHandler_v
B .
ENDP
ALIGN
END

4
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52840.sct
View File

@ -50,8 +50,8 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE {
RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE {
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE - RAM_FIXED_SIZE + MBED_RAM_START - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK MBED_RAM1_START+MBED_RAM1_SIZE EMPTY -Stack_Size { ; Stack region growing down
ARM_LIB_STACK MBED_RAM1_START + MBED_RAM1_SIZE EMPTY - Stack_Size { ; Stack region growing down
}
}