[NANO130] Remove dead code

targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PeripheralPins.c

@@ -16,119 +16,6 @@
 
 #include "PeripheralPins.h"
 
-// =====
-// Note: Commented lines are alternative possibilities which are not used per default.
-//       If you change them, you will have also to modify the corresponding xxx_api.c file
-//       for pwmout, analogin, analogout, ...
-// =====
-
-#if 0
-//*** GPIO ***
-const PinMap PinMap_GPIO[] = {
-    // GPIO A MFPL
-    {PA_0, GPIO_A, SYS_GPA_MFPL_PA0MFP_GPIO},
-    {PA_1, GPIO_A, SYS_GPA_MFPL_PA1MFP_GPIO},
-    {PA_2, GPIO_A, SYS_GPA_MFPL_PA2MFP_GPIO},
-    {PA_3, GPIO_A, SYS_GPA_MFPL_PA3MFP_GPIO},
-    {PA_4, GPIO_A, SYS_GPA_MFPL_PA4MFP_GPIO},
-    {PA_5, GPIO_A, SYS_GPA_MFPL_PA5MFP_GPIO},
-    {PA_6, GPIO_A, SYS_GPA_MFPL_PA6MFP_GPIO},
-    {PA_7, GPIO_A, SYS_GPA_MFPL_PA7MFP_GPIO},
-    // GPIO A MFPH
-    {PA_8, GPIO_A, SYS_GPA_MFPH_PA8MFP_GPIO},
-    {PA_9, GPIO_A, SYS_GPA_MFPH_PA9MFP_GPIO},
-    {PA_10, GPIO_A, SYS_GPA_MFPH_PA10MFP_GPIO},
-    {PA_11, GPIO_A, SYS_GPA_MFPH_PA11MFP_GPIO},
-    {PA_12, GPIO_A, SYS_GPA_MFPH_PA12MFP_GPIO},
-    {PA_13, GPIO_A, SYS_GPA_MFPH_PA13MFP_GPIO},
-    {PA_14, GPIO_A, SYS_GPA_MFPH_PA14MFP_GPIO},
-    {PA_15, GPIO_A, SYS_GPA_MFPH_PA15MFP_GPIO},
-    
-    // GPIO B MFPL
-    {PB_0, GPIO_B, SYS_GPB_MFPL_PB0MFP_GPIO},
-    {PB_1, GPIO_B, SYS_GPB_MFPL_PB1MFP_GPIO},
-    {PB_2, GPIO_B, SYS_GPB_MFPL_PB2MFP_GPIO},
-    {PB_3, GPIO_B, SYS_GPB_MFPL_PB3MFP_GPIO},
-    {PB_4, GPIO_B, SYS_GPB_MFPL_PB4MFP_GPIO},
-    {PB_5, GPIO_B, SYS_GPB_MFPL_PB5MFP_GPIO},
-    {PB_6, GPIO_B, SYS_GPB_MFPL_PB6MFP_GPIO},
-    {PB_7, GPIO_B, SYS_GPB_MFPL_PB7MFP_GPIO},
-    // GPIO B MFPH
-    {PB_8, GPIO_B, SYS_GPB_MFPH_PB8MFP_GPIO},
-    {PB_9, GPIO_B, SYS_GPB_MFPH_PB9MFP_GPIO},
-    {PB_10, GPIO_B, SYS_GPB_MFPH_PB10MFP_GPIO},
-    {PB_11, GPIO_B, SYS_GPB_MFPH_PB11MFP_GPIO},
-    {PB_12, GPIO_B, SYS_GPB_MFPH_PB12MFP_GPIO},
-    {PB_13, GPIO_B, SYS_GPB_MFPH_PB13MFP_GPIO},
-    {PB_14, GPIO_B, SYS_GPB_MFPH_PB14MFP_GPIO},
-    {PB_15, GPIO_B, SYS_GPB_MFPH_PB15MFP_GPIO},
-    
-    // GPIO C MFPL
-    {PC_0, GPIO_C, SYS_GPC_MFPL_PC0MFP_GPIO},
-    {PC_1, GPIO_C, SYS_GPC_MFPL_PC1MFP_GPIO},
-    {PC_2, GPIO_C, SYS_GPC_MFPL_PC2MFP_GPIO},
-    {PC_3, GPIO_C, SYS_GPC_MFPL_PC3MFP_GPIO},
-    {PC_4, GPIO_C, SYS_GPC_MFPL_PC4MFP_GPIO},
-    {PC_5, GPIO_C, SYS_GPC_MFPL_PC5MFP_GPIO},
-    {PC_6, GPIO_C, SYS_GPC_MFPL_PC6MFP_GPIO},
-    {PC_7, GPIO_C, SYS_GPC_MFPL_PC7MFP_GPIO},
-    // GPIO C MFPH
-    {PC_8, GPIO_C, SYS_GPC_MFPH_PC8MFP_GPIO},
-    {PC_9, GPIO_C, SYS_GPC_MFPH_PC9MFP_GPIO},
-    {PC_10, GPIO_C, SYS_GPC_MFPH_PC10MFP_GPIO},
-    {PC_11, GPIO_C, SYS_GPC_MFPH_PC11MFP_GPIO},
-    {PC_12, GPIO_C, SYS_GPC_MFPH_PC12MFP_GPIO},
-    {PC_13, GPIO_C, SYS_GPC_MFPH_PC13MFP_GPIO},
-    {PC_14, GPIO_C, SYS_GPC_MFPH_PC14MFP_GPIO},
-    {PC_15, GPIO_C, SYS_GPC_MFPH_PC15MFP_GPIO},
-    
-    // GPIO D MFPL
-    {PD_0, GPIO_D, SYS_GPD_MFPL_PD0MFP_GPIO},
-    {PD_1, GPIO_D, SYS_GPD_MFPL_PD1MFP_GPIO},
-    {PD_2, GPIO_D, SYS_GPD_MFPL_PD2MFP_GPIO},
-    {PD_3, GPIO_D, SYS_GPD_MFPL_PD3MFP_GPIO},
-    {PD_4, GPIO_D, SYS_GPD_MFPL_PD4MFP_GPIO},
-    {PD_5, GPIO_D, SYS_GPD_MFPL_PD5MFP_GPIO},
-    {PD_6, GPIO_D, SYS_GPD_MFPL_PD6MFP_GPIO},
-    {PD_7, GPIO_D, SYS_GPD_MFPL_PD7MFP_GPIO},
-    // GPIO D MFPH
-    {PD_8, GPIO_D, SYS_GPD_MFPH_PD8MFP_GPIO},
-    {PD_9, GPIO_D, SYS_GPD_MFPH_PD9MFP_GPIO},
-    {PD_10, GPIO_D, SYS_GPD_MFPH_PD10MFP_GPIO},
-    {PD_11, GPIO_D, SYS_GPD_MFPH_PD11MFP_GPIO},
-    {PD_12, GPIO_D, SYS_GPD_MFPH_PD12MFP_GPIO},
-    {PD_13, GPIO_D, SYS_GPD_MFPH_PD13MFP_GPIO},
-    {PD_14, GPIO_D, SYS_GPD_MFPH_PD14MFP_GPIO},
-    {PD_15, GPIO_D, SYS_GPD_MFPH_PD15MFP_GPIO},
-    
-    // GPIO E MFPL
-    {PE_0, GPIO_E, SYS_GPE_MFPL_PE0MFP_GPIO},
-    {PE_1, GPIO_E, SYS_GPE_MFPL_PE1MFP_GPIO},
-    {PE_2, GPIO_E, SYS_GPE_MFPL_PE2MFP_GPIO},
-    {PE_3, GPIO_E, SYS_GPE_MFPL_PE3MFP_GPIO},
-    {PE_4, GPIO_E, SYS_GPE_MFPL_PE4MFP_GPIO},
-    {PE_5, GPIO_E, SYS_GPE_MFPL_PE5MFP_GPIO},
-    {PE_6, GPIO_E, SYS_GPE_MFPL_PE6MFP_GPIO},
-    {PE_7, GPIO_E, SYS_GPE_MFPL_PE7MFP_GPIO},
-    // GPIO E MFPH
-    {PE_8, GPIO_E, SYS_GPE_MFPH_PE8MFP_GPIO},
-    {PE_9, GPIO_E, SYS_GPE_MFPH_PE9MFP_GPIO},
-    {PE_10, GPIO_E, SYS_GPE_MFPH_PE10MFP_GPIO},
-    {PE_11, GPIO_E, SYS_GPE_MFPH_PE11MFP_GPIO},
-    {PE_12, GPIO_E, SYS_GPE_MFPH_PE12MFP_GPIO},
-    {PE_13, GPIO_E, SYS_GPE_MFPH_PE13MFP_GPIO},
-    {PE_14, GPIO_E, SYS_GPE_MFPH_PE14MFP_GPIO},
-    
-    // GPIO F MFPL
-    {PF_0, GPIO_F, SYS_GPF_MFPL_PF0MFP_GPIO},
-    {PF_1, GPIO_F, SYS_GPF_MFPL_PF1MFP_GPIO},
-    {PF_2, GPIO_F, SYS_GPF_MFPL_PF2MFP_GPIO},
-    {PF_3, GPIO_F, SYS_GPF_MFPL_PF3MFP_GPIO},
-    {PF_4, GPIO_F, SYS_GPF_MFPL_PF4MFP_GPIO},
-    {PF_5, GPIO_F, SYS_GPF_MFPL_PF5MFP_GPIO},
-};
-#endif
-
 //*** ADC ***
 
 const PinMap PinMap_ADC[] = {

targets/TARGET_NUVOTON/TARGET_NANO100/device/startup_Nano100Series.c

@@ -28,8 +28,6 @@
 void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS)));
 
 #elif defined(__ICCARM__)
-//#define STRINGIFY(x) #x
-//#define _STRINGIFY(x) STRINGIFY(x)
 #define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
 void FUN(void);                         \
 _Pragma(_STRINGIFY(_WEAK_ALIAS_FUNC(FUN, FUN_ALIAS)))
@@ -131,7 +129,6 @@ const uint32_t __vector_handlers[] = {
 #if defined(__CC_ARM)
     (uint32_t) &Image$$ARM_LIB_STACK$$ZI$$Limit,
 #elif defined(__ICCARM__)
-    //(uint32_t) __sfe("CSTACK"),
     (uint32_t) &CSTACK$$Limit,
 #elif defined(__GNUC__)
     (uint32_t) &__StackTop,

targets/TARGET_NUVOTON/TARGET_NANO100/gpio_irq_api.c

@@ -86,7 +86,8 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
     obj->next = NULL;
 
     GPIO_T *gpio_base = NU_PORT_BASE(port_index);
-    //gpio_set(pin);
+    // NOTE: In InterruptIn constructor, gpio_irq_init() is called with gpio_init_in() which is responsible for multi-function pin setting.
+    //       There is no need to call gpio_set() redundantly.
     
     {
 #if MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_ENABLE

targets/TARGET_NUVOTON/TARGET_NANO100/i2c_api.c

@@ -75,8 +75,6 @@ static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync);
 #define NU_I2C_TIMEOUT_STOP         500000
 static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout);
 static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout);
-//static int i2c_is_stat_int(i2c_t *obj);
-//static int i2c_is_stop_det(i2c_t *obj);
 static int i2c_is_trsn_done(i2c_t *obj);
 static int i2c_is_tran_started(i2c_t *obj);
 static int i2c_addr2data(int address, int read);
@@ -551,8 +549,6 @@ static int i2c_is_trsn_done(i2c_t *obj)
     int inten_back;
     
     inten_back = i2c_set_int(obj, 0);
-    // NUC472/M453/M487
-    //i2c_int = !! (i2c_base->CON & I2C_CON_I2C_STS_Msk);
     // NANO130
     i2c_int = !! (i2c_base->INTSTS & I2C_INTSTS_INTSTS_Msk);
     status = I2C_GET_STATUS(i2c_base);
@@ -859,8 +855,6 @@ void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx,
     obj->i2c.event = event;
     i2c_buffer_set(obj, tx, tx_length, rx, rx_length);
 
-    //I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
-    
     obj->i2c.hdlr_async = handler;
     i2c_start(obj);
 }

targets/TARGET_NUVOTON/TARGET_NANO100/pinmap.c

@@ -28,20 +28,10 @@ void pin_function(PinName pin, int data)
     uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
     uint32_t port_index = NU_PINNAME_TO_PORT(pin);
     __IO uint32_t *Px_x_MFP = ((__IO uint32_t *) &SYS->PA_L_MFP) + port_index * 2 + (pin_index / 8);
-    //uint32_t MFP_Pos = NU_MFP_POS(pin_index);
     uint32_t MFP_Msk = NU_MFP_MSK(pin_index);
     
     // E.g.: SYS->PA_L_MFP  = (SYS->PA_L_MFP & (~SYS_PA_L_MFP_PA0_MFP_Msk) ) | SYS_PA_L_MFP_PA0_MFP_SC0_CD  ;
     *Px_x_MFP  = (*Px_x_MFP & (~MFP_Msk)) | data;
-    
-    // [TODO] Disconnect JTAG-DP + SW-DP signals.
-    // Warning: Need to reconnect under reset
-    //if ((pin == PA_13) || (pin == PA_14)) {
-    //
-    //}
-    //if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) {
-    //
-    //}
 }
 
 /**

targets/TARGET_NUVOTON/TARGET_NANO100/pwmout_api.c

@@ -201,8 +201,10 @@ static void pwmout_config(pwmout_t* obj)
     PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
     uint32_t chn = NU_MODSUBINDEX(obj->pwm);
     // NOTE: Support period < 1s
-    //PWM_ConfigOutputChannel(pwm_base, chn, 1000 * 1000 / obj->period_us, obj->pulsewidth_us * 100 / obj->period_us);
+    // NOTE: ARM mbed CI test fails due to first PWM pulse error. Workaround by:
-    // enable inverter to ensure the first PWM cycle is correct
+    //       1. Inverse duty cycle (100 - duty)
+    //       2. Inverse PWM output polarity
+    //       This trick is here to pass ARM mbed CI test. First PWM pulse error still remains.
     PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 100 - (obj->pulsewidth_us * 100 / obj->period_us), obj->period_us);
 }
 

targets/TARGET_NUVOTON/TARGET_NANO100/sleep.c

@@ -57,7 +57,6 @@ void hal_deepsleep(void)
 
 static void mbed_enter_sleep(struct sleep_s *obj)
 {
-#if 0
     // Check if serial allows entering power-down mode
     if (obj->powerdown) {
         obj->powerdown = serial_allow_powerdown();
@@ -75,14 +74,12 @@ static void mbed_enter_sleep(struct sleep_s *obj)
         obj->powerdown = pwmout_allow_powerdown();
     }
     // TODO: Check if other peripherals allow entering power-down mode
-#endif
+
-  
     if (obj->powerdown) {   // Power-down mode (HIRC/HXT disabled, LIRC/LXT enabled)
         SYS_UnlockReg();
         CLK_PowerDown();
         SYS_LockReg();
-    }
+    } else { // CPU halt mode (HIRC/HXT enabled, LIRC/LXT enabled)
-    else {  // CPU halt mode (HIRC/HXT enabled, LIRC/LXT enabled)
         SYS_UnlockReg();
         CLK_Idle();
         SYS_LockReg();
@@ -95,8 +92,6 @@ static void mbed_enter_sleep(struct sleep_s *obj)
 
 static void mbed_exit_sleep(struct sleep_s *obj)
 {
-    // TODO: TO BE CONTINUED
-    
     (void)obj;
 }
 

targets/TARGET_NUVOTON/TARGET_NANO100/spi_api.c

@@ -113,9 +113,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
     uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
     // NOTE:
     // NANO130: Support two-port SPI MOSI/MISO 0/1
-#if 0    
-    obj->spi.spi = (SPIName) pinmap_merge(spi_data, spi_cntl);
-#else
     if (NU_MODBASE(spi_data) == NU_MODBASE(spi_cntl)) {
         // NOTE: spi_data has subindex(port) encoded but spi_cntl hasn't.
         obj->spi.spi = (SPIName) spi_data;
@@ -123,7 +120,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
     else {
         obj->spi.spi = (SPIName) NC;
     }
-#endif
     MBED_ASSERT((int)obj->spi.spi != NC);
 
     const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
@@ -148,10 +144,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
     obj->spi.pin_sclk = sclk;
     obj->spi.pin_ssel = ssel;
 
-    //SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-    // Configure the SPI data format and frequency
-    //spi_format(obj, 8, 0, SPI_MSB); // 8 bits, mode 0
-    //spi_frequency(obj, 1000000);
     
 #if DEVICE_SPI_ASYNCH
     obj->spi.dma_usage = DMA_USAGE_NEVER;
@@ -189,8 +181,6 @@ void spi_free(spi_t *obj)
     // Disable IP clock
     CLK_DisableModuleClock(modinit->clkidx);
     
-    //((struct nu_spi_var *) modinit->var)->obj = NULL;
-    
     // Mark this module to be deinited.
     int i = modinit - spi_modinit_tab;
     spi_modinit_mask &= ~(1 << i);
@@ -280,7 +270,6 @@ int spi_master_write(spi_t *obj, int value)
     // NOTE:
     // NUC472/M453/M487: SPI_CTL.SPIEN is controlled by software (in FIFO mode).
     // NANO130: SPI_CTL.GO_BUSY is controlled by hardware in FIFO mode.
-    //SPI_TRIGGER(spi_base);
     
     // Wait for tx buffer empty
     while(! spi_writeable(obj));
@@ -316,8 +305,6 @@ int spi_slave_receive(spi_t *obj)
     // NOTE:
     // NUC472/M453/M487: SPI_CTL.SPIEN is controlled by software (in FIFO mode).
     // NANO130: SPI_CTL.GO_BUSY is controlled by hardware in FIFO mode.
-    //SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-    //SPI_TRIGGER(spi_base);
     
     return spi_readable(obj);
 };
@@ -329,7 +316,6 @@ int spi_slave_read(spi_t *obj)
     // NOTE:
     // NUC472/M453/M487: SPI_CTL.SPIEN is controlled by software (in FIFO mode).
     // NANO130: SPI_CTL.GO_BUSY is controlled by hardware in FIFO mode.
-    //SPI_TRIGGER(spi_base);
     
     // Wait for rx buffer full
     while (! spi_readable(obj));
@@ -345,7 +331,6 @@ void spi_slave_write(spi_t *obj, int value)
     // NOTE:
     // NUC472/M453/M487: SPI_CTL.SPIEN is controlled by software (in FIFO mode).
     // NANO130: SPI_CTL.GO_BUSY is controlled by hardware in FIFO mode.
-    //SPI_TRIGGER(spi_base);
     
     // Wait for tx buffer empty
     while(! spi_writeable(obj));
@@ -357,7 +342,6 @@ void spi_slave_write(spi_t *obj, int value)
 #if DEVICE_SPI_ASYNCH
 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
 {
-    //MBED_ASSERT(bits >= NU_SPI_FRAME_MIN && bits <= NU_SPI_FRAME_MAX);
     SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
     SPI_SET_DATA_WIDTH(spi_base, bit_width);
 
@@ -383,7 +367,6 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx,
     // NOTE:
     // NUC472/M453/M487: SPI_CTL.SPIEN is controlled by software (in FIFO mode).
     // NANO130: SPI_CTL.GO_BUSY is controlled by hardware in FIFO mode.
-    //SPI_TRIGGER(spi_base);
     
     if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
         // Interrupt way
@@ -413,12 +396,6 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx,
             PDMA_SAR_INC,   // Source address incremental
             NU_MODSUBINDEX(obj->spi.spi) == 0 ? (uint32_t) &spi_base->TX0 : (uint32_t) &spi_base->TX1,  // Destination address
             PDMA_DAR_FIX);  // Destination address fixed
-#if 0   // NOTE:
-        // NANO130: No burst type setting
-        PDMA_SetBurstType(obj->spi.dma_chn_id_tx, 
-            PDMA_REQ_SINGLE,    // Single mode
-            0); // Burst size
-#endif
         PDMA_EnableInt(obj->spi.dma_chn_id_tx,
             PDMA_IER_TD_IE_Msk);    // Interrupt type
         // Register DMA event handler
@@ -441,12 +418,6 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx,
                             // M451: Start of destination address
                             // NANO130: Start of destination address
             PDMA_DAR_INC);  // Destination address incremental
-#if 0   // NOTE:
-        // NANO130: No burst type setting
-        PDMA_SetBurstType(obj->spi.dma_chn_id_rx, 
-            PDMA_REQ_SINGLE,    // Single mode
-            0); // Burst size
-#endif
         PDMA_EnableInt(obj->spi.dma_chn_id_rx,
             PDMA_IER_TD_IE_Msk);    // Interrupt type
         // Register DMA event handler
@@ -483,7 +454,6 @@ void spi_abort_asynch(spi_t *obj)
         if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
             PDMA_DisableInt(obj->spi.dma_chn_id_tx, PDMA_IER_TD_IE_Msk);
             // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called.
-            //PDMA_STOP(obj->spi.dma_chn_id_tx);
             dma_enable(obj->spi.dma_chn_id_tx, 0);
         }
         //SPI_DISABLE_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
@@ -492,7 +462,6 @@ void spi_abort_asynch(spi_t *obj)
         if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
             PDMA_DisableInt(obj->spi.dma_chn_id_rx, PDMA_IER_TD_IE_Msk);
             // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called.
-            //PDMA_STOP(obj->spi.dma_chn_id_rx);
             dma_enable(obj->spi.dma_chn_id_rx, 0);
         }
         //SPI_DISABLE_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
@@ -531,15 +500,6 @@ uint32_t spi_irq_handler_asynch(spi_t *obj)
 uint8_t spi_active(spi_t *obj)
 {
     SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-    /*
-    if ((obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length)
-            || (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) ){
-        return 1;
-    } else  {
-        // interrupts are disabled, all transaction have been completed
-        // TODO: checking rx fifo, it reports data eventhough RFDF is not set
-        return DSPI_HAL_GetIntMode(obj->spi.address, kDspiRxFifoDrainRequest);
-    }*/
     
     return SPI_IS_BUSY(spi_base);
 }
@@ -585,7 +545,6 @@ static void spi_irq(spi_t *obj)
 static int spi_writeable(spi_t * obj)
 {
     // Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive
-    //return (! SPI_GET_TX_FIFO_FULL_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi)))) && (SPI_GET_RX_FIFO_COUNT(((SPI_T *) NU_MODBASE(obj->spi.spi))) < NU_SPI_FIFO_DEPTH);
     return (! SPI_GET_TX_FIFO_FULL_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi))));
 }
 
@@ -631,7 +590,6 @@ static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable, uint32_t mas
     // NOTE:
     // NANO130: SPI_IE_MASK/SPI_STATUS_INTSTS_Msk are for unit transfer IE/EF. Don't get confused.
     if (enable) {
-        //SPI_SET_SUSPEND_CYCLE(spi_base, 4);
         // Enable tx/rx FIFO threshold interrupt
         SPI_EnableInt(spi_base, mask);
     }
@@ -666,16 +624,7 @@ static uint32_t spi_event_check(spi_t *obj)
     // Receive Time-Out
     if (spi_base->STATUS & SPI_STATUS_TIME_OUT_STS_Msk) {
         spi_base->STATUS = SPI_STATUS_TIME_OUT_STS_Msk;
-        //event |= SPI_EVENT_ERROR;
     }
-#if 0   // NOTE:
-        // NANO130: No FIFO Under-RUN IF
-    // Transmit FIFO Under-Run
-    if (spi_base->STATUS & SPI_STATUS_TXUFIF_Msk) {
-        spi_base->STATUS = SPI_STATUS_TXUFIF_Msk;
-        event |= SPI_EVENT_ERROR;
-    }
-#endif
     
     return event;
 }
@@ -835,9 +784,7 @@ static uint8_t spi_get_data_width(spi_t *obj)
 
 static int spi_is_tx_complete(spi_t *obj)
 {
-    // ???: Exclude tx fifo empty check due to no such interrupt on DMA way
     return (obj->tx_buff.pos == obj->tx_buff.length);
-    //return (obj->tx_buff.pos == obj->tx_buff.length && SPI_GET_TX_FIFO_EMPTY_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi))));
 }
 
 static int spi_is_rx_complete(spi_t *obj)