diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/system_clock.c index 0c72d2ab45..79a4bb9dc3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/system_clock.c @@ -1,37 +1,31 @@ /* mbed Microcontroller Library - * Copyright (c) 2016-2020 STMicroelectronics - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Copyright (c) 2015-2021 STMicroelectronics. + * All rights reserved. * - * http://www.apache.org/licenses/LICENSE-2.0 + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + ****************************************************************************** */ /** - * This file configures the system clock as follows: - *============================================================================= - * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI - * | (external 8 MHz clock) | (internal 16 MHz) - * | 2- PLL_HSE_XTAL | or PLL_MSI - * | (external 8 MHz xtal) | (internal 4 MHz) + * This file configures the system clock depending on config from targets.json: *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 48 | 80 + * System clock source | 1- USE_PLL_HSE_EXTC (external clock) + * | 2- USE_PLL_HSE_XTAL (external xtal) + * | 3- USE_PLL_HSI (internal 16 MHz) + * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) *----------------------------------------------------------------------------- - * AHBCLK (MHz) | 48 | 80 - *----------------------------------------------------------------------------- - * APB1CLK (MHz) | 48 | 80 - *----------------------------------------------------------------------------- - * APB2CLK (MHz) | 48 | 80 - *----------------------------------------------------------------------------- - * USB capable (48 MHz precise clock) | YES | NO + * SYSCLK(MHz) | 80 + * AHBCLK (MHz) | 80 + * APB1CLK (MHz) | 80 + * APB2CLK (MHz) | 80 + * USB capable | YES *----------------------------------------------------------------------------- **/ @@ -39,8 +33,8 @@ #include "mbed_error.h" // clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (OSC_IN) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (OSC_IN/OSC_OUT) #define USE_PLL_HSI 0x2 // Use HSI internal clock #define USE_PLL_MSI 0x1 // Use MSI internal clock @@ -62,13 +56,13 @@ uint8_t SetSysClock_PLL_MSI(void); /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). + * @note This function is called in mbed_sdk_init() function (targets/TARGET_STM/mbed_overrides.c) + * and after each deepsleep period in hal_deepsleep() (targets/TARGET_STM/sleep.c) * @param None * @retval None */ -void SetSysClock(void) +MBED_WEAK void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) /* 1- Try to start with HSE and external clock */ @@ -114,31 +108,24 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; - // Used to gain time after DeepSleep in case HSI is used - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { - return 0; - } - - // Select MSI as system clock source to allow modification of the PLL configuration - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); - // Enable HSE oscillator and activate PLL with HSE as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External xtal on OSC_IN/OSC_OUT } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External clock on OSC_IN } - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; +#if HSE_VALUE==8000000 RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) +#else +#error Unsupported externall clock value, check HSE_VALUE define +#endif RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL @@ -146,10 +133,10 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { return 0; // FAIL } @@ -169,12 +156,6 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) } #endif /* DEVICE_USBDEVICE */ - // Disable MSI Oscillator - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.MSIState = RCC_MSI_OFF; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - HAL_RCC_OscConfig(&RCC_OscInitStruct); - // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 2 if (bypass == 0) { @@ -198,23 +179,17 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; - // Select MSI as system clock source to allow modification of the PLL configuration - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); - // Enable HSI oscillator and activate PLL with HSI as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz - RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) + RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } @@ -244,12 +219,6 @@ uint8_t SetSysClock_PLL_HSI(void) } #endif /* DEVICE_USBDEVICE */ - // Disable MSI Oscillator - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.MSIState = RCC_MSI_OFF; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - HAL_RCC_OscConfig(&RCC_OscInitStruct); - // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 3 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz @@ -263,7 +232,7 @@ uint8_t SetSysClock_PLL_HSI(void) /******************************************************************************/ /* PLL (clocked by MSI) used as System clock source */ /******************************************************************************/ -uint8_t SetSysClock_PLL_MSI(void) +MBED_WEAK uint8_t SetSysClock_PLL_MSI(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct = {0}; @@ -273,21 +242,15 @@ uint8_t SetSysClock_PLL_MSI(void) // Enable LSE Oscillator to automatically calibrate the MSI clock RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC32_IN/OSC32_OUT if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } - - /* Enable the CSS interrupt in case LSE signal is corrupted or not present */ - HAL_RCCEx_DisableLSECSS(); #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ /* Enable MSI Oscillator and activate PLL with MSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/system_clock.c index 0c72d2ab45..79a4bb9dc3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/system_clock.c @@ -1,37 +1,31 @@ /* mbed Microcontroller Library - * Copyright (c) 2016-2020 STMicroelectronics - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Copyright (c) 2015-2021 STMicroelectronics. + * All rights reserved. * - * http://www.apache.org/licenses/LICENSE-2.0 + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + ****************************************************************************** */ /** - * This file configures the system clock as follows: - *============================================================================= - * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI - * | (external 8 MHz clock) | (internal 16 MHz) - * | 2- PLL_HSE_XTAL | or PLL_MSI - * | (external 8 MHz xtal) | (internal 4 MHz) + * This file configures the system clock depending on config from targets.json: *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 48 | 80 + * System clock source | 1- USE_PLL_HSE_EXTC (external clock) + * | 2- USE_PLL_HSE_XTAL (external xtal) + * | 3- USE_PLL_HSI (internal 16 MHz) + * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) *----------------------------------------------------------------------------- - * AHBCLK (MHz) | 48 | 80 - *----------------------------------------------------------------------------- - * APB1CLK (MHz) | 48 | 80 - *----------------------------------------------------------------------------- - * APB2CLK (MHz) | 48 | 80 - *----------------------------------------------------------------------------- - * USB capable (48 MHz precise clock) | YES | NO + * SYSCLK(MHz) | 80 + * AHBCLK (MHz) | 80 + * APB1CLK (MHz) | 80 + * APB2CLK (MHz) | 80 + * USB capable | YES *----------------------------------------------------------------------------- **/ @@ -39,8 +33,8 @@ #include "mbed_error.h" // clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (OSC_IN) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (OSC_IN/OSC_OUT) #define USE_PLL_HSI 0x2 // Use HSI internal clock #define USE_PLL_MSI 0x1 // Use MSI internal clock @@ -62,13 +56,13 @@ uint8_t SetSysClock_PLL_MSI(void); /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). + * @note This function is called in mbed_sdk_init() function (targets/TARGET_STM/mbed_overrides.c) + * and after each deepsleep period in hal_deepsleep() (targets/TARGET_STM/sleep.c) * @param None * @retval None */ -void SetSysClock(void) +MBED_WEAK void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) /* 1- Try to start with HSE and external clock */ @@ -114,31 +108,24 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; - // Used to gain time after DeepSleep in case HSI is used - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { - return 0; - } - - // Select MSI as system clock source to allow modification of the PLL configuration - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); - // Enable HSE oscillator and activate PLL with HSE as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External xtal on OSC_IN/OSC_OUT } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External clock on OSC_IN } - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; +#if HSE_VALUE==8000000 RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) +#else +#error Unsupported externall clock value, check HSE_VALUE define +#endif RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL @@ -146,10 +133,10 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { return 0; // FAIL } @@ -169,12 +156,6 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) } #endif /* DEVICE_USBDEVICE */ - // Disable MSI Oscillator - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.MSIState = RCC_MSI_OFF; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - HAL_RCC_OscConfig(&RCC_OscInitStruct); - // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 2 if (bypass == 0) { @@ -198,23 +179,17 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; - // Select MSI as system clock source to allow modification of the PLL configuration - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); - // Enable HSI oscillator and activate PLL with HSI as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz - RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) + RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } @@ -244,12 +219,6 @@ uint8_t SetSysClock_PLL_HSI(void) } #endif /* DEVICE_USBDEVICE */ - // Disable MSI Oscillator - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.MSIState = RCC_MSI_OFF; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - HAL_RCC_OscConfig(&RCC_OscInitStruct); - // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 3 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz @@ -263,7 +232,7 @@ uint8_t SetSysClock_PLL_HSI(void) /******************************************************************************/ /* PLL (clocked by MSI) used as System clock source */ /******************************************************************************/ -uint8_t SetSysClock_PLL_MSI(void) +MBED_WEAK uint8_t SetSysClock_PLL_MSI(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct = {0}; @@ -273,21 +242,15 @@ uint8_t SetSysClock_PLL_MSI(void) // Enable LSE Oscillator to automatically calibrate the MSI clock RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC32_IN/OSC32_OUT if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } - - /* Enable the CSS interrupt in case LSE signal is corrupted or not present */ - HAL_RCCEx_DisableLSECSS(); #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ /* Enable MSI Oscillator and activate PLL with MSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/system_clock.c index 567781b7b0..79a4bb9dc3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/system_clock.c @@ -1,37 +1,31 @@ /* mbed Microcontroller Library - * Copyright (c) 2016-2020 STMicroelectronics - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Copyright (c) 2015-2021 STMicroelectronics. + * All rights reserved. * - * http://www.apache.org/licenses/LICENSE-2.0 + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + ****************************************************************************** */ /** - * This file configures the system clock as follows: - *============================================================================= - * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI - * | (external 8 MHz clock) | (internal 16 MHz) - * | 2- PLL_HSE_XTAL | or PLL_MSI - * | (external 8 MHz xtal) | (internal 4 MHz) + * This file configures the system clock depending on config from targets.json: *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 48 | 80 + * System clock source | 1- USE_PLL_HSE_EXTC (external clock) + * | 2- USE_PLL_HSE_XTAL (external xtal) + * | 3- USE_PLL_HSI (internal 16 MHz) + * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) *----------------------------------------------------------------------------- - * AHBCLK (MHz) | 48 | 80 - *----------------------------------------------------------------------------- - * APB1CLK (MHz) | 48 | 80 - *----------------------------------------------------------------------------- - * APB2CLK (MHz) | 48 | 80 - *----------------------------------------------------------------------------- - * USB capable (48 MHz precise clock) | YES | NO + * SYSCLK(MHz) | 80 + * AHBCLK (MHz) | 80 + * APB1CLK (MHz) | 80 + * APB2CLK (MHz) | 80 + * USB capable | YES *----------------------------------------------------------------------------- **/ @@ -39,8 +33,8 @@ #include "mbed_error.h" // clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (OSC_IN) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (OSC_IN/OSC_OUT) #define USE_PLL_HSI 0x2 // Use HSI internal clock #define USE_PLL_MSI 0x1 // Use MSI internal clock @@ -62,13 +56,13 @@ uint8_t SetSysClock_PLL_MSI(void); /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). + * @note This function is called in mbed_sdk_init() function (targets/TARGET_STM/mbed_overrides.c) + * and after each deepsleep period in hal_deepsleep() (targets/TARGET_STM/sleep.c) * @param None * @retval None */ -void SetSysClock(void) +MBED_WEAK void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) /* 1- Try to start with HSE and external clock */ @@ -114,31 +108,24 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; - // Used to gain time after DeepSleep in case HSI is used - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { - return 0; - } - - // Select MSI as system clock source to allow modification of the PLL configuration - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); - // Enable HSE oscillator and activate PLL with HSE as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External xtal on OSC_IN/OSC_OUT } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External clock on OSC_IN } - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; +#if HSE_VALUE==8000000 RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) +#else +#error Unsupported externall clock value, check HSE_VALUE define +#endif RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL @@ -146,14 +133,15 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; @@ -166,12 +154,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } - - // Disable MSI Oscillator - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.MSIState = RCC_MSI_OFF; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - HAL_RCC_OscConfig(&RCC_OscInitStruct); +#endif /* DEVICE_USBDEVICE */ // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 2 @@ -196,23 +179,17 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; - // Select MSI as system clock source to allow modification of the PLL configuration - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); - // Enable HSI oscillator and activate PLL with HSI as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz - RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) + RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } @@ -227,6 +204,7 @@ uint8_t SetSysClock_PLL_HSI(void) return 0; // FAIL } +#if DEVICE_USBDEVICE RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; @@ -239,12 +217,7 @@ uint8_t SetSysClock_PLL_HSI(void) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } - - // Disable MSI Oscillator - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.MSIState = RCC_MSI_OFF; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - HAL_RCC_OscConfig(&RCC_OscInitStruct); +#endif /* DEVICE_USBDEVICE */ // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 3 @@ -259,7 +232,7 @@ uint8_t SetSysClock_PLL_HSI(void) /******************************************************************************/ /* PLL (clocked by MSI) used as System clock source */ /******************************************************************************/ -uint8_t SetSysClock_PLL_MSI(void) +MBED_WEAK uint8_t SetSysClock_PLL_MSI(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct = {0}; @@ -269,21 +242,15 @@ uint8_t SetSysClock_PLL_MSI(void) // Enable LSE Oscillator to automatically calibrate the MSI clock RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC32_IN/OSC32_OUT if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } - - /* Enable the CSS interrupt in case LSE signal is corrupted or not present */ - HAL_RCCEx_DisableLSECSS(); #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ /* Enable MSI Oscillator and activate PLL with MSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; @@ -302,10 +269,13 @@ uint8_t SetSysClock_PLL_MSI(void) HAL_RCCEx_EnableMSIPLLMode(); #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ +#if DEVICE_USBDEVICE /* Select MSI output as USB clock source */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif /* DEVICE_USBDEVICE */ + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L452xE/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L452xE/system_clock.c index 68368bc21a..79a4bb9dc3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L452xE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L452xE/system_clock.c @@ -1,37 +1,31 @@ /* mbed Microcontroller Library - * Copyright (c) 2016-2020 STMicroelectronics - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Copyright (c) 2015-2021 STMicroelectronics. + * All rights reserved. * - * http://www.apache.org/licenses/LICENSE-2.0 + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + ****************************************************************************** */ /** - * This file configures the system clock as follows: - *============================================================================= - * System clock source s | 1- PLL_HSE_EXTC | 3- PLL_HSI - * | (external 8 MHz clock) | (internal 16 MHz) - * | 2- PLL_HSE_XTAL | or PLL_MSI - * | (external 8 MHz xtal) | (internal 4 MHz) + * This file configures the system clock depending on config from targets.json: *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 48 | 80 + * System clock source | 1- USE_PLL_HSE_EXTC (external clock) + * | 2- USE_PLL_HSE_XTAL (external xtal) + * | 3- USE_PLL_HSI (internal 16 MHz) + * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) *----------------------------------------------------------------------------- - * AHBCLK (MHz) | 48 | 80 - *----------------------------------------------------------------------------- - * APB1CLK (MHz) | 48 | 80 - *----------------------------------------------------------------------------- - * APB2CLK (MHz) | 48 | 80 - *----------------------------------------------------------------------------- - * USB capable (48 MHz precise clock) | YES | NO + * SYSCLK(MHz) | 80 + * AHBCLK (MHz) | 80 + * APB1CLK (MHz) | 80 + * APB2CLK (MHz) | 80 + * USB capable | YES *----------------------------------------------------------------------------- **/ @@ -39,8 +33,8 @@ #include "mbed_error.h" // clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (OSC_IN) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (OSC_IN/OSC_OUT) #define USE_PLL_HSI 0x2 // Use HSI internal clock #define USE_PLL_MSI 0x1 // Use MSI internal clock @@ -62,13 +56,13 @@ uint8_t SetSysClock_PLL_MSI(void); /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). + * @note This function is called in mbed_sdk_init() function (targets/TARGET_STM/mbed_overrides.c) + * and after each deepsleep period in hal_deepsleep() (targets/TARGET_STM/sleep.c) * @param None * @retval None */ -void SetSysClock(void) +MBED_WEAK void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) /* 1- Try to start with HSE and external clock */ @@ -117,17 +111,21 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Enable HSE oscillator and activate PLL with HSE as source RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External xtal on OSC_IN/OSC_OUT } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External clock on OSC_IN } - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; +#if HSE_VALUE==8000000 RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) +#else +#error Unsupported externall clock value, check HSE_VALUE define +#endif RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL @@ -135,10 +133,10 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { return 0; // FAIL } @@ -187,11 +185,11 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz - RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) + RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } @@ -234,7 +232,7 @@ uint8_t SetSysClock_PLL_HSI(void) /******************************************************************************/ /* PLL (clocked by MSI) used as System clock source */ /******************************************************************************/ -uint8_t SetSysClock_PLL_MSI(void) +MBED_WEAK uint8_t SetSysClock_PLL_MSI(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct = {0}; @@ -244,21 +242,15 @@ uint8_t SetSysClock_PLL_MSI(void) // Enable LSE Oscillator to automatically calibrate the MSI clock RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC32_IN/OSC32_OUT if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } - - /* Enable the CSS interrupt in case LSE signal is corrupted or not present */ - HAL_RCCEx_DisableLSECSS(); #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ /* Enable MSI Oscillator and activate PLL with MSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L471xG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L471xG/system_clock.c index a194e6eeb4..79a4bb9dc3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L471xG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L471xG/system_clock.c @@ -1,25 +1,23 @@ /* mbed Microcontroller Library - * Copyright (c) 2016-2020 STMicroelectronics - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Copyright (c) 2015-2021 STMicroelectronics. + * All rights reserved. * - * http://www.apache.org/licenses/LICENSE-2.0 + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + ****************************************************************************** */ /** - * This file configures the system clock as follows: + * This file configures the system clock depending on config from targets.json: *----------------------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) - * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * System clock source | 1- USE_PLL_HSE_EXTC (external clock) + * | 2- USE_PLL_HSE_XTAL (external xtal) * | 3- USE_PLL_HSI (internal 16 MHz) * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) *----------------------------------------------------------------------------- @@ -35,8 +33,8 @@ #include "mbed_error.h" // clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (OSC_IN) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (OSC_IN/OSC_OUT) #define USE_PLL_HSI 0x2 // Use HSI internal clock #define USE_PLL_MSI 0x1 // Use MSI internal clock @@ -58,13 +56,13 @@ uint8_t SetSysClock_PLL_MSI(void); /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). + * @note This function is called in mbed_sdk_init() function (targets/TARGET_STM/mbed_overrides.c) + * and after each deepsleep period in hal_deepsleep() (targets/TARGET_STM/sleep.c) * @param None * @retval None */ -void SetSysClock(void) +MBED_WEAK void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) /* 1- Try to start with HSE and external clock */ @@ -113,17 +111,21 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Enable HSE oscillator and activate PLL with HSE as source RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External xtal on OSC_IN/OSC_OUT } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External clock on OSC_IN } - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; +#if HSE_VALUE==8000000 RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) +#else +#error Unsupported externall clock value, check HSE_VALUE define +#endif RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL @@ -131,10 +133,10 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { return 0; // FAIL } @@ -183,11 +185,11 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz - RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) + RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } @@ -230,7 +232,7 @@ uint8_t SetSysClock_PLL_HSI(void) /******************************************************************************/ /* PLL (clocked by MSI) used as System clock source */ /******************************************************************************/ -uint8_t SetSysClock_PLL_MSI(void) +MBED_WEAK uint8_t SetSysClock_PLL_MSI(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct = {0}; @@ -240,21 +242,15 @@ uint8_t SetSysClock_PLL_MSI(void) // Enable LSE Oscillator to automatically calibrate the MSI clock RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC32_IN/OSC32_OUT if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } - - /* Enable the CSS interrupt in case LSE signal is corrupted or not present */ - HAL_RCCEx_DisableLSECSS(); #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ /* Enable MSI Oscillator and activate PLL with MSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/system_clock.c index a194e6eeb4..79a4bb9dc3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/system_clock.c @@ -1,25 +1,23 @@ /* mbed Microcontroller Library - * Copyright (c) 2016-2020 STMicroelectronics - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Copyright (c) 2015-2021 STMicroelectronics. + * All rights reserved. * - * http://www.apache.org/licenses/LICENSE-2.0 + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + ****************************************************************************** */ /** - * This file configures the system clock as follows: + * This file configures the system clock depending on config from targets.json: *----------------------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) - * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * System clock source | 1- USE_PLL_HSE_EXTC (external clock) + * | 2- USE_PLL_HSE_XTAL (external xtal) * | 3- USE_PLL_HSI (internal 16 MHz) * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) *----------------------------------------------------------------------------- @@ -35,8 +33,8 @@ #include "mbed_error.h" // clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (OSC_IN) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (OSC_IN/OSC_OUT) #define USE_PLL_HSI 0x2 // Use HSI internal clock #define USE_PLL_MSI 0x1 // Use MSI internal clock @@ -58,13 +56,13 @@ uint8_t SetSysClock_PLL_MSI(void); /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). + * @note This function is called in mbed_sdk_init() function (targets/TARGET_STM/mbed_overrides.c) + * and after each deepsleep period in hal_deepsleep() (targets/TARGET_STM/sleep.c) * @param None * @retval None */ -void SetSysClock(void) +MBED_WEAK void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) /* 1- Try to start with HSE and external clock */ @@ -113,17 +111,21 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Enable HSE oscillator and activate PLL with HSE as source RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External xtal on OSC_IN/OSC_OUT } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External clock on OSC_IN } - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; +#if HSE_VALUE==8000000 RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) +#else +#error Unsupported externall clock value, check HSE_VALUE define +#endif RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL @@ -131,10 +133,10 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { return 0; // FAIL } @@ -183,11 +185,11 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz - RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) + RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } @@ -230,7 +232,7 @@ uint8_t SetSysClock_PLL_HSI(void) /******************************************************************************/ /* PLL (clocked by MSI) used as System clock source */ /******************************************************************************/ -uint8_t SetSysClock_PLL_MSI(void) +MBED_WEAK uint8_t SetSysClock_PLL_MSI(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct = {0}; @@ -240,21 +242,15 @@ uint8_t SetSysClock_PLL_MSI(void) // Enable LSE Oscillator to automatically calibrate the MSI clock RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC32_IN/OSC32_OUT if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } - - /* Enable the CSS interrupt in case LSE signal is corrupted or not present */ - HAL_RCCEx_DisableLSECSS(); #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ /* Enable MSI Oscillator and activate PLL with MSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/system_clock.c index a194e6eeb4..79a4bb9dc3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/system_clock.c @@ -1,25 +1,23 @@ /* mbed Microcontroller Library - * Copyright (c) 2016-2020 STMicroelectronics - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Copyright (c) 2015-2021 STMicroelectronics. + * All rights reserved. * - * http://www.apache.org/licenses/LICENSE-2.0 + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + ****************************************************************************** */ /** - * This file configures the system clock as follows: + * This file configures the system clock depending on config from targets.json: *----------------------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) - * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * System clock source | 1- USE_PLL_HSE_EXTC (external clock) + * | 2- USE_PLL_HSE_XTAL (external xtal) * | 3- USE_PLL_HSI (internal 16 MHz) * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) *----------------------------------------------------------------------------- @@ -35,8 +33,8 @@ #include "mbed_error.h" // clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (OSC_IN) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (OSC_IN/OSC_OUT) #define USE_PLL_HSI 0x2 // Use HSI internal clock #define USE_PLL_MSI 0x1 // Use MSI internal clock @@ -58,13 +56,13 @@ uint8_t SetSysClock_PLL_MSI(void); /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). + * @note This function is called in mbed_sdk_init() function (targets/TARGET_STM/mbed_overrides.c) + * and after each deepsleep period in hal_deepsleep() (targets/TARGET_STM/sleep.c) * @param None * @retval None */ -void SetSysClock(void) +MBED_WEAK void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) /* 1- Try to start with HSE and external clock */ @@ -113,17 +111,21 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Enable HSE oscillator and activate PLL with HSE as source RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External xtal on OSC_IN/OSC_OUT } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External clock on OSC_IN } - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; +#if HSE_VALUE==8000000 RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) +#else +#error Unsupported externall clock value, check HSE_VALUE define +#endif RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL @@ -131,10 +133,10 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { return 0; // FAIL } @@ -183,11 +185,11 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz - RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) + RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } @@ -230,7 +232,7 @@ uint8_t SetSysClock_PLL_HSI(void) /******************************************************************************/ /* PLL (clocked by MSI) used as System clock source */ /******************************************************************************/ -uint8_t SetSysClock_PLL_MSI(void) +MBED_WEAK uint8_t SetSysClock_PLL_MSI(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct = {0}; @@ -240,21 +242,15 @@ uint8_t SetSysClock_PLL_MSI(void) // Enable LSE Oscillator to automatically calibrate the MSI clock RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC32_IN/OSC32_OUT if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } - - /* Enable the CSS interrupt in case LSE signal is corrupted or not present */ - HAL_RCCEx_DisableLSECSS(); #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ /* Enable MSI Oscillator and activate PLL with MSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c index a194e6eeb4..79a4bb9dc3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c @@ -1,25 +1,23 @@ /* mbed Microcontroller Library - * Copyright (c) 2016-2020 STMicroelectronics - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Copyright (c) 2015-2021 STMicroelectronics. + * All rights reserved. * - * http://www.apache.org/licenses/LICENSE-2.0 + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + ****************************************************************************** */ /** - * This file configures the system clock as follows: + * This file configures the system clock depending on config from targets.json: *----------------------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) - * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * System clock source | 1- USE_PLL_HSE_EXTC (external clock) + * | 2- USE_PLL_HSE_XTAL (external xtal) * | 3- USE_PLL_HSI (internal 16 MHz) * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) *----------------------------------------------------------------------------- @@ -35,8 +33,8 @@ #include "mbed_error.h" // clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (OSC_IN) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (OSC_IN/OSC_OUT) #define USE_PLL_HSI 0x2 // Use HSI internal clock #define USE_PLL_MSI 0x1 // Use MSI internal clock @@ -58,13 +56,13 @@ uint8_t SetSysClock_PLL_MSI(void); /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). + * @note This function is called in mbed_sdk_init() function (targets/TARGET_STM/mbed_overrides.c) + * and after each deepsleep period in hal_deepsleep() (targets/TARGET_STM/sleep.c) * @param None * @retval None */ -void SetSysClock(void) +MBED_WEAK void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) /* 1- Try to start with HSE and external clock */ @@ -113,17 +111,21 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Enable HSE oscillator and activate PLL with HSE as source RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External xtal on OSC_IN/OSC_OUT } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External clock on OSC_IN } - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; +#if HSE_VALUE==8000000 RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) +#else +#error Unsupported externall clock value, check HSE_VALUE define +#endif RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL @@ -131,10 +133,10 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { return 0; // FAIL } @@ -183,11 +185,11 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz - RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) + RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } @@ -230,7 +232,7 @@ uint8_t SetSysClock_PLL_HSI(void) /******************************************************************************/ /* PLL (clocked by MSI) used as System clock source */ /******************************************************************************/ -uint8_t SetSysClock_PLL_MSI(void) +MBED_WEAK uint8_t SetSysClock_PLL_MSI(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct = {0}; @@ -240,21 +242,15 @@ uint8_t SetSysClock_PLL_MSI(void) // Enable LSE Oscillator to automatically calibrate the MSI clock RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC32_IN/OSC32_OUT if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } - - /* Enable the CSS interrupt in case LSE signal is corrupted or not present */ - HAL_RCCEx_DisableLSECSS(); #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ /* Enable MSI Oscillator and activate PLL with MSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/system_clock.c index e2a239f473..79a4bb9dc3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/system_clock.c @@ -1,25 +1,23 @@ /* mbed Microcontroller Library - * Copyright (c) 2016-2020 STMicroelectronics - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Copyright (c) 2015-2021 STMicroelectronics. + * All rights reserved. * - * http://www.apache.org/licenses/LICENSE-2.0 + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + ****************************************************************************** */ /** - * This file configures the system clock as follows: + * This file configures the system clock depending on config from targets.json: *----------------------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) - * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * System clock source | 1- USE_PLL_HSE_EXTC (external clock) + * | 2- USE_PLL_HSE_XTAL (external xtal) * | 3- USE_PLL_HSI (internal 16 MHz) * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) *----------------------------------------------------------------------------- @@ -35,8 +33,8 @@ #include "mbed_error.h" // clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (OSC_IN) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (OSC_IN/OSC_OUT) #define USE_PLL_HSI 0x2 // Use HSI internal clock #define USE_PLL_MSI 0x1 // Use MSI internal clock @@ -58,13 +56,13 @@ uint8_t SetSysClock_PLL_MSI(void); /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). + * @note This function is called in mbed_sdk_init() function (targets/TARGET_STM/mbed_overrides.c) + * and after each deepsleep period in hal_deepsleep() (targets/TARGET_STM/sleep.c) * @param None * @retval None */ -void SetSysClock(void) +MBED_WEAK void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) /* 1- Try to start with HSE and external clock */ @@ -113,17 +111,21 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Enable HSE oscillator and activate PLL with HSE as source RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External xtal on OSC_IN/OSC_OUT } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External clock on OSC_IN } - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; +#if HSE_VALUE==8000000 RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) +#else +#error Unsupported externall clock value, check HSE_VALUE define +#endif RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL @@ -183,11 +185,11 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz - RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) + RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } @@ -230,7 +232,7 @@ uint8_t SetSysClock_PLL_HSI(void) /******************************************************************************/ /* PLL (clocked by MSI) used as System clock source */ /******************************************************************************/ -uint8_t SetSysClock_PLL_MSI(void) +MBED_WEAK uint8_t SetSysClock_PLL_MSI(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct = {0}; @@ -240,20 +242,15 @@ uint8_t SetSysClock_PLL_MSI(void) // Enable LSE Oscillator to automatically calibrate the MSI clock RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC32_IN/OSC32_OUT if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } - - /* Enable the CSS interrupt in case LSE signal is corrupted or not present */ - HAL_RCCEx_DisableLSECSS(); #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ /* Enable MSI Oscillator and activate PLL with MSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/system_clock.c index 95b9ba8c83..46a6226348 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/system_clock.c @@ -1,25 +1,23 @@ /* mbed Microcontroller Library - * Copyright (c) 2016-2020 STMicroelectronics - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Copyright (c) 2015-2021 STMicroelectronics. + * All rights reserved. * - * http://www.apache.org/licenses/LICENSE-2.0 + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + ****************************************************************************** */ /** - * This file configures the system clock as follows: + * This file configures the system clock depending on config from targets.json: *----------------------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) - * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * System clock source | 1- USE_PLL_HSE_EXTC (external clock) + * | 2- USE_PLL_HSE_XTAL (external xtal) * | 3- USE_PLL_HSI (internal 16 MHz) * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) *----------------------------------------------------------------------------- @@ -35,8 +33,8 @@ #include "mbed_error.h" // clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (OSC_IN) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (OSC_IN/OSC_OUT) #define USE_PLL_HSI 0x2 // Use HSI internal clock #define USE_PLL_MSI 0x1 // Use MSI internal clock @@ -56,12 +54,13 @@ uint8_t SetSysClock_PLL_MSI(void); /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings - * @note This function is called in mbed_sdk_init() and hal_deepsleep() functions + * @note This function is called in mbed_sdk_init() function (targets/TARGET_STM/mbed_overrides.c) + * and after each deepsleep period in hal_deepsleep() (targets/TARGET_STM/sleep.c) * @param None * @retval None */ -void SetSysClock(void) +MBED_WEAK void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) /* 1- Try to start with HSE and external clock */ @@ -102,50 +101,57 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; - // Enable HSE oscillator and activate PLL with HSE as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT - } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN + __HAL_RCC_PWR_CLK_ENABLE(); + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) { + return 0; // FAIL } - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz + + // Enable HSE oscillator and activate PLL with HSE as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External xtal on OSC_IN/OSC_OUT + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External clock on OSC_IN + } +#if DEVICE_USBDEVICE + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; +#else + RCC_OscInitStruct.HSI48State = RCC_HSI48_OFF; +#endif /* DEVICE_USBDEVICE */ + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) +#if HSE_VALUE==8000000 + RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) +#else +#error Unsupported externall clock value, check HSE_VALUE define +#endif RCC_OscInitStruct.PLL.PLLN = 30; // VCO output clock = 240 MHz (8 MHz * 30) RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 120 MHz (240 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 120 MHz if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } +#if DEVICE_USBDEVICE + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkIniRCC_PeriphClkInittStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; /* 48 MHz */ + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } +#endif /* DEVICE_USBDEVICE */ + // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 120 MHz RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 120 MHz RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 120 MHz RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 120 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { return 0; // FAIL } -#if DEVICE_USBDEVICE - RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; - RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; // 96 MHz - RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; // 48 MHz - RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; - if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { - return 0; // FAIL - } -#endif /* DEVICE_USBDEVICE */ - return 1; // OK } #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ @@ -160,46 +166,49 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; + __HAL_RCC_PWR_CLK_ENABLE(); + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) { + return 0; // FAIL + } + // Enable HSI oscillator and activate PLL with HSI as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; +#if DEVICE_USBDEVICE + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; +#else + RCC_OscInitStruct.HSI48State = RCC_HSI48_OFF; +#endif /* DEVICE_USBDEVICE */ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz - RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) - RCC_OscInitStruct.PLL.PLLN = 30; // VCO output clock = 240 MHz (8 MHz * 30) + RCC_OscInitStruct.PLL.PLLM = 4; // 4 MHz + RCC_OscInitStruct.PLL.PLLN = 60; // 240 MHz RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 120 MHz (240 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 120 MHz if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } +#if DEVICE_USBDEVICE + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; /* 48 MHz */ + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } +#endif /* DEVICE_USBDEVICE */ + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 120 MHz RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 120 MHz RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 120 MHz RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 120 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { return 0; // FAIL } -#if DEVICE_USBDEVICE - RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; - RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; - if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { - return 0; // FAIL - } -#endif /* DEVICE_USBDEVICE */ - return 1; // OK } #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ @@ -208,30 +217,30 @@ uint8_t SetSysClock_PLL_HSI(void) /******************************************************************************/ /* PLL (clocked by MSI) used as System clock source */ /******************************************************************************/ -uint8_t SetSysClock_PLL_MSI(void) +MBED_WEAK uint8_t SetSysClock_PLL_MSI(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + __HAL_RCC_PWR_CLK_ENABLE(); + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) { + return 0; // FAIL + } + #if MBED_CONF_TARGET_LSE_AVAILABLE // Enable LSE Oscillator to automatically calibrate the MSI clock RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC32_IN/OSC32_OUT if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } - - /* Enable the CSS interrupt in case LSE signal is corrupted or not present */ - HAL_RCCEx_DisableLSECSS(); #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ /* Enable MSI Oscillator and activate PLL with MSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/system_clock.c index d7928d5d6e..08b200c609 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/system_clock.c @@ -1,25 +1,23 @@ /* mbed Microcontroller Library - * Copyright (c) 2016-2020 STMicroelectronics - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Copyright (c) 2015-2021 STMicroelectronics. + * All rights reserved. * - * http://www.apache.org/licenses/LICENSE-2.0 + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + ****************************************************************************** */ /** - * This file configures the system clock as follows: + * This file configures the system clock depending on config from targets.json: *----------------------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) - * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * System clock source | 1- USE_PLL_HSE_EXTC (external clock) + * | 2- USE_PLL_HSE_XTAL (external xtal) * | 3- USE_PLL_HSI (internal 16 MHz) * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) *----------------------------------------------------------------------------- @@ -35,8 +33,8 @@ #include "mbed_error.h" // clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X2 on board) +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (OSC_IN) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (OSC_IN/OSC_OUT) #define USE_PLL_HSI 0x2 // Use HSI internal clock #define USE_PLL_MSI 0x1 // Use MSI internal clock @@ -56,12 +54,13 @@ uint8_t SetSysClock_PLL_MSI(void); /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings - * @note This function is called in mbed_sdk_init() and hal_deepsleep() functions + * @note This function is called in mbed_sdk_init() function (targets/TARGET_STM/mbed_overrides.c) + * and after each deepsleep period in hal_deepsleep() (targets/TARGET_STM/sleep.c) * @param None * @retval None */ -void SetSysClock(void) +MBED_WEAK void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) /* 1- Try to start with HSE and external clock */ @@ -102,6 +101,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; + __HAL_RCC_PWR_CLK_ENABLE(); if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) { return 0; // FAIL } @@ -109,18 +109,22 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Enable HSE oscillator and activate PLL with HSE as source RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 16 MHz xtal on OSC_IN/OSC_OUT + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External xtal on OSC_IN/OSC_OUT } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 16 MHz clock on OSC_IN + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External clock on OSC_IN } #if DEVICE_USBDEVICE RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; #else RCC_OscInitStruct.HSI48State = RCC_HSI48_OFF; #endif /* DEVICE_USBDEVICE */ - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 16 MHz + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; +#if HSE_VALUE==16000000 RCC_OscInitStruct.PLL.PLLM = 4; // 4 MHz +#else +#error Unsupported externall clock value, check HSE_VALUE define +#endif RCC_OscInitStruct.PLL.PLLN = 60; // 240 MHz RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; @@ -162,6 +166,11 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; + __HAL_RCC_PWR_CLK_ENABLE(); + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) { + return 0; // FAIL + } + // Enable HSI oscillator and activate PLL with HSI as source RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -208,26 +217,30 @@ uint8_t SetSysClock_PLL_HSI(void) /******************************************************************************/ /* PLL (clocked by MSI) used as System clock source */ /******************************************************************************/ -uint8_t SetSysClock_PLL_MSI(void) +MBED_WEAK uint8_t SetSysClock_PLL_MSI(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + __HAL_RCC_PWR_CLK_ENABLE(); + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) { + return 0; // FAIL + } + +#if MBED_CONF_TARGET_LSE_AVAILABLE // Enable LSE Oscillator to automatically calibrate the MSI clock RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { - RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC32_IN/OSC32_OUT + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL } +#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ - HAL_RCCEx_DisableLSECSS(); /* Enable MSI Oscillator and activate PLL with MSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; @@ -240,8 +253,11 @@ uint8_t SetSysClock_PLL_MSI(void) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } + +#if MBED_CONF_TARGET_LSE_AVAILABLE /* Enable MSI Auto-calibration through LSE */ HAL_RCCEx_EnableMSIPLLMode(); +#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ #if DEVICE_USBDEVICE /* Select MSI output as USB clock source */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4S5xI/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4S5xI/system_clock.c index d9d0c93074..46a6226348 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4S5xI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4S5xI/system_clock.c @@ -1,25 +1,23 @@ /* mbed Microcontroller Library - * Copyright (c) 2016-2020 STMicroelectronics - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Copyright (c) 2015-2021 STMicroelectronics. + * All rights reserved. * - * http://www.apache.org/licenses/LICENSE-2.0 + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + ****************************************************************************** */ /** - * This file configures the system clock as follows: + * This file configures the system clock depending on config from targets.json: *----------------------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) - * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * System clock source | 1- USE_PLL_HSE_EXTC (external clock) + * | 2- USE_PLL_HSE_XTAL (external xtal) * | 3- USE_PLL_HSI (internal 16 MHz) * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) *----------------------------------------------------------------------------- @@ -35,8 +33,8 @@ #include "mbed_error.h" // clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (OSC_IN) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (OSC_IN/OSC_OUT) #define USE_PLL_HSI 0x2 // Use HSI internal clock #define USE_PLL_MSI 0x1 // Use MSI internal clock @@ -56,12 +54,13 @@ uint8_t SetSysClock_PLL_MSI(void); /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings - * @note This function is called in mbed_sdk_init() and hal_deepsleep() functions + * @note This function is called in mbed_sdk_init() function (targets/TARGET_STM/mbed_overrides.c) + * and after each deepsleep period in hal_deepsleep() (targets/TARGET_STM/sleep.c) * @param None * @retval None */ -void SetSysClock(void) +MBED_WEAK void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) /* 1- Try to start with HSE and external clock */ @@ -102,54 +101,57 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; + __HAL_RCC_PWR_CLK_ENABLE(); if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) { return 0; // FAIL } // Enable HSE oscillator and activate PLL with HSE as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External xtal on OSC_IN/OSC_OUT } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External clock on OSC_IN } - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz +#if DEVICE_USBDEVICE + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; +#else + RCC_OscInitStruct.HSI48State = RCC_HSI48_OFF; +#endif /* DEVICE_USBDEVICE */ + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) +#if HSE_VALUE==8000000 + RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) +#else +#error Unsupported externall clock value, check HSE_VALUE define +#endif RCC_OscInitStruct.PLL.PLLN = 30; // VCO output clock = 240 MHz (8 MHz * 30) RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 120 MHz (240 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 120 MHz if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } +#if DEVICE_USBDEVICE + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkIniRCC_PeriphClkInittStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; /* 48 MHz */ + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } +#endif /* DEVICE_USBDEVICE */ + // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 120 MHz RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 120 MHz RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 120 MHz RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 120 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { return 0; // FAIL } -#if DEVICE_USBDEVICE - RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; - RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; // 96 MHz - RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; // 48 MHz - RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; - if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { - return 0; // FAIL - } -#endif /* DEVICE_USBDEVICE */ - return 1; // OK } #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ @@ -164,46 +166,49 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; + __HAL_RCC_PWR_CLK_ENABLE(); + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) { + return 0; // FAIL + } + // Enable HSI oscillator and activate PLL with HSI as source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; +#if DEVICE_USBDEVICE + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; +#else + RCC_OscInitStruct.HSI48State = RCC_HSI48_OFF; +#endif /* DEVICE_USBDEVICE */ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz - RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) - RCC_OscInitStruct.PLL.PLLN = 30; // VCO output clock = 240 MHz (8 MHz * 30) + RCC_OscInitStruct.PLL.PLLM = 4; // 4 MHz + RCC_OscInitStruct.PLL.PLLN = 60; // 240 MHz RCC_OscInitStruct.PLL.PLLP = 7; RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 120 MHz (240 MHz / 2) + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 120 MHz if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } +#if DEVICE_USBDEVICE + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; /* 48 MHz */ + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } +#endif /* DEVICE_USBDEVICE */ + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 120 MHz RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 120 MHz RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 120 MHz RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 120 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { return 0; // FAIL } -#if DEVICE_USBDEVICE - RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; - RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; - RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; - if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { - return 0; // FAIL - } -#endif /* DEVICE_USBDEVICE */ - return 1; // OK } #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ @@ -212,26 +217,30 @@ uint8_t SetSysClock_PLL_HSI(void) /******************************************************************************/ /* PLL (clocked by MSI) used as System clock source */ /******************************************************************************/ -uint8_t SetSysClock_PLL_MSI(void) +MBED_WEAK uint8_t SetSysClock_PLL_MSI(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + __HAL_RCC_PWR_CLK_ENABLE(); + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) { + return 0; // FAIL + } + +#if MBED_CONF_TARGET_LSE_AVAILABLE // Enable LSE Oscillator to automatically calibrate the MSI clock RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update - RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { - RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC32_IN/OSC32_OUT + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL } +#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ - HAL_RCCEx_DisableLSECSS(); /* Enable MSI Oscillator and activate PLL with MSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; @@ -244,8 +253,11 @@ uint8_t SetSysClock_PLL_MSI(void) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } + +#if MBED_CONF_TARGET_LSE_AVAILABLE /* Enable MSI Auto-calibration through LSE */ HAL_RCCEx_EnableMSIPLLMode(); +#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ #if DEVICE_USBDEVICE /* Select MSI output as USB clock source */