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{
"name" : "drivers" ,
"config" : {
"uart-serial-txbuf-size" : {
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"help" : "Default TX buffer size for a BufferedSerial instance (unit Bytes))" ,
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"value" : 256
} ,
"uart-serial-rxbuf-size" : {
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"help" : "Default RX buffer size for a BufferedSerial instance (unit Bytes))" ,
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"value" : 256
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} ,
Revise MbedCRC template
* Use compile-time detection of hardware CRC capability, so unneeded
code and tables do not go into the image.
* Add global JSON config option to allow choice between no tables,
16-entry tables or 256-entry tables for software CRC. Default set
to 16-entry, reducing ROM size from previous 256-entry.
* Allow manual override in template parameter to force software or
bitwise CRC for a particular instance.
* Micro-optimisations, particularly use of `RBIT` instruction and
optimising bitwise computation using inline assembler.
Incompatible changes:
* Remove special-case "POLY_32BIT_REV_ANSI" - users can use standard
POLY_32BIT_ANSI, which now uses the same 16-entry tables by default,
or can use hardware acceleration, which was disabled for
POLY_32BIT_REV_ANSI. MbedCRC<POLY_32BIT_ANSI, 32, CrcMode::TABLE> can
be used to force software like POLY_32BIT_REV_ANSI.
* The precomputed table for POLY_16BIT_IBM had errors - this has been
corrected, but software CRC results will be different from the previous
software calculation.
* < 8-bit CRC results are no longer are shifted up in the output value,
but placed in the lowest bits, like other sizes. This means that code
performing the SD command CRC will now need to use `(crc << 1) | 1`,
rather than `crc | 1`.
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"crc-table-size" : {
"macro_name" : "MBED_CRC_TABLE_SIZE" ,
"help" : "Number of entries in each of MbedCRC's pre-computed software tables. Higher values increase speed, but also increase image size. The value has no effect if the target performs the CRC in hardware. Permitted values are 0, 16 or 256." ,
"value" : 16
} ,
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"spi_count_max" : {
"help" : "The maximum number of SPI peripherals used at the same time. Determines RAM allocated for SPI peripheral management. If null, limit determined by hardware." ,
"value" : null
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} ,
"qspi_io0" : {
"help" : "QSPI data I/O 0 pin" ,
"value" : "QSPI_FLASH1_IO0"
} ,
"qspi_io1" : {
"help" : "QSPI data I/O 1 pin" ,
"value" : "QSPI_FLASH1_IO1"
} ,
"qspi_io2" : {
"help" : "QSPI data I/O 2 pin" ,
"value" : "QSPI_FLASH1_IO2"
} ,
"qspi_io3" : {
"help" : "QSPI data I/O 3 pin" ,
"value" : "QSPI_FLASH1_IO3"
} ,
"qspi_sck" : {
"help" : "QSPI clock pin" ,
"value" : "QSPI_FLASH1_SCK"
} ,
"qspi_csn" : {
"help" : "QSPI chip select pin" ,
"value" : "QSPI_FLASH1_CSN"
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} ,
"ospi_io0" : {
"help" : "OSPI data I/O 0 pin" ,
"value" : "OSPI_FLASH1_IO0"
} ,
"ospi_io1" : {
"help" : "OSPI data I/O 1 pin" ,
"value" : "OSPI_FLASH1_IO1"
} ,
"ospi_io2" : {
"help" : "OSPI data I/O 2 pin" ,
"value" : "OSPI_FLASH1_IO2"
} ,
"ospi_io3" : {
"help" : "OSPI data I/O 3 pin" ,
"value" : "OSPI_FLASH1_IO3"
} ,
"ospi_io4" : {
"help" : "OSPI data I/O 4 pin" ,
"value" : "OSPI_FLASH1_IO4"
} ,
"ospi_io5" : {
"help" : "OSPI data I/O 5 pin" ,
"value" : "OSPI_FLASH1_IO5"
} ,
"ospi_io6" : {
"help" : "OSPI data I/O 6 pin" ,
"value" : "OSPI_FLASH1_IO6"
} ,
"ospi_io7" : {
"help" : "OSPI data I/O 7 pin" ,
"value" : "OSPI_FLASH1_IO7"
} ,
"ospi_sck" : {
"help" : "OSPI clock pin" ,
"value" : "OSPI_FLASH1_SCK"
} ,
"ospi_csn" : {
"help" : "OSPI chip select pin" ,
"value" : "OSPI_FLASH1_CSN"
} ,
"ospi_dqs" : {
"help" : "OSPI dqs pin" ,
"value" : "OSPI_FLASH1_DQS"
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}
}
}