mirror of https://github.com/ARMmbed/mbed-os.git
159 lines
4.8 KiB
C
159 lines
4.8 KiB
C
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/**************************************************************************//**
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* @file crc.h
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* @version V1.00
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* $Revision: 2 $
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* $Date: 15/06/10 4:50p $
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* @brief Nano100 series CRC driver header file
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*
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* @note
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* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __CRC_H__
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#define __CRC_H__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
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@{
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*/
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/** @addtogroup NANO100_CRC_Driver CRC Driver
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@{
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*/
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/** @addtogroup NANO100_CRC_EXPORTED_CONSTANTS CRC Exported Constants
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@{
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*/
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/*---------------------------------------------------------------------------------------------------------*/
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/* CRC Polynomial Mode Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define CRC_CCITT 0x00000000UL /*!<CRC Polynomial Mode - CCITT */
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#define CRC_8 0x40000000UL /*!<CRC Polynomial Mode - CRC8 */
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#define CRC_16 0x80000000UL /*!<CRC Polynomial Mode - CRC16 */
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#define CRC_32 0xC0000000UL /*!<CRC Polynomial Mode - CRC32 */
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/*---------------------------------------------------------------------------------------------------------*/
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/* Checksum, Write data Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define CRC_CHECKSUM_COM 0x08000000UL /*!<CRC Checksum Complement */
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#define CRC_CHECKSUM_RVS 0x02000000UL /*!<CRC Checksum Reverse */
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#define CRC_WDATA_COM 0x04000000UL /*!<CRC Write Data Complement */
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#define CRC_WDATA_RVS 0x01000000UL /*!<CRC Write Data Reverse */
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/*---------------------------------------------------------------------------------------------------------*/
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/* CPU Write Data Length Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define CRC_CPU_WDATA_8 0x00000000UL /*!<CRC 8-bit CPU Write Data */
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#define CRC_CPU_WDATA_16 0x10000000UL /*!<CRC 16-bit CPU Write Data */
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#define CRC_CPU_WDATA_32 0x20000000UL /*!<CRC 32-bit CPU Write Data */
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/*@}*/ /* end of group NANO100_CRC_EXPORTED_CONSTANTS */
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/** @addtogroup NANO100_CRC_EXPORTED_FUNCTIONS CRC Exported Functions
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@{
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*/
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/**
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* @brief Enable CRC Interrupt
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*
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* @param[in] u32Mask Interrupt mask
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*
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* @return None
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*
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* @details This macro enable the interrupts.
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*/
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#define CRC_ENABLE_INT(u32Mask) (PDMACRC->DMAIER |= (u32Mask))
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/**
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* @brief Disable CRC Interrupt
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*
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* @param[in] u32Mask Interrupt mask
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*
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* @return None
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*
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* @details This macro disable the interrupts.
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*/
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#define CRC_DISABLE_INT(u32Mask) (PDMACRC->DMAIER &= ~(u32Mask))
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/**
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* @brief Get CRC Interrupt Flag
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*
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* @param[in] None
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*
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* @return Interrupt Flag
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*
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* @details This macro gets the interrupt flag.
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*/
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#define CRC_GET_INT_FLAG() ((uint32_t)(PDMACRC->DMAISR))
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/**
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* @brief Clear CRC Interrupt Flag
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*
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* @param[in] u32Mask Interrupt mask
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*
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* @return None
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*
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* @details This macro clear the interrupt flag.
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*/
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#define CRC_CLR_INT_FLAG(u32Mask) (PDMACRC->DMAISR |= (u32Mask))
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/**
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* @brief Set CRC seed value
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*
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* @param[in] u32Seed Seed value
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*
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* @return None
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*
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* @details This macro set seed value.
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*/
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#define CRC_SET_SEED(u32Seed) { PDMACRC->SEED = (u32Seed); PDMACRC->CTL |= DMA_CRC_CTL_CRC_RST_Msk; }
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/**
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* @brief Get CRC Seed value
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*
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* @param[in] None
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*
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* @return Seed Value
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*
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* @details This macro gets the seed value.
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*/
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#define CRC_GET_SEED() ((uint32_t)(PDMACRC->SEED))
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/**
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* @brief CRC write data
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*
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* @param[in] u32Data write data
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*
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* @return None
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*
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* @details This macro write CRC data.
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*/
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#define CRC_WRITE_DATA(u32Data) (PDMACRC->WDATA = (u32Data))
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/*********************************************************************/
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void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen);
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void CRC_StartDMATransfer(uint32_t u32SrcAddr, uint32_t u32ByteCount);
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uint32_t CRC_GetChecksum(void);
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/*@}*/ /* end of group NANO100_CRC_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group NANO100_CRC_Driver */
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/*@}*/ /* end of group NANO100_Device_Driver */
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#ifdef __cplusplus
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}
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#endif
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#endif //__CRC_H__
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/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
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