mirror of https://github.com/ARMmbed/mbed-os.git
101 lines
2.6 KiB
C
101 lines
2.6 KiB
C
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/**************************************************************************//**
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* @file crc.c
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* @version V1.00
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* $Revision: 3 $
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* $Date: 14/09/29 3:50p $
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* @brief Nano100 series CRC driver source file
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*
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* @note
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* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "Nano100Series.h"
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/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
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@{
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*/
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/** @addtogroup NANO100_CRC_Driver CRC Driver
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@{
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*/
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/** @addtogroup NANO100_CRC_EXPORTED_FUNCTIONS CRC Exported Functions
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@{
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*/
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/**
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* @brief CRC Open
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*
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* @param[in] u32Mode CRC Polynomial Mode \ref CRC_CCITT, \ref CRC_8, \ref CRC_16, \ref CRC_32
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* @param[in] u32Attribute Parameter attribute \ref CRC_CHECKSUM_COM, \ref CRC_CHECKSUM_RVS, \ref CRC_WDATA_COM, \ref CRC_WDATA_RVS
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* @param[in] u32Seed Seed value
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* @param[in] u32DataLen CPU Write Data Length \ref CRC_CPU_WDATA_8, \ref CRC_CPU_WDATA_16, \ref CRC_CPU_WDATA_32
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*
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* @return None
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*
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* @details This function enable the CRC channel.
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*/
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void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen)
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{
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PDMAGCR->GCRCSR |= DMA_GCR_GCRCSR_CRC_CLK_EN_Msk;
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PDMACRC->SEED = u32Seed;
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PDMACRC->CTL = u32Mode | u32Attribute | u32DataLen | DMA_CRC_CTL_CRCCEN_Msk;
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/* When operated in CPU PIO mode, setting RST bit will reload the initial seed value (CRC_SEED register) */
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PDMACRC->CTL |= DMA_CRC_CTL_CRC_RST_Msk;
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}
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/**
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* @brief CRC Start DMA transfer
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*
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* @param[in] u32SrcAddr Source address
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* @param[in] u32ByteCount Calculate byte count
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*
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* @return None
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*
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* @details This function start DMA transfer.
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*/
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void CRC_StartDMATransfer(uint32_t u32SrcAddr, uint32_t u32ByteCount)
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{
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PDMACRC->DMASAR = u32SrcAddr;
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PDMACRC->DMABCR = u32ByteCount;
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PDMACRC->CTL |= DMA_CRC_CTL_TRIG_EN_Msk;
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}
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/**
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* @brief Get CRC Checksum
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*
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* @param[in] None
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*
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* @return Checksum
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*
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* @details This macro get the CRC checksum
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*/
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uint32_t CRC_GetChecksum(void)
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{
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switch (PDMACRC->CTL & DMA_CRC_CTL_CRC_MODE_Msk) {
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case CRC_CCITT:
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case CRC_16:
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return (PDMACRC->CHECKSUM & 0xffff);
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case CRC_32:
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return (PDMACRC->CHECKSUM);
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case CRC_8:
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return (PDMACRC->CHECKSUM & 0xff);
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default:
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return 0;
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}
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}
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/*@}*/ /* end of group NANO100_CRC_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group NANO100_CRC_Driver */
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/*@}*/ /* end of group NANO100_Device_Driver */
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/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
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