mirror of https://github.com/ARMmbed/mbed-os.git
592 lines
18 KiB
C
592 lines
18 KiB
C
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/**************************************************************************//**
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* @file cmsis_iccarm.h
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* @brief CMSIS compiler ICCARM (IAR compiler) header file
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* @version V5.0.3
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* @date 29. August 2017
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******************************************************************************/
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//------------------------------------------------------------------------------
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//
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// Copyright (c) 2017 IAR Systems
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//
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// Licensed under the Apache License, Version 2.0 (the "License")
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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//------------------------------------------------------------------------------
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#ifndef __CMSIS_ICCARM_H__
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#define __CMSIS_ICCARM_H__
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#ifndef __ICCARM__
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#error This file should only be compiled by ICCARM
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#endif
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#pragma system_include
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#define __IAR_FT _Pragma("inline=forced") __intrinsic
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#if (__VER__ >= 8000000)
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#define __ICCARM_V8 1
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#else
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#define __ICCARM_V8 0
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#endif
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#pragma language=extended
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#ifndef __ALIGNED
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#if __ICCARM_V8
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#define __ALIGNED(x) __attribute__((aligned(x)))
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#elif (__VER__ >= 7080000)
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/* Needs IAR language extensions */
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#define __ALIGNED(x) __attribute__((aligned(x)))
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#else
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#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
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#define __ALIGNED(x)
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#endif
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#endif
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/* Define compiler macros for CPU architecture, used in CMSIS 5.
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*/
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#if __ARM_ARCH_7A__
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/* Macro already defined */
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#else
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#if defined(__ARM7A__)
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#define __ARM_ARCH_7A__ 1
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#endif
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#endif
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#ifndef __ASM
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#define __ASM __asm
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#endif
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#ifndef __INLINE
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#define __INLINE inline
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#endif
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#ifndef __NO_RETURN
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#define __NO_RETURN _Pragma("object_attribute=__noreturn")
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#endif
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#ifndef __PACKED
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/* Needs IAR language extensions */
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#if __ICCARM_V8
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#define __PACKED __attribute__((packed, aligned(1)))
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#else
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#define __PACKED __packed
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#endif
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#endif
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#ifndef __PACKED_STRUCT
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/* Needs IAR language extensions */
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#if __ICCARM_V8
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#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
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#else
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#define __PACKED_STRUCT __packed struct
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#endif
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#endif
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#ifndef __PACKED_UNION
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/* Needs IAR language extensions */
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#if __ICCARM_V8
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#define __PACKED_UNION union __attribute__((packed, aligned(1)))
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#else
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#define __PACKED_UNION __packed union
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#endif
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#endif
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#ifndef __RESTRICT
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#define __RESTRICT restrict
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#endif
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#ifndef __STATIC_INLINE
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#define __STATIC_INLINE static inline
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#endif
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#ifndef __STATIC_FORCEINLINE
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#define __STATIC_FORCEINLINE _Pragma("inline=forced") static inline
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#endif
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#ifndef __FORCEINLINE
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#define __FORCEINLINE _Pragma("inline=forced")
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#endif
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#ifndef __UNALIGNED_UINT16_READ
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#pragma language=save
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#pragma language=extended
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__IAR_FT uint16_t __iar_uint16_read(void const *ptr) {
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return *(__packed uint16_t*)(ptr);
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}
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#pragma language=restore
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#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
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#endif
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#ifndef __UNALIGNED_UINT16_WRITE
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#pragma language=save
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#pragma language=extended
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__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) {
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*(__packed uint16_t*)(ptr) = val;;
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}
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#pragma language=restore
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#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
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#endif
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#ifndef __UNALIGNED_UINT32_READ
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#pragma language=save
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#pragma language=extended
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__IAR_FT uint32_t __iar_uint32_read(void const *ptr) {
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return *(__packed uint32_t*)(ptr);
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}
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#pragma language=restore
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#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
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#endif
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#ifndef __UNALIGNED_UINT32_WRITE
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#pragma language=save
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#pragma language=extended
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__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) {
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*(__packed uint32_t*)(ptr) = val;;
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}
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#pragma language=restore
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#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
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#endif
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#if 0
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#ifndef __UNALIGNED_UINT32 /* deprecated */
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#pragma language=save
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#pragma language=extended
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__packed struct __iar_u32 { uint32_t v; };
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#pragma language=restore
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#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
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#endif
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#endif
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#ifndef __USED
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#if __ICCARM_V8
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#define __USED __attribute__((used))
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#else
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#define __USED _Pragma("__root")
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#endif
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#endif
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#ifndef __WEAK
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#if __ICCARM_V8
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#define __WEAK __attribute__((weak))
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#else
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#define __WEAK _Pragma("__weak")
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#endif
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#endif
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#ifndef __ICCARM_INTRINSICS_VERSION__
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#define __ICCARM_INTRINSICS_VERSION__ 0
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#endif
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#if __ICCARM_INTRINSICS_VERSION__ == 2
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#if defined(__CLZ)
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#undef __CLZ
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#endif
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#if defined(__REVSH)
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#undef __REVSH
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#endif
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#if defined(__RBIT)
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#undef __RBIT
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#endif
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#if defined(__SSAT)
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#undef __SSAT
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#endif
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#if defined(__USAT)
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#undef __USAT
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#endif
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#include "iccarm_builtin.h"
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#define __enable_irq __iar_builtin_enable_interrupt
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#define __disable_irq __iar_builtin_disable_interrupt
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#define __enable_fault_irq __iar_builtin_enable_fiq
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#define __disable_fault_irq __iar_builtin_disable_fiq
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#define __arm_rsr __iar_builtin_rsr
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#define __arm_wsr __iar_builtin_wsr
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#if __FPU_PRESENT
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#define __get_FPSCR() (__arm_rsr("FPSCR"))
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#else
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#define __get_FPSCR() ( 0 )
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#endif
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#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", VALUE))
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#define __get_CPSR() (__arm_rsr("CPSR"))
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#define __get_mode() (__get_CPSR() & 0x1FU)
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#define __set_CPSR(VALUE) (__arm_wsr("CPSR", (VALUE)))
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#define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE)))
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#define __get_FPEXC() (__arm_rsr("FPEXC"))
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#define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE))
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#define __get_CP(cp, op1, RT, CRn, CRm, op2) \
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(RT = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2))
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#define __set_CP(cp, op1, RT, CRn, CRm, op2) \
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(__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, RT))
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#include "cmsis_cp15.h"
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#define __NOP __iar_builtin_no_operation
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__IAR_FT uint8_t __CLZ(uint32_t val) {
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return __iar_builtin_CLZ(val);
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}
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#define __CLREX __iar_builtin_CLREX
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#define __DMB __iar_builtin_DMB
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#define __DSB __iar_builtin_DSB
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#define __ISB __iar_builtin_ISB
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#define __LDREXB __iar_builtin_LDREXB
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#define __LDREXH __iar_builtin_LDREXH
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#define __LDREXW __iar_builtin_LDREX
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#define __RBIT __iar_builtin_RBIT
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#define __REV __iar_builtin_REV
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#define __REV16 __iar_builtin_REV16
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__IAR_FT int32_t __REVSH(int32_t val) {
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return __iar_builtin_REVSH((int16_t)val);
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}
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#define __ROR __iar_builtin_ROR
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#define __RRX __iar_builtin_RRX
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#define __SEV __iar_builtin_SEV
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#define __SSAT __iar_builtin_SSAT
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#define __STREXB __iar_builtin_STREXB
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#define __STREXH __iar_builtin_STREXH
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#define __STREXW __iar_builtin_STREX
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#define __USAT __iar_builtin_USAT
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#define __WFE __iar_builtin_WFE
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#define __WFI __iar_builtin_WFI
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#define __SADD8 __iar_builtin_SADD8
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#define __QADD8 __iar_builtin_QADD8
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#define __SHADD8 __iar_builtin_SHADD8
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#define __UADD8 __iar_builtin_UADD8
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#define __UQADD8 __iar_builtin_UQADD8
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#define __UHADD8 __iar_builtin_UHADD8
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#define __SSUB8 __iar_builtin_SSUB8
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#define __QSUB8 __iar_builtin_QSUB8
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#define __SHSUB8 __iar_builtin_SHSUB8
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#define __USUB8 __iar_builtin_USUB8
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#define __UQSUB8 __iar_builtin_UQSUB8
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#define __UHSUB8 __iar_builtin_UHSUB8
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#define __SADD16 __iar_builtin_SADD16
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#define __QADD16 __iar_builtin_QADD16
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#define __SHADD16 __iar_builtin_SHADD16
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#define __UADD16 __iar_builtin_UADD16
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#define __UQADD16 __iar_builtin_UQADD16
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#define __UHADD16 __iar_builtin_UHADD16
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#define __SSUB16 __iar_builtin_SSUB16
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#define __QSUB16 __iar_builtin_QSUB16
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#define __SHSUB16 __iar_builtin_SHSUB16
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#define __USUB16 __iar_builtin_USUB16
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#define __UQSUB16 __iar_builtin_UQSUB16
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#define __UHSUB16 __iar_builtin_UHSUB16
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#define __SASX __iar_builtin_SASX
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#define __QASX __iar_builtin_QASX
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#define __SHASX __iar_builtin_SHASX
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#define __UASX __iar_builtin_UASX
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#define __UQASX __iar_builtin_UQASX
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#define __UHASX __iar_builtin_UHASX
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#define __SSAX __iar_builtin_SSAX
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#define __QSAX __iar_builtin_QSAX
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#define __SHSAX __iar_builtin_SHSAX
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#define __USAX __iar_builtin_USAX
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#define __UQSAX __iar_builtin_UQSAX
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#define __UHSAX __iar_builtin_UHSAX
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#define __USAD8 __iar_builtin_USAD8
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#define __USADA8 __iar_builtin_USADA8
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#define __SSAT16 __iar_builtin_SSAT16
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#define __USAT16 __iar_builtin_USAT16
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#define __UXTB16 __iar_builtin_UXTB16
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#define __UXTAB16 __iar_builtin_UXTAB16
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#define __SXTB16 __iar_builtin_SXTB16
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#define __SXTAB16 __iar_builtin_SXTAB16
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#define __SMUAD __iar_builtin_SMUAD
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#define __SMUADX __iar_builtin_SMUADX
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#define __SMMLA __iar_builtin_SMMLA
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#define __SMLAD __iar_builtin_SMLAD
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#define __SMLADX __iar_builtin_SMLADX
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#define __SMLALD __iar_builtin_SMLALD
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#define __SMLALDX __iar_builtin_SMLALDX
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#define __SMUSD __iar_builtin_SMUSD
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#define __SMUSDX __iar_builtin_SMUSDX
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#define __SMLSD __iar_builtin_SMLSD
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#define __SMLSDX __iar_builtin_SMLSDX
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#define __SMLSLD __iar_builtin_SMLSLD
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#define __SMLSLDX __iar_builtin_SMLSLDX
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#define __SEL __iar_builtin_SEL
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#define __QADD __iar_builtin_QADD
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#define __QSUB __iar_builtin_QSUB
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#define __PKHBT __iar_builtin_PKHBT
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#define __PKHTB __iar_builtin_PKHTB
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#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
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#if !__FPU_PRESENT
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#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
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#endif
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#include <intrinsics.h>
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#if !__FPU_PRESENT
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#define __get_FPSCR() (0)
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#endif
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|
||
|
|
#pragma diag_suppress=Pe940
|
||
|
|
#pragma diag_suppress=Pe177
|
||
|
|
|
||
|
|
#define __enable_irq __enable_interrupt
|
||
|
|
#define __disable_irq __disable_interrupt
|
||
|
|
#define __enable_fault_irq __enable_fiq
|
||
|
|
#define __disable_fault_irq __disable_fiq
|
||
|
|
#define __NOP __no_operation
|
||
|
|
|
||
|
|
#define __get_xPSR __get_PSR
|
||
|
|
|
||
|
|
__IAR_FT void __set_mode(uint32_t mode)
|
||
|
|
{
|
||
|
|
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
|
||
|
|
}
|
||
|
|
|
||
|
|
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) {
|
||
|
|
return __LDREX((unsigned long *)ptr);
|
||
|
|
}
|
||
|
|
|
||
|
|
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) {
|
||
|
|
return __STREX(value, (unsigned long *)ptr);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
__IAR_FT uint32_t __RRX(uint32_t value) {
|
||
|
|
uint32_t result;
|
||
|
|
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
|
||
|
|
return(result);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) {
|
||
|
|
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
|
||
|
|
}
|
||
|
|
|
||
|
|
__IAR_FT uint32_t __get_FPEXC(void)
|
||
|
|
{
|
||
|
|
#if (__FPU_PRESENT == 1)
|
||
|
|
uint32_t result;
|
||
|
|
__ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
|
||
|
|
return(result);
|
||
|
|
#else
|
||
|
|
return(0);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
__IAR_FT void __set_FPEXC(uint32_t fpexc)
|
||
|
|
{
|
||
|
|
#if (__FPU_PRESENT == 1)
|
||
|
|
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) \
|
||
|
|
__ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
|
||
|
|
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) \
|
||
|
|
__ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
|
||
|
|
|
||
|
|
#include "cmsis_cp15.h"
|
||
|
|
|
||
|
|
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||
|
|
|
||
|
|
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
|
||
|
|
|
||
|
|
|
||
|
|
__IAR_FT uint32_t __get_SP_usr(void)
|
||
|
|
{
|
||
|
|
uint32_t cpsr;
|
||
|
|
uint32_t result;
|
||
|
|
__ASM volatile(
|
||
|
|
"MRS %0, cpsr \n"
|
||
|
|
"CPS #0x1F \n" // no effect in USR mode
|
||
|
|
"MOV %1, sp \n"
|
||
|
|
"MSR cpsr_c, %2 \n" // no effect in USR mode
|
||
|
|
"ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
|
||
|
|
);
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
__IAR_FT void __set_SP_usr(uint32_t topOfProcStack)
|
||
|
|
{
|
||
|
|
uint32_t cpsr;
|
||
|
|
__ASM volatile(
|
||
|
|
"MRS %0, cpsr \n"
|
||
|
|
"CPS #0x1F \n" // no effect in USR mode
|
||
|
|
"MOV sp, %1 \n"
|
||
|
|
"MSR cpsr_c, %2 \n" // no effect in USR mode
|
||
|
|
"ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
|
||
|
|
);
|
||
|
|
}
|
||
|
|
|
||
|
|
#define __get_mode() (__get_CPSR() & 0x1FU)
|
||
|
|
|
||
|
|
|
||
|
|
__STATIC_INLINE
|
||
|
|
void __L1C_CleanInvalidateCache(uint32_t op)
|
||
|
|
{
|
||
|
|
__ASM volatile(
|
||
|
|
" PUSH {R4-R11} \n"
|
||
|
|
|
||
|
|
" MRC p15, 1, R6, c0, c0, 1 \n" // Read CLIDR
|
||
|
|
" ANDS R3, R6, #0x07000000 \n" // Extract coherency level
|
||
|
|
" MOV R3, R3, LSR #23 \n" // Total cache levels << 1
|
||
|
|
" BEQ Finished \n" // If 0, no need to clean
|
||
|
|
|
||
|
|
" MOV R10, #0 \n" // R10 holds current cache level << 1
|
||
|
|
"Loop1: ADD R2, R10, R10, LSR #1 \n" // R2 holds cache "Set" position
|
||
|
|
" MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
|
||
|
|
" AND R1, R1, #7 \n" // Isolate those lower 3 bits
|
||
|
|
" CMP R1, #2 \n"
|
||
|
|
" BLT Skip \n" // No cache or only instruction cache at this level
|
||
|
|
|
||
|
|
" MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
|
||
|
|
" ISB \n" // ISB to sync the change to the CacheSizeID reg
|
||
|
|
" MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
|
||
|
|
" AND R2, R1, #7 \n" // Extract the line length field
|
||
|
|
" ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
|
||
|
|
" MOVW R4, #0x3FF \n"
|
||
|
|
" ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
|
||
|
|
" CLZ R5, R4 \n" // R5 is the bit position of the way size increment
|
||
|
|
" MOVW R7, #0x7FFF \n"
|
||
|
|
" ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
|
||
|
|
|
||
|
|
"Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
|
||
|
|
|
||
|
|
"Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
|
||
|
|
" ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
|
||
|
|
" CMP R0, #0 \n"
|
||
|
|
" BNE Dccsw \n"
|
||
|
|
" MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
|
||
|
|
" B cont \n"
|
||
|
|
"Dccsw: CMP R0, #1 \n"
|
||
|
|
" BNE Dccisw \n"
|
||
|
|
" MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
|
||
|
|
" B cont \n"
|
||
|
|
"Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW. Clean and Invalidate by Set/Way
|
||
|
|
"cont: SUBS R9, R9, #1 \n" // Decrement the Way number
|
||
|
|
" BGE Loop3 \n"
|
||
|
|
" SUBS R7, R7, #1 \n" // Decrement the Set number
|
||
|
|
" BGE Loop2 \n"
|
||
|
|
"Skip: ADD R10, R10, #2 \n" // Increment the cache number
|
||
|
|
" CMP R3, R10 \n"
|
||
|
|
" BGT Loop1 \n"
|
||
|
|
|
||
|
|
"Finished: \n"
|
||
|
|
" DSB \n"
|
||
|
|
" POP {R4-R11} "
|
||
|
|
);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
__STATIC_INLINE
|
||
|
|
void __FPU_Enable(void)
|
||
|
|
{
|
||
|
|
__ASM volatile(
|
||
|
|
//Permit access to VFP/NEON, registers by modifying CPACR
|
||
|
|
" MRC p15,0,R1,c1,c0,2 \n"
|
||
|
|
" ORR R1,R1,#0x00F00000 \n"
|
||
|
|
" MCR p15,0,R1,c1,c0,2 \n"
|
||
|
|
|
||
|
|
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
|
||
|
|
" ISB \n"
|
||
|
|
|
||
|
|
//Enable VFP/NEON
|
||
|
|
" VMRS R1,FPEXC \n"
|
||
|
|
" ORR R1,R1,#0x40000000 \n"
|
||
|
|
" VMSR FPEXC,R1 \n"
|
||
|
|
|
||
|
|
//Initialise VFP/NEON registers to 0
|
||
|
|
" MOV R2,#0 \n"
|
||
|
|
|
||
|
|
#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT >= 16
|
||
|
|
//Initialise D16 registers to 0
|
||
|
|
" VMOV D0, R2,R2 \n"
|
||
|
|
" VMOV D1, R2,R2 \n"
|
||
|
|
" VMOV D2, R2,R2 \n"
|
||
|
|
" VMOV D3, R2,R2 \n"
|
||
|
|
" VMOV D4, R2,R2 \n"
|
||
|
|
" VMOV D5, R2,R2 \n"
|
||
|
|
" VMOV D6, R2,R2 \n"
|
||
|
|
" VMOV D7, R2,R2 \n"
|
||
|
|
" VMOV D8, R2,R2 \n"
|
||
|
|
" VMOV D9, R2,R2 \n"
|
||
|
|
" VMOV D10,R2,R2 \n"
|
||
|
|
" VMOV D11,R2,R2 \n"
|
||
|
|
" VMOV D12,R2,R2 \n"
|
||
|
|
" VMOV D13,R2,R2 \n"
|
||
|
|
" VMOV D14,R2,R2 \n"
|
||
|
|
" VMOV D15,R2,R2 \n"
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32
|
||
|
|
//Initialise D32 registers to 0
|
||
|
|
" VMOV D16,R2,R2 \n"
|
||
|
|
" VMOV D17,R2,R2 \n"
|
||
|
|
" VMOV D18,R2,R2 \n"
|
||
|
|
" VMOV D19,R2,R2 \n"
|
||
|
|
" VMOV D20,R2,R2 \n"
|
||
|
|
" VMOV D21,R2,R2 \n"
|
||
|
|
" VMOV D22,R2,R2 \n"
|
||
|
|
" VMOV D23,R2,R2 \n"
|
||
|
|
" VMOV D24,R2,R2 \n"
|
||
|
|
" VMOV D25,R2,R2 \n"
|
||
|
|
" VMOV D26,R2,R2 \n"
|
||
|
|
" VMOV D27,R2,R2 \n"
|
||
|
|
" VMOV D28,R2,R2 \n"
|
||
|
|
" VMOV D29,R2,R2 \n"
|
||
|
|
" VMOV D30,R2,R2 \n"
|
||
|
|
" VMOV D31,R2,R2 \n"
|
||
|
|
".endif \n"
|
||
|
|
#endif
|
||
|
|
//Initialise FPSCR to a known state
|
||
|
|
" VMRS R2,FPSCR \n"
|
||
|
|
" MOV32 R3,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
|
||
|
|
" AND R2,R2,R3 \n"
|
||
|
|
" VMSR FPSCR,R2 \n");
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
#undef __IAR_FT
|
||
|
|
#undef __ICCARM_V8
|
||
|
|
|
||
|
|
#pragma diag_default=Pe940
|
||
|
|
#pragma diag_default=Pe177
|
||
|
|
|
||
|
|
#endif /* __CMSIS_ICCARM_H__ */
|