mbed-os/TESTS/mbed_hal/qspi/qspi_test_utils.h

/* mbed Microcontroller Library
 * Copyright (c) 2018-2018 ARM Limited
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef MBED_QSPI_TEST_UTILS_H
#define MBED_QSPI_TEST_UTILS_H

#include "flash_configs/flash_configs.h"
#include "unity/unity.h"

#define QSPI_NONE (-1)

struct QspiCommand {

    void configure(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width,
                   qspi_bus_width_t alt_width, qspi_address_size_t addr_size, qspi_alt_size_t alt_size,
                   int dummy_cycles = 0);

    void build(int instruction, int address = QSPI_NONE, int alt = QSPI_NONE);

    qspi_command_t * get();

    qspi_command_t cmd;
};

struct Qspi {
    qspi_t handle;
    QspiCommand cmd;
};

// MODE_Command_Address_Data_Alt
#define MODE_1_1_1      QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE
#define MODE_1_1_2      QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL,   QSPI_CFG_BUS_DUAL
#define MODE_1_2_2      QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL,   QSPI_CFG_BUS_DUAL,   QSPI_CFG_BUS_DUAL
#define MODE_1_1_4      QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD,   QSPI_CFG_BUS_SINGLE
#define MODE_1_4_4      QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD,   QSPI_CFG_BUS_QUAD,   QSPI_CFG_BUS_QUAD

#define WRITE_1_1_1     MODE_1_1_1, QSPI_CMD_WRITE_1IO
#ifdef QSPI_CMD_WRITE_4IO
#define WRITE_1_4_4     MODE_1_4_4, QSPI_CMD_WRITE_4IO
#endif


#define READ_1_1_1      MODE_1_1_1, QSPI_CMD_READ_1IO,  QSPI_READ_1IO_DUMMY_CYCLE
#define READ_1_1_2      MODE_1_1_2, QSPI_CMD_READ_1I2O, QSPI_READ_1I2O_DUMMY_CYCLE
#define READ_1_2_2      MODE_1_2_2, QSPI_CMD_READ_2IO,  QSPI_READ_2IO_DUMMY_CYCLE
#define READ_1_1_4      MODE_1_1_4, QSPI_CMD_READ_1I4O, QSPI_READ_1I4O_DUMMY_CYCLE
#define READ_1_4_4      MODE_1_4_4, QSPI_CMD_READ_4IO,  QSPI_READ_4IO_DUMMY_CYCLE


#define ADDR_SIZE_8  QSPI_CFG_ADDR_SIZE_8
#define ADDR_SIZE_16 QSPI_CFG_ADDR_SIZE_16
#define ADDR_SIZE_24 QSPI_CFG_ADDR_SIZE_24
#define ADDR_SIZE_32 QSPI_CFG_ADDR_SIZE_32

#define ALT_SIZE_8  QSPI_CFG_ALT_SIZE_8
#define ALT_SIZE_16 QSPI_CFG_ALT_SIZE_16
#define ALT_SIZE_24 QSPI_CFG_ALT_SIZE_24
#define ALT_SIZE_32 QSPI_CFG_ALT_SIZE_32

#define STATUS_REG      QSPI_CMD_RDSR
#define CONFIG_REG      QSPI_CMD_RDCR
#define SECURITY_REG    QSPI_CMD_RDSCUR


#define SECTOR_ERASE  QSPI_CMD_ERASE_SECTOR
#define BLOCK_ERASE   QSPI_CMD_ERASE_BLOCK_64


#define SECTOR_ERASE_MAX_TIME   QSPI_ERASE_SECTOR_MAX_TIME
#define BLOCK32_ERASE_MAX_TIME  QSPI_ERASE_BLOCK_32_MAX_TIME
#define BLOCK64_ERASE_MAX_TIME  QSPI_ERASE_BLOCK_64_MAX_TIME
#define PAGE_PROG_MAX_TIME      QSPI_PAGE_PROG_MAX_TIME
#define WRSR_MAX_TIME           QSPI_WRSR_MAX_TIME
#define WAIT_MAX_TIME           QSPI_WAIT_MAX_TIME



qspi_status_t read_register(uint32_t cmd, uint8_t *buf, uint32_t size, Qspi &q);

bool flash_wait_for(uint32_t time_us, Qspi &qspi);

void flash_init(Qspi &qspi);

qspi_status_t write_enable(Qspi &qspi);

qspi_status_t write_disable(Qspi &qspi);

qspi_status_t dual_enable(Qspi &qspi);

qspi_status_t dual_disable(Qspi &qspi);

qspi_status_t quad_enable(Qspi &qspi);

qspi_status_t quad_disable(Qspi &qspi);

qspi_status_t fast_mode_enable(Qspi &qspi);

qspi_status_t erase(uint32_t erase_cmd, uint32_t flash_addr, Qspi &qspi);

#define  WAIT_FOR(timeout, q) \
    if(!flash_wait_for(timeout, q)) { \
        TEST_ASSERT_MESSAGE(false, "flash_wait_for failed!!!"); \
    }

#endif // MBED_QSPI_TEST_UTILS_H